System and method for simulating power integrity at system-on-chip level

Abstract

The present invention discloses a system single chip level power integrity simulation system, which calculates the node current curve of each standard cell based on the gate level netlist and workload of each core area and the time delay and current curve of each standard cell under its load capacitance; generates the current curve of each core power bump based on the corresponding relationship between the standard cells and the core power bumps; calculates the current curve of each input and output power bump based on the data activity and current step response of each input and output buffer and the electrical connection relationship between each input and output power bump and the input and output buffers; and obtains the power transmission network based on the current curves of each core power bump and each input and output power bump. Therefore, the technical effect of accurate simulation results and fast simulation speed can be achieved.

Description

Technical Field

[0001] The present invention relates to a power integrity simulation system and method thereof, in particular to a system single chip level power integrity simulation system and method thereof. Background Art

[0002] Power integrity simulation is the bottleneck of current and future system-on-chip design, which directly affects the performance of the system on a chip (SoC). Due to the following two current factors, power integrity simulation remains a challenge.

[0003] The first factor is that all simulations related to power integrity need to be performed in a complete system-on-chip environment. The commercially used simulation program that focuses on integrated circuits (SPICE) cannot handle system-on-chip level power integrity simulation due to its limited simulation capabilities. The number of standard cells in a general system-on-chip currently exceeds 10 million, which makes other existing simulation tools (such as Redhawk) very long when performing system-on-chip level power integrity simulation, usually taking a week. Therefore, the traditional power integrity simulation method is to use the Redhawk tool to perform the power integrity simulation of the core area of ​​the system-on-chip, and the power integrity simulation of the input and output areas of the system-on-chip to perform SPICE, while the interaction between the core area and the input and output areas is ignored due to the simulator capacity problem. However, the Redhawk tool or SPICE does not have sufficient capabilities to handle the power integrity simulation in a complete system-on-chip environment. In addition, when using SPICE to perform power integrity simulation of the input and output areas, SPICE simulates the current curve for a short time and then repeats it to meet the long-term simulation, but this simulation method is inaccurate.

[0004] The second factor is that power integrity and power delivery noise depend largely on the workload of the SoC (i.e., the application environment of the SoC). Therefore, thousands of application scenarios should be considered when performing power integrity simulation to understand the limitations of power delivery noise and its statistical information on workloads, so that designers can focus on optimizing designs for specific workloads. However, different workloads will cause different activities of the gates in the SoC, and each core power bump corresponding to the standard cells will have different current curves, making the generation of current curves for evaluating the power integrity of different workloads very time-consuming in traditional SoC-level power integrity simulation methods.

[0005] In summary, it can be seen that the prior art has the problem of inaccuracy in power integrity simulation using simulation programs focused on integrated circuits and the problem that the generation of current curves for evaluating the power integrity of different workloads is very time-consuming. Therefore, it is necessary to propose improved technical means to solve this problem. Summary of the invention

[0006] In order to solve the above problems existing in the prior art, the present invention discloses a system-on-chip level power integrity simulation system and method thereof.

[0007] First, the present invention discloses a system-on-chip level power integrity simulation system, which includes: a memory module and a processor, the memory module is used to store a plurality of instructions, the processor is used to execute the instructions stored in the memory module, so as to perform a power integrity simulation program on the system-on-chip, wherein the system-on-chip includes a plurality of input-output regions and a plurality of core regions. The power integrity simulation program includes: an acquisition module is used to obtain the node activity of each standard cell in each core region in a binary mode based on the gate-level netlist and the workload of each core region; a classification module is used to classify the standard cells in each core region based on the gate-level netlist of each core region and the plurality of core power bumps defined in each core region, so that the standard cells in each core region correspond to different core power bumps in the same core region; a cell current module is used to obtain the cell delay and current curve of each standard cell under its load capacitance based on the load capacitance of each standard cell and the standard cell library. a node current module connected to the acquisition module and the cell current module, for calculating the node current curve of each standard cell according to the node activity of each standard cell in the binary mode and the time delay and current curve of each standard cell under its load capacitance; a core current module connected to the node current module and the classification module, for superimposing the node current curve of each standard cell based on the corresponding relationship between the standard cells and the core power bumps to generate the current curve of each core power bump; a simulation module, for simulating the current step response of each input / output buffer (I / O buffer) in each input / output region by means of a simulation program focusing on integrated circuits; an input / output current module connected to the simulation module, for superimposing the node current curve of each standard cell based on the data activity and current step response of each input / output buffer and the time delay and current curve of each input / output power bump (I / O power The invention relates to a power supply module, wherein the power supply module is connected to the input-output current module and the core current module to obtain a power delivery network (PDN) based on the current curve of each core power bump generated by the core current module and the current curve of each input-output power bump calculated by the input-output current module.

[0008] In addition, the present invention discloses a system single chip level power integrity simulation method for performing power integrity simulation on a system single chip, wherein the system single chip includes multiple input and output regions and multiple core regions, and the system single chip level power integrity simulation method includes the following steps: (a) obtaining node activities of each standard cell in each core region in a binary mode based on a gate-level netlist and a workload of each core region; (b) classifying the standard cells in each core region based on a gate-level netlist of each core region and multiple core power bumps defined in each core region, so that the standard cells in each core region correspond to different core power bumps in the same core region; (c) obtaining a time delay and current curve of each standard cell under its load capacitance based on a load capacitance of each standard cell and a standard cell library; (d) classifying the node activities of each standard cell in a binary mode based on a gate-level netlist and a workload of each core region; (e) classifying the node activities of each standard cell in a binary mode based on a gate-level netlist and a plurality of core power bumps defined in each core region; (f) classifying the node activities of each standard cell in a binary mode based on a gate-level netlist and a plurality of core power bumps defined in each core region; (g ... (e) superimposing the node current curve of each standard cell based on the corresponding relationship between the standard cells and the core power bumps to generate the current curve of each core power bump; (f) simulating the current step response of each input / output buffer in each input / output region by means of a simulation program focusing on integrated circuits; (g) calculating the current curve of each input / output power bump based on the data activity and current step response of each input / output buffer and the electrical connection relationship between each input / output power bump and the input / output buffers; and (h) obtaining a power transmission network based on the current curve of each core power bump generated in step (e) and the current curve of each input / output power bump calculated in step (g).

[0009] The system and method disclosed in the present invention are as described above. The difference from the prior art is that the present invention calculates the node current curve of each standard cell based on the gate-level netlist and workload of each core area and the time delay and current curve of each standard cell under its load capacitance; generates the current curve of each core power bump based on the correspondence between the standard cells and the core power bumps; calculates the current curve of each input-output power bump based on the data activity and current step response of each input-output buffer and the electrical connection relationship between each input-output power bump and the input-output buffers; and obtains the power transmission network based on the current curves of each core power bump and each input-output power bump.

[0010] Through the above technical means, the present invention can achieve the technical effects of accurate simulation results and fast simulation speed. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1A FIG. 1 is a schematic diagram of components of an embodiment of a system-on-chip level power integrity simulation system of the present invention.

[0012] Figure 1B FIG. 1 is a system architecture diagram of an embodiment of a system-on-chip level power integrity simulation system of the present invention.

[0013] Figure 2 for Figure 1B A flow chart of a method according to an embodiment of the present invention for executing a power integrity simulation program by a system-on-chip level power integrity simulation system.

[0014] Figure 3 FIG. 1 is a schematic diagram of an embodiment of a system on a chip.

[0015] Figure 4 A schematic diagram of an embodiment of a gate-level netlist of a core area.

[0016] Figure 5 A schematic diagram of an embodiment of an input / output power bump and its electrical connection to a plurality of input / output buffers.

[0017] Description of reference numerals:

[0018] 10 Input and output power bumps

[0019] 20 core power bump

[0020] 50A, 50B, 50C standard unit

[0021] 60A, 60B, 60C Input and output buffers

[0022] 100 System-on-Chip Level Power Integrity Simulation System

[0023] 101 Processor

[0024] 102 Memory Module

[0025] 103 Bus

[0026] 110 Get Module

[0027] 120 Classification Module

[0028] 130 Unit Current Module

[0029] 140 Node Current Module

[0030] 150 Core Current Module

[0031] 160 Simulation Module

[0032] 170 Input and output current module

[0033] 180 Power Module

[0034] 300 System on Chip

[0035] 310 Input and Output Area

[0036] 320 Core Area

[0037] X,Y,Z Node

[0038] X',Y',Z' input driver DETAILED DESCRIPTION

[0039] The following will describe the implementation methods of the present invention in detail with reference to drawings and examples, so that the implementation process of how the present invention applies technical means to solve technical problems and achieve technical effects can be fully understood and implemented accordingly.

[0040] Please refer to " Figure 1A "and" Figure 1B ”, “ Figure 1A ” is a schematic diagram of components of an embodiment of the system-on-chip power integrity simulation system of the present invention, Figure 1B ” is a system architecture diagram of an embodiment of the system on a chip level power integrity simulation system of the present invention. In this embodiment, the system on a chip level power integrity simulation system 100 may include but is not limited to hardware components such as one or more processors 101, one or more memory modules 102, and a bus 103, wherein the bus 103 may connect different hardware components. Through the included multiple hardware components, the system on a chip level power integrity simulation system 100 can be applied to a computing device to execute corresponding software or application programs.

[0041] The bus 103 may include one or more types of buses, such as a data bus, an address bus, a control bus, an expansion bus, and / or a local bus. The bus of the computing device includes, but is not limited to, an ISA bus, a PCI bus, a VESA local bus, a USB bus, a PCI-E bus, etc.

[0042] In this embodiment, the processor 101 may be coupled to the bus 103. The processor 101 may include a register group or register space, which may be completely set on the processing chip, or all or part of it may be set outside the processing chip and coupled to the processor 101 via a dedicated electrical connection and / or via the bus 103. The processor 101 may be a processing unit, a microprocessor, or any suitable processing element. When the system-on-chip power integrity simulation system 100 includes multiple processors, the processors may be the same or similar processors, and are coupled and communicated through the bus 103. The processor 101 may interpret a series of multiple instructions to perform specific operations or operations, such as mathematical operations, logical operations, data comparison, copying / moving data, etc., so as to execute various applications, modules and / or components.

[0043] In addition, the processor 101 may be coupled to a chipset or electrically connected to the chipset via a bus 103. The chipset is composed of one or more integrated circuits (ICs), including a memory controller and a peripheral input / output (I / O) controller, that is, the memory controller and the peripheral input / output controller may be included in one integrated circuit, or may be implemented using two or more integrated circuits. The chipset generally provides input / output and memory management functions, as well as multiple general and / or special registers, timers, etc., wherein the above-mentioned general and / or special registers and timers can be accessed or used by one or more processors 101 coupled or electrically connected to the chipset.

[0044] In addition, the processor 101 can also access the data in the memory module 102 and the large-capacity storage area installed on the system-on-chip power integrity simulation system 100 through the memory controller. The above-mentioned memory module 102 includes any type of volatile memory and / or non-volatile memory (NVRAM) memory, such as static random access memory (SRAM), dynamic random access memory (DRAM), flash memory (Flash), read-only memory (ROM), etc. The above-mentioned large-capacity storage area can include any type of storage device or storage medium, such as a hard disk drive, an optical disk, a flash memory (flash memory), a memory card, a solid-state disk (SSD) or any other storage device, etc. In other words, the memory controller can access the data in the static random access memory, the dynamic random access memory, the flash memory, the hard disk drive, and the solid-state disk.

[0045] In addition, the processor 101 can also connect and communicate with peripheral devices or interfaces such as peripheral output devices, peripheral input devices, communication interfaces and GPS receivers through the peripheral input / output controller via the bus 103. The peripheral input device can be any type of input device, such as a keyboard, a mouse, a trackball, a touchpad, a joystick, etc. The peripheral output device can be any type of output device, such as a display, a printer, etc. The peripheral input device and the peripheral output device can also be the same device, such as a touch screen, etc. The communication interface can include a wireless communication interface and / or a wired communication interface. The wireless communication interface can include an interface supporting wireless area networks such as Wi-Fi, Zigbee, Bluetooth, infrared, near field communication (NFC), mobile communication networks such as 3G / 4G / 5G, or other wireless data transmission protocols. The wired communication interface can be an Ethernet device, an asynchronous transfer mode (ATM) device, a DSL modem, a cable modem, etc. The processor 101 can periodically poll various peripheral devices and interfaces, so that the system single chip level power integrity simulation system 100 can input and output data through various peripheral devices and interfaces.

[0046] like" Figure 1B ” As shown, the system single chip level power integrity simulation system 100 comprises an acquisition module 110, a classification module 120, a unit current module 130, a node current module 140, a core current module 150, a simulation module 160, an input-output current module 170 and a power module 180. The node current module 140 can be connected to the acquisition module 110 and the unit current module 130, the core current module 150 can be connected to the node current module 140 and the classification module 120, the input-output current module 170 can be connected to the simulation module 160, and the power module 180 can be connected to the input The output current module 170 and the core current module 150. Among them, the acquisition module 110, the classification module 120, the unit current module 130, the node current module 140, the core current module 150, the simulation module 160, the input and output current module 170 and the power module 180 are usually generated after the processor 101 executes a specific program loaded into the memory module 102, or are included in the processor 101. In actual implementation, the system single chip level power integrity simulation system 100 can be applied to but not limited to tablet computers, desktop computers or notebook computers.

[0047] Next, see “ Figure 2 ”, “ Figure 2 "for" Figure 1B” is a flowchart of an embodiment of a method for executing a power integrity simulation program in a system-on-chip level power integrity simulation system. In this embodiment, the power integrity simulation program can be used to perform power integrity simulation on a system-on-chip 300, wherein the system-on-chip 300 may include a plurality of input-output regions 310 and a plurality of core regions 320 (such as “ Figure 3 " Figure 3 ” is a schematic diagram of an embodiment of a system single chip, each input-output region 310 may include at least one input-output power bump 10 and a plurality of input-output buffers (not shown), each input-output power bump 10 supplies power to the input-output buffer electrically connected thereto; each core region 320 may include at least one core power bump 20 and a plurality of standard cells (not shown), each core power bump 20 supplies power to the standard cells electrically connected thereto, and the standard cells electrically connected to the same core power bump 20 are connected in series or in an array; wherein the standard cells electrically connected to the same core power bump 20 are connected in series or in an array; The standard cells electrically connected to the bump 20 are divided into several levels, and the output end of the B-th level standard cell is connected to the input end of the (B+1)-th level standard cell, B is a positive integer greater than or equal to 1 and less than or equal to the number of standard cells electrically connected to the same core power bump 20; when the standard cells electrically connected to the same core power bump 20 are connected in an array, the standard cell in the X-th row and the Y-th column is the (X×Y)-th level standard cell, X and Y are both positive integers greater than or equal to 1, and (X×Y) is less than or equal to the number of standard cells electrically connected to the same core power bump 20.

[0048] Each standard cell may include an input pin and an output pin and may process a signal received via the input pin to output a signal via the output pin; for example, the standard cell may be a basic cell (such as an AND logic gate, an OR logic gate, a NOR logic gate, or an inverter), a complex cell (such as a complex cell composed of an OR logic gate / AND logic gate / inverter (OR / AND / INVERTER, OAI) or a complex cell composed of an AND logic gate / OR logic gate / inverter (AND / OR / INVERTER, AOI)) or a storage element (such as a master-slave bistable flip-flop or latch).

[0049] Please refer to " Figure 1B "and"" Figure 2The power integrity simulation program includes the following steps: obtaining the node activity of each standard cell in each core area in a binary mode based on the gate-level netlist and the workload of each core area (step 210); classifying the standard cells in each core area based on the gate-level netlist of each core area and the multiple core power bumps defined in each core area so that the standard cells in each core area correspond to different core power bumps in the same core area (step 220); obtaining the time delay and current curve of each standard cell under its load capacitance based on the load capacitance of each standard cell and the standard cell library (step 230); obtaining the time delay and current curve of each standard cell under its load capacitance based on the node activity of each standard cell in the binary mode and the time delay and current curve of each standard cell under its load capacitance; ... The method comprises the steps of: calculating a node current curve of each standard cell based on a curve (step 240); superimposing the node current curve of each standard cell based on the corresponding relationship between the standard cells and the core power bumps to generate a current curve of each core power bump (step 250); simulating the current step response of each input / output buffer in each input / output region by a simulation program focusing on integrated circuits (step 260); calculating the current curve of each input / output power bump based on the data activity and current step response of each input / output buffer and the electrical connection relationship between each input / output power bump and the input / output buffers (step 270); and obtaining a power transmission network based on the current curve of each core power bump and the current curve of each input / output power bump (step 280).

[0050] In step 210, the acquisition module 110 may acquire the node activity of each standard cell in each core region 320 in the binary mode based on the gate-level netlist and workload of each core region 320. More specifically, the acquisition module 110 may perform register transfer level (RTL) design using Verilog hardware description language (e.g., ModelSim simulation tool, VCS simulation tool, or NC-Sim simulation tool) according to the gate-level netlist and workload of each core region 320, thereby acquiring the node activity of each standard cell in each core region 320 in the binary mode. For example, please refer to “ Figure 4 ”, “ Figure 4" is a schematic diagram of an embodiment of a gate-level netlist of a core area. In this embodiment, the gate-level netlist of the core area 320 may include a standard cell 50A, a standard cell 50B and a standard cell 50C, the standard cell 50A includes a node X, the standard cell 50B includes a node Y, and the standard cell 50C includes a node Z. The acquisition module 110 can obtain the node activity of the node X as "0110100...", the node activity of the node Y as "0010110...", and the node activity of the node Z as "0010100..." based on the gate-level netlist of the core area 320 and the workload.

[0051] In step 220, the classification module 120 can classify the standard cells in each core region 320 based on the gate-level netlist of each core region 320 and the multiple core power bumps 20 defined in each core region 320, so that the standard cells in each core region 320 correspond to different core power bumps 20 in the same core region 320. More specifically, the classification module 120 can first perform automatic placement and routing (APR) based on the gate-level netlist of each core region 320 to obtain a floor plan of each core region 320; then, based on the floor plan of each core region 320, a corresponding netlist file is generated using professional software, each netlist file including multiple parasitic capacitors; finally, based on each netlist file, a standard cell corresponding to each core power bump 20 is obtained, and then the standard cells in each core region 320 are classified, so that the standard cells in each core region 320 correspond to different core power bumps 20 in the same core region 320. For example, the classification module 120 can generate a netlist file with parasitic capacitance based on the floor plan of each core area 320 using professional software STAR-RC (i.e., generate a netlist file corresponding to each core area), wherein the format of each netlist file can be standard parasitic exchange format (SPEF). Since it can be known from each netlist file that the power supply of the standard cells in each core area 320 belongs to different core power bumps 20, the standard cells in each core area 320 can be classified so that the standard cells in each core area 320 correspond to different core power bumps 20 in the same core area 320.

[0052] In step 230, the cell current module 130 can obtain the time delay and current curve of each standard cell under its load capacitance based on the load capacitance of each standard cell and the standard cell library. The standard cell library stores information of multiple standard cells, such as the name and function of the standard cell, timing information (including time delay, current curve and transition time), power information and layout information. The transition time is the time required for the signal waveform to move from 10% to 90% of its final value.

[0053] In more detail, the cell current module 130 can first obtain the load capacitance of each standard cell based on the standard cell library. Among the standard cells corresponding to the same core power bump, when the standard cell is a first-level standard cell, the load capacitance of the standard cell includes its own metal parasitic capacitance; when a certain standard cell is an N-th level standard cell (N is a positive integer greater than or equal to 2, and less than or equal to the number of the standard cells corresponding to the same core power bump), the load capacitance of the standard cell includes its own metal parasitic capacitance and the capacitance of the gate of the next-level standard cell. Among the standard cells corresponding to the same core power bump, when the standard cell is a first-level standard cell, the cell current module 130 can obtain the time delay, current curve and conversion time of the standard cell according to the standard cell library and the load capacitance of the standard cell; and when a certain standard cell is an N-th level standard cell, the cell current module 130 can use the conversion time of the (N-1)-th level standard cell as the input characteristic of the standard cell, and obtain the time delay, current curve and conversion time of the N-th level standard cell according to the standard cell library, the load capacitance and input characteristics of the N-th level standard cell.

[0054] In step 240, the node current module 140 can calculate the node current curve of each standard cell according to the node activity of each standard cell in the binary mode and the time delay and current curve of each standard cell under its load capacitance. For example, see " Figure 4", since each node can only obtain power from the corresponding core power bump when its node activity changes from 0 to 1, the node X can obtain the corresponding node current curve (i.e., the node current curve of node X) by calculation based on the change process of its node activity from 0 to 1, the time delay of the previous stage, and the current curve at the conversion time. Since the standard cell 50A only includes the node X, the node current curve of the standard cell 50A is equal to the node current curve of the node X; the node Y can obtain the corresponding node according to the change process of its node activity from 0 to 1, the time delay of the previous stage, and the current curve at the conversion time. The node current curve of node Z (i.e., the node current curve of node Y) can be obtained by calculating the node current curve of node Z according to the change process of its node activity from 0 to 1, the maximum time delay among the time delays of its input drivers (i.e., X' and Y'), and the maximum conversion time of the conversion times between nodes X and Y. Since the standard cell 50C only includes node Z, the node current curve of standard cell 50C is equal to the node current curve of node Z.

[0055] In step 250, the core current module 150 may superimpose the node current curve of each standard cell based on the corresponding relationship between the standard cells and the core power bumps 20 to generate a current curve of each core power bump 20. In other words, the core current module 150 may add the node current curves of the standard cells correspondingly connected to the same core power bump 20 to obtain the current curve of the core power bump 20.

[0056] In step 260, the simulation module 160 can simulate the current step response of each input-output buffer in each input-output region 310 by SPICE. In more detail, the simulation module 160 can simulate the current change of the current measurement point when the data received by the data input terminal of each input-output buffer changes from 0 to 1 (i.e., the rising edge of the data); and the current change of the current measurement point when the data received by the data input terminal of each input-output buffer changes from 1 to 0 (i.e., the falling edge of the data); therefore, the simulation module 160 can simulate the current step response of each input-output buffer. In other words, the simulation module 160 can be used to simulate each input-output buffer to quickly generate a corresponding current curve under different data patterns.

[0057] In step 270, the input / output current module 170 may calculate the current curve of each input / output power bump 10 based on the data activity and current step response of each input / output buffer and the electrical connection relationship between each input / output power bump 10 and the input / output buffers. In more detail, the input / output current module 170 may first obtain the current curve of each input / output buffer based on the data activity and current step response of each input / output buffer; then, calculate the current curve of each input / output power bump 10 based on the current curve of the input / output buffers electrically connected to the same input / output power bump 10.

[0058] For example, see " Figure 5 ”, “ Figure 5 ” is a schematic diagram of an embodiment of an input / output power bump and its electrical connection to a plurality of input / output buffers. In this embodiment, the input / output power bump 10 is electrically connected to three input / output buffers (i.e., input / output buffer 60A, input / output buffer 60B, and input / output buffer 60C) (the input / output power bump 10 supplies power to these input / output buffers). The data input end of each input / output buffer can receive an input data string (e.g., “10100101101” or “1100110001”) (i.e., each input / output buffer has its data activity). For the input data string of each input / output buffer (e.g., “10100101101” or “1100110001”), if the current input data is compared with the previous input data and changes from 0 to 1, the input / output The current measurement point of the input / output buffer changes in steps; if the current input data changes from 1 to 0 compared with the previous input data, the current measurement point of the input / output buffer changes in steps; if the current input data does not change compared with the previous input data (i.e., the current input data and the previous input data are both 0 or 1), the current measurement point of the input / output buffer does not change. Therefore, according to the above method, the current curve of each input / output buffer under its specific data activity (i.e., it receives a specific input data string) can be quickly generated. In this embodiment, the input / output current module 170 can add the current curves of the input / output buffer 60A, the input / output buffer 60B, and the input / output buffer 60C under their specific data activities to obtain the current curve of the input / output power bump 10.

[0059] In step 280, the power module 180 may obtain a power transmission network based on the current curve of each core power bump 20 and the current curve of each input / output power bump 10. More specifically, the power module 180 may obtain the power transmission network in a Z parameter or S parameter format based on the current curve of each core power bump 20 generated in step 250 and the current curve of each input / output power bump 10 calculated and obtained in step 270.

[0060] Through the above steps, the current curve of each core power bump 20, the current curve of each input and output power bump 10, and the power transmission network can be quickly constructed considering different SoC application scenarios (i.e., different workloads); it has scalability from a single input and output area to the entire SoC level; and the granularity of the basic unit or higher-level hierarchy cell can be used to adjust the speed and accuracy of the simulation, and has an adaptive tradeoff.

[0061] In summary, the difference between the present invention and the prior art lies in that the node current curve of each standard cell is calculated based on the gate-level netlist and workload of each core region and the time delay and current curve of each standard cell under its load capacitance; the current curve of each core power bump is generated based on the correspondence between the standard cells and the core power bumps; the current curve of each input / output power bump is calculated based on the data activity and current step response of each input / output buffer and the electrical connection relationship between each input / output power bump and the input / output buffers; and the power transmission network is obtained based on the current curves of each core power bump and each input / output power bump. By this technical means, the technical effect of accurate simulation results and fast simulation speed can be achieved.

[0062] Although the present invention is disclosed as above with the aforementioned embodiments, it is not intended to limit the present invention. Any technician in this field can make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of patent protection of the present invention shall be based on the scope defined by the claims attached to this specification.

Claims

1. A system-on-chip level power integrity simulation system, characterized in that: include: A memory module for storing a plurality of instructions; as well as The processor is used to execute the instructions stored in the memory module to perform a power integrity simulation program on a system on a chip, wherein the system on a chip includes a plurality of input and output areas and a plurality of core areas, and the power integrity simulation program includes: An acquisition module, for acquiring node activities of each standard cell in each core region in a binary mode based on a gate-level netlist and a workload of each core region; A classification module, for classifying the standard cells in each core region based on the gate-level netlist of each core region and a plurality of core power bumps defined in each core region, so that the standard cells in each core region correspond to different core power bumps in the same core region; A cell current module is used to calculate the load capacitance of each standard cell based on the standard cell library. Obtaining a time delay and current curve of each standard unit under its load capacitance; A node current module connected to the acquisition module and the cell current module for calculating a node current curve of each standard cell according to the node activity of each standard cell in the binary mode and the time delay and the current curve of each standard cell under its load capacitance; A core current module, connected to the node current module and the classification module, for superimposing the node current curve of each standard cell based on the corresponding relationship between the standard cells and the core power bumps to generate a current curve of each core power bump; A simulation module for simulating the current step response of each I / O buffer in each I / O region by using a simulation program focused on integrated circuits (SPICE); An input / output current module connected to the simulation module and used to calculate a current curve of each input / output power bump based on the data activity of each input / output buffer and the current step response and the electrical connection relationship between each input / output power bump and the input / output buffers; and The power module is connected to the input-output current module and the core current module to obtain a power transmission network based on the current curve of each core power bump generated by the core current module and the current curve of each input-output power bump calculated by the input-output current module.

2. The system-on-chip level power integrity simulation system according to claim 1, characterized in that: The classification module first performs automatic layout and routing based on the gate-level netlist of each core area to obtain a floor plan of each core area; then, a corresponding netlist file is generated based on the floor plan of each core area, and each netlist file includes a plurality of parasitic capacitors; finally, the standard unit corresponding to the power supply of each core power bump is obtained based on each netlist file, and then the standard units in each core area are classified so that the standard units in each core area correspond to different core power bumps in the same core area.

3. The system-on-chip level power integrity simulation system according to claim 1, characterized in that: The cell current module first obtains the load capacitance of each of the standard cells, wherein the load capacitance of each of the standard cells includes metal parasitic capacitance, or includes the metal parasitic capacitance and the capacitance of the gate of the next level standard cell; then, among the standard cells corresponding to the same core power bump, when the standard cell is a first level standard cell, the time delay, the current curve and the conversion time of the standard cell are obtained according to the standard cell library and the load capacitance of the standard cell; and when the standard cell is an N-th level standard cell, the conversion time of the (N-1)-th level standard cell is used as an input characteristic, and the time delay, the current curve and the conversion time of the N-th level standard cell are obtained according to the standard cell library, the load capacitance of the N-th level standard cell and the input characteristic, wherein N is a positive integer greater than or equal to 2, and less than or equal to the number of the standard cells corresponding to the same core power bump.

4. The system-on-chip level power integrity simulation system according to claim 1, characterized in that: The input / output current module first obtains the current curve of each input / output buffer based on the data activity and the current step response of each input / output buffer; and then calculates the current curve of each input / output power bump based on the current curves of the input / output buffers electrically connected to the same input / output power bump.

5. The system-on-chip level power integrity simulation system according to claim 1, characterized in that: The power module obtains the power transmission network in a Z parameter or S parameter format based on the current curve of each core power bump generated by the core current module and the current curve of each input / output power bump calculated and obtained by the input / output current module.

6. A system single chip level power integrity simulation method, used to perform power integrity simulation on a system single chip, the system single chip comprising a plurality of input and output areas and a plurality of core areas, the system single chip level power integrity simulation method comprising the following steps: (a) obtaining node activity of each standard cell in each core region in a binary mode based on a gate-level netlist and a workload of each core region; (b) classifying the standard cells in each core region based on the gate-level netlist of each core region and a plurality of core power bumps defined in each core region, so that the standard cells in each core region correspond to different core power bumps in the same core region; (c) obtaining a time delay and current curve of each standard cell under its load capacitance based on the load capacitance of each standard cell and the standard cell library; (d) calculating a node current curve of each standard cell according to the node activity of each standard cell in the binary mode and the time delay and the current curve of each standard cell under its load capacitance; (e) superimposing the node current curve of each of the standard cells based on the corresponding relationship between the standard cells and the core power bumps to generate a current curve of each of the core power bumps; (f) simulating the current step response of each input / output buffer in each of the input / output regions by a simulation program focused on integrated circuits; (g) calculating a current curve of each input / output power bump based on the data activity of each input / output buffer and the current step response and the electrical connection relationship between each input / output power bump and the input / output buffers; and (h) obtaining a power transmission network based on the current curve of each of the core power bumps generated in step (e) and the current curve of each of the input and output power bumps calculated and obtained in step (g).

7. The system single chip level power integrity simulation method according to claim 6, characterized in that: The step (b) further comprises: Performing automatic placement and routing based on the gate-level netlist of each core region to obtain a floor plan of each core region; Generate a corresponding netlist file based on the floor plan of each core area, each of the netlist files including a plurality of parasitic capacitors; and The standard cell corresponding to each core power bump is obtained based on each netlist file, and the standard cells in each core area are classified so that the standard cells in each core area correspond to different core power bumps in the same core area.

8. The system single chip level power integrity simulation method according to claim 6, characterized in that: The step (c) further comprises: Obtaining the load capacitance of each of the standard cells, wherein the load capacitance of each of the standard cells includes metal parasitic capacitance, or includes capacitance of the metal parasitic capacitance and a gate of a next-level standard cell; and Among the standard cells corresponding to the same core power bump, when the standard cell is a first-level standard cell, the time delay, the current curve and the conversion time of the standard cell are obtained according to the standard cell library and the load capacitance of the standard cell; when the standard cell is an N-th level standard cell, the conversion time of the (N-1)-th level standard cell is used as an input characteristic, and the time delay, the current curve and the conversion time of the N-th level standard cell are obtained according to the standard cell library, the load capacitance of the N-th level standard cell and the input characteristic, wherein N is a positive integer greater than or equal to 2 and less than or equal to the number of the standard cells corresponding to the same core power bump.

9. The system single chip level power integrity simulation method according to claim 6, characterized in that: The step (g) further comprises: Obtaining a current curve of each of the input-output buffers based on the data activity and the current step response of each of the input-output buffers; and The current curve of each input / output power bump is calculated based on the current curve of the input / output buffers electrically connected to the same input / output power bump.

10. The system single chip level power integrity simulation method according to claim 6, characterized in that: The step (h) further includes: obtaining the power transmission network in a Z parameter or S parameter format based on the current curve of each core power bump generated in the step (e) and the current curve of each input and output power bump calculated and obtained in the step (g).

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