Display device

Abstract

A display device is provided. The display device includes first dots connected to first scan lines, second dots connected to second scan lines and arranged in a first direction alternately with the first dots and in a second direction different from the first direction, a scan driver including first stages connected to the first scan lines and second stages connected to the second scan lines, respectively, and a data driver connected to the first dots and the second dots through data lines. The first stages are connected to first clock lines, the second stages are connected to second clock lines, the first stages other than a first start stage are connected to respective first scan lines of respective previous first stages, respectively, and the second stages other than a second start stage are connected to respective second scan lines of respective previous second stages, respectively.

Description

[0001] This application claims priority to and all benefits derived therefrom of Korean Patent Application No. 10-2020-0096230, filed on July 31, 2020, the contents of which are incorporated herein by reference in their entirety. Technical Field

[0002] Embodiments of the present invention relate to display devices. Background Technology

[0003] With the development of information technology, the importance of display devices as the connection medium between users and information has been highlighted. In response, the use of display devices such as liquid crystal displays and organic light-emitting diode displays is increasing.

[0004] When a display device displays moving images, it can display the images at a high frequency to smoothly represent motion. Conversely, when a display device displays still images, there is no motion, so even if the images are displayed at a low frequency, no problem will occur. In addition, displaying images at a low frequency is advantageous in terms of power consumption. Summary of the Invention

[0005] However, when the display frequency of a display device switches from a high frequency to a low frequency, flicker can be visually detected due to the change in the cycle of brightness reduction. Additionally, flicker may occur when displaying specific patterns when the display device is driven at a low frequency.

[0006] The technical problem to be solved is to provide a display device that can prevent flicker when the display frequency switches from a high frequency to a low frequency.

[0007] Another technical problem to be solved is to provide a display device that can prevent flickering when displaying a specific pattern during low-frequency driving.

[0008] The display device in an embodiment of the present invention includes a first point, a second point, a scan driver, and a data driver. The first point is connected to a first scan line, and the second point is connected to a second scan line and is alternately arranged with the first point in a first direction and a second direction different from the first direction. The scan driver includes a plurality of first stages respectively connected to a plurality of first scan lines and a plurality of second stages respectively connected to a plurality of second scan lines. The data driver is connected to the first point and the second point via data lines. The plurality of first stages are connected to a first clock line, and the plurality of second stages are connected to a second clock line different from the first clock line. Except for a first start stage among the plurality of first stages, each of the plurality of first stages is connected to a corresponding first scan line of a corresponding previous first stage among the plurality of first scan lines of the plurality of first stages. And except for a second start stage among the plurality of second stages, each of the plurality of second stages is connected to a corresponding second scan line of a corresponding previous second stage among the plurality of second scan lines of the plurality of second stages.

[0009] In an implementation, each of the first point and the second point may include a first color pixel, a second color pixel, and a third color pixel arranged in a first direction, and the first color, the second color, and the third color may be different from each other.

[0010] In one implementation, each of the multiple data lines can be connected to a pixel of a single color.

[0011] In an implementation, one of a plurality of first points may include pixels of a first color, pixels of a second color, pixels of a third color, and pixels of a second color arranged in a first direction. One of a plurality of second points arranged in a second direction from one of the plurality of first points may include pixels of a third color, pixels of a second color, pixels of a first color, and pixels of a second color arranged in the first direction, and the first color, second color, and third color may be different from each other.

[0012] In one implementation, one of the multiple data lines may be alternately connected to a pixel of a first color and a pixel of a third color, and another of the multiple data lines may be connected to a pixel of a second color.

[0013] In one implementation, a first starting stage among a plurality of first stages and a second starting stage among a plurality of second stages may be connected to the same scan start line.

[0014] In one implementation, during each first frame period, the scan driver may alternately apply a pass-through level scan signal to the first scan line and the second scan line.

[0015] In one implementation, during the first subframe period within each second frame period, the scan driver may apply a scan signal at an on level to the first scan line and maintain a scan signal at an off level in the second scan line. During the second subframe period within each second frame period, the scan driver may apply a scan signal at an on level to the second scan line and maintain a scan signal at an off level in the first scan line.

[0016] In an implementation, the second frame time period may be longer than the first frame time period.

[0017] In one implementation, during the first frame period, a first clock signal with a conduction level can be applied to a first clock line, and a second clock signal with a conduction level can be applied to a second clock line, and the first clock signal and the second clock signal can have different phases.

[0018] In one implementation, during the first subframe period, a first clock signal at an on level can be applied to the first clock line, and a second clock signal at an off level can be maintained on the second clock line. During the second subframe period, the second clock signal at an on level can be applied to the second clock line, and the first clock signal at an off level can be maintained on the first clock line.

[0019] In the implementation, the periods during which the first clock signal with the conduction level is applied to the first clock line can be the same for the first frame period and the first subframe period.

[0020] In the implementation, during the first frame period and the second subframe period, the period of the second clock signal with the conduction level applied to the second clock line can be the same for each other.

[0021] In one implementation, the periods during which the first scan signal with a conduction level is applied to the first scan line can be the same for both the first frame period and the first subframe period.

[0022] In the implementation, during the first frame period and the second subframe period, the period during which the second scan signal with the conduction level is applied to the second scan line can be the same for each other.

[0023] In one implementation, the period during which the first clock signal with a conduction level is applied to the first clock line in the first subframe period may be shorter than the period during which the first clock signal with a conduction level is applied in the first frame period.

[0024] In one implementation, the period during which the second clock signal at the on level is applied to the second clock line in the second subframe period may be shorter than the period during which the second clock signal at the on level is applied in the first frame period.

[0025] In one implementation, the period during which the first scan signal with a conduction level is applied to the first scan line in the first subframe period may be shorter than the period during which the first scan signal with a conduction level is applied in the first frame period.

[0026] In one implementation, the period during which the second scan signal at the on level is applied to the second scan line in the second subframe period may be shorter than the period during which the second scan signal at the on level is applied in the first frame period.

[0027] In one implementation, the data driver may be powered off during at least some of the first and second subframe periods. Attached Figure Description

[0028] The accompanying drawings are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.

[0029] Figure 1 This is a diagram used to explain embodiments of the display device according to the present invention.

[0030] Figure 2 This is a diagram used to explain an embodiment of the pixels according to the present invention.

[0031] Figure 3 This is a diagram used to explain an embodiment of the scan driver according to the present invention.

[0032] Figure 4 This is a diagram used to explain the implementation of the level according to the present invention.

[0033] Figure 5 This is a diagram used to explain an embodiment of the driving method of the scan driver according to the present invention.

[0034] Figures 6 to 9 This is a diagram used to explain the implementation of the first frame time period and the second frame time period according to the present invention.

[0035] Figures 10 to 13 This is a diagram used to explain another embodiment of the first frame time period and the second frame time period according to the present invention.

[0036] Figure 14 This is a diagram used to explain another embodiment of the first frame time period and the second frame time period according to the present invention.

[0037] Figure 15 This is a diagram used to explain another embodiment of the scan driver according to the present invention.

[0038] Figure 16 This is a diagram used to explain an embodiment of the pixel unit according to the present invention.

[0039] Figure 17 This is a diagram used to explain another embodiment of the pixel unit according to the present invention.

[0040] Figure 18 This is a diagram used to explain another embodiment of the pixel unit according to the present invention. Detailed Implementation

[0041] Embodiments of the present invention will be described in detail below with reference to the accompanying drawings, so that those skilled in the art can readily implement the invention. Embodiments of the present invention may be implemented in various different forms and are not limited to those described herein.

[0042] For clarity in describing the invention, parts irrelevant to the specification have been omitted, and the same reference numerals denote the same or similar parts throughout the specification. Therefore, the aforementioned reference numerals may be used in other figures.

[0043] Furthermore, for ease of description, the dimensions and thicknesses of each component shown in the figures are arbitrarily depicted, and therefore the invention is not necessarily limited to those shown in the figures. In the figures, thicknesses may be exaggerated to clearly represent layers and regions.

[0044] What will be understood is that when an element is referred to as being "on" another element, it can be directly on the other element, or there can be an intermediate element between them. Conversely, when an element is referred to as being "directly" on another element, there is no intermediate element.

[0045] It will be understood that although the terms “first,” “second,” “third,” etc., may be used herein to describe various elements, components, areas, layers, and / or parts, these elements, components, areas, layers, and / or parts should not be limited by these terms. These terms are used only to distinguish one element, component, area, layer, or part from another. Therefore, the first “element,” “component,” “area,” “layer,” or “part” discussed below may be referred to as the second element, component, area, layer, or part without departing from the teachings herein.

[0046] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. Unless the content clearly indicates otherwise, the singular forms “a,” “an,” and “the” as used herein are intended to include the plural forms, thereby including “at least one.” “Or” means “and / or.” As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items. It will also be understood that the terms “comprises” and / or “comprising” or “includes” and / or “including,” when used in this specification, indicate the presence of the stated features, areas, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, areas, integers, steps, operations, elements, components, and / or clusters thereof.

[0047] Furthermore, relative terms such as “lower” or “bottom” and “upper” or “top” may be used herein to describe the relationship between one element and another as shown in the figures. It will be understood that, in addition to the orientations shown in the figures, the relative terms are also intended to cover different orientations of the device. In an implementation, when a device in one of the figures is flipped, an element described as being on the “lower” side of another element will subsequently be oriented on the “upper” side of that other element. Thus, the exemplary term “lower” can cover both “lower” and “upper” orientations depending on the specific orientation of the figure. Similarly, when a device in one of the figures is flipped, an element described as being “below” or “below” other elements will subsequently be oriented as being “above” other elements. Thus, the exemplary term “below” or “below” can cover both “upper” and “lower” orientations.

[0048] Given the measurements discussed and the errors associated with a particular number of measurements (i.e., limitations of the measurement system), the terms "about" or "approximately" as used herein include the stated values ​​and mean within an acceptable range of deviation for a particular value as determined by one of ordinary skill in the art. For example, "about" could mean within one or more standard deviations, or within ±30%, ±20%, ±10%, or ±5% of the stated value.

[0049] Unless otherwise specified, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. It will also be understood that, unless expressly defined herein, terms, such as those defined in common dictionaries, shall be interpreted as having the same meaning as they have in the relevant field and in the context of this invention, and shall not be interpreted in an idealized or overly formal sense.

[0050] The embodiments are described herein with reference to cross-sectional views, which are schematic illustrations of idealized implementations. Therefore, variations in the shape of the illustrations are expected, resulting from factors such as manufacturing techniques and / or tolerances. Consequently, the embodiments described herein should not be construed as limited to the specific shapes of the regions shown herein, but will include deviations in shape caused, for example, by manufacturing processes. In the embodiments, regions shown or described as flat may generally have rough and / or non-linear characteristics. Furthermore, sharp corners shown may be rounded. Therefore, the regions shown in the figures are schematic in nature, and their shapes are not intended to represent the precise shapes of the regions, nor are they intended to limit the scope of the claims.

[0051] Figure 1 This is a diagram used to explain an embodiment of the display device 10 according to the present invention.

[0052] Reference Figure 1 The display device 10 in the embodiments of the present invention may include a timing controller 11, a data driver 12, a scan driver 13, and a pixel unit 14.

[0053] The timing controller 11 can receive external input signals from an external processor. These external input signals may include a vertical synchronization signal, a horizontal synchronization signal, a data enable signal, and RGB data, etc. The vertical synchronization signal may include multiple pulses. Based on the timing of each pulse, it can indicate the end of the previous frame period and the beginning of the current frame period. The interval between adjacent pulses of the vertical synchronization signal may correspond to a frame period. The horizontal synchronization signal may include multiple pulses. Based on the timing of each pulse, it can indicate the end of the previous horizontal period and the beginning of a new horizontal period. The interval between adjacent pulses of the horizontal synchronization signal may correspond to a horizontal period. The data enable signal can indicate the supply of RGB data during the horizontal period. In response to the data enable signal, RGB data can be supplied in pixel rows during the horizontal period. The RGB data corresponding to a frame can also be referred to as an input image. When the gray levels of consecutive input images are substantially the same, the timing controller 11 can determine the consecutive input images as still images. When the gray levels of consecutive input images are substantially different, the timing controller 11 can determine the consecutive input images as moving images.

[0054] The data driver 12 can provide a data voltage corresponding to the grayscale of the input image to the pixel PXij. In an embodiment, for example, the data driver 12 can sample the grayscale using a clock signal and apply the data voltage corresponding to the grayscale to a plurality of data lines DL1 to DLn in units of scan lines, where n can be an integer greater than 0.

[0055] The scan driver 13 can receive clock signals and scan start signals from the timing controller 11, and generate scan signals to be provided to multiple scan lines SL1, SL2, SL3, ... and SLm, where m can be an integer greater than 0.

[0056] Pixel unit 14 may include multiple dots. Each dot may include at least two pixels of different colors. A dot may be a display unit for displaying combined colors. In an embodiment, for example, an external processor may provide grayscale in units of dots. Each pixel PXij may be connected to a corresponding data line and a corresponding scan line, where i and j may be integers greater than 0. In an embodiment, for example, pixel PXij may mean a pixel whose scan transistor is connected to the i-th scan line and the j-th data line.

[0057] Although not shown, the display device 10 may also include a transmit driver. The transmit driver may receive clock signals and transmit stop signals, etc., from the timing controller 11, and generate transmit signals to be provided to the transmit line. In an embodiment, for example, the transmit driver may include transmit stages connected to the transmit line. The transmit stage may be configured as a shift register. In an embodiment, for example, a first transmit stage may generate a transmit signal at a shutdown level based on a transmit stop signal at a shutdown level, and the remaining transmit stages may sequentially generate transmit signals at shutdown levels based on the transmit signal at a shutdown level of the previous transmit stage.

[0058] When the display device 10 includes the aforementioned emitter driver, each pixel PXij may also include a transistor connected to the emitter line. This transistor can be turned off during the data write period of each pixel PXij to prevent the pixel PXij from emitting light. In the following description, cases without an emitter driver will be presented as examples.

[0059] Figure 2 This is a diagram used to explain an embodiment of the pixel PXij according to the present invention.

[0060] The first transistor T1 may include a gate electrode connected to the i-th scan line SLi, a first electrode connected to the j-th data line DLj, and a second electrode connected to the second electrode of the storage capacitor Cst. The first transistor T1 may also be referred to as a scan transistor.

[0061] The second transistor T2 may include a gate electrode connected to the second electrode of the first transistor T1, a first electrode connected to the first power line ELVDDL, and a second electrode connected to the anode of the light-emitting diode LD. The second transistor T2 may also be referred to as a driver transistor.

[0062] The storage capacitor Cst may include a first electrode connected to the first power line ELVDDL and a second electrode connected to the gate electrode of the second transistor T2.

[0063] The light-emitting diode (LD) may include an anode connected to a second electrode of a second transistor T2 and a cathode connected to a second power supply line ELVSSL. During the emission period of the LD, a first power supply voltage applied to the first power supply line ELVDDL may be greater than a second power supply voltage applied to the second power supply line ELVSSL.

[0064] Here, the first transistor T1 and the second transistor T2 are shown as p-type transistors. However, those skilled in the art can replace at least one transistor with an n-type transistor by inverting the phase of the signal.

[0065] When a scan signal with a conduction level (here, logic low level) is applied through the i-th scan line SL1, the first transistor T1 can be turned on. At this time, the data voltage applied to the j-th data line DLj can be stored in the storage capacitor Cst.

[0066] The drive current corresponding to the voltage difference between the first and second electrodes of the storage capacitor Cst can flow between the first and second electrodes of the second transistor T2. Therefore, the light-emitting diode LD can emit light with a brightness corresponding to the data voltage.

[0067] Next, when a scan signal with a turn-off level (here, logic high level) is applied through the i-th scan line SL1, the first transistor T1 can be turned off, and the j-th data line DLj and the second electrode of the storage capacitor Cst can be electrically disconnected. Therefore, even if the data voltage of the j-th data line DLj changes, the voltage stored in the second electrode of the storage capacitor Cst can remain unchanged.

[0068] The embodiments of the present invention can be applied not only to Figure 2 The pixel PXij can also be applied to pixels with another pixel circuit according to the prior art.

[0069] Figure 3 This is a diagram used to explain an embodiment of the scan driver 13 according to the present invention.

[0070] The scan driver 13 may include a plurality of first-stage ST1, ST3, ... connected to a plurality of first scan lines SL1, SL3, ... and a plurality of second-stage ST2, ST4, ... connected to a plurality of second scan lines SL2, SL4, ...

[0071] Multiple first scan lines SL1, SL3, ... can be connected to multiple first points. In an embodiment, for example, the multiple first scan lines SL1, SL3, ... can be odd-numbered scan lines. In an embodiment, for example, the multiple first stages ST1, ST3, ... can be odd-numbered stages.

[0072] Multiple second scan lines SL2, SL4, ... can be connected to multiple second points. In an embodiment, for example, the multiple second scan lines SL2, SL4, ... can be even-numbered scan lines. In an embodiment, for example, the multiple second levels ST2, ST4, ... can be even-numbered levels.

[0073] Each of the multiple stages ST1 to ST4 may include a first input terminal 1001, a second input terminal 1002, a third input terminal 1003, and an output terminal 1004. A first start stage ST1 among the multiple first stages ST1, ST3, ... and a second start stage ST2 among the multiple second stages ST2, ST4, ... may be connected to the same scan start line FLML. In an embodiment, for example, the first input terminal 1001 of the first start stage ST1 and the first input terminal 1001 of the second start stage ST2 may be connected to the same scan start line FLML. The output terminal 1004 of the first start stage ST1 may be connected to a first scan line SL1, and the output terminal 1004 of the second start stage ST2 may be connected to a second scan line SL2.

[0074] Each of the plurality of first stages ST3, ... other than the first start stage ST1 can be connected to the first scan line of the preceding first stage. Each of the plurality of second stages ST4, ... other than the second start stage ST2 can be connected to the second scan line of the preceding second stage. In an embodiment, for example, the first input terminal 1001 of the first stage ST3 can be connected to the first scan line SL1 of the first start stage ST1. Additionally, the first input terminal 1001 of the second stage ST4 can be connected to the second scan line SL2 of the second start stage ST2.

[0075] Multiple first-stage ST1, ST3, ... can be connected to first clock lines CKL1 and CKL3. First clock lines CKL1 and CKL3 can be alternately connected to the second input terminals 1002 and 1003 of the multiple first-stage ST1, ST3, ... . Multiple second-stage ST2, ST4, ... can be connected to second clock lines CKL2 and CKL4, which are different from the first clock lines CKL1 and CKL3. Second clock lines CKL2 and CKL4 can be alternately connected to the second input terminals 1002 and 1003 of the multiple second-stage ST2, ST4, ...

[0076] Each of the multiple stages ST1 through ST4 can be connected to power supply line VHPL and power supply line VLPL. Here, the voltage of power supply line VHPL can be set to a shutdown level (gate shutdown voltage, logic high level). Conversely, the voltage of power supply line VLPL can be set to a turn-on level (gate turn-on voltage, logic low level).

[0077] exist Figure 3 In one embodiment, the first start stage ST1 and the second start stage ST2 can be connected to the same scan start line FLML. However, in another embodiment, the first start stage ST1 and the second start stage ST2 can be connected to different scan start lines.

[0078] Figure 4 This is a diagram used to explain the implementation of the level according to the present invention.

[0079] exist Figure 4 For ease of description, the first initial stage ST1 and the first stage ST3 are shown as examples. (See also...) Figure 4 The first start stage ST1 may include a first drive unit 1210, a second drive unit 1220 and an output unit (e.g., a buffer) 1230.

[0080] The output unit 1230 can control the voltage supplied to the output terminal 1004 in response to the voltages of nodes NP1 and NP2. For this purpose, the output unit 1230 may include transistors M5 and M6.

[0081] Transistor M5 may be arranged between power line VHPL and output terminal 1004, and the gate electrode of transistor M5 may be connected to node NP1. Transistor M5 may control the connection between power line VHPL and output terminal 1004 in response to the voltage applied to node NP1.

[0082] Transistor M6 may be arranged between output terminal 1004 and third input terminal 1003, and the gate electrode of transistor M6 may be connected to node NP2. Transistor M6 may control the connection between output terminal 1004 and third input terminal 1003 in response to a voltage applied to node NP2. Output unit 1230 may be driven as a buffer. Additionally, transistors M5 and M6 may include multiple transistors connected in parallel.

[0083] The first driving unit 1210 can control the voltage of node NP3 in response to signals supplied to the first input terminals 1001 to the third input terminals 1003. For this purpose, the first driving unit 1210 may include transistors M2 to M4.

[0084] Transistor M2 may be disposed between the first input terminal 1001 and node NP3, and the gate electrode of transistor M2 may be connected to the second input terminal 1002. Transistor M2 may control the connection between the first input terminal 1001 and node NP3 in response to a signal supplied to the second input terminal 1002.

[0085] Transistor M3 and transistor M4 may be connected in series between node NP3 and power line VHPL. Transistor M3 may be positioned between transistor M4 and node NP3, and the gate electrode of transistor M3 may be connected to the third input terminal 1003. Transistor M3 may control the connection between transistor M4 and node NP3 in response to a signal supplied to the third input terminal 1003.

[0086] Transistor M4 can be positioned between transistor M3 and the power line VHPL, and the gate electrode of transistor M4 can be connected to node NP1. Transistor M4 can control the connection between transistor M3 and the power line VHPL in response to the voltage at node NP1.

[0087] The second driving unit 1220 can control the voltage of node NP1 in response to the voltage of the second input terminal 1002 and node NP3. For this purpose, the second driving unit 1220 may include transistor M1, transistor M7, transistor M8, capacitor CP1, and capacitor CP2.

[0088] Capacitor CP1 can be connected between node NP2 and output terminal 1004. Capacitor CP1 can be charged using the voltage corresponding to the on and off states of transistor M6.

[0089] Capacitor CP2 can be connected between node NP1 and power line VHPL. Capacitor CP2 can be charged using the voltage applied to node NP1.

[0090] Transistor M7 may be arranged between node NP1 and the second input terminal 1002, and the gate electrode of transistor M7 may be connected to node NP3. Transistor M7 may control the connection between node NP1 and the second input terminal 1002 in response to the voltage of node NP3.

[0091] Transistor M8 may be arranged between node NP1 and power line VLPL, and the gate electrode of transistor M8 may be connected to the second input terminal 1002. Transistor M8 may control the connection between node NP1 and power line VLPL in response to a signal at the second input terminal 1002.

[0092] Transistor M1 can be positioned between nodes NP3 and NP2, and its gate electrode can be connected to the power supply line VLPL. Transistor M1 can maintain the electrical connection between nodes NP3 and NP2 while remaining in a conducting state. Furthermore, transistor M1 can limit the voltage drop width of node NP3 in response to the voltage at node NP2. In other words, even when the voltage at node NP2 drops below the voltage at the power supply line VLPL, the voltage at node NP3 can remain at least as high as the voltage obtained by subtracting the threshold voltage of transistor M1 from the voltage at the power supply line VLPL.

[0093] Figure 5 This is a diagram used to explain an embodiment of the driving method of the scan driver 13 according to the present invention. Figure 5 For ease of description, the operation process using the first starting level ST1 will be described as an instance.

[0094] Reference Figure 5 The first clock signals CK1 and CK3 may have four horizontal periods of 4H, and may be supplied in different horizontal periods. In other words, the first clock signal CK3 may be configured as a signal shifted by half a period (i.e., two horizontal periods) from the first clock signal CK1. Additionally, the scan start signal FLM supplied to the first input terminal 1001 may be supplied synchronously with the first clock signal CK1 supplied to the second input terminal 1002. One horizontal period of 1H may correspond to the period of the pulse of the horizontal synchronization signal Hsync.

[0095] In the following text, "the predetermined signal is supplied" may mean that the predetermined signal has an on level (here, logic low). "The supply of the predetermined signal is stopped" may mean that the predetermined signal has an off level (here, logic high).

[0096] Additionally, when the scan start signal FLM is supplied, the first input terminal 1001 can be set to a logic low level, and when the scan start signal FLM is not supplied, the first input terminal 1001 can be set to a logic high level. Furthermore, when a clock signal is supplied to the second input terminal 1002 and the third input terminal 1003, the second input terminal 1002 and the third input terminal 1003 can be set to a logic low level, and when a clock signal is not supplied, the second input terminal 1002 and the third input terminal 1003 can be set to a logic high level.

[0097] To describe the operation process in detail, firstly, the scan start signal FLM can be supplied synchronously with the first clock signal CK1.

[0098] When the first clock signal CK1 is supplied, transistors M2 and M8 are turned on. When transistor M2 is turned on, the first input terminal 1001 and node NP3 are electrically connected. Here, since transistor M1 is turned on for most of this period, node NP2 can maintain an electrical connection with node NP3.

[0099] When the first input terminal 1001 and node NP3 are electrically connected, the voltage VNP2 of node NP2 and the voltage VNP3 of node NP3 can be set to a low level by the scan start signal FLM supplied to the first input terminal 1001. When the voltage VNP2 of node NP2 and the voltage VNP3 of node NP3 are set to a low level, transistors M6 and M7 can be turned on.

[0100] When transistor M6 is turned on, the third input terminal 1003 and the output terminal 1004 can be electrically connected. Here, the third input terminal 1003 can be set to a high-level voltage (i.e., no first clock signal CK3 is supplied), and therefore, a high-level voltage can be output to the output terminal 1004. When transistor M7 is turned on, the second input terminal 1002 and node NP1 can be electrically connected. According to the first clock signal CK1 supplied to the second input terminal 1002, the voltage VNP1 of node NP1 can be set to a low level.

[0101] Furthermore, when the first clock signal CK1 is supplied, transistor M8 can be turned on. When transistor M8 is turned on, the voltage of power line VLPL can be supplied to node NP1. Here, the voltage of power line VLPL can be set to the same (or similar) voltage as the low level of the first clock signal CK1, and therefore, node NP1 can stably maintain a low voltage level.

[0102] When node NP1 is set to a low voltage level, transistors M4 and M5 are turned on. When transistor M4 is turned on, power line VHPL and transistor M3 are electrically connected. Here, since transistor M3 is set to the off state, node NP3 can stably maintain a low voltage level even when transistor M4 is turned on. When transistor M5 is turned on, the voltage of power line VHPL can be supplied to output terminal 1004. Here, the voltage of power line VHPL can be set to the same (or similar) voltage as the high voltage supplied to the third input terminal 1003, and therefore, output terminal 1004 can stably maintain a high voltage level.

[0103] Subsequently, the supply of the scan start signal FLM and the first clock signal CK1 can be stopped. When the supply of the first clock signal CK1 stops, transistors M2 and M8 can be turned off. At this time, transistors M6 and M7 can remain on in response to the voltage stored in capacitor CP1. That is, nodes NP2 and NP3 can maintain a low voltage level through the voltage stored in capacitor CP1.

[0104] When transistor M6 remains on, output terminal 1004 and third input terminal 1003 remain electrically connected. When transistor M7 remains on, node NP1 remains electrically connected to second input terminal 1002. Here, the voltage at second input terminal 1002 can be set to a high level when the supply of the first clock signal CK1 stops, and therefore, node NP1 can also be set to a high level. When a high level voltage is supplied to node NP1, transistors M4 and M5 can be turned off.

[0105] Subsequently, the first clock signal CK3 can be supplied to the third input terminal 1003. At this time, since transistor M6 is set to the on state, the first clock signal CK3 supplied to the third input terminal 1003 can be supplied to the output terminal 1004. In this case, the output terminal 1004 can output the first clock signal CK3 as the on level first scan signal SS1 to the first scan line SL1.

[0106] When the first clock signal CK3 is supplied to the output terminal 1004, due to the connection of capacitor CP1, the voltage at node NP2 can drop to a level lower than the voltage of the power supply line VLPL. Therefore, transistor M6 can stably remain in the on state.

[0107] Even when the voltage of node NP2 decreases, node NP3 can maintain the voltage of power line VLPL approximately by means of transistor M1 (e.g., by subtracting the threshold voltage of transistor M1 from the voltage of power line VLPL).

[0108] After the first scan signal SS1 at the conduction level is output to the first scan line SL1, the supply of the first clock signal CK3 can be stopped. When the supply of the first clock signal CK3 stops, the output terminal 1004 can output a high-level voltage. In addition, the voltage VNP2 at node NP2 can rise approximately to the voltage of the power supply line VLPL in response to the high-level voltage at the output terminal 1004.

[0109] Subsequently, a first clock signal CK1 can be supplied. When the first clock signal CK1 is supplied, transistors M2 and M8 can be turned on. When transistor M2 is turned on, the first input terminal 1001 and node NP3 can be electrically connected. At this time, the scan start signal FLM can be de-supplied to the first input terminal 1001, and therefore, node NP3 can be set to a high-level voltage. Therefore, a high-level voltage can be supplied to nodes NP3 and NP2, and therefore, transistors M6 and M7 can be turned off.

[0110] When transistor M8 is turned on, the voltage of power line VLPL can be supplied to node NP1, and therefore, transistors M4 and M5 can be turned on. When transistor M5 is turned on, the voltage of power line VHPL can be supplied to output terminal 1004. Thereafter, transistors M4 and M5 can remain turned on in response to the voltage charged in capacitor CP2, and therefore, output terminal 1004 can stably receive the voltage of power line VHPL.

[0111] Additionally, when the first clock signal CK3 is supplied, transistor M3 can be turned on. At this time, since transistor M4 is set to the on state, the voltage of power line VHPL can be supplied to nodes NP3 and NP2. Under these circumstances, transistors M6 and M7 can be stably kept off.

[0112] The first stage ST3 can receive the output signal (i.e., the scan signal) of the first stage ST1 to synchronize with the first clock signal CK1. In this case, the first stage ST3 can output the first scan signal SS3 with the on level to the first scan line SL3 in synchronization with the first clock signal CK1. Multiple first stages ST1, ST3, ... can sequentially output the scan signal with the on level to multiple first scan lines SL1, SL3, ... while repeating the above process.

[0113] Figure 4 and Figure 5 The descriptions of the multiple first-level ST1, ST3, ... shown can be applied in essentially the same way to the multiple second-level ST2, ST4, ... Figure 4 and Figure 5The levels and their driving methods are examples, and other conventional levels and driving methods can be used to configure the implementation of the present invention.

[0114] Figures 6 to 9 This is a diagram used to explain the implementation of the first frame time period FP1 and the second frame time period FP2 according to the present invention.

[0115] The display device 10 can operate in a first display mode including a plurality of first frame periods FP1, or in a second display mode including a plurality of second frame periods FP2. The second frame periods FP2 may be longer than the first frame periods FP1. In an embodiment, for example, the second frame period FP2 may be an integer multiple of the first frame periods FP1. In an embodiment, for example, the second frame period FP2 may be 2p times the first frame period FP1, where p may be an integer greater than 0. Figure 6 In one implementation, the second frame time period FP2 can be twice the first frame time period FP1.

[0116] The first display mode is suitable for displaying moving images by displaying input images (frames) at a high frequency. The second display mode is suitable for displaying still images by displaying input images at a low frequency. When a still image is detected while displaying a moving image, the display device 10 can switch from the first display mode to the second display mode. Conversely, when a moving image is detected while displaying a still image, the display device 10 can switch from the second display mode to the first display mode.

[0117] Reference Figure 6 For ease of description, the description will be based on the j-th data line DLj and the first pixel PX1j and the second pixel PX2j. In one embodiment, the first pixel PX1j may be connected to the j-th data line DLj and the first scan line SL1. The first pixel PX1j may belong to a first point. In another embodiment, the second pixel PX2j may be connected to the j-th data line DLj and the second scan line SL2. The second pixel PX2j may belong to a second point.

[0118] In each first frame period FP1, the data driver 12 can sequentially apply data voltages corresponding to scan lines to the data lines. In an embodiment, for example, the data driver 12 can sequentially apply multiple data voltages DT1, DT2, ..., DT(m-1), and DTm to the j-th data line DLj. Assuming the first frame period FP1 is 1 / 60 second, the first data voltage DT1 can be supplied to the first pixel PX1j at a frequency of 60 Hz. Therefore, the first pixel PX1j can emit light with the highest brightness at the time the first data voltage DT1 is applied, and then the brightness may gradually decrease due to leakage current. (Refer to...) Figure 6The waveform of the brightness of the first pixel PX1j corresponding to multiple first frame time periods FP1 is shown as an example.

[0119] Each second frame period FP2 may include a first subframe period SFP1 and a second subframe period SFP2. The lengths of the first subframe period SFP1 and the second subframe period SFP2 may be the same. In an implementation, assuming that the second frame period FP2 is 1 / 30 of a second, then for example, each of the first subframe period SFP1 and the second subframe period SFP2 may be 1 / 60 of a second.

[0120] In each first subframe period SFP1, the data driver 12 may sequentially apply a data voltage corresponding to a first point to the data line. In an embodiment, for example, the data driver 12 may sequentially apply multiple data voltages DT1, DT3, ..., and DT(m-1) to the j-th data line DLj. In each second subframe period SFP2, the data driver 12 may sequentially apply a data voltage corresponding to a second point to the data line. In an embodiment, for example, the data driver 12 may sequentially apply multiple data voltages DT2, DT4, ..., and DTm to the j-th data line DLj.

[0121] Therefore, the first data voltage DT1 can be supplied to the first pixel PX1j at a frequency of 30Hz. Thus, the first pixel PX1j can emit light with the highest brightness at the point when the first data voltage DT1 is applied, and then the brightness may gradually decrease due to leakage current. (Refer to...) Figure 6 The waveform of the brightness of the first pixel PX1j corresponding to multiple second frame time periods FP2 is shown as an example. Furthermore, a second data voltage DT2 can be applied to the second pixel PX2j at a frequency of 30Hz. Therefore, the second pixel PX2j may emit light with the highest brightness at the time the second data voltage DT2 is applied, and then the brightness may gradually decrease due to leakage current. (Refer to...) Figure 6 The waveform of the brightness of the second pixel PX2j corresponding to multiple second frame time periods FP2 is shown as an example.

[0122] In this case, since the first pixel PX1j and the second pixel PX2j are arranged to be adjacent to each other, the first data voltage DT1 and the second data voltage DT2 can be substantially the same or similar in a typical input image.

[0123] Because the time points when the first pixel PX1j has the highest brightness and the time points when the second pixel PX2j has the highest brightness are arranged alternately, the user can recognize the frequency of the waveform AVG of the average brightness of the first pixel PX1j and the second pixel PX2j as 60Hz. Therefore, even when switching between the first display mode and the second display mode, visual flickering caused by the difference in brightness waveforms can be prevented.

[0124] Reference Figure 7 The control signals in the first frame time period FP1 are shown as an example.

[0125] During the first frame period FP1, the timing controller 11 can apply the first clock signal CK1 and the first clock signal CK3 at the conduction level to the first clock line CKL1 and the first clock line CKL3, and can apply the second clock signal CK2 and the second clock signal CK4 at the conduction level to the second clock line CKL2 and the second clock line CKL4. The first clock signal CK1 and the first clock signal CK3, as well as the second clock signal CK2 and the second clock signal CK4, may have different phases. In an embodiment, for example, the first clock signal CK1, the second clock signal CK2, the first clock signal CK3, and the second clock signal CK4 at the conduction level can be supplied sequentially in the order of first clock line CKL1, second clock line CKL2, first clock line CKL3, and second clock line CKL4. In an embodiment, for example, the cycle of each of the first clock signal CK1, the second clock signal CK2, the first clock signal CK3, and the second clock signal CK4 at the conduction level may be four horizontal periods 4H.

[0126] Additionally, the timing controller 11 can apply a scan start signal FLM at the on level to the scan start line FLML. In this case, the length of the scan start signal FLM at the on level can be set to overlap with the first clock signal CK1 and the second clock signal CK2 at the on level. In an embodiment, for example, the length of the scan start signal FLM at the on level can be two horizontal periods 2H.

[0127] During the first frame period FP1, the scan driver 13 can alternately apply multiple scan signals SS1, SS2, SS3, SS4, ... at the on level to multiple first scan lines SL1, SL3, ... and multiple second scan lines SL2, SL4, ...

[0128] Reference Figure 5The driving method can generate a first scan signal SS1 at the conduction level in response to a first clock signal CK3 at the conduction level. Additionally, a second scan signal SS2 at the conduction level can be generated in response to a second clock signal CK4 at the conduction level. Similarly, a first scan signal SS3 at the conduction level can be generated in response to a first clock signal CK1 at the conduction level. Additionally, a second scan signal SS4 at the conduction level can be generated in response to a second clock signal CK2 at the conduction level.

[0129] The data driver 12 can synchronously supply data voltages with each of a plurality of scan signals SS1, SS2, SS3, SS4, ... at an on-level. In an embodiment, for example, the data driver 12 can supply data voltages for the current level cycle in response to a grayscale latched by a logic high-level data enable signal DE in the previous level cycle.

[0130] Reference Figure 8 The control signals in the first subframe period SFP1 within the second frame period FP2 are shown as an example.

[0131] During the first subframe period SFP1, the timing controller 11 can apply the on-level first clock signals CK1 and CK3 to the first clock lines CKL1 and CKL3, and maintain the off-level second clock signals CK2 and CK4 in the second clock lines CKL2 and CKL4. The periods for which the on-level first clock signals CK1 and CK3 are applied to the first clock lines CKL1 and CKL3 during the first frame period FP1 and the first subframe period SFP1 can be the same. In an embodiment, for example, the period of each of the on-level first clock signals CK1 and CK3 can be four horizontal periods 4H.

[0132] Furthermore, the timing controller 11 can apply a scan start signal FLM at the on level to the scan start line FLML. In this case, the length of the scan start signal FLM at the on level can be set to overlap with the first clock signal CK1 at the on level. In an embodiment, the length of the scan start signal FLM at the on level can be two horizontal periods 2H as shown, but, for example, it can be set to one horizontal period 1H.

[0133] During the first subframe period SFP1, the scan driver 13 can apply multiple first scan signals SS1, SS3, ... at the on level to multiple first scan lines SL1, SL3, ... and maintain multiple second scan signals SS2, SS4, ... at the off level in multiple second scan lines SL2, SL4, ... . The period for which the multiple first scan signals SS1, SS3, ... at the on level are applied to the multiple first scan lines SL1, SL3, ... during the first frame period FP1 and the first subframe period SFP1 can be the same.

[0134] The data driver 12 can synchronously supply data voltage with each of the plurality of first scan signals SS1, SS3, ... at the on level. In this case, since it is not necessary to synchronously supply data voltage with the plurality of second scan signals SS2, SS4, ..., the period of the data enable signal DE at the on level in the first subframe segment SFP1 can be longer than the period of the data enable signal DE at the on level in the first frame segment FP1. Therefore, since the period at which the data driver 12 changes the data voltage is increased, there is an advantage of reduced dynamic power of the data driver 12.

[0135] Reference Figure 9 The control signals in the second subframe period SFP2 within the second frame period FP2 are shown as an example.

[0136] During the second subframe period SFP2, the on-level second clock signal CK2 and the second clock signal CK4 can be applied to the second clock lines CKL2 and CKL4, and the off-level first clock signals CK1 and CK3 can be maintained in the first clock lines CKL1 and CKL3. During the first frame period FP1 and the second subframe period SFP2, the periods for which the on-level second clock signal CK2 and the second clock signal CK4 are applied to the second clock lines CKL2 and CKL4 can be the same. In an embodiment, for example, the period of each of the on-level second clock signal CK2 and the second clock signal CK4 can be four horizontal periods 4H.

[0137] Furthermore, the timing controller 11 can apply a scan start signal FLM at the on level to the scan start line FLML. In this case, the length of the scan start signal FLM at the on level can be set to overlap with the second clock signal CK2 at the on level. In an embodiment, the length of the scan start signal FLM at the on level can be two horizontal periods 2H as shown, but, for example, it can be set to one horizontal period 1H.

[0138] During the second subframe period SFP2, the scan driver 13 can apply multiple second scan signals SS2, SS4, ... at the on level to multiple second scan lines SL2, SL4, ... and maintain multiple first scan signals SS1, SS3, ... at the off level in multiple first scan lines SL1, SL3, ... . The periods for applying the multiple second scan signals SS2, SS4, ... at the on level to the multiple second scan lines SL2, SL4, ... during the first frame period FP1 and the second subframe period SFP2 can be the same.

[0139] The data driver 12 can synchronously supply data voltage with each of the multiple second scan signals SS2, SS4, ... at the on level. In this case, since it is not necessary to supply data voltage synchronously with the multiple first scan signals SS1, SS3, ..., the period of the data enable signal DE at the on level in the second subframe period SFP2 can be longer than the period of the data enable signal DE at the on level in the first frame period FP1. Therefore, since the period at which the data driver 12 changes the data voltage is increased, there is an advantage of reduced dynamic power of the data driver 12.

[0140] Figures 10 to 13 This is a diagram used to explain the implementation of the first frame time period FP1 and the second frame time period FP2' according to the present invention.

[0141] exist Figure 10 In the implementation method, the brightness waveform and driving method of the first pixel PX1j in the first frame time period FP1 can be compared with... Figure 6 Those are the same. Additionally, in Figure 10 In the implementation, the individual luminance waveforms and the average luminance waveform AVG of the first pixel PX1j and the second pixel PX2j in the second frame time period FP2' can be substantially the same as... Figure 6 Those are the same.

[0142] However, since each of the first subframe period SFP1' and the second subframe period SFP2' includes a data blank period BPC, Figure 10 The driving method in the second frame period FP2' of the implementation may differ from that of the previous implementation. Figure 6 The implementation method is as follows. In this implementation, for example, the length of each of the first subframe period SFP1' and the second subframe period SFP2' may be the same as the length of each of the first subframe period SFP1 and the second subframe period SFP2. Figure 10 In this implementation, the data driver 12 can be compared to Figure 6The data driver 12 supplies data voltage during short time periods. The data blank period (BPC) can be the remaining time period after the data driver 12 supplies data voltage in each of the first subframe period (SFP1') and the second subframe period (SFP2'). During the data blank period (BPC), all or at least a portion of the data driver 12 (e.g., gamma amplifier, digital logic circuitry) can be de-energized to reduce power consumption.

[0143] Reference Figure 11 The control signals in the first subframe segment SFP1' within the second frame segment FP2' are shown as an example. Specifically, Figure 11 The control signals in the first subframe time SFP1', excluding the data blank time BPC, are shown.

[0144] During the first subframe period SFP1', the timing controller 11 may apply the first clock signals CK1 and CK3 at the on level to the first clock lines CKL1 and CKL3, and maintain the second clock signals CK2 and CK4 at the off level in the second clock lines CKL2 and CKL4. In the illustrated embodiment, the period during which the first clock signals CK1 and CK3 at the on level are applied to the first clock lines CKL1 and CKL3 in the first subframe period SFP1' may be shorter than the period during which the first clock signals CK1 and CK3 at the on level are applied in the first frame period FP1. In the embodiment, for example, the period of each of the first clock signals CK1 and CK3 at the on level may be two horizontal periods 2H.

[0145] The timing controller 11 can apply a pass-through level scan start signal FLM to the scan start line FLML. In this case, the length of the pass-through level scan start signal FLM can be set to overlap with the pass-through level first clock signal CK1. In an embodiment, for example, the length of the pass-through level scan start signal FLM can be set to one horizontal period 1H.

[0146] During the first subframe period SFP1', the scan driver 13 can apply multiple first scan signals SS1, SS3, ... at the on level to multiple first scan lines SL1, SL3, ... and maintain multiple second scan signals SS2, SS4, ... at the off level in multiple second scan lines SL2, SL4, ... The period during which the multiple first scan signals SS1, SS3, ... at the on level are applied to the multiple first scan lines SL1, SL3, ... during the first subframe period SFP1' can be shorter than the period during which the multiple first scan signals SS1, SS3, ... at the on level are applied in the first frame period FP1.

[0147] The data driver 12 can supply data voltage synchronously with each of a plurality of first scan signals SS1, SS3, ... at the on level.

[0148] Reference Figure 12 The control signals in the data blank period BPC within the second frame time period FP2' are shown as an example. In the data blank period BPC, there are multiple clock signals CK1, CK2, CK3 and CK4 that can be kept at the off level, multiple scan signals SS1, SS2, SS3, SS4, ... at the off level, and a scan start signal FLM at the off level.

[0149] As described above, during the data blank period (BPC), all or at least a portion of the data driver 12 (e.g., gamma amplifier, digital logic circuitry) can be powered off to reduce power consumption.

[0150] Reference Figure 13 The control signals in the second subframe period SFP2' within the second frame period FP2' are shown as an example. Specifically, Figure 13 The control signals in the second subframe period SFP2', excluding the data blank period BPC, are shown.

[0151] During the second subframe period SFP2', the on-level second clock signal CK2 and the second clock signal CK4 can be applied to the second clock lines CKL2 and CKL4, while the off-level first clock signals CK1 and CK3 can be maintained in the first clock lines CKL1 and CKL3. The period for which the on-level second clock signals CK2 and CK4 are applied to the second clock lines CKL2 and CKL4 during the second subframe period SFP2' can be shorter than the period for which the on-level second clock signals CK2 and CK4 are applied during the first frame period FP1. In an embodiment, for example, the period of each of the on-level second clock signals CK2 and CK4 can be two horizontal periods 2H.

[0152] Furthermore, the timing controller 11 can apply a scan start signal FLM at an on-level to the scan start line FLML. In this case, the length of the scan start signal FLM at an on-level can be set to overlap with the second clock signal CK2 at an on-level. In an embodiment, for example, the length of the scan start signal FLM at an on-level can be set to one horizontal period 1H.

[0153] During the second subframe period SFP2', the scan driver 13 can apply multiple second scan signals SS2, SS4, ... at the on level to multiple second scan lines SL2, SL4, ... and maintain multiple first scan signals SS1, SS3, ... at the off level in multiple first scan lines SL1, SL3, ... The period during which the multiple second scan signals SS2, SS4, ... at the on level are applied to the multiple second scan lines SL2, SL4, ... during the second subframe period SFP2' can be shorter than the period during which the multiple second scan signals SS2, SS4, ... at the on level are applied in the first frame period FP1.

[0154] The data driver 12 can supply data voltage synchronously with each of the plurality of second scan signals SS2, SS4, ... at the on level.

[0155] Figure 14 This is a diagram illustrating an embodiment of the first frame time period FP1 and the second frame time period FP2 in another embodiment of the present invention.

[0156] exist Figure 14 In the implementation method, the brightness waveform and driving method of the first pixel PX1j in the first frame time period FP1 are the same as those of the first pixel PX1j. Figure 6 Those are the same.

[0157] Figure 14The driving method in the second frame period FP2 can be similar to Figure 10 The driving method differs from the previous one in that each second frame period FP2" includes four sub-frame periods SFP1", SFP2", SFP3", and SFP4". In one implementation, for example, the second frame period FP2" may be four times the length of the first frame period FP1 and may be 1 / 15 of a second. In another implementation, for example, each of the multiple sub-frame periods SFP1", SFP2", SFP3", and SFP4" may be 1 / 60 of a second.

[0158] exist Figure 10 In the implementation method, two points form a group, but in Figure 14 In this implementation, the difference lies in that four adjacent points form a group. The first pixel PX1j of the first point can receive the data voltage SF1D and emit light with the highest brightness in the first subframe period SFP1”. The second pixel PX2j of the second point can receive the data voltage SF2D and emit light with the highest brightness in the second subframe period SFP2”. The third pixel PX3j of the third point can receive the data voltage SF3D and emit light with the highest brightness in the third subframe period SFP3”. The fourth pixel PX4j of the fourth point can receive the data voltage SF4D and emit light with the highest brightness in the fourth subframe period SFP4”. Therefore, even when each of the first pixel PX1j, the second pixel PX2j, the third pixel PX3j, and the fourth pixel PX4j emits light at a frequency of 15Hz, the frequency of the waveform AVG of the average brightness of the group of the first pixel PX1j, the second pixel PX2j, the third pixel PX3j, and the fourth pixel PX4j can be identified as 60Hz.

[0159] Reference Figure 10 and Figure 14 The number of subframe time periods included in the second frame time period FP2' and FP2" can be set differently.

[0160] Figure 15 This is a diagram used to explain an embodiment of the scan driver 13” according to the present invention.

[0161] Figure 15 The scan driver 13” can be obtained from Figure 3 The scan driver 13 is partially modified to apply... Figure 14 The driving method. The internal circuit configuration of the scan driver 13” and the multiple stages ST1 to ST4 of the scan driver 13 can be the same.

[0162] However, with Figure 3 The scan driver 13 is divided into two different groups (odd-numbered groups and even-numbered groups). Figure 15The scan driver 13” can be divided into four levels. In an embodiment, for example, the first level group may include a plurality of (4q+1) levels ST1, ..., and each of the plurality of (4q+1) levels ST1, ... may be alternately connected to clock line CKL1 and clock line CKL5, where q may be a positive integer. The second level group may include a plurality of (4q+2) levels ST2, ..., and each of the plurality of (4q+2) levels ST2, ... may be alternately connected to clock line CKL2 and clock line CKL6. The third level group may include a plurality of (4q+3) levels ST3, ..., and each of the plurality of (4q+3) levels ST3, ... may be alternately connected to clock line CKL3 and clock line CKL7. The fourth level group may include a plurality of (4q+4) levels ST4, ..., and each of the plurality of (4q+4) levels ST4, ... may be alternately connected to clock line CKL4 and clock line CKL8.

[0163] The first input terminals 1001 of the first stage ST1, ST2, ST3 and ST4 of each stage group can be connected to the scan start line FLML. Since the driving method of the scan driver 13” is similar to that of the scan driver 14, repeated descriptions will be omitted.

[0164] Figure 16 This is a diagram used to explain an embodiment of the pixel unit 14r according to the present invention.

[0165] Reference Figure 16 A pixel unit 14r with an RGB stripe structure is shown as an example.

[0166] Each of the plurality of points DT11, DT12, DT13, DT14, DT21, DT22, DT23, DT24, DT31, DT32, DT33, DT34, DT41, DT42, DT43, and DT44 may include pixels of a first color, pixels of a second color, and pixels of a third color arranged in the first direction DR1. In this case, the first color, the second color, and the third color may be different from each other. In an implementation, for example, the first color may be red, the second color may be green, and the third color may be blue.

[0167] Here, the color of a pixel can mean that it is caused by… Figure 2 The color of the light emitted by the light-emitting diode (LD). Furthermore, the position of the pixel is described based on the location of the surface from which the light emitted by the LD originates.

[0168] Multiple data lines DL1, DL2, DL3, DL4, DL5, DL6, DL7, DL8, DL9, DL10, DL11, and DL12 can each be connected to a pixel of a single color. In an embodiment, multiple data lines DL1, DL4, DL7, and DL10 can be connected to red pixels PXi1 (e.g., PX11, PX21, PX31, PX41), red pixels PXi4 (e.g., PX14, PX24, PX34, PX44), red pixels PXi7 (e.g., PX17, PX27, PX37, PX47), and red pixels PXi10 (e.g., PX110, PX210, PX310, and PX410), respectively. For example, multiple data lines DL2, DL5, DL8, and DL11 can be connected to green pixels PXi2 (e.g., PX12, PX22, PX32, PX42), green pixels PXi5 (e.g., PX15, PX25, PX35, PX45), green pixels PXi8 (e.g., PX18, PX28, PX38, PX48), and green pixels PXi11 (e.g., PX111, PX211, PX311, and PX411), respectively. In addition, for example, multiple data lines DL3, DL6, DL9 and DL12 can be connected to blue pixel PXi3 (e.g., PX13, PX23, PX33, PX43), blue pixel PXi6 (e.g., PX16, PX26, PX36, PX46), blue pixel PXi9 (e.g., PX19, PX29, PX39, PX49), and blue pixel PXi12 (e.g., PX112, PX212, PX312 and PX412), respectively.

[0169] Multiple points DT11 to DT14 and DT31 to DT34 connected to the first scan lines SL1 and SL3 may be alternately arranged on the second direction DR2 with multiple points DT21 to DT24 and DT41 to DT44 connected to the second scan lines SL2 and SL4. However, in Figure 16 In this embodiment, the points connected to the first scan line SL1 and the first scan line SL3 and the points connected to the second scan line SL2 and the second scan line SL4 may be arranged on the first direction DR1 without alternation. The first direction DR1 and the second direction DR2 may be orthogonal to each other.

[0170] Figure 17 This is a diagram used to explain an embodiment of the pixel unit 14 according to the present invention.

[0171] Reference Figure 17 This illustrates a pixel unit 14 with an RGB stripe structure in another embodiment of the invention. Due to the structure of multiple points DT11 to DT44 and multiple data lines DL1 to DL12... Figure 16Those are the same, so repeated descriptions will be omitted.

[0172] In the illustrated embodiment, a plurality of first points DT11, DT22, DT13, DT24, DT31, DT42, DT33, and DT44 can be connected to first scan lines SL1 and SL3. A plurality of second points DT21, DT12, DT23, DT14, DT41, DT32, DT43, and DT34 can be connected to second scan lines SL2 and SL4. In this case, the plurality of second points DT21, DT12, DT23, DT14, DT41, DT32, DT43, and DT34 can be alternately arranged on the first direction DR1 and the second direction DR2 with the plurality of first points DT11, DT22, DT13, DT24, DT31, DT42, DT33, and DT44. In an implementation, for example, when a plurality of first points DT11, DT22, DT13, DT24, DT31, DT42, DT33, and DT44 are arranged to correspond to squares of one color (e.g., white squares) on the chessboard, a plurality of second points DT21, DT12, DT23, DT14, DT41, DT32, DT43, and DT34 may be arranged to correspond to squares of another color (e.g., black squares) on the chessboard.

[0173] When using Figure 17 When pixel unit 14 is used, in each of the first subframe period SFP1 and the second subframe period SFP2 of the second display mode, the white and black portions of the horizontal stripe pattern can be displayed in a balanced manner to prevent flickering. In an embodiment, for example, the horizontal stripe pattern can be a pattern in which pixels PX11 to PX112 and PX31 to PX312 in odd-numbered rows are displayed as white and pixels PX21 to PX212 and PX41 to PX412 in even-numbered rows are displayed as black.

[0174] Figure 18 This is a diagram used to explain an embodiment of pixel unit 14' in another embodiment of the present invention.

[0175] Reference Figure 18 A pixel unit 14' with a pentile structure is shown as an example.

[0176] In the illustrated embodiment, a plurality of first points DT11', DT22', DT13', DT31', DT42', and DT33' can be connected to first scan lines SL1 and SL3. A plurality of second points DT21', DT12', DT23', DT41', DT32', and DT43' can be connected to second scan lines SL2 and SL4. In this case, the plurality of second points DT21', DT12', DT23', DT41', DT32', and DT43' can be alternately arranged on the first direction DR1 and the second direction DR2 with the plurality of first points DT11', DT22', DT13', DT31', DT42', and DT33'. In an implementation, for example, when multiple first points DT11', DT22', DT13', DT31', DT42', and DT33' are arranged to correspond to the white squares on the chessboard, multiple second points DT21', DT12', DT23', DT41', DT32', and DT43' can be arranged to correspond to the black squares on the chessboard.

[0177] One of the multiple first points DT11', DT22', DT13', DT31', DT42' and DT33', first point DT11' may include a first color pixel PX11, a second color pixel PX12, a third color pixel PX13 and a second color pixel PX14 arranged on the first direction DR1.

[0178] The second point DT21', arranged on the second direction DR2 starting from the first point DT11', may include a third color pixel PX21, a second color pixel PX22, a first color pixel PX23, and a second color pixel PX24 arranged on the first direction DR1.

[0179] The second point DT12', arranged on the first direction DR1 starting from the first point DT11', may include a first color pixel PX15, a second color pixel PX16, a third color pixel PX17, and a second color pixel PX18 arranged on the first direction DR1.

[0180] Another first point DT22' among the multiple first points DT11', DT22', DT13', DT31', DT42' and DT33' may include a third color pixel PX25, a second color pixel PX26, a first color pixel PX27, and a second color pixel PX28 arranged on the first direction DR1.

[0181] The second point DT32', arranged on the second direction DR2 starting from the first point DT22', may include a first color pixel PX35, a second color pixel PX36, a third color pixel PX37, and a second color pixel PX38 arranged on the first direction DR1.

[0182] The second point DT23', arranged on the first direction DR1 starting from the first point DT22', may include a third color pixel PX29, a second color pixel PX210, a first color pixel PX211, and a second color pixel PX212 arranged on the first direction DR1.

[0183] Each of the plurality of first data lines DL1, DL3, DL5, DL7, DL9, and DL11 among the plurality of data lines DL1 to DL12 may be alternately connected to pixels of a first color and a third color. Each of the plurality of second data lines DL2, DL4, DL6, DL8, DL10, and DL12 among the plurality of data lines DL1 to DL12 may be connected to pixels of a second color. The plurality of first data lines DL1, DL3, DL5, DL7, DL9, and DL11 may be arranged alternately with the plurality of second data lines DL2, DL4, DL6, DL8, DL10, and DL12 in a first direction DR1. The plurality of data lines DL1 to DL12 may extend substantially in a second direction DR2.

[0184] Even when using Figure 18 When the pixel unit is 14', it can also obtain the same as Figure 17 The same effect. That is, when using Figure 18 When the pixel unit 14' is in the second display mode, in each of the first subframe period SFP1 and the second subframe period SFP2, the white and black portions of the horizontal stripe pattern can be displayed in a balanced manner, thereby preventing flickering.

[0185] The display device according to the present invention can prevent visual recognition from flickering when the display frequency switches from a high frequency to a low frequency.

[0186] The display device according to the invention can prevent flickering when displaying a specific pattern during low-frequency driving.

[0187] The accompanying drawings and the detailed description of the invention described above are merely illustrative. It will be understood that the invention has been disclosed for illustrative purposes only and is not intended to limit the meaning or scope of the invention as set forth in the claims. Therefore, those skilled in the art will appreciate that various modifications and equivalent embodiments are possible without departing from the scope of the invention. Thus, the true scope of the invention should be determined by the technical concept of the appended claims.

Claims

1. A display device, comprising: Firstly, the first point is connected to the first scan line but not to the second scan line; Secondly, the second point is connected to the second scan line but not to the first scan line, and is alternately arranged with the first point in a first direction and in a second direction different from the first direction; A scan driver, the scan driver comprising a plurality of first stages respectively connected to a plurality of first scan lines and a plurality of second stages respectively connected to a plurality of second scan lines; as well as The data driver is connected to the first point and the second point via a data cable. The plurality of first stages are connected to the first clock line. The plurality of second-stage connections are connected to a second clock line that is different from the first clock line. Wherein, apart from the first starting level among the plurality of first levels, each of the plurality of first levels is connected to the corresponding first scan line of the corresponding previous first level among the plurality of first scan lines of the plurality of first levels, and In this context, apart from the second starting level among the plurality of second levels, the second levels among the plurality of second levels are respectively connected to the corresponding second scan lines of the corresponding previous second level among the plurality of second scan lines of the plurality of second levels.

2. The display device according to claim 1, wherein Each of the first point and the second point includes pixels of a first color, pixels of a second color, and pixels of a third color arranged in the first direction, and The first color, the second color, and the third color are different from each other.

3. The display device of claim 2, wherein, Each of the multiple data lines is connected to a pixel of a single color.

4. The display device according to claim 1, wherein One of the plurality of first points includes pixels of a first color, pixels of a second color, pixels of a third color, and pixels of the second color arranged in the first direction. Wherein, one of the plurality of second points arranged in the second direction from one of the plurality of first points includes pixels of the third color, pixels of the second color, pixels of the first color, and pixels of the second color arranged in the first direction, and The first color, the second color, and the third color are different from each other.

5. The display device of claim 4, wherein, One of the plurality of data lines is alternately connected to the pixel of the first color and the pixel of the third color, and In this configuration, another data line among the plurality of data lines is connected to the pixel of the second color.

6. The display device according to claim 1, wherein The first starting stage of the plurality of first stages and the second starting stage of the plurality of second stages are connected to the same scan start line.

7. The display device of claim 6, wherein, During each first frame period, the scan driver alternately applies a pass-through level scan signal to the first scan line and the second scan line.

8. The display device of claim 7, wherein, During the first subframe period within each second frame period, the scan driver applies the scan signal at an on level to the first scan line and maintains the scan signal at an off level in the second scan line. During the second subframe period within each second frame period, the scan driver applies the scan signal at an on level to the second scan line and maintains the scan signal at an off level in the first scan line.

9. The display device of claim 8, wherein, The second frame period is longer than the first frame period.

10. The display device of claim 8, wherein, During the first frame period, a first clock signal with an on level is applied to the first clock line, and a second clock signal with an on level is applied to the second clock line. The first clock signal and the second clock signal have different phases. During the first subframe period, a first clock signal at an on level is applied to the first clock line, and a second clock signal at an off level is maintained on the second clock line. During the second subframe period, the second clock signal at the on level is applied to the second clock line, and the first clock signal at the off level is maintained in the first clock line.

Images