external chip driver system

Abstract

An external chip driving system includes a decision circuit, multiple first adjustable enhancement circuits, multiple second adjustable enhancement circuits, a pull-up circuit, and a pull-down circuit. The decision circuit outputs first and second decision signals based on a frequency signal and an input signal. In response to the first and second decision signals and one of the first selection signals, each of the first adjustable enhancement circuits generates a first control signal. In response to the first and second decision signals and one of the second selection signals, each of the second adjustable enhancement circuits generates a second control signal. Because the signal amplitude attenuates and becomes distorted during high-speed data transmission, in this disclosure, the first driver in the pull-up circuit is activated in response to the corresponding first control signal, and the second driver in the pull-down circuit is activated in response to the corresponding second control signal, thereby increasing the slew rate of the output signal and reducing the distortion of the output data.

Description

Technical Field

[0001] This case relates to an external chip driving system and a signal compensation method, and more particularly to an external chip driving system and a signal compensation method for improving signal distortion. Background Technology

[0002] With the advancement of modern technology, memory operating speeds have become increasingly faster. During high-speed data transmission, signal amplitude attenuation occurs, causing signal distortion.

[0003] Therefore, how to improve signal distortion in high-speed data transmission is an important issue in this field. Summary of the Invention

[0004] This disclosure provides an external chip driving system comprising a decision circuit, a plurality of first adjustable enhancement circuits, and pull-up circuits. The decision circuit outputs a first decision signal and a second decision signal based on a frequency and input data. The first adjustable enhancement circuits are coupled to the decision circuit. Each of the first adjustable enhancement circuits generates one of a plurality of first control signals in response to the first decision signal, the second decision signal, and one of the plurality of first selection signals. The pull-up circuits include a plurality of first drivers. Each of the first drivers is coupled to a corresponding one of the plurality of first adjustable enhancement circuits, and each of the first drivers is enabled in response to a corresponding one of the plurality of first control signals.

[0005] The chip-side driving system disclosed in this document includes a decision circuit that generates a pulse with a high level as a first decision signal when the input data is converted from a first level to a second level; and a decision circuit that generates another pulse with a low level as a second decision signal when the input data is converted from a second level to a first level.

[0006] In the chip external driving system disclosed in this document, when both the first decision signal and the second decision signal are at a low level, the first adjustable enhancement circuits set all the first control signals to a high system voltage, thereby turning off all the first drivers; and when both the first decision signal and the second decision signal are at a high level, the first adjustable enhancement circuits set all the first control signals to a low system voltage, thereby turning on all the first drivers.

[0007] The chip external driving system disclosed in this document, wherein when the first decision signal is at a low level and the second decision signal is at a high level, the first adjustable enhancement circuits respectively provide the first selection signals as the first control signals, causing a portion of the first drivers to be turned off and another portion of the first drivers to be turned on.

[0008] This disclosure discloses an external-chip driving system, wherein each of the first adjustable enhancement circuits includes a first multiplexer, a second multiplexer, and a third multiplexer. The first multiplexer receives a first decision signal, a system low voltage, and an enable signal. When the enable signal is at a high level, the first multiplexer outputs the first decision signal; when the enable signal is at a low level, the first multiplexer outputs the system low voltage. The second multiplexer receives a second decision signal, a system high voltage, and the enable signal. When the enable signal is at a high level, the second multiplexer outputs the second decision signal; when the enable signal is at a low level, the second multiplexer outputs the system high voltage. The third multiplexer is coupled to the first and second multiplexers. The third multiplexer receives the system low voltage, the system high voltage, one of the first selection signals, a third decision signal from the first multiplexer, and a fourth decision signal from the second multiplexer; and the third multiplexer outputs one of the first control signals in response to the third and fourth decision signals.

[0009] The chip external driving system disclosed in this document includes a third multiplexer that outputs a system low voltage as one of the first control signals when the third decision signal and the fourth decision signal are at a high level; a third multiplexer that outputs a system high voltage as one of the first control signals when the third decision signal and the fourth decision signal are at a low level; and a third multiplexer that outputs one of the first selection signals when the third decision signal is at a low level and the fourth decision signal is at a high level.

[0010] The chip-side driving system disclosed in this document, wherein the first drivers are P-type metal-oxide-semiconductor field-effect transistors.

[0011] Another embodiment of this disclosure provides an external chip driving system including a decision circuit, a plurality of second adjustable enhancement circuits, and a pull-down circuit. The decision circuit outputs a first decision signal and a second decision signal based on a frequency and input data. The first adjustable enhancement circuit is coupled to the decision circuit. Each of the second adjustable enhancement circuits generates one of a plurality of second control signals in response to the first decision signal, the second decision signal, and one of a plurality of second selection signals. The pull-down circuit includes a plurality of second drivers. Each of the second drivers is coupled to a corresponding one of the plurality of second adjustable enhancement circuits, and each of the second drivers is enabled in response to a corresponding one of the plurality of second control signals.

[0012] The chip external driving system disclosed in this document includes a decision circuit that generates a pulse with a high level as a first decision signal when the input data is converted from a first level to a second level; and a decision circuit that generates a pulse with a low level as a second decision signal when the input data is converted from a second level to a first level.

[0013] The chip external driving system disclosed in this document includes a second adjustable enhancement circuit that sets the second control signals to a high system voltage when both the first decision signal and the second decision signal are at a low level, thereby turning on all the second drivers; and a second adjustable enhancement circuit that sets the second control signals to a low system voltage when both the first decision signal and the second decision signal are at a high level, thereby turning off all the second drivers.

[0014] The chip external driving system disclosed in this document, wherein when the first decision signal is at a low level and the second decision signal is at a high level, the second adjustable enhancement circuit provides the second selection signals as the second control signals, causing a portion of the second drivers to be turned off and another portion of the second drivers to be turned on.

[0015] The chip-side driving system disclosed in this document includes a first multiplexer, a second multiplexer, and a third multiplexer, each of the second adjustable enhancement circuits. The first multiplexer receives a first decision signal, a system low voltage, and an enable signal, and outputs the first decision signal when the enable signal is high, and outputs the system low voltage when the enable signal is low. The second multiplexer receives a second decision signal, a system high voltage, and an enable signal, and outputs the second decision signal when the enable signal is high, and outputs the system high voltage when the enable signal is low. The third multiplexer is coupled to the first and second multiplexers, and receives the system low voltage, the system high voltage, one of the second selection signals, a third decision signal from the first multiplexer, and a fourth decision signal from the second multiplexer, and outputs one of the second control signals in response to the third and fourth decision signals.

[0016] The chip-side driving system disclosed in this document includes a third multiplexer that outputs a system low voltage as a second control signal when the third and fourth decision signals are at a high level. When the third and fourth decision signals are at a low level, the third multiplexer outputs a system high voltage as the second control signal; and when the third decision signal is at a low level and the fourth decision signal is at a high level, the third multiplexer outputs one of the second selection signals.

[0017] The chip-side driving system disclosed in this document, wherein the second drivers are N-type metal-oxide-semiconductor field-effect transistors.

[0018] Another aspect of this disclosure provides a signal compensation method. The signal compensation method includes: generating a pulse with a high level as a first decision signal when input data is converted from a first level to a second level; generating a pulse with a low level as a second decision signal when the input data is converted from the second level to the first level; generating a plurality of first control signals in response to the first decision signal, the second decision signal, and a plurality of first selection signals; generating a plurality of second control signals in response to the first decision signal, the second decision signal, and the plurality of second selection signals; activating a plurality of first drivers in response to the first control signals; and activating a plurality of second drivers in response to the second control signals.

[0019] This disclosure further provides an external chip driving system. The external chip driving system includes a decision circuit, a first adjustable enhancement circuit, a second adjustable enhancement circuit, a pull-up circuit, and a pull-down circuit. The decision circuit outputs a first decision signal and a second decision signal based on frequency and input data. The first adjustable enhancement circuit is coupled to the decision circuit, and generates a first control signal in response to the first decision signal, the second decision signal, and a first selection signal. The second adjustable enhancement circuit is coupled to the decision circuit, and generates a second control signal in response to the first decision signal, the second decision signal, and a second selection signal. The pull-up circuit is enabled in response to the first control signal. The pull-down circuit is enabled in response to the second control signal.

[0020] In summary, in the various embodiments disclosed in this document, the number of control signals switching to the enable level is controlled by the enable signal and the selection signal, and the timing of the control signals at the enable level is controlled by the decision signal. The timing and number of drivers enabled by the pull-up and pull-down circuits are determined by the corresponding control signals. Therefore, the slew rate of the output signal generated by the external driver system during rise and fall can be controlled to meet actual requirements. Attached Figure Description

[0021] To make the above and other objects, features, advantages and embodiments of this disclosure more apparent and understandable, the accompanying drawings are described below:

[0022] Figure 1 This is a schematic diagram of an external chip driving system according to some embodiments of the present disclosure.

[0023] Figure 2 This is a schematic diagram of a pull-up drive circuit and a pull-down drive circuit according to some embodiments of this disclosure.

[0024] Figures 3A to 3DThis is a schematic diagram of a P-type driver according to some embodiments of the present disclosure.

[0025] Figures 4A to 4D This is a schematic diagram of an N-type driver according to some embodiments of the present disclosure.

[0026] Figure 5 This is a schematic diagram of a first adjustable enhancement circuit and a second adjustable enhancement circuit according to some embodiments of the present disclosure.

[0027] Figure 6 This is a schematic diagram of an adjustable enhancement circuit according to some embodiments of the present disclosure.

[0028] Figure 7 This is a schematic diagram of an external chip driving system according to some embodiments of the present disclosure. Detailed Implementation

[0029] The following examples are described in detail with reference to the accompanying drawings. However, the provided examples are not intended to limit the scope of this disclosure, and the description of the structural operation is not intended to limit the order of execution. Any structure resulting from the recombination of elements and producing a device with equivalent functionality is within the scope of this disclosure. Furthermore, the illustrations are for illustrative purposes only and are not drawn to their original dimensions. For ease of understanding, the same or similar elements will be labeled with the same symbols in the following description.

[0030] Unless otherwise specified, the terms used throughout the specification and claims generally have their ordinary meaning in the context of the art, the disclosure, and the specific content.

[0031] It should be noted that the terms "first," "second," etc. are used in this article to describe different components. These terms are only used to distinguish components or operations described using the same technical terms.

[0032] In this document, when a component is referred to as “coupled” or “coupled,” it may mean “electrically coupled” or “electrically coupled.” “Coupled” or “coupled” can also be used to indicate the operation or interaction between two or more components. Furthermore, the terms “comprising,” “including,” “having,” “containing,” etc., used in this document are open-ended terms, meaning “including but not limited to.” Additionally, the term “and / or” as used in this document includes any one or more of the related listed items and all combinations thereof.

[0033] Please see Figure 1 . Figure 1 This is a schematic diagram of an external chip driving system 100 according to some embodiments of this disclosure. Figure 1As shown, the off-chip driver system 100 includes a decision circuit 120, an off-chip driver (OCD) front-end driver circuit 140, and an off-chip driver (OCD) driver circuit 160. In some embodiments, the off-chip driver front-end driver circuit 140 includes a first compensation circuit 142 and a second compensation circuit 144. The first compensation circuit 142 includes a plurality of first adjustable enhancement circuits AEC1_1 to AEC_y. The second compensation circuit 144 includes a plurality of second adjustable enhancement circuits AEC2_1 to AEC2_z. In some embodiments, the off-chip driver driver circuit 160 includes a pull-up circuit 162 and a pull-down circuit 164. Generally, the off-chip driver system 100 includes an off-chip driver control circuit (OCD control) and an on-die termination (ODT). Figure 1 The signals illustrated (e.g., OPTp, DUP, DDN) are only a portion of the control signals for external drivers. In some other embodiments, there will be on-chip stop control signals and other external driver control signals.

[0034] Structurally, the decision circuit 120 is coupled to the front-end drive circuit 140 of the external chip driver. The front-end drive circuit 140 of the external chip driver is coupled to the external chip driver circuit 160. Specifically, the first compensation circuit 142 is coupled to the decision circuit 120 and the pull-up drive circuit 162. The second compensation circuit 144 is coupled to the decision circuit 120 and the pull-down drive circuit 164.

[0035] Please see Figure 2 , Figure 2 This is a schematic diagram of a pull-up drive circuit 162 and a pull-down drive circuit 164 according to some embodiments of this disclosure. Figure 2 As shown, the pull-up drive circuit 162 includes a main unit 162a and a selection unit 162b. The main unit 162a includes a P-type driver Pd0 and a transistor R1. The selection unit 162b includes multiple P-type drivers Pd1 to Pdy and a transistor R2, where y in Pdy is an integer.

[0036] Structurally, P-type driver Pd0 is coupled to the system high voltage VDD and node N1. Transistor R1 is coupled to node N1 and the input / output pad I / O. Transistor R1 is coupled to node N1 and the input / output pad I / O. P-type drivers Pd1 to Pdy are coupled to the system high voltage VDD and node N2. Transistor R2 is coupled to node N2 and the input / output pad I / O.

[0037] Similarly, such as Figure 2As shown, the pull-down drive circuit 164 includes a main unit 164a and a selection unit 164b. The main unit 164a includes an N-type driver Nd0 and a transistor R3. The selection unit 164b includes multiple N-type drivers Nd1 to Ndz and a transistor R4, where z in Ndz is an integer.

[0038] Structurally, N-type driver Nd0 is coupled to the system low voltage VSS and node N3. Transistor R3 is coupled to node N3 and the input / output pad I / O. Transistor R3 is coupled to node N3 and the input / output pad I / O. N-type drivers Nd1 to Ndz are coupled to the system low voltage VSS and node N4. Transistor R4 is coupled to node N4 and the input / output pad I / O. In some embodiments, the values ​​of transistors R1, R2, R3, and R4 can be 0 or any value greater than 0.

[0039] Please see Figures 3A to 3D . Figures 3A to 3D This is a schematic diagram of P-type drivers Pd_a to Pd_d according to some embodiments of this disclosure. In some embodiments, Figure 2 The P-type drivers Pd0 to Pdy shown in the diagram can be understood as follows: Figure 3A The illustration includes transistor MP <1> The P-type driver Pd_a. Transistor MP <1> The first terminal is coupled to the system high voltage VDD. Transistor MP <1> The second terminal is coupled to the input / output pad I / O. Transistor MP <1> The control terminal is used to receive the pull-up control signal PUP_k. Transistor MP <1> It is used to turn on based on the pull-up control signal PUP_k with a low level, so as to provide the system high voltage VDD to the input / output pad I / O.

[0040] In some other embodiments, such as Figure 2 The P-type drivers Pd0 to Pdy shown can be understood as follows: Figure 3B The P-type driver Pd_b shown is... Figure 3C The P-type driver Pd_c shown is or Figure 3D The P-type driver Pd_d is shown. (As shown in the image...) Figure 3B As shown, the P-type driver Pd_b contains transistor MP <1> and resistor R5, and resistor R5 is connected to transistor MP <1> Series connection. For example... Figure 3C As shown, the P-type driver Pd_c contains multiple transistors MP connected in series. <1> ~MP <x>.like Figure 3D As shown, the P-type driver Pd_d contains multiple transistors MP connected in series. <1> ~MP <x>And resistor R5, and resistor R5 is connected to transistor MP. <1> ~MP <x>Series connection. The above MP <x>X is an integer. Architecturally, transistor MP...<k+1> Coupled transistor MP <k>The first end, and the transistor MP<k+1> and MP <k>Where k is an integer less than X. Operationally, the transistor MP... <2> ~MP <x>Similar to transistor MP <1> This will not be elaborated upon here.

[0041] It is worth noting that, although Figure 2 The illustrated P-type drivers Pd0 to Pdy receive pull-up control signals PUP_a and PUP_b1 to PUP_by, respectively. For ease of understanding and clarity, the pull-up control signals are... Figures 3A to 3D In this configuration, all pull-up control signals received by the P-type drivers Pd_a to Pd_d are represented by PUP_k. That is, the pull-up control signal PUP_k can be any of the pull-up control signals PUP_a, PUP_b1 to PUP_by. Furthermore, when the P-type drivers Pd_a to Pd_d are implemented by a P-type driver including the selection unit 162b, such as... Figures 4A to 4D Node N1 can be replaced by node N2.

[0042] Please see Figures 4A to 4D . Figures 4A to 4D This is a schematic diagram of N-type drivers Nd_a to Nd_d according to some embodiments of this disclosure. In some embodiments, in Figure 2 The N-type drivers Nd_0 to Nd_z in the text can each be understood as: Figures 4A to 4D The N-type drivers Nd_a to Nd_d are shown. Figures 4A to 4D The N-type driver Nd shown is similar to Figures 3A to 3D The P-type driver Pd is shown, but in Figures 4A to 4D The N-type driver Nd shown is in Figures 3A to 3D The difference between the P-type driver Pd shown is that the N-type transistor MN <1> ~MN <x>Replaced P-type transistor MP <1> ~MP <x>The pull-down control signal PDN_k replaces the pull-up control signal PUP_k, and the system low voltage VSS replaces the system high voltage VDD. In other words, in Figures 3A to 3D In this process, current flows from the top of Pd in ​​the P-type driver (e.g., the system high voltage VDD) to the bottom (e.g., node N1). Figures 4A to 4D In this configuration, current flows from the top of the N-type driver (e.g., node N3) to the bottom (e.g., system low voltage VSS). For the sake of simplicity, this will not be elaborated further.

[0043] Similarly, although in Figure 2 The N-type drivers Nd0 to Ndz in the diagram receive pull-down control signals PDN_a and PDN_b1 to PDN_bz, respectively. For ease of understanding, in... Figures 4A to 4D In this configuration, all pull-down control signals received by the N-type drivers Nd_a to Nd_d are represented by PDN_k. That is, the pull-down control signal PDN_k can be the corresponding pull-down control signals PDN_a, PDN_b1 to PDN_bz. Furthermore, when the N-type drivers Nd_a to Nd_d are implemented by an N-type driver including the selection unit 164b, in... Figures 4A to 4D Node N3 can be replaced by node N4.

[0044] It is worth noting that the P-type drivers Pd_a to Pd_d and the N-type drivers Nd_a to Nd_d are merely examples and are not intended to limit the scope of this disclosure. Any circuit implementing pull-up and pull-down circuits is within the scope of this disclosure. That is, the design of the pull-up drive circuit 162 and the pull-down drive circuit 164 can be adjusted by those skilled in the art.

[0045] Please refer to the following: Figure 1 In terms of configuration, decision circuit 120 receives frequency CLK and input data Din0, and outputs a first decision signal DUP and a second decision signal DDN based on the input data Din0. External driver front-end circuit 140 receives input data Din1, the first decision signal DUP, and the second decision signal DDN. First compensation circuit 142 generates a pull-up control signal PUP based on the first decision signal DUP, the second decision signal DDN, the first selection signal OPTp, and the first enable signal ENp, and outputs the pull-up control signal PUP to pull-up driver circuit 162. Second compensation circuit 144 generates a pull-down control signal PDN based on the first decision signal DUP, the second decision signal DDN, the second selection signal OPTn, and the second enable signal ENn, and outputs the pull-down control signal PDN to pull-down driver circuit 164. Pull-up driver circuit 162 provides a system high voltage to the input / output pad I / O based on the pull-up control signal PUP. The pull-down drive circuit 164 is used to provide system low voltage to the input / output pad I / O based on the pull-down control signal PDN.

[0046] It is worth noting that, for easier and clearer understanding, as shown in the following formulas (a) and (b), Figure 1 The pull-up control signal PUP shown in the diagram represents Figure 2 The diagram shows multiple pull-up control signals PUP_a and PUP_b1 to PUP_y, and... Figure 1 The pull-down control signal PDN shown in the diagram represents, for example... Figure 2 The pull-down control signals PDN_a and PDN_bz are illustrated in the diagram. Similarly, Figure 1 The first selection signal OPT_p shown in the figure represents Figure 5 The diagram shows multiple first selection signals OPTp_1 to OPTp_y, and Figure 1 The second selection signal OPTn shown in the figure represents Figure 5 The second selection signals OPTn_1 to OPTn_z are shown in the figure. Figure 1 The first enable signal ENp shown in the diagram represents Figure 5 The diagram shows multiple first enable signals ENp_1 to ENp_y, and Figure 1 The second enable signal ENn shown in the diagram represents Figure 5 The diagram shows multiple second enabling signals ENn_1 to ENn_z.

[0047] PUP=PUP_a+PUP_b1+PUP_b2+……+PUP_by《Formula (a)》

[0048] PDN=PDN_a+PDN_b1+PDN_b2+……+PDN_by《Formula (b)》

[0049] Generally, the drivers Pd1 to Pdy of selection unit 162b and the drivers Nd1 to Ndz of selection unit 164b are selectively turned on according to selection signals OPTp_1 to OPTp_y and OPTn_1 to OPTn_z, respectively, and the selection signals OPTp_1 to OPTp_y and OPTn_1 to OPTn_z are each determined according to ZQ calibration. In this disclosure, the drivers Pd1 to Pdy and Nd1 to Ndz are selectively turned on according to control signals PUP_b1 to PUP_by and PDN_b1 to PDN_bz, respectively, and the control signals PUP_b1 to PUP_by and PDN_b1 to PDN_bz are each determined according to the first decision signal DUP, the second decision signal DDN, the selection signals OPTp_1 to OPT_y and OPTn_1 to OPT_z, and the first enable signal ENp_1 to ENp_y.

[0050] For more details, please refer to the following: Figure 1 , Figure 2 as well as Figure 5 . Figure 5 This is a schematic diagram of a first adjustable enhancement circuit AEC1_1 to AEC1_y and a second adjustable enhancement circuit AEC2_1 to AEC2_z according to some embodiments of this disclosure. Figure 5 As shown, each of the first adjustable enhancement circuits AEC1_1 to AEC1_y is used to receive the corresponding of the first decision signal DUP, the second decision signal DDN, the first selection signal OPTp_1 to OPIp_y, and the first enable signal ENp_1 to EN_y. Each of the first adjustable enhancement circuits AEC1_1 to AEC1_y is also used to generate the corresponding of the pull-up control signals PUP_b1 to PUP_by. For example, when the second enable signal ENp_1 is at a low level, the first adjustable enhancement circuit AEC1_1 outputs the first selection signal OPTp_1 as the pull-up control signal PUP_b1; and when the second enable signal ENp_1 is at a high level, the first adjustable enhancement circuit AEC1_1 outputs either the system high voltage VDD or the system low voltage VSS as the pull-up control signal PUP_b1. The first adjustable enhancement circuits AEC1_2 to AEC1_y are similar to the first adjustable enhancement circuit AEC1_1, and will not be described again here.

[0051] like Figure 2 As shown, each of the P-type drivers Pd1 to Pdy is selectively turned on according to the corresponding pull-up control signals PUP_b1 to PUP_by. For example, when the pull-up control signal PUP_b1 is at a high level, the P-type driver Pd1 is turned on or off, and when the pull-up control signal PUP_b1 is at a low level, the P-type driver Pd1 is turned on. In other words, the first adjustable enhancement circuits AEC1_1 to AEC1_y correspond to the P-type drivers Pd1 to Pdy, respectively. Each of the first adjustable enhancement circuits AEC1_1 to AEC1_y outputs the corresponding pull-up control signals PUP_b1 to PUP_by according to the corresponding first enable signals ENp_1 to ENp_y, and each of the first adjustable enhancement circuits AEC1_1 to AEC1_y controls the corresponding P-type drivers Pd1 to Pdy to turn on or off according to the corresponding pull-up control signals PUP_b1 to PUP_by. It is worth noting that, as Figure 2 As shown, the P-type driver Pd0 of the main unit 162a is selectively turned on according to the pull-up control signal PUP_a. The pull-up control signal PUP_a can be determined according to the input data Din1. That is, in this disclosure, the operation of the selection unit 162b can be changed by the first adjustable enhancement circuits AEC1_1 to AEC1_y. The operation of the main unit 162a remains unchanged.

[0052] Similarly, such as Figure 5 As shown, each of the second adjustable enhancement circuits, AEC2_1 to AEC2_z, receives the corresponding of the first decision signal DUP, the second decision signal DDN, the second selection signals OPTn_1 to OPTn_z, and the corresponding of the second enable signals ENn_1 to ENn_z. Each of the second adjustable enhancement circuits AEC2_1 to AEC2_z also generates the corresponding of the pull-down control signals PDN_b1 to PDN_bz. For example, when the second enable signal ENn_1 is at a low level, the second adjustable enhancement circuit AEC2_1 outputs the second selection signal OPTn_1 as the pull-down control signal PDN_b1, and when the second enable signal ENn_1 is at a high level, the second adjustment circuit AEC2_1 outputs either the system high voltage VDD or the system low voltage VSS as the pull-down control signal PDN_b1. The second adjustable enhancement circuits AEC2_2 to AEC2_z are similar to the second adjustable enhancement circuit AEC2_1, and will not be described again here.

[0053] like Figure 2 As shown, each of the N-type drivers Nd1 to Ndz is selectively enabled based on the corresponding pull-down control signals PDN_z1 to PDN_bz. For example, when the pull-down control signal PDN_b1 is low-order, the N-type driver Nd1 is disabled; when the pull-down control signal PDN_b1 is high-order, the N-type driver Nd1 is enabled. In other words, the second adjustable enhancement circuits AEC2_1 to AEC2_z correspond to the N-type drivers Nd1 to Ndz, respectively. Each of the second adjustable enhancement circuits AEC2_1 to AEC2_z outputs pull-down control signals PDN_b1 to PDN_bz based on the corresponding second enable signals ENn_1 to EN_z, and each of the second adjustable enhancement circuits AEC2_1 to AEC2_z controls the corresponding N-type drivers Nd1 to Ndy to be enabled or disabled based on the pull-down control signals PDN_b1 to PDN_bz. It is worth noting that, as Figure 2 As shown, the N-type driver Nd0 of the main unit 164a is selectively turned on according to the pull-down control signal PDN_a. The pull-down control signal PDN_a can be determined according to the input data Din1. That is, in this disclosure, the operation of the selection unit 164b can be changed by the second adjustment enhancement circuits AEC2_1 to AEC2_z. The operation of the main unit 164a remains unchanged.

[0054] Please see Figure 6 , Figure 6 This is a schematic diagram of an adjustment enhancement circuit (AEC) according to some embodiments of this disclosure. In some embodiments, such as Figure 6 The adjustment enhancement circuit AEC shown can be used to achieve, for example... Figure 1 as well as Figure 5 The first adjustable enhancement circuits AEC1_1 to AEC1_y and the second adjustable enhancement circuits AEC2_1 to AEC2_z are shown. Figure 6 As shown, the adjustable enhancement circuit AEC includes two multiplexers, MUX1 and MUX2, and an up-down enhancement controller (UDEC).

[0055] In detail, the multiplexer MUX1 has an input terminal with pin "L" coupled to the system low voltage VSS. The multiplexer also has an input terminal with pin "H" to receive the first decision signal DUP. The control terminal of the multiplexer MUX1 receives the corresponding enable signals ENp / ENn. When the enable signals ENp / ENn are at a low level, the multiplexer MUX1 sets the third decision signal D_P to the system low voltage VSS, and when the enable signals ENp / ENn are at a high level, the multiplexer MUX1 outputs the first decision signal DUP as the third decision signal D_P.

[0056] Similarly, the multiplexer MUX2 has an input terminal with pin "L" coupled to the system high voltage VDD. The multiplexer MUX2 also has an input terminal with pin "H" for receiving the second decision signal DDN. The control terminal of the multiplexer MUX2 receives the corresponding enable signals ENp / ENn. When the enable signals ENp / ENn are at a low level, the multiplexer MUX2 sets the fourth decision signal D_N to the system high voltage VDD, and when the enable signals ENp / ENn are at a high level, the multiplexer MUX2 outputs the second decision signal DDN as the fourth decision signal D_N.

[0057] It is worth noting that, such as Figure 6 The adjustable enhancement circuit AEC shown is merely an example, and any circuit that can be implemented by truth table 1 can be understood as an adjustable enhancement circuit AEC.

[0058] Truth Table 1

[0059] ENp / ENn D_P D_N PUP / PDN L L H OPTp / OPTn H DUP DDN According to truth table 2

[0060] In some embodiments, the up / down enhancement controller UDEC can be implemented by the multiplexer MUX3. For example... Figure 6 As shown, the multiplexer MUX3 is a two-to-four multiplexer. The multiplexer MUX3 has an input pin "HH" coupled to the system low voltage VSS. The multiplexer MUX3 has an input pin "LL" coupled to the system high voltage VDD. The multiplexer MUX3 has an input pin "LH" used to receive the corresponding selection signals OPTp / OPTn. The multiplexer MUX3 has an input pin "HL" that is either floating or coupled to the output of the multiplexer MUX3. The two control pins of the multiplexer MUX3 are used to receive the third decision signal D_P and the fourth decision signal D_N.

[0061] When both the third decision signal D_P and the fourth decision signal D_N are at low levels, the multiplexer MUX3 sets the control signals PUP_b / PDN_b to the system high voltage VDD. When both the third decision signal D_P and the fourth decision signal D_N are at high levels, the multiplexer MUX3 sets the control signals PUP_b / PDN_b to the system low voltage VSS. When the third decision signal D_P is at a low level and the fourth decision signal is at a high level, the multiplexer MUX3 outputs the selection signals OPTp / OPTn as the control signals PUP_b / PDN_b.

[0062] It is worth noting that, such as Figure 6 The upper and lower enhancement controller UDEC shown is only an example. Any circuit that can be implemented by truth table 2 can be understood as an upper and lower enhancement circuit UDEC.

[0063] D_P D_N PUP_b / PDN_b L L VDD L H OPTp / OPTn H L maintain H H VSS

[0064] Truth Table 2

[0065] Thus, when the enable signals ENp and ENn are at low levels, the selection signals OPTp_1 to OPTp_y and OPTn_1 to OPTn_z determined by the ZQ calibration can be understood as control signals PUP and PDN. When the enable signals ENp and ENn are at high levels, the levels of all control signals PUP_b and PDN_b are determined based on the first decision signal DUP and the second decision signal DDN. Therefore, regardless of how many selection signals OPTp_1 to OPTp_y and OPTn_1 to OPT_z are determined by the ZQ calibration, by setting all enable signals ENp and ENn to high levels, all drivers of selection units 162b and 164b can operate according to the decision signals DUP and DDN.

[0066] Please see Figure 7 , Figure 7 This is a schematic diagram of a chip external driving system 100 according to some embodiments of this disclosure. For ease of explanation, Figure 1 , Figure 5 as well as Figure 6 The operation of the illustrated adjustable enhancement circuits AEC1_1 to AEC1_y and AEC2_1 to AEC2_z will be coordinated with Figure 7 The signal is explained. For example... Figure 7 As shown, when the input data Din is at a high level, the pull-up drive circuit 162 will provide a high voltage to the input / output pad I / O to increase the level of the output signal OUT. Conversely, when the input data Din is at a low level, the pull-down drive circuit 164 will provide a low voltage to the input / output pad I / O to decrease the level of the output signal OUT.

[0067] Specifically, the number of P-type drivers enabled is controlled by the number of pull-up control signals at the low level, and the number of pull-up control signals at the low level is determined based on a pre-configured number of the first selection signal. Similarly, the number of N-type drivers enabled is controlled by the number of pull-down control signals at the high level, and the number of pull-down control signals at the high level is determined based on a pre-configured number of the second selection signal. The pre-configured number is determined by ZQ calibration.

[0068] For example, if the number of first selection signals is pre-configured to be 2, when the input data Din1 is at a high level, the two pull-up control signals (e.g., PUP_b1 and PUP_b2) become low levels according to the two first selection signals (e.g., OPTp_1 and OPT_2), and the two P-type drivers (e.g., Pd1 and Pd2) are turned on in response to the pull-up control signals (e.g., PUP_b1 and PUP_b2). Simultaneously, the other P-type drivers (e.g., Pd3 to Pdy) are turned off in response to their corresponding pull-up control signals (e.g., PUP_b3 to PUP_by) based on the other first selection signals (e.g., OPTp_3 to OPTp_y) being at a high level.

[0069] To give another example, if the number of second selection signals is pre-configured to 1, when the input data Din1 is at a low level, one of the pull-down control signals (e.g., PDN_b1) becomes at a high level based on one of the second selection signals (e.g., OPTn_1), and one of the N-type drivers (e.g., Nd1) is turned on in response to the corresponding pull-down control signal (e.g., PDN_b1). Simultaneously, the other N-type drivers (e.g., Nd2 to Ndz) are turned off in response to the corresponding pull-down control signals (e.g., PDN_b2 to PDN_bz) based on the other second selection signals (e.g., OPTn_2 to OPTn_z) being at a low level.

[0070] Therefore, ideally, the output signal OUT of the input / output pad I / O should be the same as the input data Din1. However, in high-speed data transmission, the amplitude of the transmitted signal attenuates. If the frequency is increased to reduce the amplitude attenuation during transmission, the data signal will become severely distorted. For example, when the input data Din1 initially transitions from a low level to a high level, the output data of the output signal OUT (such as...) Figure 7 The waveform of time period P1 shown will be too low to be clear. Similarly, when the input data Din1 initially transitions from a high level to a low level, the output data of the output signal OUT (such as...) Figure 7 The waveform of time period P2 shown is too high to be clear.

[0071] Therefore, in this disclosure, when the input signal Din transitions from a low level to a high level, the decision circuit 120 detects the timing point and generates and outputs a high pulse as the first decision signal DUP. Conversely, when the input signal Din transitions from a high level to a low level, the decision circuit 120 detects the timing point and generates and outputs a low pulse as the second decision signal DDN. Furthermore, the adjustable enhancement circuits AEC1_1 to AEC1_y and AEC2_1 to AEC2_z of the external driver front-end circuit 140 are controlled by enable signals ENp and ENn, thereby generating control signals PUP_b and PDN_b based on the decision signals DUP and DDN. When the enable signals ENp and ENn are at a high level, the levels of the control signals PUP_b and PDN_b are determined based on the first decision signal DUP and the second decision signal DDN. When the enable signals ENp and EN are at low levels, the levels of the control signals PUP_b and PDN_b are determined based on the selection signals OPTp_1~OPTp_y and OPTn_b1~OPTn_bz, respectively, and the selection signals OPTp_1~OPTp_y and OPTn_b1~OPTn_bz are determined by ZQ calibration.

[0072] In detail, when the enable signals ENp and ENn are at high levels, if both the first decision signal DUP and the second decision signal DDN are at high levels (e.g., a high pulse of the first decision signal DUP), all the pull-up control signals PUP_b1 to PUP_by generated by the first adjustable enhancement circuits AEC1_1 to AEC1_y and all the pull-down control signals PDN_b1 to PDN_bz generated by the second adjustable enhancement circuits AEC2_1 to AEC2_z are at low levels. Therefore, in response to the control signals PUP_b1 to PUP_by and PDN_b1 to PDN_bz, all P-type drivers Pd0 to Pdy will be turned on, and all N-type drivers Nd0 to Ndz will be turned off. That is, the P-type drivers are quickly turned on to pull the output signal OUT high, and the N-type drivers are quickly turned off so that the output signal OUT is not pulled low. Therefore, the slew rate of the output signal OUT during its rise can be improved.

[0073] Similarly, when the enable signals ENp and ENn are at high levels, if both the first decision signal DUP and the second decision signal DDN are at low levels (e.g., a low pulse of the second decision signal DDN), all the pull-up control signals PUP_b1 to PUP_by generated by the first adjustable enhancement circuits AEC1_1 to AEC1_y and all the pull-down control signals PDN_b1 to PDN_bz generated by the second adjustable enhancement circuits AEC2_1 to AEC2_z are at high levels. Therefore, in response to the control signals PUP_b1 to PUP_by and PDN_b1 to PDN_bz, all P-type drivers Pd0 to Pdy will be turned off, and all N-type drivers Nd0 to Ndz will be turned on. That is, the P-type drivers are quickly turned off so that the output signal OUT is not charged too high, and the N-type drivers are quickly turned on, thereby pulling the output signal OUT low. Therefore, the slew rate of the output signal OUT during its descent can be improved.

[0074] Furthermore, when the first decision signal DUP is at a low level and the second decision signal DDN is at a high level (e.g., the first decision signal DUP and the second decision signal DDN do not have a pulse period), the levels of the pull-up control signals PUP_b1 to PUP_by generated by the first adjustable enhancement circuits AEC1_1 to AEC1_y are determined based on the first selection signals OPTp_1 to OPTp_y, and the levels of the pull-up control signals PDN_b1 to PDN_bz generated by the second adjustable enhancement circuits AEC2_1 to AEC2_z are determined based on the second selection signals OPTn_1 to OPTn_z. That is, when the input signal Din remains unchanged, only the driver corresponding to the pre-configured selection signal will operate. This is similar to the state when the enable signals ENp and ENn are at a low level, and will not be described further here.

[0075] Thus, regardless of the pre-configured quantity determined by ZQ calibration, by setting the enable signals ENp and ENn to a high level, all P-type drivers Pd0 to Pdy will be activated when the input signal Din1 transitions from a low level to a high level, and all N-type drivers Nd0 to Nd1 will be activated when the input signal Din1 transitions from a high level to a low level. This increases the slew rate of the output signal OUT, and therefore increases the output data of the input / output pad I / O (such as...). Figure 7 The waveforms of time periods P3 and P4 shown are clearer (reducing distortion).

[0076] It is important to note that, as explained above, all drivers Pd0-Pdy or Nd0-Ndz will operate precisely when the enable signals ENp and ENn are high, and this is not intended to limit the scope of this disclosure. In other words, in some other embodiments, the number of drivers Pd0-Pdy or Nd0-Ndz that will operate can be configured by the number of enable signals ENp and ENn.

[0077] Furthermore, such as Figure 1 The frequency CLK shown is merely an example. In some embodiments, the decision circuit 120 can generate input data Din, a first decision signal DUP, and a second decision signal DDN without generating the corresponding frequency CLK. Input data Din1 is input data Din0 after delay processing, thereby aligning the signals processed by the decision circuit 120 in time.

[0078] In some embodiments, the decision circuit 120 may be implemented by electronic components, such as components of a feed-forward equalizer or a pre-emphasis decision technical circuit. Specifically, the decision circuit 120 receives input data Din1 and compares the voltage levels of the next input data with the current input data. When the voltage level of the next input data is higher than the voltage level of the current input data, the decision circuit 120 generates a pulse of the first decision signal DUP (e.g., ...). Figure 7 The waveforms shown in time periods P1 and P3). When the voltage level of the next input data is lower than the voltage level of the current input data, the decision circuit 120 generates a pulse of the second decision signal DDN (e.g., ...). Figure 7 The waveforms shown in time periods P2 and P4).

[0079] The above description includes exemplary operations. However, these operations do not need to be performed in a specific order. The operations mentioned in the embodiments can be adjusted according to actual needs, unless otherwise specified, and can be performed simultaneously or partially simultaneously.

[0080] It should be noted that the icons, embodiments, features, and circuits in the various embodiments can be combined with each other as long as they do not contradict each other. The circuits shown in the icons are merely illustrative and simplified for simplicity and ease of understanding. Furthermore, those skilled in the art will understand that the various embodiments and circuit units can be implemented by different types of analog or digital circuits, or by different circuits with integrating circuits. Components can also be integrated into a single chip with integrating circuits. The foregoing description is merely illustrative and is not intended to limit this disclosure.

[0081] In summary, in the various embodiments disclosed herein, the number of control signals PUP and PDN at the enable level is controlled by enable signals ENp and ENn and selection signals OPTp and OPTn, and the timing of control signals PUP and PDN at the enable level is controlled by decision signals DUP and DDN. The activation time and number of drivers Pd0 to Pdy of the pull-up circuit and Nd0 to Ndz of the pull-down circuit are determined by the corresponding control signals PUP and PDN. Therefore, the slew rate of the output signal OUT generated by the external driver system during rise and fall can be controlled to meet actual requirements.

[0082] Although the present disclosure has been described above with reference to embodiments, it is not intended to limit the present disclosure. Any person skilled in the art may make various modifications and refinements without departing from the spirit and scope of the present disclosure. Therefore, the scope of protection of the present disclosure shall be determined by the claims.

[0083]

Explanation of symbols

[0084] To make the above and other objects, features, advantages and embodiments of this disclosure more apparent and understandable, the accompanying symbols are explained as follows:

[0085] 100: External driver system for chips

[0086] 120: Decision Circuit

[0087] 140: Front-end drive circuit of external chip driver

[0088] 142: First compensation circuit

[0089] 144: Second compensation circuit

[0090] 160: External driver circuit for the chip

[0091] 162: Pull-up drive circuit

[0092] 164: Pull-down driver circuit

[0093] 162a, 164a: Principal Units

[0094] 162b, 164b: Selection Unit

[0095] UDEC: Upward and Downward Enhancement Controller

[0096] MUX1, MUX2, MUX3: Multiplexers

[0097] R1, R2, R3, R4, R5, R6: Transistors

[0098] AEC: Adjustable Enhancement Circuit

[0099] AEC1_1~AEC1_y: First adjustable enhancement circuit

[0100] AEC2_1~AEC2_z: Second Adjustable Enhancement Circuit

[0101] Pd0, Pd_a, Pd_b, Pd_c, Pd_d: P-type drivers

[0102] Nd0, Nd_a, Nd_b, Nd_c, Nd_d: N-type driver

[0103] MP <1> ~MP <x>:transistor

[0104] MN <1> ~MN <x>:transistor

[0105] R5: Resistor

[0106] CLK: Frequency

[0107] Din0, Din1: Input data

[0108] DUP: First Decision Signal

[0109] DDN: Second Decision Signal

[0110] PUP: Pull-up control signal

[0111] PDN: Pull-down control signal

[0112] PUP_a, PUP_b, PUP_b1~PUP_by, PUP_k: Pull-up control signals

[0113] PDN_a, PDN_b, PDN_b1~PDN_bz, PDN_k: Pull-down control signals

[0114] OPTp_1~OPTp_y: First selection signal

[0115] OPTn_1~OPTn_z: Second selection signal

[0116] ENp: First enable signal

[0117] ENn: Second enabling signal

[0118] OUT: Output signal

[0119] VDD: System high voltage

[0120] VSS: System Low Voltage

[0121] I / O: Input / Output Pads

[0122] P1, P2, P3, P4: Time Period

[0123] N1, N2, N3, N4: Nodes.< / x> < / x> < / x> < / x> < / x> < / k> < / k> < / x> < / x> < / x> < / x>

Claims

1. A chip external driving system, characterized in that, Include: The decision circuit is used to output a first decision signal and a second decision signal based on the frequency and input data. A plurality of first adjustable enhancement circuits are coupled to the decision circuit, wherein each of the first adjustable enhancement circuits is configured to generate one of a plurality of first control signals in response to one of a plurality of first selection signals, the first decision signal, and the second decision signal, wherein each of the first adjustable enhancement circuits includes: The first multiplexer is used to receive the first decision signal, the system low voltage, and the enable signal; The second multiplexer is used to receive the second decision signal, the system high voltage, and the enable signal; as well as A third multiplexer is coupled to the first multiplexer and the second multiplexer; as well as The pull-up circuit includes a plurality of first drivers, wherein each of the first drivers is coupled to a corresponding one of the first adjustable enhancement circuits, and each of the first drivers is enabled in response to a corresponding one of the first control signals.

2. The chip external driving system according to claim 1, characterized in that, in, When the input data is converted from the first level to the second level, the decision circuit generates a pulse with a higher level as the first decision signal. as well as When the input data is converted from the second level to the first level, the decision circuit generates another pulse with a lower level as the second decision signal.

3. The chip external driving system according to claim 1, characterized in that, in, When both the first decision signal and the second decision signal are at a low level, the first adjustable enhancement circuits set all the first control signals to a system high voltage, thereby turning off all the first drivers; and When both the first decision signal and the second decision signal are at a high level, the first adjustable enhancement circuits set all the first control signals to a low system voltage, thereby turning on all the first drivers.

4. The chip external driving system according to claim 1, characterized in that, When the first decision signal is at a low level and the second decision signal is at a high level, the first adjustable enhancement circuits provide the first selection signals as the first control signals, causing a portion of the first drivers to turn off and another portion of the first drivers to turn on.

5. The chip external driving system according to claim 1, characterized in that, Among each of these first adjustable enhancement circuits: When the enable signal is at a high level, the first multiplexer outputs the first decision signal; when the enable signal is at a low level, the first multiplexer outputs the system low voltage. When the enable signal is at the high level, the second multiplexer outputs the second decision signal; when the enable signal is at the low level, the second multiplexer outputs the system high voltage. as well as The third multiplexer is used to receive the system low voltage, the system high voltage, one of the first selection signals, a third decision signal from the first multiplexer, and a fourth decision signal from the second multiplexer, and the third multiplexer is used to output one of the first control signals in response to the third decision signal and the fourth decision signal.

6. The chip external driving system according to claim 5, characterized in that, in, When the third decision signal and the fourth decision signal are at the high level, the third multiplexer is used to output the system low voltage as one of the first control signals; When the third decision signal and the fourth decision signal are at the low level, the third multiplexer is used to output the system high voltage as one of the first control signals; as well as When the third decision signal is at the low level and the fourth decision signal is at the high level, the third multiplexer is used to output the first selection signal.

7. The chip external driving system according to claim 5, characterized in that, These first drivers are P-type metal-oxide-semiconductor field-effect transistors.

8. A chip external driving system, characterized in that, Include: The decision circuit is used to output a first decision signal and a second decision signal based on the frequency and input data. A plurality of second adjustable enhancement circuits are coupled to the decision circuit, wherein each of the second adjustable enhancement circuits is configured to generate one of a plurality of second control signals in response to one of a plurality of second selection signals, the first decision signal, and the second decision signal, wherein each of the second adjustable enhancement circuits includes: The first multiplexer is used to receive the first decision signal, the system low voltage, and the enable signal; The second multiplexer is used to receive the second decision signal, the system high voltage, and the enable signal; as well as A third multiplexer is coupled to the first multiplexer and the second multiplexer; as well as The pull-down circuit includes a plurality of second drivers, each of which is coupled to a corresponding one of the second adjustable enhancement circuits, and each of the second drivers is enabled in response to a corresponding one of the second control signals.

9. The chip external driving system according to claim 8, characterized in that, in, When the input data is converted from the first level to the second level, the decision circuit generates a pulse with a higher level as the first decision signal. as well as When the input data is converted from the second level to the first level, the decision circuit generates a pulse with a low level as the second decision signal.

10. The chip external driving system according to claim 8, characterized in that, in, When both the first decision signal and the second decision signal are at a low level, the second adjustable enhancement circuit sets the second control signals to a high system voltage, thereby enabling all the second drivers; and When both the first decision signal and the second decision signal are at a high level, the second adjustable enhancement circuit sets the second control signals to a low system voltage, thereby turning off all the second drivers.

11. The chip external driving system according to claim 8, characterized in that, When the first decision signal is at a low level and the second decision signal is at a high level, the second adjustable enhancement circuit provides the second selection signals as the second control signals, causing a portion of the second drivers to turn off and another portion of the second drivers to turn on.

12. The chip external driving system according to claim 8, characterized in that, In each of these second adjustable enhancement circuits: When the enable signal is at a high level, the first multiplexer is used to output the first decision signal; when the enable signal is at a low level, the first multiplexer is used to output the system low voltage. When the enable signal is at a high level, the second multiplexer is used to output the second decision signal; when the enable signal is at a low level, the second multiplexer is used to output the system high voltage. as well as The third multiplexer is used to receive the system low voltage, the system high voltage, one of the second selection signals, a third decision signal from the first multiplexer, and a fourth decision signal from the second multiplexer, and the third multiplexer is used to output one of the second control signals in response to the third decision signal and the fourth decision signal.

13. The chip external driving system according to claim 12, characterized in that, in, When the third decision signal and the fourth decision signal are at the high level, the third multiplexer is used to output the system low voltage as the second control signal; When the third decision signal and the fourth decision signal are at the low level, the third multiplexer is used to output the high voltage of the system as the second control signal; as well as When the third decision signal is at a low level and the fourth decision signal is at a high level, the third multiplexer is used to output the second selection signal.

14. The chip external driving system according to claim 8, characterized in that, These second drivers are N-type metal-oxide-semiconductor field-effect transistors.

15. A chip external driving system, characterized in that, Include: The decision circuit is used to output a first decision signal and a second decision signal based on the frequency and input data; A first adjustable enhancement circuit is coupled to the decision circuit, wherein the first adjustable enhancement circuit is configured to generate a first control signal in response to the first decision signal, the second decision signal, and the first selection signal; A second adjustable enhancement circuit is coupled to the decision circuit, wherein the second adjustable enhancement circuit is used to generate a second control signal in response to the first decision signal, the second decision signal and the second selection signal; A pull-up circuit is used to enable the circuit in response to the first control signal; as well as A pull-down circuit is used to enable the circuit in response to the second control signal. The first adjustable enhancement circuit and the second adjustable enhancement circuit each include: The first multiplexer is used to receive the first decision signal, the system low voltage, and the enable signal; The second multiplexer is used to receive the second decision signal, the system high voltage, and the enable signal; as well as A third multiplexer is coupled to the first multiplexer and the second multiplexer.

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