Method for performing programming management in a memory device, memory device, and controller

Abstract

The present invention discloses a method for programming management in a memory device, the memory device and its controller. The memory device includes a non-volatile memory, and the non-volatile memory includes a plurality of non-volatile memory components. The method includes: before programming a target non-volatile memory component among the plurality of non-volatile memory components, the controller checks whether another non-volatile memory component among the plurality of non-volatile memory components has been programmed; and when the another non-volatile memory component has been programmed and enters a non-busy state, the controller programs the target non-volatile memory component. The beneficial effect of the present invention is that it can avoid the instantaneous power consumption of the memory device exceeding the predetermined product specifications without increasing additional costs.

Description

[0001] This application is a divisional application of a Chinese invention application with an application date of October 17, 2017, an application number of 201710965790.0, and an invention title of "Method for Programming Management in a Memory Device, Memory Device, and Controller". Technical Field

[0002] The present invention relates to the access of flash memory, and in particular, to a method for programming management in a memory device and related memory devices and their controllers. Background Art

[0003] In recent years, due to the continuous development of memory technologies, various portable memory devices (such as memory cards compliant with the SD / MMC, CF, MS, or XD standards) have been widely implemented in many applications. Therefore, the access control of the memories in these portable memory devices has become a quite popular topic.

[0004] In the case of the commonly used NAND flash memory, it can be mainly classified into two major categories of flash memories: single level cell (SLC) and multiple level cell (MLC). Each transistor regarded as a memory cell in the single level cell flash memory has only two charge values, which are used to represent the logic value 0 and the logic value 1 respectively. In addition, the storage capacity of each transistor regarded as a memory unit in the multiple level cell flash memory is fully utilized, and a higher voltage is used to drive it, so as to record at least two groups of bit information (such as 00, 01, 11, 10) in a transistor through different levels of voltage; theoretically, the recording density of the multiple level cell flash memory can reach at least twice that of the single level cell flash memory, which is very good news for the related industries of NAND flash memory that once encountered bottlenecks in the development process.

[0005] Compared with the single level cell flash memory, since the multiple level cell flash memory is cheaper and can provide a larger capacity in a limited space, the multiple level cell flash memory quickly becomes the mainstream adopted by portable memory devices on the market. However, the problems caused by the instability of the multiple level cell flash memory also emerge one by one. In order to ensure that the access control of the portable memory device to the flash memory complies with relevant specifications, the controller of the flash memory usually has certain management mechanisms to properly manage the access of data.

[0006] According to related technologies, memory devices with these management mechanisms still have deficiencies. For example, in response to certain types of write / program operations, the instantaneous power consumption of the memory device may be too large and exceed the predetermined product specifications. Therefore, a novel method and memory access architecture are needed to achieve the optimal performance of the memory device without side effects or with a lower likelihood of side effects. Summary of the Invention

[0007] An object of the present invention is to disclose a method for programming management in a memory device, as well as a related memory device and its controller, to solve the above problems.

[0008] Another object of the present invention is to disclose a method for programming management in a memory device, as well as a related memory device and its controller, to achieve the optimal performance of the memory device without side effects or with a lower likelihood of side effects.

[0009] At least one embodiment of the present invention discloses a method for programming management in a memory device, wherein the memory device includes a non-volatile memory (NV memory), and the non-volatile memory includes a plurality of non-volatile memory elements. For example, the method may include: before programming a target non-volatile memory element among the plurality of non-volatile memory elements, checking whether another non-volatile memory element among the plurality of non-volatile memory elements has been programmed; and when the another non-volatile memory element has been programmed and enters a non-busy state, programming the target non-volatile memory element.

[0010] At least one embodiment of the present invention discloses a memory device, which includes: a non-volatile memory for storing information, wherein the non-volatile memory includes a plurality of non-volatile memory components; and a controller coupled to the non-volatile memory for controlling the operation of the memory device. For example, the controller may include a processing circuit, and the processing circuit may be used to control the controller according to an instruction from a host device to allow the host device to access the non-volatile memory through the controller. Additionally, before programming a target non-volatile memory component among the plurality of non-volatile memory components, the controller checks whether another non-volatile memory component among the plurality of non-volatile memory components has been programmed. Furthermore, when the another non-volatile memory component has been programmed and enters a non-busy state, the controller programs the target non-volatile memory component.

[0011] At least one embodiment of the present invention discloses a controller of a memory device, wherein the memory device includes the controller and a non-volatile memory, and the non-volatile memory includes a plurality of non-volatile memory components. For example, the controller may include a processing circuit, and the processing circuit may be used to control the controller according to an instruction from a host device to allow the host device to access the non-volatile memory through the controller. Additionally, before programming a target non-volatile memory component among the plurality of non-volatile memory components, the controller checks whether another non-volatile memory component among the plurality of non-volatile memory components has been programmed. Furthermore, when the another non-volatile memory component has been programmed and enters a non-busy state, the controller programs the target non-volatile memory component.

[0012] One of the advantages of the present invention is that through proper programming management, the present invention can properly control the operation of the controller to avoid the instantaneous power consumption of the memory device exceeding the predetermined product specifications. Additionally, implementing according to the related embodiments of the present invention does not incur many additional costs, and even saves costs more than the related technologies. Therefore, the problems of the related technologies can be solved, and the overall cost does not increase much. Compared with the related technologies, the present invention can achieve the optimized performance of the memory device without side effects or with less likelihood of side effects. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 A schematic diagram of a memory device and a host device according to a first embodiment of the present invention.

[0014] Figure 2A Illustrates a local page address linking table in a block of a flash chip.

[0015] Figure 2B Compare Figure 2A The one-dimensional array example and two-dimensional array example of the shown local page address linking table.

[0016] Figure 3 Is a flowchart of a method for programming management in a memory device according to an embodiment of the present invention.

[0017] Figure 4 Is a flowchart of a method for programming management in a memory device according to another embodiment of the present invention.

[0018] Figure 5 Illustrates a chip-enable (CE) control scheme in an embodiment, where the chip-enable control scheme can be applied to Figure 3 the shown method and Figure 4 the shown method.

[0019] Figure 6 Illustrates a power consumption control scheme in an embodiment, where the power consumption control scheme can be applied to Figure 3 the shown method and Figure 4 the shown method.

[0020] Among them, the reference numerals are explained as follows:

[0021] 100 Memory device

[0022] 110 Memory controller

[0023] 112 Microprocessor

[0024] 112C Program code

[0025] 112M Read-only memory

[0026] 114 Control logic circuit

[0027] 116 Buffer memory

[0028] 118 Transmission interface circuit

[0029] 120 Non-volatile memory

[0030] 122-1, 122-2, …, 122-N Non-volatile memory components

[0031] 200 Main device

[0032] 300, 320 Methods for programming management in the memory device

[0033] Method

[0034] 302, 322 Steps for selecting memory components

[0035] 304 Steps for recording the selection order of memory components

[0036] 306 Steps for determining whether the memory components at the preset selection interval have been programmed

[0037] Steps

[0038] 308, 328 Waiting steps

[0039] 310, 330 Steps for starting the programming of memory components

[0040] 324 Steps for determining the status of other memory components

[0041] 326 Steps for determining whether the total number of memory components in the busy state is less than the preset value

[0042] CE1, CE2, CE3, CE4 Chip enable signals

[0043] PWR1, PWR2, PWR3, PWR4 Power consumption Detailed implementation manners

[0044] I. Memory system

[0045] Please refer to Figure 1 , Figure 1Schematic diagram of a memory device 100 and a host device 200 according to a first embodiment of the present invention. For example, the memory device 100 may be a portable memory device (e.g., a memory card compliant with the SD / MMC, CF, MS, or XD standard) or a solid state drive (SSD). Additionally, examples of the host device 200 may include (but are not limited to): a multifunctional mobile phone, a tablet, a wearable device, and a personal computer such as a desktop computer and a laptop computer. According to this embodiment, the memory device 100 may include a controller such as a memory controller 110, and may further include a non-volatile memory (NV memory) 120, wherein the controller is used to access the non-volatile memory 120, and the non-volatile memory 120 is used to store information. The non-volatile memory 120 may include a plurality of non-volatile memory elements 122-1, 122-2,..., and 122-N, where the symbol "N" may represent a positive integer greater than one. For example, the non-volatile memory 120 may be a Flash memory, and the non-volatile memory elements 122-1, 122-2,..., and 122-N may be respectively a plurality of Flash memory chips or a plurality of Flash memory dice, but the present invention is not limited thereto.

[0046] As Figure 1As shown, the memory controller 110 may include a processing circuit such as a microprocessor 112, a memory such as a read only memory (ROM) 112M, a control logic circuit 114, a buffer memory 116, and a transmission interface circuit 118, where these components may be coupled to each other through a bus. The buffer memory 116 is implemented as a random access memory (RAM). Additionally, the read only memory 112M of this embodiment is used to store a program code 112C, and the microprocessor 112 is used to execute the program code 112C to control the access to the non-volatile memory 120. Note that the program code 112C may also be stored in the buffer memory 116 or any form of memory. Furthermore, the control logic circuit 114 may include an error correction code circuit (not shown) to protect data or perform error correction, and the transmission interface circuit 118 may conform to a specific communication standard (such as the Serial Advanced Technology Attachment (SATA) standard, the Universal Serial Bus (USB) standard, or the Peripheral Component Interconnect Express (PCIE) standard) and communicate according to the specific communication standard.

[0047] In this embodiment, the host device 200 may access the memory device 100 by sending instructions and corresponding logical addresses to the memory controller 110. The memory controller 110 receives the instructions and the logical addresses, and controls the non-volatile memory 120 to read, write / program, or erase a memory unit with a physical address in the non-volatile memory 120, where the physical address corresponds to the logical address.

[0048] II. Page Address Linking Table

[0049] Figure 2A Illustrates a local page address linking table in a block of a flash chip 0, where the flash chip 0 may be an example of the above flash memory chip. As Figure 2A shown, the flash chip 0 includes a plurality of blocks 0, 1, 2,..., and M. Note that a block is an erase unit. In other words, when data needs to be erased, the microprocessor 112 erases all the data stored in the block at the same time. Additionally, a block, such as Figure 2AThe illustrated block 0 includes multiple pages. For example, block 0 of flash chip 0 includes 128 pages. In such a block as block 0, these pages are divided into two partitions, namely a data partition for storing data and a table partition for storing a local page address linked list 0. The pages in the data partition of the block can be referred to as the data pages of the block, and any one of the data pages can include a data byte region (DBR) and a spare byte region (SBR).

[0050] According to this embodiment, the number of pages in the data partition and the number of pages in the table partition can be determined as needed. For example, pages 0, 1, 2, …, 126 can be used to store data, and the remaining pages in the block are used to store the local page address linked list 0. According to some embodiments, the data partition can include less than 127 pages, and the table partition can include two or more pages. Also for example, the total number of pages in the block, the number of pages in the data partition, and the number of pages in the table partition can be changed respectively. Note that one page is a write unit. In other words, when data needs to be written, the microprocessor 112 writes data equivalent to one page into one page at a time. According to this embodiment, Figure 1 Each block in the multiple blocks of each flash chip in the illustrated non-volatile memory 120 can have a local page address linked list. For the sake of simplicity, only the local page address linked list 0 of block 0 of flash chip 0 is illustrated in Figure 2A , because the functions and operations of each local page address linked list are similar to each other.

[0051] In this embodiment, the time point when the local page address linked list 0 is established is when all the data pages in block 0 have been written, that is, when they have been fully programmed. However, before the data pages in block 0 are fully programmed, the microprocessor 112 temporarily stores a temporary local page address linked list 0 in the random access memory; when any link relationship between a physical page address and a logical page address in block 0 changes, the microprocessor 112 updates the temporary local page address linked list 0.

[0052] According to this embodiment, the arrangement order of a field (item) in the temporary / non-temporary local page address linked list (for example, the temporary local page address linked list 0 or the local page address linked list 0) represents a physical page address, and the content in this field represents a related logical page address. For example, assume that i P and j P are respectively Figure 2A the example table positions of the temporary / non-temporary local page address linked list shown (i P , j P) the number of columns and rows therein, and i P = 0, 1, … etc. and j P = 0, 1, … etc. In Figure 2A this two-dimensional array example of the temporary / non-temporary local page address link table shown, corresponding to the (i P *4 + j P )-th field, the example table position (i P , j P ) represents a physical page number PPN, which can be described as follows: PPN = (PBN * DPC + i P *4 + j P );

[0053] where the parameter PBN represents the physical block number of the physical block under discussion (for example: PBN = 0, 1, 2, … etc., corresponding to blocks 0, 1, 2, … etc. respectively), and the parameter DPC represents the number of data pages in each block (for example: it can be 127 in this embodiment). This is only for illustrative purposes and not a limitation of the present invention. For ease of understanding, the temporary / non-temporary local page address link table can be depicted as a single row, as Figure 2B shown in the right half. Given that i P is still the number of columns and i P = 0, 1, … etc., then in Figure 2B this one-dimensional array example shown in the right half, for the temporary / non-temporary local page address link table of block PBN, the example table position corresponding to the i P -th field i P represents a physical page address (PBN * DPC + i P ). That is, for this one-dimensional array example, the above formula can be rewritten as follows: PPN = (PBN * DPC + i P ).

[0054] For example, when the host device 200 transmits an instruction to the microprocessor 112 to write some data at a logical page address 0x0002, the microprocessor 112 may write the data and the logical page address 0x0002 into the data bit group area DBR and the spare bit group area SBR of page 0 in block 0 of the flash chip 0 respectively, and write the logical page address 0x0002 into the first field of the temporary local page address link table 0, so as to indicate thereby that the logical page address 0x0002 is linked / mapped to page 0 in block 0 of the flash chip 0, and its physical page address is 0x0000. And so on. When all data pages in block 0 have been written, the microprocessor 112 may copy the latest version of the temporary local page address link table 0 to establish the local page address link table 0. Note that the logical page addresses {0x0002, 0x0001, 0x0002, 0x0005, 0x0003, 0x0007, 0x0010, 0x0008, …, 0x0000, 0x0009, 0x0004} may be used as examples of the logical addresses. According to some embodiments, the logical addresses may be varied.

[0055] According to some embodiments, the range of logical page addresses in a local page address link table such as the local page address link table 0 may be greater than the number of pages in a block such as block 0.

[0056] According to some embodiments, the microprocessor 112 may establish a global page address link table in the random access memory according to multiple local page address link tables respectively corresponding to multiple blocks to record / update the relationship between the physical address and the logical address.

[0057] III. Performance Control

[0058] The memory controller 110 may manage the programming operations in the memory device 100 to solve the problems of the related art with fewer or no side effects. For example, the memory controller 110 may dynamically adjust the scheduling of the programming operations to achieve the optimal performance of the memory device 100.

[0059] Figure 3FIG. 300 is a flowchart of a method 300 for programming management in a memory device according to an embodiment of the present invention. The method 300 can be applied to the memory device 100 and can be applied to the controller such as the memory controller 110. For example, under the control of the processing circuit such as the microprocessor 112, the memory controller 110 can operate the method 300. For simplicity of description, it is assumed that the memory device 100 can have a single channel, and the total number of non-volatile memory components in the single channel can be 4 (N = 4), and the following description is made taking these non-volatile memory components (which can be non-volatile memory components 122-1, 122-2, 122-3, and 122-4 respectively) as examples; however, the present invention is not limited thereto. The method 300 can also be applied to a memory device 100 in which the total channel count NCH, the number of non-volatile memory components per channel (NV-memory-element-count per channel) NPC, or the total number N of non-volatile memory components is any positive integer, where N = (NPC * NCH).

[0060] In step 302, the memory controller 110 can select one of the unprogrammed memory components. For example, before this, the non-volatile memory components 122-1, 122-2, and 122-3 have been selected and the selection has not been cancelled, and only the non-volatile memory component 122-4 can be selected. Therefore, in step 302, the memory controller 110 selects the non-volatile memory component 122-4.

[0061] In step 304, the memory controller 110 can record the selection order of this memory component. Assume that the non-volatile memory components 122-1, 122-2, and 122-3 have been selected, and the selection orders are 0, 1, and 2 respectively. For example, the selection order of the non-volatile memory component 122-4 is 3.

[0062] In step 306, the memory controller 110 may determine whether the memory components within a preset selection interval have been programmed according to the selection order. If so, step 310 is executed; if not, step 308 is executed. The preset selection interval is used to determine the association between the previously selected non-volatile memory components and the currently selected non-volatile memory components, and the value of the preset selection interval is less than the total number of non-volatile memory components. According to the selection order, the selection intervals of the non-volatile memory components 122-1, 122-2, and 122-3 relative to the non-volatile memory component 122-4 are 3 (e.g., (3 - 0) = 3), 2 (e.g., (3 - 1) = 2), and 1 (e.g., (3 - 2) = 1), respectively. Assuming the preset selection interval is 3, the memory components within the preset selection interval correspond to the non-volatile memory component 122-1. The memory controller 110 may check whether the non-volatile memory component 122-1 is in a busy state or a non-busy state. According to this embodiment, the non-busy state may be a ready state, but the present invention is not limited thereto.

[0063] In step 308, the memory controller 110 may wait for a preset time; then, step 306 is executed. Since the non-volatile memory components 122-1, 122-2, and 122-3 have been selected and are currently being programmed, in order to prevent the memory device 100 from consuming too much power, the memory controller 110 waits for a preset time, e.g., 50 ns, and then executes step 306 to determine whether the non-volatile memory component 122-1 has been programmed. If so, the programming of the non-volatile memory component 122-4 is then performed.

[0064] In step 310, the memory controller 110 may start programming this memory component. When the non-volatile memory component 122-1 has been programmed and enters the non-busy state, the memory controller 110 may program the selected non-volatile memory component 122-4. In this way, the method 300 can avoid programming the selected non-volatile memory component 122-4 until the non-volatile memory component 122-1 enters the non-busy state and then program the selected non-volatile memory component 122-4, so as to achieve at least one object of the present invention. Then, the operation of the method 300 ends.

[0065] In addition, step 310 may further include deleting the selection order of this memory component. After that, when method 300 is executed again, since the selection order of the memory components that have been programmed is deleted, the non-volatile memory components corresponding to the remaining selection order are still being programmed and are in a busy state. Therefore, the judgment result of step 306 conforms to the actual situation of non-volatile memory components 122-1, 122-2, 122-3, and 122-4.

[0066] In the above embodiment, the selection and programming order of non-volatile memory components 122-1, 122-2, 122-3, and 122-4 is randomly selected. Therefore, step 304 is necessary. In another implementation, the selection of non-volatile memory components 122-1, 122-2, 122-3, and 122-4 is fixed, that is, the selection order is fixed. In this case, step 304 is unnecessary and can be omitted.

[0067] In the above embodiment, the value of the preset programming interval may preferably be equal to the total number of non-volatile memory components minus one; however, the present invention is not limited thereto. For example, the value of the preset programming interval may be any positive integer less than the total number of non-volatile memory components.

[0068] Figure 4 FIG. 320 is a flowchart of a method 320 for programming management in a memory device according to another embodiment of the present invention. Among them, steps 322, 328, and 330 are respectively equivalent to steps 302, 308, and 310, and steps 324 and 326 are respectively different from steps 304 and 306.

[0069] In step 324, the memory controller 110 may judge the status of other memory components. For example, when non-volatile memory components 122-1, 122-2, and 122-3 have been selected and are being programmed, the status of non-volatile memory components 122-1, 122-2, and 122-3 is all in a busy state.

[0070] In step 326, the memory controller 110 may determine whether the total number of memory components in the busy recording state is less than a preset value. If so, step 330 is executed; if not, step 328 is executed. Assume that the preset value is 3. In this case, since the states of the non-volatile memory components 122-1, 122-2, and 122-3 are all in the busy recording state, the total number of busy recording states is not less than 3, so step 328 is executed. When the state of one of the non-volatile memory components 122-1, 122-2, and 122-3 changes from the busy recording state to the non-busy state, for example: the non-volatile memory component 122-1 first completes programming and changes from the busy recording state to the non-busy state, making the total number of memory components in the busy recording state less than the preset value, so step 330 is executed to program the non-volatile memory component 122-4.

[0071] According to some embodiments, before programming a target non-volatile memory component 122-n among the multiple non-volatile memory components 122-1, 122-2, …, and 122-N (the symbol “n” can represent any positive integer falling within the range [1, N]), the memory controller 110 can check whether another non-volatile memory component among the multiple non-volatile memory components 122-1, 122-2, …, and 122-N is in the busy state or the non-busy state. For example, the non-busy state can be the ready state, but the present invention is not limited thereto. When the other non-volatile memory component enters the non-busy state, the memory controller 110 can program the target non-volatile memory component 122-n. For example, the memory controller 110 can avoid programming the target non-volatile memory component 122-n until the other non-volatile memory component enters the non-busy state. In a predetermined logic sequence of the multiple non-volatile memory components 122-1, 122-2, …, and 122-N, the other non-volatile memory component is a subsequent non-volatile memory component of the target non-volatile memory component 122-n. For ease of understanding, the predetermined logic sequence can be {{122-1, 122-2, …, 122-N}, {122-1, 122-2, …, 122-N}, …} (which is composed of repetitions of the sequence {122-1, 122-2, …, 122-N}), but the present invention is not limited thereto. When the target non-volatile memory component 122-n represents a certain non-volatile memory component in the predetermined logic sequence {{122-1, 122-2, …, 122-N}, {122-1, 122-2, …, 122-N}, …}, among the predetermined logic sequence {{122-1, 122-2, …, 122-N}, {122-1, 122-2, …, 122-N}, …}, the other non-volatile memory component is located after this non-volatile memory component. For example: in the predetermined logic sequence, the other non-volatile memory component can be the next non-volatile memory component of the target non-volatile memory component 122-n, such as the non-volatile memory component 122-(n + 1) or the non-volatile memory component 122-(n + 1 - N), where, if n < N, the next non-volatile memory component represents the non-volatile memory component 122-(n + 1), otherwise (this means n = N), the next non-volatile memory component represents the non-volatile memory component 122-(n + 1 - N) (which is 122-1 when n = N).In this situation, among the multiple non-volatile memory components 122-1, 122-2, … and 122-N, the maximum value of the number of non-volatile memory components simultaneously in the busy state can be equal to the total number of the multiple non-volatile memory components 122-1, 122-2, … and 122-N minus one. Additionally, the predetermined logic sequence can indicate the order of the programming operations applicable to the multiple non-volatile memory components 122-1, 122-2, … and 122-N. In response to at least one request from outside the memory device 100, the memory controller 110 can program the multiple non-volatile memory components 122-1, 122-2, … and 122-N in turn according to the predetermined logic sequence. For example, the at least one request can represent at least one write instruction transmitted by the host device 200 to the memory device 100. In response to the at least one write instruction, the memory device 100 can perform a series of programming operations on the multiple non-volatile memory components 122-1, 122-2, … and 122-N to store a series of data into the non-volatile memory 120 as soon as possible while avoiding problems of related technologies (such as the instantaneous power consumption exceeding the predetermined product specifications). Based on method 200, the memory controller 110 can manage the series of programming operations to achieve the optimized performance of the memory device 100 without side effects or with less likelihood of side effects.

[0072] According to some embodiments, the memory controller 110 may program a group of non-volatile memory components among the plurality of non-volatile memory components 122-1, 122-2, …, and 122-N simultaneously, and make the number of the group of non-volatile memory components less than or equal to a predetermined non-volatile memory element count, where the predetermined non-volatile memory element count is less than the total number of the plurality of non-volatile memory components 122-1, 122-2, …, and 122-N. For example, during the operation of checking whether the other non-volatile memory component is in the busy state or the non-busy state, the target non-volatile memory component 122-n has not been selected as a non-volatile memory component in the group of non-volatile memory components. When the other non-volatile memory component enters the non-busy state, the memory controller 110 may select the target non-volatile memory component 122-n as the non-volatile memory component in the group of non-volatile memory components. Another example: before the operation of checking whether the other non-volatile memory component is in the busy state or the non-busy state is performed, the other non-volatile memory component has been selected as one of the group of non-volatile memory components. When the other non-volatile memory component enters the non-busy state, the other non-volatile memory component is no longer one of the group of non-volatile memory components.

[0073] Figure 5 A chip-enable (CE) control scheme illustrated in an embodiment, and the chip-enable control scheme can be applied to Figure 3 the method 300 shown and Figure 4The method 320 shown. Assume N = 4, but the present invention is not limited thereto. In this case, the plurality of non-volatile memory components 122-1, 122-2, … and 122-N may represent four non-volatile memory components 122-1, 122-2, 122-3, and 122-4. The memory controller 110 may control the states of the chip enable signals CE1, CE2, CE3, CE4 respectively to enable or disable these four non-volatile memory components 122-1, 122-2, 122-3, and 122-4. For example: when any one of the chip enable signals CE1, CE2, CE3, CE4 is at a low voltage level, the non-volatile memory component controlled by this chip enable signal may be in the busy state. Another example: when any one of the chip enable signals CE1, CE2, CE3, CE4 is at a high voltage level, the non-volatile memory component controlled by this chip enable signal may be in the non-busy state, such as the ready state. When needed, the memory controller 110 may poll any one of the chip enable signals CE1, CE2, CE3, CE4 to know whether the non-volatile memory component controlled by this chip enable signal is in the busy state or the non-busy state. According to this embodiment, the memory controller 110 may control the chip enable signals CE1, CE2, CE3, CE4 to be at the low voltage level simultaneously, but the present invention is not limited thereto.

[0074] Figure 6 A power consumption control scheme shown in an embodiment, and the power consumption control scheme can be applied to Figure 3 the method 300 shown and Figure 4 the method 320 shown. Figure 6 The horizontal axis shown represents time. The respective power consumptions PWR1, PWR2, PWR3, PWR4 of the non-volatile memory components 122-1, 122-2, 122-3, and 122-4 may be presented in various different shades, where the heavily shaded part may represent the high power consumption caused by the programming operation, the lightly shaded part may represent the low power consumption caused by the non-programming operation, and the non-shaded part may represent no power consumption or extremely low power consumption. As Figure 6 shown in the upper half, assume that programming the non-volatile memory components 122-1, 122-2, 122-3, and 122-4 simultaneously may cause the power consumption of the memory device 100 to exceed a predetermined power limitation. As Figure 6As shown in the lower part, the memory controller 110 can be programmed and managed based on method 300 to avoid such problems, where the arrow pointing to the end of some heavily shaded parts can indicate that the memory controller 110 can achieve the optimized performance of the memory device 100.

[0075] According to this embodiment, the memory controller 110 can control the number of non-volatile memory components that are simultaneously in the busy state among the non-volatile memory components 122-1, 122-2, 122-3, and 122-4. For example: among the non-volatile memory components 122-1, 122-2, 122-3, and 122-4, the maximum value of the number of non-volatile memory components that are simultaneously in the busy state can be equal to the total number of non-volatile memory components 122-1, 122-2, 122-3, and 122-4 minus one, that is, 3, where the predetermined logical sequence can be {{122-1, 122-2, 122-3, 122-4}, {122-1, 122-2, 122-3, 122-4},...}, but the present invention is not limited thereto. Thus, the memory controller 110 can maintain the number of non-volatile memory components that are simultaneously programmed among the non-volatile memory components 122-1, 122-2, 122-3, and 122-4 to not exceed the predetermined number of non-volatile memory components, so as to control the power consumption of the memory device 100 within the predetermined power limit.

[0076] The above are only the preferred embodiments of the present invention and are not used to limit the present invention. For those skilled in the art, the present invention can have various changes and modifications. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included within the protection scope of the present invention.

Claims

1. A method for programming management in a memory device, the memory device including a non-volatile memory, the non-volatile memory including a plurality of non-volatile memory components, characterized in that, The method includes: Before programming a target non-volatile memory component among the multiple non-volatile memory components, checking whether another non-volatile memory component among the multiple non-volatile memory components has completed programming; And When the another non-volatile memory component has completed programming and enters a non-busy state, programming the target non-volatile memory component, where When the multiple non-volatile memory components are selected, they respectively correspond to a selection order, and the another non-volatile memory component is a non-volatile memory component having a preset selection interval relative to the target non-volatile memory component.

2. The method according to claim 1, wherein The multiple non-volatile memory components respectively represent multiple flash die, and the value of the preset selection interval is less than the total number of the multiple non-volatile memory components or equal to the total number of the multiple non-volatile memory components minus one.

3. The method according to claim 1, wherein During the operation of checking whether the another non-volatile memory component has completed programming, checking whether the another non-volatile memory component is in a busy state or the non-busy state.

4. The method according to claim 3, wherein The method further includes: Simultaneously programming a group of non-volatile memory components among the multiple non-volatile memory components, and making the number of the group of non-volatile memory components less than or equal to a predetermined number of non-volatile memory components, where the predetermined number of non-volatile memory components is less than the total number of the multiple non-volatile memory components.

5. The method according to claim 4, wherein During the operation of checking whether the another non-volatile memory component is in the busy state or the non-busy state, the target non-volatile memory component has not been selected as a non-volatile memory component in the group of non-volatile memory components; And the method further includes: When the another non-volatile memory component enters the non-busy state, selecting the target non-volatile memory component as the non-volatile memory component in the group of non-volatile memory components.

6. The method according to claim 4, wherein Before the operation of checking whether the another non-volatile memory component is in the busy state or the non-busy state is performed, the another non-volatile memory component has been selected as one of the group of non-volatile memory components; and when the another non-volatile memory component enters the non-busy state, the another non-volatile memory component is not one of the group of non-volatile memory components.

7. A memory device, characterized in that, It includes: A non-volatile memory for storing information, where the non-volatile memory includes multiple non-volatile memory components; And A controller coupled to the non-volatile memory for controlling the operation of the memory device, where the controller includes: A processing circuit for controlling the controller according to an instruction from a host device, To allow the host device to access the non-volatile memory through the controller, where: Before programming a target non-volatile memory component among the multiple non-volatile memory components, the controller checks whether another non-volatile memory component among the multiple non-volatile memory components has completed programming; and When the other non-volatile memory component has completed programming and enters a non-busy state, the controller programs the target non-volatile memory component, where the multiple non-volatile memory components respectively correspond to a selection order when selected, and the other non-volatile memory component is a non-volatile memory component having a preset selection interval relative to the target non-volatile memory component.

8. The memory device according to claim 7, wherein the multiple non-volatile memory components respectively represent multiple flash die, and the value of the preset selection interval is less than the total number of the multiple non-volatile memory components or equal to the total number of the multiple non-volatile memory components minus one.

9. A controller of a memory device, the memory device including the controller and a non-volatile memory, the non-volatile memory including a plurality of non-volatile memory components, characterized in that, The controller includes: a processing circuit for controlling the controller according to an instruction from a host device to allow the host device to access the non-volatile memory through the controller, where: before programming a target non-volatile memory component among the multiple non-volatile memory components, the controller checks whether another non-volatile memory component among the multiple non-volatile memory components has completed programming; and when the other non-volatile memory component has completed programming and enters a non-busy state, the controller programs the target non-volatile memory component, where the multiple non-volatile memory components respectively correspond to a selection order when selected, and the other non-volatile memory component is a non-volatile memory component having a preset selection interval relative to the target non-volatile memory component.

10. The controller according to claim 9, characterized in that, the multiple non-volatile memory components respectively represent multiple flash die, and the value of the preset selection interval is less than the total number of the multiple non-volatile memory components or equal to the total number of the multiple non-volatile memory components minus one.

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