Memory system, memory device, and method for operating a memory device

Abstract

Embodiments of the disclosed technology relate to a memory system, a memory device, and a method for operating the memory device. Based on embodiments of the disclosed technology, when programming data into a first memory cell in a first memory block in turbo programming mode, the memory device may apply a first number of programming pulses to the first memory cell, the first number of programming pulses being less than the number of programming pulses applied to the first memory cell when writing data to the first memory cell in the case of resetting the turbo programming mode. When migrating the data to be written to the first memory cell to a second memory cell in a second memory block, the memory device may apply a second number of programming pulses to the second memory cell, the second number of programming pulses being greater than the first number of programming pulses.

Description

[0001] Cross - reference to related applications

[0002] This patent document claims the priority and benefit of a Korean patent application filed on Jul. 27, 2020, with application number 10 - 2020 - 0092868, which is incorporated herein by reference in its entirety. Technical field

[0003] Embodiments of the disclosed technology relate to a memory system, a memory device, and a method for operating a memory device. Background art

[0004] A memory system includes a data storage device that stores data based on requests from a host such as a computer, a server, a smart phone, or a tablet PC or other electronic device. Examples of memory systems range from traditional disk - based hard disk drives (HDDs) to semiconductor - based data storage devices such as solid - state drives (SSDs), universal flash storage devices (UFSs), or embedded MMC (eMMC) devices.

[0005] The memory system may further include a memory controller for controlling the memory device. The memory controller may receive commands from the host and, based on the received commands, may execute the commands or control read / write / erase operations on the memory devices (volatile memory and / or non - volatile memory) included in the memory system. The memory controller may execute firmware operations that perform logical operations for controlling such operations.

[0006] As the speed of data communication between the memory system and the host increases, there is a requirement for the memory system to provide better performance to meet the quality - of - service (QoS) requirements of the host. To meet such requirements of the memory system, various technologies are being developed to increase the write speed and data storage capacity of the memory system. Summary of the invention

[0007] The technology disclosed in this patent document, which can be implemented in some embodiments of the disclosed technology, may provide a memory system, a memory device, and a method for operating a memory device that can provide a faster write speed.

[0008] In addition, embodiments of the disclosed technology may provide a memory system, a memory device, and a method for operating a memory device that can significantly increase the speed of write operations without affecting the reliability of the write operations.

[0009] On the one hand, embodiments of the disclosed technology may provide a memory system that includes: a memory device; and a memory controller that communicates with the memory device and is configured to control the memory device to perform operations.

[0010] The memory device may include a first storage block and a second storage block, each of the first storage block and the second storage block including memory cells for storing data and being operable to perform operations on one or more memory cells, the operations including a read operation for reading data stored in one or more memory cells and a program operation for writing new data into one or more memory cells.

[0011] The memory controller may determine whether to set or reset the turbo programming mode and may determine the number of program pulses applied when writing data to the first storage block in the turbo programming mode.

[0012] When writing data to a first memory cell included in the first storage block in a state where the turbo programming mode is set, the memory device may apply a first number of program pulses to the first memory cell.

[0013] When migrating data from the first memory cell to a second memory cell included in the second storage block, the memory device may apply a second number of program pulses to the second memory cell.

[0014] The first number of program pulses may be less than the number of program pulses applied when writing data to the first memory cell in a state where the turbo programming mode is reset.

[0015] The second number of program pulses may be greater than the first number of program pulses.

[0016] The number of data bits stored in the first memory cell may be less than the number of data bits stored in the second memory cell.

[0017] Meanwhile, the memory device may determine the first number of program pulses based on a maximum retention time corresponding to a maximum time for which data is retained in the first memory cell.

[0018] The program pulses may be ISPP (Incremental Step Pulse Programming) voltage pulses. The memory device may determine the voltage difference between the program pulses to be applied to the first memory cell based on the maximum retention time.

[0019] The memory device may differently determine the time point for migrating data from the first memory cell to the second memory cell based on the access frequency of the data stored in the first memory cell.

[0020] When the memory device is in an idle state, the memory device may migrate data from a first memory cell to a second memory cell.

[0021] On the other hand, embodiments of the disclosed technology may provide a memory device.

[0022] The memory device may include: a first memory block including first memory cells for storing data and operable to perform a programming operation for writing data into the first memory cells; and a second memory block including second memory cells for storing data and operable to perform a programming operation for writing data into the second memory cells.

[0023] When writing data into the first memory cells included in the first memory block in a state where the turbo programming mode is set, the memory device may apply a first number of programming pulses to the first memory cells, where the number of programming pulses to be applied to the first memory block may be determined in the turbo programming mode.

[0024] When migrating data from the first memory cells to the second memory cells included in the second memory block, the memory device may apply a second number of programming pulses to the second memory cells.

[0025] The first number of programming pulses may be less than the number of programming pulses applied when writing data into the first memory cells in a state where the turbo programming mode is reset.

[0026] The second number of programming pulses may be greater than the first number of programming pulses.

[0027] On the other hand, embodiments of the disclosed technology may provide a method for operating a memory device including a first memory block and a second memory block.

[0028] The method for operating the memory device may include the step of writing data by applying a first number of programming pulses to the first memory cells included in the first memory block in a state where the turbo programming mode is set, where the number of programming pulses applied when writing data into the first memory block may be determined in the turbo programming mode.

[0029] In addition, the method for operating the memory device may include the step of migrating data from the first memory cells to the second memory cells by applying a second number of programming pulses to the second memory cells included in the second memory block.

[0030] The first number of programming pulses may be less than the number of programming pulses applied when writing data into the first memory cells in a state where the turbo programming mode is reset.

[0031] The second quantity of programming pulses can be greater than the first quantity of programming pulses.

[0032] The number of data bits stored in the first memory cell can be less than the number of data bits stored in the second memory cell.

[0033] Meanwhile, the first quantity of programming pulses can be determined based on a maximum retention time corresponding to a maximum time for which data is retained in the first memory cell.

[0034] The programming pulses can be ISPP (Incremental Step Pulse Programming) voltage pulses. The voltage difference between the programming pulses to be applied to the first memory cell can be determined based on the maximum retention time. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1 is a schematic diagram showing a configuration of a memory system according to an embodiment of the disclosed technology.

[0036] Figure 2 is a block diagram schematically showing a memory device according to an embodiment of the disclosed technology.

[0037] Figure 3 is a diagram showing a structure of word lines and bit lines of a memory device according to an embodiment of the disclosed technology.

[0038] Figure 4 is a diagram showing an operation of a memory device according to an embodiment of the disclosed technology.

[0039] Figure 5 is a diagram showing an operation of a memory device applying programming pulses to a first memory cell according to an embodiment of the disclosed technology.

[0040] Figure 6 is a diagram showing a maximum retention time in some embodiments of the disclosed technology.

[0041] Figure 7 is a diagram showing an example of a first pulse quantity based on a maximum retention time in some embodiments of the disclosed technology.

[0042] Figure 8 is a diagram showing an example of a voltage difference between ISPP pulses based on a maximum retention time in some embodiments of the disclosed technology.

[0043] Figure 9 is a flowchart showing an example of an operation of migrating data from a first memory cell to a second memory cell in some embodiments of the disclosed technology.

[0044] Figure 10A flowchart showing another example of an operation for migrating data from a first memory cell to a second memory cell in some embodiments of the disclosed technology.

[0045] Figure 11 A flowchart showing a method for operating a memory device based on some embodiments of the disclosed technology.

[0046] Figure 12 A diagram showing the configuration of a computing system based on some embodiments of the disclosed technology. Detailed Description

[0047] Hereinafter, embodiments of the disclosed technology will be described in detail with reference to the accompanying drawings.

[0048] Figure 1 A diagram showing a schematic configuration of a memory system 100 based on embodiments of the disclosed technology.

[0049] In some embodiments, the memory system 100 may include a memory device 110 configured to store data, and a memory controller 120 configured to control the memory device 110.

[0050] The memory device 110 may include a plurality of memory blocks, each memory block including a predetermined number of memory cells for storing data. The memory device 110 may be configured to operate in response to control signals received from the memory controller 120. Operations of the memory device 110 may include, for example, a read operation for reading data stored in one or more memory cells, a programming operation (also referred to as a “write operation”) for writing new data into one or more memory cells, and an erase operation for deleting or erasing data stored in one or more memory cells.

[0051] The memory cells in the memory device 110 may be used to store data and may be arranged in a memory cell array including a plurality of memory cells. In some embodiments where the memory device 110 is a flash memory device, the memory cell array may be divided into memory blocks of memory cells, and each memory block includes different pages of memory cells. In some embodiments of a NAND flash memory device, a page of cells is the smallest memory unit that can be programmed (or written) and read, and data stored in the memory cells can be erased at the memory block level.

[0052] In some embodiments, the memory device 110 may be implemented as various types such as: double data rate synchronous dynamic random access memory (DDR SDRAM), low power double data rate 4th generation (LPDDR4) SDRAM, graphics double data rate (GDDR) SDRAM, low power DDR (LPDDR), Rambus dynamic random access memory (RDRAM), NAND flash memory, vertical NAND flash memory, NOR flash memory, resistive random access memory (RRAM), phase change random access memory (PRAM), magnetoresistive random access memory (MRAM), ferroelectric random access memory (FRAM), or spin transfer torque random access memory (STT-RAM).

[0053] The memory device 110 may be implemented in a three-dimensional array structure. Some embodiments of the disclosed technology may be applied to any type of flash memory device having a charge storage layer. In an embodiment, the charge storage layer may be formed of a conductive material, and such a charge storage layer may be referred to as a conductive floating gate. In another embodiment, the charge storage layer may be formed of an insulating material, and such a flash memory device is generally referred to as a charge trapping flash (CTF).

[0054] The memory device 110 may be configured to receive commands and addresses from the memory controller 120 to access a region of the memory cell array selected using the address. That is, the memory device 110 may perform an operation corresponding to the received command on a memory region in the memory device, the memory region having a physical address corresponding to the address received from the memory controller 120.

[0055] In some embodiments, the memory device 110 may perform programming (write) operations, read operations, erase operations, etc. During a programming operation, the memory device 110 may program data in a memory location selected by the address. During a read operation, the memory device 110 may read data from the region selected by the address. During an erase operation, the memory device 110 may erase data stored in the memory location selected by the address.

[0056] The memory controller 120 may control write operations (programming operations), read operations, erase operations, and background operations to be performed on the memory device 110. Background operations may include operations implemented to optimize the overall performance of the memory device 110 such as: garbage collection (GC) operations, wear leveling (WL) operations, and bad block management (BBM) operations.

[0057] The memory controller 120 can control the operation of the memory device 110 at the request of the host. Optionally, when the memory controller 120 performs such background operations of the memory device, even without a request from the host, the memory controller 120 can control the operation of the memory device 110.

[0058] The memory controller 120 and the host can be separate devices. In some embodiments, the memory controller 120 and the host can be integrated in a single device. In the following description, the memory controller 120 and the host are discussed as separate devices, for example.

[0059] Referring Figure 1 , the memory controller 120 can include a memory interface 122, a control circuit 123, and a host interface 121.

[0060] The host interface 121 can be configured to provide an interface for communicating with the host.

[0061] When receiving a command from the host HOST, the control circuit 123 can receive the command through the host interface 121 and can perform operations to process the received command.

[0062] The memory interface 122 can be directly or indirectly connected to the memory device 110 to provide an interface for communicating with the memory device 110. That is, the memory interface 122 can be configured to provide an interface to the memory device 110 and the memory controller 120 for the memory controller 120 to perform memory operations on the memory device 110 based on control signals and commands from the control circuit 123.

[0063] The control circuit 123 can be configured to control the operation of the memory device 110. For example, the control circuit 123 can include a processor 124 and a working memory 125. The control circuit 123 can further include an error detection / correction circuit (ECC circuit) 126.

[0064] The processor 124 can control all operations of the memory controller 120. The processor 124 can perform logical operations. The processor 124 can communicate with the host HOST through the host interface 121. The processor 124 can communicate with the memory device 110 through the memory interface 122.

[0065] The processor 124 can perform the functions of a flash translation layer (FTL) to effectively manage memory operations on the memory system 100. The processor 124 can convert a logical block address (LBA) provided by the host to a physical block address (PBA) through the FTL. The FTL can receive the LBA and convert the LBA to the PBA by using a mapping table.

[0066] Based on the mapping unit, the FTL can adopt various address mapping methods. Typical address mapping methods can include page mapping method, block mapping method, and hybrid mapping method.

[0067] The processor 124 can be configured to randomize the data received from the host to write the randomized data into the memory cell array. For example, the processor 124 can randomize the data received from the host by using a randomization seed. The randomized data is provided to the memory device 110 and written into the memory cell array.

[0068] The processor 124 can be configured to derandomize the data received from the memory device 110 during a read operation. For example, the processor 124 can derandomize the data received from the memory device 110 by using a derandomization seed. The derandomized data can be output to the host HOST.

[0069] The processor 124 can run firmware (FW) to control the operation of the memory controller 120. In other words, the processor 124 can control all operations of the memory controller 120 and, to perform logical operations, can run (drive) the firmware loaded into the working memory 125 during startup.

[0070] Firmware refers to a program or software stored on a certain non-volatile memory and running inside the memory system 100.

[0071] In some embodiments, the firmware can include various functional layers. For example, the firmware can include at least one of the following: a flash translation layer (FTL) configured to convert a logical address in a host HOST request into a physical address of the memory device 110; a host interface layer (HIL) configured to interpret commands issued by the host HOST to a data storage device such as the memory system 100 (storage device) and pass the command to the FTL; and a flash interface layer (FIL) configured to pass commands issued by the FTL to the memory device 110.

[0072] For example, the firmware can be stored in the memory device 110 and then loaded into the working memory 125.

[0073] The working memory 125 can store the firmware, program code, commands, or data items required to operate the memory controller 120. The working memory 125 can include, for example, at least one of static RAM (SRAM), dynamic RAM (DRAM), and synchronous RAM (SDRAM) as volatile memories.

[0074] The error detection / correction circuit 126 may be configured to detect and correct one or more error bits in data by using error detection and correction codes. For example, the data subjected to error detection and correction may include the data stored in the working memory 125 and the data retrieved from the memory device 110.

[0075] The error detection / correction circuit 126 may be implemented to decode data by using an error correction code. The error detection / correction circuit 126 may be implemented by using various decoding schemes. For example, a decoder that performs non-systematic code decoding or a decoder that performs systematic code decoding may be used.

[0076] In some embodiments, the error detection / correction circuit 126 may detect one or more error bits based on sectors. That is, each piece of read data may include a plurality of sectors. In this patent document, a sector may refer to a data unit smaller than a read unit (page) of a flash memory. The sectors constituting the read data may be mapped to addresses.

[0077] The error detection / correction circuit 126 may calculate a bit error rate (BER) and determine, on a sector-by-sector basis, whether the number of error bits in the data is within the error correction capability. For example, if the BER is higher than a reference value, the error detection / correction circuit 126 may determine that the error bits in the corresponding sector are uncorrectable and mark the corresponding sector as "failed". If the BER is less than or equal to the reference value, the error detection / correction circuit 126 may determine that the corresponding sector is correctable or may mark the corresponding sector as "passed".

[0078] The error detection / correction circuit 126 may sequentially perform error detection and correction operations on all the read data. When the sectors included in the read data are correctable, the error detection / correction circuit 126 may proceed to the next sector to check whether an error correction operation is required for the next sector. After completing the error detection and correction operations on all the read data in this manner, the error detection / correction circuit 126 may obtain information about which sectors are considered uncorrectable. The error detection / correction circuit 126 may provide the information (e.g., the addresses of the uncorrectable sectors) to the processor 124.

[0079] The memory system 100 may further include a bus 127 to provide a channel between the components 121, 122, 124, 125, and 126 of the memory controller 120. The bus 127 may include, for example, a control bus for transmitting various types of control signals and commands and a data bus for transmitting various types of data.

[0080] The above-described components 121, 122, 124, 125, and 126 of the memory controller 120 are provided only as examples. Note that some of the above-described components 121, 122, 124, 125, and 126 of the memory controller 120 may be omitted, or some of the above-described components 121, 122, 124, 125, and 126 of the memory controller 120 may be integrated into a single component. In some embodiments, one or more other components may be added to the memory controller 120.

[0081] Figure 2 is a block diagram schematically showing a memory device 110 according to an embodiment of the disclosed technology.

[0082] In some embodiments, a memory device 110 according to an embodiment of the disclosed technology may include a memory cell array 210, an address decoder 220, a read / write circuit 230, control logic 240, and a voltage generation circuit 250.

[0083] The memory cell array 210 may include a plurality of memory blocks BLK1 to BLKz, where z is a natural number equal to or greater than 2.

[0084] In the plurality of memory blocks BLK1 to BLKz, a plurality of word lines WL and a plurality of bit lines BL may be arranged in rows and columns, and a plurality of memory cells MC may be arranged.

[0085] The plurality of memory blocks BLK1 to BLKz may be connected to the address decoder 220 through a plurality of word lines WL. The plurality of memory blocks BLK1 to BLKz may be connected to the read / write circuit 230 through a plurality of bit lines BL.

[0086] Each of the plurality of memory blocks BLK1 to BLKz may include a plurality of memory cells. For example, the plurality of memory cells are non-volatile memory cells. In some embodiments, such non-volatile memory cells may be arranged in a vertical channel structure.

[0087] The memory cell array 210 may be configured as a memory cell array having a two-dimensional structure. In some embodiments, the memory cell array 210 may be arranged in a three-dimensional structure.

[0088] Each of the plurality of memory cells included in the memory cell array 210 can store at least one bit of data. For example, each of the plurality of memory cells included in the memory cell array 210 can be a single-level cell (SLC) configured to store one bit of data per memory cell. As another example, each of the plurality of memory cells included in the memory cell array 210 can be a multi-level cell (MLC) configured to store two bits of data per memory cell. As another example, each of the plurality of memory cells included in the memory cell array 210 can be a three-level cell (TLC) configured to store three bits of data per memory cell. As another example, each of the plurality of memory cells included in the memory cell array 210 can be a quad-level cell (QLC) configured to store four bits of data per memory cell. As another example, the memory cell array 210 can include a plurality of memory cells, and each of the plurality of memory cells can be configured to store at least five bits of data per memory cell.

[0089] Referring to Figure 2 , the address decoder 220, the read / write circuit 230, the control logic 240, and the voltage generation circuit 250 can operate as peripheral circuits configured to drive the memory cell array 210.

[0090] The address decoder 220 can be connected to the memory cell array 210 through a plurality of word lines WL.

[0091] The address decoder 220 can be configured to operate in response to commands and control signals from the control logic 240.

[0092] The address decoder 220 can receive an address through an input / output buffer inside the memory device 110. The address decoder 220 can be configured to decode the block address among the received addresses. The address decoder 220 can select at least one memory block based on the decoded block address.

[0093] The address decoder 220 can receive a read voltage Vread and a pass voltage Vpass from the voltage generation circuit 250.

[0094] During a read operation, the address decoder 220 can apply the read voltage Vread to the selected word line WL inside the selected memory block, and apply the pass voltage Vpass to the remaining unselected word lines WL.

[0095] During a program verification operation, the address decoder 220 can apply a verification voltage generated by the voltage generation circuit 250 to the selected word line WL inside the selected memory block, and can apply the pass voltage Vpass to the remaining unselected word lines WL.

[0096] The address decoder 220 may be configured to decode the column addresses among the received addresses. The address decoder 220 may transmit the decoded column addresses to the read / write circuit 230.

[0097] The memory device 110 may perform read operations and program operations page by page. The addresses received when read operations and program operations are requested may include at least one of a block address, a row address, and a column address.

[0098] The address decoder 220 may select a memory block and a word line based on the block address and the row address. The column address may be decoded by the address decoder 220 and provided to the read / write circuit 230.

[0099] The address decoder 220 may include at least one of a block decoder, a row decoder, a column decoder, and an address buffer.

[0100] The read / write circuit 230 may include a plurality of page buffers PB. When the memory cell array 210 performs a read operation, the read / write circuit 230 may operate as a "read circuit", and when the memory cell array 210 performs a write operation, the read / write circuit 230 may operate as a "write circuit".

[0101] The above-mentioned read / write circuit 230 is also referred to as a page buffer circuit including a plurality of page buffers PB, or a data register circuit. The read / write circuit 230 may include data buffers participating in data processing functions, and in some embodiments, may further include cache buffers for data caching.

[0102] The plurality of page buffers PB may be connected to the memory cell array 210 through a plurality of bit lines BL. In order to detect or sense the threshold voltage Vth of the memory cells during read operations and program verification operations, the plurality of page buffers PB may continuously supply sense currents to the bit lines BL connected to the memory cells to detect a change in the amount of current that changes according to the programming state of the corresponding memory cells at the sense nodes, and may hold or latch the corresponding voltages as sense data.

[0103] The read / write circuit 230 may operate in response to page buffer control signals output from the control logic 240.

[0104] During a read operation, the read / write circuit 230 senses the voltage value of a memory cell and reads out the voltage value as data. The read / write circuit 230 temporarily stores the retrieved data and outputs the data DATA to the input / output buffer of the memory device 110. In an embodiment, in addition to the page buffer PB or the page register, the read / write circuit 230 may further include a column selection circuit.

[0105] The control logic 240 may be connected to the address decoder 220, the read / write circuit 230, and the voltage generation circuit 250. The control logic 240 may receive a command CMD and a control signal CTRL through the input / output buffer of the memory device 110.

[0106] The control logic 240 may be configured to control all operations of the memory device 110 in response to the control signal CTRL. The control logic 240 may output a control signal for adjusting the voltage level of the sense nodes of the plurality of page buffers PB to a precharge voltage level.

[0107] The control logic 240 may control the read / write circuit 230 to perform a read operation in the memory cell array 210. The voltage generation circuit 250 may generate a read voltage Vread and a pass voltage Vpass used during the read operation in response to a voltage generation circuit control signal output from the control logic 240.

[0108] The memory block BLK included in the memory device 110 may include a plurality of pages PG. In some embodiments, a plurality of memory cells arranged in columns form a memory cell string, and a plurality of memory cells arranged in rows form a page. Each of the plurality of pages PG is coupled to one of the word lines WL, and each of the memory strings STR is coupled to one of the bit lines BL.

[0109] In the memory block BLK, the plurality of word lines WL and the plurality of bit lines BL may be arranged in rows and columns. For example, each of the plurality of word lines WL may be arranged in a row direction, and each of the plurality of bit lines BL may be arranged in a column direction. As another example, each of the plurality of word lines WL may be arranged in a column direction, and each of the plurality of bit lines BL may be arranged in a row direction.

[0110] In some embodiments, the plurality of word lines WL and the plurality of bit lines BL may intersect each other to address a single memory cell in the array of the plurality of memory cells MC. In some embodiments, each memory cell MC may include a transistor TR, and the transistor TR includes a material layer that can hold charge.

[0111] For example, the transistor TR disposed in each memory cell MC may include a drain, a source, and a gate. The drain (or source) of the transistor TR may be directly or via another transistor TR connected to the corresponding bit line BL. The source (or drain) of the transistor TR may be directly or via another transistor TR connected to the source line (which may be ground). The gate of the transistor TR may include a floating gate (FG) surrounded by an insulator and a control gate (CG) to which a gate voltage is applied from the word line WL.

[0112] In each of the plurality of memory blocks BLK1 to BLKz, a first selection line (also referred to as a source selection line or a drain selection line) may be additionally disposed outside the first outermost word line closer to the read / write circuit 230 among the two outermost word lines, and a second selection line (also referred to as a drain selection line or a source selection line) may be additionally disposed outside the other second outermost word line.

[0113] In some embodiments, at least one dummy word line may be additionally disposed between the first outermost word line and the first selection line. Additionally, at least one dummy word line may be additionally disposed between the second outermost word line and the second selection line.

[0114] The read operation and the programming operation (write operation) of the memory block may be performed page by page, and the erase operation may be performed block by block.

[0115] Figure 3 is a diagram showing the structure of the word line WL and the bit line BL of the memory device 110 according to an embodiment of the disclosed technology.

[0116] In some embodiments, the memory device 110 has a core region in which memory cells MC are arranged, and an auxiliary region for including circuits (e.g., the remaining region other than the core region) for performing operations of the memory cell array 210.

[0117] In the core region, a certain number of memory cells arranged in one direction may be referred to as a "page" PG, and a certain number of memory cells connected in series may be referred to as a "memory cell string" STR.

[0118] The word lines WL1 to WL9 may be connected to the row decoder 310. The bit line BL may be connected to the column decoder 320. The data register 330 corresponding to Figure 2 the read / write circuit 230 may be present between the plurality of bit lines BL and the column decoder 320.

[0119] The plurality of word lines WL1 to WL9 may correspond to the plurality of pages PG.

[0120] For example, as Figure 3As shown, each of the multiple word lines WL1 to WL9 can correspond to a page PG. When each of the multiple word lines WL1 to WL9 has a relatively large size, each of the multiple word lines WL1 to WL9 can correspond to at least two (e.g., two or four) pages PG. Each page PG is the smallest unit for performing programming and read operations, and all memory cells MC within the same page PG can perform programming operations and read operations simultaneously.

[0121] Multiple bit lines BL can be connected to the column decoder 320. In some embodiments, the multiple bit lines BL can be divided into odd-numbered bit lines BL and even-numbered bit lines BL such that a pair of an odd-numbered bit line and an even-numbered bit line are commonly coupled to the column decoder 320.

[0122] When accessing the memory cell MC, the row decoder 310 and the column decoder 320 are used to locate the desired memory cell based on the address.

[0123] Since all data processing of the memory device 110, including programming operations and read operations, occurs via the data register 330, the data register 330 plays an important role. If the data processing of the data register 330 is delayed, all other areas need to wait until the data register 330 completes data processing, thereby reducing the overall performance of the memory device 110.

[0124] Referring to Figure 3 the example shown, in a memory cell string STR, multiple transistors TR1 to TR9 can be respectively connected to multiple word lines WL1 to WL9. The multiple transistors TR1 to TR9 correspond to the memory cells MC. In this example, the multiple transistors TR1 to TR9 include a control gate CG and a floating gate FG.

[0125] The multiple word lines WL1 to WL9 include two outermost word lines WL1 and WL9. A first select line DSL can be additionally arranged outside the first outermost word line WL1, and compared with the other outermost word line WL9, the first outermost word line WL1 is closer to the data register 330 and has a shorter signal path. A second select line SSL can be additionally arranged outside the other second outermost word line WL9.

[0126] A first select transistor D-TR controlled by the first select line DSL to be turned on / off has a gate electrode connected to the first select line DSL but does not include a floating gate FG. A second select transistor S-TR controlled by the second select line SSL to be turned on / off has a gate electrode connected to the second select line SSL but does not include a floating gate FG.

[0127] The first select transistor D-TR serves as a switching circuit that connects a corresponding memory cell string STR and a data register 330. The second select transistor S-TR serves as a switching circuit that connects a corresponding memory cell string STR to a source line SL. That is, the first select transistor D-TR and the second select transistor S-TR can be used to enable or disable a corresponding memory cell string STR.

[0128] In some embodiments, the memory system 100 applies a predetermined on voltage Vcc to the gate electrode of the first select transistor D-TR to turn on the first select transistor D-TR, and applies a predetermined off voltage (e.g., 0V) to the gate electrode of the second select transistor S-TR to turn off the second select transistor S-TR.

[0129] The memory system 100 turns on both the first select transistor D-TR and the second select transistor S-TR during a read operation or a verify operation. Thus, during a read operation or a verify operation, current can flow through a corresponding memory cell string STR and to a source line SL corresponding to ground, so that the voltage level of a bit line BL can be measured. However, during a read operation, there may be a time difference in the on / off timing between the first select transistor D-TR and the second select transistor S-TR.

[0130] During an erase operation, the memory system 100 can apply a predetermined voltage (e.g., +20V) to a substrate through a source line SL. During an erase operation, the memory system 100 applies a certain voltage to allow both the first select transistor D-TR and the second select transistor S-TR to float. Thus, the applied erase voltage can remove charges from a floating gate FG of a selected memory cell.

[0131] Figure 4 is a diagram illustrating the operation of a memory device 110 according to some embodiments of the disclosed technology.

[0132] In some embodiments, the memory device 110 may include a first memory block BLK_1 and a second memory block BLK_2. Each of the first memory block BLK_1 and the second memory block BLK_2 is one of the memory blocks described with reference to Figure 1 description.

[0133] In some embodiments of the disclosed technology, when writing data to the memory device 110, the memory controller 120 may first write the data to a memory location and then migrate the data to another memory location. For example, the memory device 110 may first write the data to a first memory cell MC_1 included in the first memory block BLK_1, as Figure 4 shown.

[0134] In some embodiments, in turbo programming mode, a reduced number of incremental step pulse program (ISPP) programming pulses may be used to perform a programming operation. The memory controller 120 may determine whether the turbo programming mode TP_MODE is set or reset, and in the turbo programming mode, may determine the number of ISPP programming pulses to be applied to the first memory block BLK_1. The memory controller 120 may provide information indicating whether the memory device 110 is using the turbo programming mode TP_MODE.

[0135] The memory device 110 may write data into the first memory cell MC_1 included in the first memory block BLK_1.

[0136] The first number of ISPP programming pulses to be applied to the first memory cell MC_1 during the programming operation of the first memory cell MC_1 may vary depending on whether the turbo programming mode TP_MODE is being used, which will be discussed below with reference to Figure 5 be discussed.

[0137] After writing data into the first memory cell MC_1, the memory device 110 may migrate the data in the first memory cell MC_1 to the second memory cell MC_2 included in the second memory block BLK_2.

[0138] During the programming operation, the memory device 110 may first write data into the first memory cell MC_1, and then when a specific condition is satisfied, migrate the data from the first memory cell MC_1 to the second memory cell MC_2.

[0139] The number of data bits that the first memory cell MC_1 can store may be less than the number of data bits that the second memory cell MC_2 can store. For example, the first memory cell MC_1 may be programmed as a single-level cell (SLC), and the second memory cell MC_2 may be programmed as a multi-level cell (MLC), triple-level cell (TLC), or quad-level cell (QLC) or a higher-level cell. As another example, the first memory cell MC_1 may be programmed as an MLC, and the second memory cell MC_2 may be programmed as a TLC or QLC.

[0140] Typically, SLC programming operations are faster than MLC, TLC, or QLC programming operations, and MLC programming operations are faster than TLC or QLC programming operations. In some embodiments of the disclosed technology, when writing data to a TLC or QLC (or MLC) memory cell, memory controller 120 takes advantage of the faster speed of SLC (or MLC) programming operations when performing MLC, TLC, or QLC programming operations by first writing the data to an SLC (or MLC) memory cell and then migrating the data from the SLC (or MLC) memory cell to the MLC, TLC, or QLC memory cell. In the example discussed above, the number of data bits stored in the first memory cell MC_1 is less than the number of data bits stored in the second memory cell MC_2 because the number of ISPP programming pulses applied to the first memory cell MC_1 is less than the number of ISPP programming pulses applied to the second memory cell MC_2, and thus, the programming speed of the first memory cell MC_1 is faster than the programming speed of the second memory cell MC_2.

[0141] In this way, a memory system implemented based on some embodiments of the disclosed technology can increase the write speed by utilizing a two-step programming operation while maintaining its high data storage capacity. That is, first write the data to the first memory cell MC_1 at a higher programming speed and then migrate the data from the first memory cell MC_1 to the second memory cell MC_2 with a higher data storage capacity.

[0142] Hereinafter, the operation of the memory device 110 applying programming pulses to write data to the first memory cell MC_1 and the second memory cell MC_2 will be described.

[0143] Figure 5 FIG. is a diagram showing the operation of the memory device 110 applying a programming pulse to the first memory cell MC_1 based on some embodiments of the disclosed technology.

[0144] When writing data to the first memory cell MC_1, the memory device 110 can use the incremental step pulse programming (ISPP) method.

[0145] ISPP is a programming and verification strategy that uses a programming voltage that increases in step voltage. For example, a memory cell is programmed using i (where i is a natural number) programming pulses, and the magnitude of the programming pulses gradually increases, and the programming pulses are applied to the control gate of the memory cell. A verification voltage is applied between the programming voltages to verify whether the memory cell has been programmed to the desired threshold voltage, and the process is repeated until it is verified that the memory cell has been programmed.

[0146] Data written through ISPP has a smaller memory cell threshold voltage distribution, thereby reducing the error rate in the data and improving the reliability of the programming operation.

[0147] However, the ISPP scheme iteratively applies programming voltage pulses and verification voltage pulses, and the time taken to complete the programming operation increases proportionally with the number of programming pulses applied to the memory cell.

[0148] Referring to Figure 5 , when writing data to the first memory cell MC_1 in the turbo programming mode TP_MODE (turbo programming mode "set"), the memory device 110 may apply m ISPP programming pulses VP1, VP2,..., VPm (m is an integer equal to or greater than 0 and is referred to as the "first pulse number") to the first memory cell MC_1.

[0149] On the other hand, when writing data to the first memory cell MC_1 outside the turbo programming mode TP_MODE (turbo programming mode "reset"), the memory device 110 may apply k ISPP programming pulses VP1', VP2',..., VPk-1', VPk' (k is an integer equal to or greater than 0) to the first memory cell MC_1.

[0150] The first pulse number (m) is less than k. That is, in the turbo programming mode TP_MODE (turbo programming mode "set"), the memory device 110 can reduce the number of IPSS programming pulses applied to the first memory cell MC_1, thereby improving the programming speed.

[0151] When writing data to the first memory cell MC_1 included in the first memory block BLK_1, the memory device 110 may apply m ISPP programming pulses VP1, VP2,..., VPm (m is an integer equal to or greater than 0) to the first memory cell MC_1. Additionally, when migrating data from the first memory cell MC_1 to the second memory cell MC_2 included in the second memory block BLK_2, the memory device 110 may apply n ISPP programming pulses VP1', VP2',..., VPn-1', VPn' (n is a natural number and is referred to as the "second pulse number") to the second memory cell MC_2.

[0152] The number n of the second pulses is greater than the number m of the first pulses. That is, when writing data into the first memory cell MC_1, the memory device 110 can reduce the number of ISPP programming pulses applied to the first memory cell MC_1 to achieve a faster programming speed. Since the first memory cell MC_1 storing a small number of data bits can complete the programming operation faster than the memory cells storing a relatively large number of data bits, the memory device 110 can reduce the number of ISPP programming pulses applied to the first memory cell MC_1, thereby achieving a faster programming speed.

[0153] In addition, when migrating data from the first memory cell MC_1 to the second memory cell MC_2, more ISPP programming pulses will be applied to the second memory cell MC_2 to reduce the possibility of errors occurring in the data.

[0154] This can ensure that the reliability of the data stored in the second memory cell MC_2 reaches at least a predetermined level (e.g., 1 year).

[0155] Figure 6 is a diagram showing the maximum retention time TM of some embodiments based on the disclosed technology.

[0156] Referring to Figure 6 , when writing data into the first memory cell MC_1 included in the first memory block BLK1 in the turbo programming mode TP_MODE (turbo mode “set”), the memory device 110 can apply m ISPP programming pulses VP1, VP2, ……, VPm (m is an integer equal to or greater than 0 and is referred to as “the number of the first pulses”) to the first memory cell MC_1. In addition, when migrating data from the first memory cell MC_1 to the second memory cell MC_2 included in the second memory block BLK_2, the memory device 110 can apply n ISPP programming pulses VP1', VP2', ……, VPn-1', VPn' (n is a natural number and is referred to as “the number of the second pulses”) to the second memory cell MC_2.

[0157] The number n of the second pulses is greater than the number m of the first pulses. That is, when migrating data from the first memory cell MC_1 to the second memory cell MC_2, the memory device 110 can increase the number n of the second pulses which is the number of ISPP programming pulses applied to the second memory cell MC_2, and the number of the second pulses is greater than the number of the first pulses, thereby reducing the error rate in the written data.

[0158] This can ensure that the reliability of the data stored in the second memory cell MC_2 reaches at least a predetermined level (e.g., 1 year).

[0159] Referring toFigure 6 There may be a delay between the time point when the memory device 110 writes data to the first memory cell MC_1 and the time point when the memory device 110 migrates the data from the first memory cell MC_1 to the second memory cell MC_2.

[0160] For example, the memory device 110 may delay the data migration from the first memory cell MC_1 to the second memory cell MC_2 in order to perform another pending operation with a higher priority (e.g., a read operation). As another example, in order to minimize the negative impact of the migration operation on the performance of the memory system, the memory device 110 may perform the data migration operation from the first memory cell MC_1 to the second memory cell MC_2 when specific conditions are met.

[0161] Therefore, once the memory device 110 writes data to the first memory cell MC_1, the data remains in the first memory cell MC_1 until the memory device 110 migrates the data to the second memory cell MC_2. The maximum time between the first time point T1 when the data is written to the first memory cell MC_1 and the second time point T2 when the data is migrated to the second memory cell MC_2 can be defined as the maximum retention time TM. That is, the data written to the first memory cell MC_1 can be retained for the maximum retention time TM.

[0162] The first pulse number is the number of ISPP programming pulses applied to the first memory cell MC_1 when writing data to the first memory cell MC_1, and the memory device 110 can determine the first pulse number based on the maximum retention time TM.

[0163] In some embodiments, the maximum retention time TM can be determined by the memory controller 120. The memory controller 120 can notify the memory device 110 of the maximum retention time TM.

[0164] As another example, the maximum retention time TM can be determined based on the history of previously used retention times. For example, if the history of previously used retention times is 3 hours, 6 hours, and 1 day, the maximum retention time TM can be set to 1 day.

[0165] In order for the data to be normally migrated from the first memory cell MC_1 to the second memory cell MC_2, the data should be retained in the first memory cell MC_1 during the above-mentioned maximum retention time TM. Therefore, the memory device 110 can apply a sufficient number of ISPP programming pulses as the first pulse number so that the data can be retained in the first memory cell MC_1 for at least the maximum retention time TM.

[0166] The number of first pulses can be increased proportionally to an increase in the maximum retention time TM. For example, when data needs to be retained in the first memory cell MC_1 for up to two days, the value of the number of first pulses is greater than when data needs to be retained in the first memory cell MC_1 for up to one day.

[0167] Figure 7 is a diagram showing an example of the number of first pulses based on the maximum retention time TM in some embodiments of the disclosed technology.

[0168] Referring to Figure 7 , if the maximum retention time TM is less than one day, the number of first pulses can be set to "1". If the maximum retention time TM is equal to or greater than one day and less than three days, the number of first pulses can be set to "3". If the maximum retention time TM is equal to or greater than three days and less than seven days, the number of first pulses can be set to "5". If the maximum retention time TM is equal to or greater than 7 days, the number of first pulses can be set to "7". However, note that Figure 7 the number of first pulses and the maximum retention time TM are shown as examples, and the maximum retention time TM and the number of first pulses associated with the maximum retention time TM can vary.

[0169] Figure 8 is a diagram showing an example of the voltage difference between ISPP pulses based on the maximum retention time TM in some embodiments of the disclosed technology.

[0170] Referring to Figure 8 , the voltage difference between the ISPP programming pulses applied when writing data to the first memory cell MC_1 can be determined based on the above maximum retention time TM.

[0171] For example, it will be assumed that when the maximum retention time TM is three days, the voltage difference between the ISPP programming pulses is the first voltage difference VTH_DIFF1, and it will be assumed that when the maximum retention time TM is five days, the voltage difference between the ISPP programming pulses is the second voltage difference VTH_DIFF2.

[0172] The magnitude of the first voltage difference VTH_DIFF1 can be greater than the magnitude of the second voltage difference VTH_DIFF2. That is, the greater the maximum retention time TM, the smaller the voltage difference between the ISPP programming pulses applied when writing data to the first memory cell MC_1.

[0173] In some embodiments, the memory device 110 can use various methods to determine the time point at which data to be programmed in the first memory cell MC_1 is migrated to the second memory cell MC_2. Specific embodiments related thereto will now be described.

[0174] Figure 9 It is a flowchart showing an example of an operation of migrating data to be programmed in a first memory cell MC_1 to a second memory cell MC_2 in some embodiments of the disclosed technology.

[0175] Referring to Figure 9 , the memory device 110 can differently determine the time point for migrating the data to be written to the first memory cell MC_1 to the second memory cell MC_2 based on whether the data written to the first memory cell MC_1 is cold data. In some embodiments, cold data refers to data that is not frequently accessed compared to hot data that is frequently accessed.

[0176] First, the memory device 110 can determine whether the data stored in the first memory cell MC_1 is cold data (S910). Cold data refers to data that the host HOST accesses at a lower frequency. On the contrary, warm data or hot data refers to data that the host HOST accesses at a higher frequency.

[0177] For example, if the number of times of reading the data stored in the first memory cell MC_1 within a configured unit time is less than the configured threshold number of reads, the memory device 110 can determine that the data stored in the first memory cell MC_1 is cold data, and if the number of times of reading the data stored in the first memory cell MC_1 within a configured unit time is equal to / higher than the configured threshold number of reads, it can determine that the data stored in the first memory cell MC_1 is warm data or hot data.

[0178] As another example, the memory device 110 can determine whether the data stored in the first memory cell MC_1 is cold data based on a command from the memory controller 120 indicating whether the data stored in the first memory cell MC_1 is cold data.

[0179] If the data programmed in the first memory cell MC_1 is cold data (Yes in S910), the memory device 110 can migrate the data stored in the first memory cell MC_1 to the second memory cell MC_2 at a first time point (S920).

[0180] On the other hand, if the data stored in the first memory cell MC_1 is not cold data (No in S910), the memory device 110 can migrate the data stored in the first memory cell MC_1 to the second memory cell MC_2 at a second time point (S930).

[0181] The second time point is after the first time point. That is, the time point for migrating the data stored in the first memory cell MC_1 is before the time point for migrating the data stored in the first memory cell MC_1 when the data stored in the first memory cell MC_1 is warm data or hot data, in the case where the data stored in the first memory cell MC_1 is cold data. This is because cold data accessed by the host HOST at a lower frequency is preferably stored in the second memory block BLK_2 that can store a large amount of data, compared to the first memory block BLK_1 that enables high-speed access.

[0182] Figure 10 It is a flowchart showing another example of an operation of migrating the data stored in the first memory cell MC_1 to the second memory cell MC_2 in some embodiments of the disclosed technology.

[0183] First, the memory device 110 may determine whether the memory device 110 is in an idle state (S1010).

[0184] The idle state means a state in which the memory device 110 is not performing an operation requested by the host HOST or the memory controller 120 (e.g., a read / program / erase operation, or a background operation such as garbage collection, wear leveling, or read recovery).

[0185] If the memory device 110 is in an idle state (Yes in S1010), the memory device 110 may migrate the data stored in the first memory cell MC_1 to the second memory cell MC_2 (S1020). This is because the migration operation does not affect any operation requested by the host HOST or the memory controller 120.

[0186] On the other hand, if the memory device 110 is not in an idle state (No in S1010), the memory device 110 may keep the data stored in the first memory cell MC_1 intact and may not migrate the data to the second memory cell MC_2 (S1030).

[0187] Figure 11 It is a flowchart showing a method for operating the memory device 110 based on some embodiments of the disclosed technology.

[0188] A method for operating a memory device 110 may include a step (S1110) of programming data by applying a first number of ISPP programming pulses to a first memory cell MC_1 included in a first memory block BLK_1. The turbo programming mode TP_MODE may be set in this state, and the turbo programming mode TP_MODE is a mode for determining the number of ISPP programming pulses applied when writing data to the first memory block BLK_1.

[0189] Additionally, a method for operating a memory device 110 may include a step (S1120) of migrating data from the first memory cell MC_1 to a second memory cell MC_2 included in a second memory block BLK_2 by applying a second number of ISPP programming pulses to the second memory cell MC_2.

[0190] The first number of pulses is less than the number of ISPP programming pulses applied to the first memory cell MC_1 when writing data to the first memory cell MC_1 in a state where the turbo programming mode TP_MODE is reset.

[0191] The second number of pulses is greater than the first number of pulses.

[0192] Meanwhile, the number of bits of data stored in the first memory cell MC_1 may be less than the number of bits of data stored in the second memory cell MC_2.

[0193] The first number of pulses may be determined based on the maximum value of the maximum retention time, that is, the maximum time during which the data written to the first memory cell MC_1 can be held in the first memory cell MC_1.

[0194] The voltage difference between the ISPP programming pulses applied when writing data to the first memory cell may be determined based on the above maximum retention time.

[0195] Figure 12 It is a diagram showing the configuration of a computing system 1200 according to an embodiment of the disclosed technology.

[0196] Refer to Figure 12, a computing system 1200 according to an embodiment of the disclosed technology may include: a memory system 100, electrically connected to a system bus 1260; a CPU 1210 configured to control all operations of the computing system 1200; a RAM 1220 configured to store data and information related to the operations of the computing system 1200; a user interface / user experience (UI / UX) module 1230 configured to provide a user environment to a user; a communication module 1240 configured to communicate with external devices in a wired and / or wireless manner; and a power management module 1250 configured to manage the power used by the computing system 1200.

[0197] The computing system 1200 may be a personal computer (PC), or may include mobile terminals such as smart phones, tablets, or various electronic devices.

[0198] The computing system 1200 may further include a battery for supplying an operating voltage, and may further include an application chipset, a graphics-related module, a camera image processor, and a DRAM. Other elements will be obvious to those skilled in the art.

[0199] The memory system 100 may include not only devices configured to store data on a disk such as a hard disk drive (HDD), but also devices configured to store data in non-volatile memory such as a solid state drive (SSD), a universal flash device, or an embedded MMC (eMMC) device. The non-volatile memory may include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), flash memory, phase change RAM (PRAM), magnetic RAM (MRAM), resistive RAM (RRAM), ferroelectric RAM (FRAM), etc. Additionally, the memory system 100 may be implemented as various types of storage devices and installed inside various electronic devices.

[0200] In some embodiments of the above-disclosed technology, the operation latency time of the memory system may be minimized. Additionally, based on embodiments of the disclosed technology, the overhead that occurs during the process of invoking a specific function may be minimized. Although various specific features have been used to describe the various embodiments of the disclosed technology, the disclosed embodiments and other embodiments may be modified, varied, and improved based on the content disclosed and illustrated in this patent document.

Claims

1. A memory system, comprising: A memory device, including a first memory block and a second memory block, each of the first memory block and the second memory block including memory cells for storing data and performing operations on one or more memory cells, the operations including a read operation for reading data stored in one or more memory cells and a program operation for writing new data into one or more memory cells; And A memory controller, communicating with the memory device and controlling the memory device to perform operations, wherein the memory controller determines whether to set or reset a turbo program mode and determines the number of program pulses applied when writing data into the first memory block in the turbo program mode, Wherein the memory device: When writing data into a first memory cell included in the first memory block in a state where the turbo program mode is set, applies a first number of program pulses to the first memory cell; And When migrating the data from the first memory cell to a second memory cell included in the second memory block, applies a second number of program pulses to the second memory cell, Wherein the first number of the program pulses is less than the number of program pulses applied when writing data into the first memory cell in a state where the turbo program mode is reset, Wherein the second number of the program pulses is greater than the first number of the program pulses, and When the turbo program mode is set, the first memory cell is in the turbo program mode, and when the turbo program mode is reset, the first memory cell is not in the turbo mode.

2. The memory system according to claim 1, wherein the number of data bits stored in the first memory cell is less than the number of data bits stored in the second memory cell.

3. The memory system according to claim 1, wherein the memory device determines the first number of the program pulses based on a maximum retention time, the maximum retention time corresponding to the maximum time for which data is retained in the first memory cell.

4. The memory system according to claim 3, wherein the program pulse is an incremental step pulse programming voltage pulse, and wherein the memory device determines the voltage difference between the program pulses to be applied to the first memory cell based on the maximum retention time.

5. The memory system according to claim 4, wherein the memory device differently determines the time point at which the data to be programmed in the first memory cell is migrated to the second memory cell based on the access frequency of the data stored in the first memory cell.

6. The memory system according to claim 1, wherein when the memory device is in an idle state, the memory device migrates data from the first memory cell to the second memory cell.

7. A memory device, comprising: A first memory block, including first memory cells for storing data, and performing a programming operation of writing data into the first memory cells; and A second memory block, including second memory cells for storing data, and performing a programming operation of writing data into the second memory cells, wherein the memory device: When writing data into the first memory cells included in the first memory block in a state where the turbo programming mode is set, applies a first number of programming pulses to the first memory cells, wherein the number of programming pulses to be applied to the first memory block is determined in the turbo programming mode, When migrating the data from the first memory cells to the second memory cells included in the second memory block, applies a second number of programming pulses to the second memory cells, wherein the first number of the programming pulses is less than the number of programming pulses applied when writing data into the first memory cells in a state where the turbo programming mode is reset, wherein the second number of the programming pulses is greater than the first number of the programming pulses, and When the turbo programming mode is set, the first memory cells are in the turbo programming mode, and when the turbo programming mode is reset, the first memory cells are not in the turbo mode.

8. The memory device according to claim 7, wherein the number of data bits stored in the first memory cells is less than the number of data bits stored in the second memory cells.

9. The memory device according to claim 7, wherein the memory device determines the first number of the programming pulses based on a maximum retention time, and the maximum retention time corresponds to the maximum time for which data is retained in the first memory cells.

10. The memory device according to claim 9, wherein the programming pulses are incremental step pulse programming voltage pulses, and wherein the memory device determines a voltage difference between the programming pulses to be applied to the first memory cells based on the maximum retention time.

11. The memory device according to claim 10, wherein the memory device differently determines a time point at which the data to be programmed in the first memory cells is migrated to the second memory cells based on an access frequency of the data stored in the first memory cells.

12. The memory device according to claim 7, wherein when the memory device is in an idle state, the memory device migrates data from the first memory cells to the second memory cells.

13. A method of operating a memory device, the memory device including a first memory block and a second memory block, the method comprising: Writing data by applying a first number of programming pulses to first memory cells included in the first memory block in a state where the turbo programming mode is set, wherein the number of programming pulses applied when writing data into the first memory block is determined in the turbo programming mode; and The data is migrated from the first memory cell to the second memory cell by applying a second quantity of programming pulses to second memory cells included in the second memory block, wherein a first quantity of the programming pulses is less than a quantity of programming pulses applied when writing data to the first memory cell in a state where the turbo programming mode is reset, wherein a second quantity of the programming pulses is greater than the first quantity of the programming pulses, and when the turbo programming mode is set, the first memory cell is in the turbo programming mode, and when the turbo programming mode is reset, the first memory cell is not in the turbo mode.

14. The method according to claim 13, wherein a number of data bits stored in the first memory cell is less than a number of data bits stored in the second memory cell.

15. The method according to claim 13, wherein the first quantity of the programming pulses is determined based on a maximum retention time corresponding to a maximum time for which data is retained in the first memory cell.

16. The method according to claim 15, wherein the programming pulses are incremental step pulse programming voltage pulses, and wherein a voltage difference between the programming pulses to be applied to the first memory cell is determined based on the maximum retention time.

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