Internal Voltage Generation Circuit and Semiconductor Memory Device Including the Same

Abstract

The present application relates to an internal voltage generation circuit and a semiconductor memory device including the same. An internal voltage generation circuit may include: a voltage comparison circuit configured to generate a control voltage by comparing a reference voltage with an internal voltage fed back thereto; a voltage driving circuit configured to generate an internal voltage based on the control voltage; and a drivability control circuit configured to control the voltage level of the control voltage based on an enable signal enabled during active operation, so as to control the drivability of the voltage driving circuit.

Description

Technical Field

[0001] Various embodiments generally relate to an internal voltage generating circuit and a semiconductor memory device including the same, and more particularly, to an internal voltage generating circuit that stably generates an internal voltage in an interval in which the internal voltage is used and a semiconductor memory device including the same. Background Art

[0002] Typically, integrated circuits, including semiconductor devices and semiconductor memory devices, receive external voltages and generate internal voltages to perform circuit operations. Therefore, integrated circuits are equipped with internal voltage generation circuits to generate internal voltages. The internal voltage generated by the internal voltage generation circuit can be supplied to internal circuits that require internal voltages. Therefore, when designing an internal voltage generation circuit, it is important to provide sufficient internal voltage to the internal circuits. Summary of the Invention

[0003] Various embodiments are directed to an internal voltage generating circuit capable of increasing drivability of a control voltage during active operation using an internal voltage.

[0004] In addition, various embodiments relate to an internal voltage generating circuit capable of generating a stable internal voltage when characteristics of a transistor vary according to process, voltage, and temperature (PVT) deviation.

[0005] In an embodiment, an internal voltage generating circuit includes: a voltage comparison circuit configured to generate a control voltage by comparing a reference voltage with a feedback voltage fed back to the voltage comparison circuit; a voltage driving circuit configured to generate an internal voltage based on the control voltage, the internal voltage being used to generate the feedback voltage; and a drivability control circuit configured to control a voltage level of the control voltage based on an enable signal enabled during active operation so as to control the drivability of the voltage driving circuit.

[0006] In an embodiment, a semiconductor memory device includes: a voltage comparison circuit configured to generate a control voltage by comparing a reference voltage with a feedback voltage fed back to the voltage comparison circuit; a voltage driving circuit configured to generate an internal voltage based on the control voltage, the internal voltage being used to generate the feedback voltage; a drivability control circuit configured to control a voltage level of the control voltage based on an enable signal enabled during an active operation so as to control the drivability of the voltage driving circuit; and a load control circuit configured to adjust a resistance value reflected in the drivability control circuit based on data information input to or output from a memory cell array circuit driven by the internal voltage.

[0007] In an embodiment, a semiconductor memory device includes: a memory cell array configured to store data; and an internal voltage generating circuit including: a voltage comparison circuit configured to generate a control voltage by comparing a reference voltage with a feedback voltage; a voltage driving circuit configured to generate an internal voltage based on the control voltage and provide the internal voltage to the memory cell array, the internal voltage being fed back to the voltage comparison circuit as a feedback voltage; and a drivability control circuit configured to adjust a voltage level of the control voltage based on at least one of a process, voltage, temperature (PVT) deviation, and a value in data to control the drivability of the voltage driving circuit.

[0008] According to an embodiment, the internal voltage generating circuit may generate a stable internal voltage during active operation, thereby providing stable circuit operation for an internal circuit receiving the internal voltage.

[0009] Furthermore, even if the characteristics of the transistor vary, the internal voltage generating circuit can generate a stable internal voltage, thereby improving the reliability of the internal voltage generating circuit.

[0010] The objects of the present disclosure are not limited to those mentioned herein; other objects that are not described will become apparent to those skilled in the art to which the present disclosure pertains from the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 is a block diagram showing a configuration of an internal voltage generating circuit according to an embodiment.

[0012] Figure 2 is to show that Figure 1 A circuit diagram of the circuit configuration of the internal voltage generating circuit.

[0013] Figure 3 It shows that according to the embodiment Figure 2 A block diagram of a partial configuration of a variation of the internal voltage generating circuit.

[0014] Figure 4 is to show that Figure 3 A circuit diagram of the circuit configuration of a drivability control circuit and a deviation control circuit.

[0015] Figure 5 is a block diagram showing a configuration of a semiconductor memory device according to an embodiment. DETAILED DESCRIPTION

[0016] The present specification of the present disclosure provides structural and functional details relating to various embodiments. However, the scope of the present invention is not limited to any embodiment disclosed, nor to any specific details provided herein. That is, it will be understood by those skilled in the art based on this disclosure that any embodiment can be modified in various ways and can have various forms. Therefore, the present invention covers all such variations that fall within the scope of the claims (including their equivalents). In addition, a particular embodiment may not include all the mentioned purposes or effects, nor may it include only these purposes and effects. Therefore, the scope of the present invention is not limited thereto.

[0017] Throughout the specification, references to "an embodiment" or the like do not necessarily refer to only one embodiment, and different references to any such phrase do not necessarily refer to the same embodiment. The term "embodiment" when used herein does not necessarily refer to all embodiments.

[0018] Terms such as "first" and "second" are used to distinguish one element from another element having the same or similar name. A first element in one instance may be called a second element in another instance without indicating any substantial change in the elements themselves.

[0019] Unless clearly indicated otherwise or clear from the context that only one is intended, the singular is intended to include the plural. Open-ended terms such as "including" or "having" should be understood to indicate the presence of the stated characteristics, quantities, steps, operations, elements, components, or combinations thereof, but do not exclude the possibility that one or more other characteristics, quantities, steps, operations, elements, components, or combinations thereof exist or can be added.

[0020] In each step, symbols (e.g., a, b, and c) are used for ease of description and do not necessarily indicate any particular order of steps or operations. Consistent with the teachings herein, unless a specific order is clearly described or the context indicates such an order, the steps / operations may be performed in any suitable order. In some cases, two or more steps / operations may be performed substantially simultaneously.

[0021] Unless otherwise defined, all terms (including technical or scientific terms) used herein have the same meaning as commonly understood by those skilled in the art. Unless clearly defined in this application, terms defined in commonly used dictionaries should be interpreted in the context of the relevant technology and should not be interpreted in an ideal or overly formal manner.

[0022] Figure 1 is a block diagram showing a configuration of an internal voltage generating circuit 1000 according to an embodiment.

[0023] Reference Figure 1The internal voltage generating circuit 1000 may be configured to generate the internal voltage V_IN based on the reference voltage V_REF. The internal voltage generating circuit 1000 may include a voltage comparison circuit 100, a voltage driving circuit 200, and a drivability control circuit 300.

[0024] The voltage comparison circuit 100 may be configured to generate a control voltage DRVP by comparing a reference voltage V_REF with a feedback voltage V_FD fed back to the voltage comparison circuit 100. When the voltage level of the internal voltage V_IN becomes less than or equal to the voltage level corresponding to the reference voltage V_REF, the voltage comparison circuit 100 may enable the control voltage DRVP. Figure 2 As described, the voltage driving circuit 200 can be provided by, for example, a voltage divider (see Figure 2 ) divides the internal voltage V_IN to generate a feedback voltage V_FD, and provides the feedback voltage V_FD to the voltage comparison circuit 100. Therefore, the feedback voltage V_FD may be the internal voltage V_IN or may be derived from the internal voltage V_IN.

[0025] The voltage driving circuit 200 may be configured to generate an internal voltage V_IN based on the control voltage DRVP. When the control voltage DRVP is enabled, the voltage driving circuit 200 may generate the internal voltage V_IN using an external voltage (eg, an external power supply voltage) applied to the VCC terminal.

[0026] The drivability control circuit 300 can be configured to control the voltage level of the control voltage DRVP based on an enable signal EN enabled during active operation to control the drivability of the voltage driver circuit 200. The drivability control circuit 300 can drive (i.e., charge) the node outputting the control voltage DRVP to a set voltage level based on the enable signal EN. Active operation can indicate operation of the internal circuit using the internal voltage V_IN. In an embodiment, the internal voltage generation circuit 1000 can generate the internal voltage V_IN even during standby operation prior to active operation.

[0027] The internal voltage generation circuit 1000 can generate the internal voltage V_IN during standby operation and active operation. Specifically, the internal voltage generation circuit 1000 can drive the node outputting the control voltage DRVP to a set voltage level based on the enable signal EN enabled during active operation. Therefore, the drivability of the voltage driving circuit 200 can be increased based on the control voltage DRVP having a voltage level adjusted during active operation.

[0028] Figure 2 It shows Figure 1 FIG. 1 is a circuit diagram of a circuit configuration of an internal voltage generating circuit 1000 .

[0029] Reference Figure 2 The internal voltage generating circuit 1000 may include a voltage comparison circuit 100, a voltage driving circuit 200, and a drivability control circuit 300. The voltage comparison circuit 100 may include a comparison circuit 110 and a current mirror circuit 120. The voltage driving circuit 200 may include a driving circuit 210 and a voltage divider circuit 220. The drivability control circuit 300 may include a switch circuit 310 and a load circuit 320.

[0030] The comparison circuit 110 of the voltage comparison circuit 100 may be configured to compare a reference voltage VREF with a feedback voltage V_FD corresponding to the internal voltage V_IN or derived from the internal voltage V_IN via the voltage divider circuit 220. The comparison circuit 110 may include first and second PMOS transistors P1 and P2, first and second resistors R1 and R2, first and second NMOS transistors N1 and N2, and a current source I.

[0031] A first PMOS transistor P1 may be coupled between an external power supply voltage terminal VCC and a first node ND1, and a second PMOS transistor P2 may be coupled between the external power supply voltage terminal VCC and a second node ND2. A first resistor R1 and a second resistor R2 may be coupled in series between the first node ND1 and the second node ND2. The first resistor R1 and the second resistor R2 may be configured to set a conduction level of the first PMOS transistor P1 and the second PMOS transistor P2. A common node between the first resistor R1 and the second resistor R2 may be coupled to the gates of the first PMOS transistor P1 and the second PMOS transistor P2. One end of a current source I may be coupled to a ground power supply voltage terminal VSS, and the other end of the current source I may be coupled to the first NMOS transistor N1 and the second NMOS transistor N2. The first NMOS transistor N1 may be coupled between the first node ND1 and the current source I and receive a reference voltage V_REF via its gate. The second NMOS transistor N2 may be coupled between the second node ND2 and the current source I and receive a feedback voltage V_FD via its gate.

[0032] The current mirror circuit 120 of the voltage comparison circuit 100 may be configured to generate a control voltage DRVP through a mirroring operation according to signals output from the first node ND1 and the second node ND2 of the comparison circuit 110. The current mirror circuit 120 may include third and fourth PMOS transistors P3 and P4 and third and fourth NMOS transistors N3 and N4.

[0033] A third PMOS transistor P3 and a third NMOS transistor N3 may be coupled in series between an external power supply voltage terminal VCC and a ground power supply voltage terminal VSS. A fourth PMOS transistor P4 and a fourth NMOS transistor N4 may be coupled in series between the external power supply voltage terminal VCC and the ground power supply voltage terminal VSS. The gate of the third PMOS transistor P3 may be coupled to a first node ND1, and the gate of the fourth PMOS transistor P4 may be coupled to a second node ND2. The drain and gate of the third NMOS transistor N3 and the gate of the fourth NMOS transistor N4 may be coupled together to perform a current mirroring operation.

[0034] The driving circuit 210 of the voltage driving circuit 200 may be configured to drive the internal voltage V_IN based on the control voltage DRVP. The driving circuit 210 may include a fifth PMOS transistor P5 coupled between the external power supply voltage terminal VCC and the output terminal outputting the internal voltage V_IN and configured to receive the control voltage DRVP through its gate.

[0035] The voltage divider circuit 220 of the voltage driving circuit 200 may be configured to generate a feedback voltage V_FD by dividing the internal voltage V_IN according to the resistance values of the third resistor R3 and the fourth resistor R4 of the voltage divider circuit 220. The third resistor R3 and the fourth resistor R4 may be connected in series between the ground power supply voltage terminal VSS and the output terminal outputting the internal voltage V_IN. The third resistor R3 and the fourth resistor R4 may be connected to a common node outputting the feedback voltage V_FD.

[0036] The switch circuit 310 of the drivability control circuit 300 may be configured to perform a switching operation based on an enable signal EN. The switch circuit 310 may include a fifth NMOS transistor N5 coupled to an output terminal of the output control voltage DRVP and configured to receive the enable signal EN through its gate.

[0037] The load circuit 320 of the drivability control circuit 300 may be configured to reflect the resistance value in the switch circuit 310. The load circuit 320 may include a sixth NMOS transistor N6 coupled between the switch circuit 310 and the ground power supply voltage terminal VSS and commonly coupled to the gates of the third NMOS transistor N3 and the fourth NMOS transistor N4.

[0038] Hereinafter, the circuit operation of the internal voltage generating circuit 1000 is described.

[0039] During standby operation, the voltage level of the feedback voltage V_FD may be lower than the voltage level of the reference voltage V_REF. Therefore, the first NMOS transistor N1 may be turned on based on the voltage level of the reference voltage V_REF, which is higher than the voltage level of the feedback voltage V_FD. As the first NMOS transistor N1 turns on, the voltage level of the first node ND1 may decrease, and the third PMOS transistor P3 may turn on. Therefore, the third NMOS transistor N3 and the fourth NMOS transistor N4 may turn on. The voltage level of the control voltage DRVP may be lowered through a current mirroring operation. Therefore, the fifth PMOS transistor P5 of the driver circuit 210 serving as the voltage driver circuit 200 may cause the power applied to the external power supply voltage terminal VCC to be transmitted as the internal voltage V_IN corresponding to the voltage level of the control voltage DRVP.

[0040] Then, the voltage level of the feedback voltage V_FD may become higher than the voltage level of the reference voltage V_REF. Therefore, the second NMOS transistor N2 may be turned on based on the voltage level of the feedback voltage V_FD being higher than the voltage level of the reference voltage V_REF. As the second NMOS transistor N2 is turned on, the voltage level of the second node ND2 may decrease, and the voltage level of the control voltage DRVP may increase. Therefore, the fifth PMOS transistor P5 of the voltage driving circuit 200 may cause the power applied to the external power supply voltage terminal VCC to be transmitted as the internal voltage V_IN corresponding to the voltage level of the control voltage DRVP.

[0041] As described above, the internal voltage generating circuit 1000 can generate and maintain the internal voltage V_IN corresponding to the reference voltage V_REF during the standby operation. Hereinafter, the active operation of the internal voltage generating circuit 1000 is described.

[0042] During active operation, the enable signal EN can be enabled from logic "low" to logic "high." Consequently, the fifth NMOS transistor N5 of the switch circuit 310 serving as the drivability control circuit 300 can be turned on. The load circuit 320 can have a resistance value corresponding to the voltage level applied to its gate. Therefore, the drivability control circuit 300 can discharge the output terminal of the voltage comparison circuit 100 to the ground power supply voltage terminal VSS based on the enable signal EN. That is, the control voltage DRVP can be pulled down based on the enable signal EN. The fifth PMOS transistor P5 can then be turned on based on the pulled-down control voltage DRVP. Therefore, when the internal voltage V_IN is applied to the external power supply voltage terminal VCC during active operation, a sufficient amount of power can be provided. When a sufficient amount of power is provided when the internal voltage V_IN is applied to the external power supply voltage terminal VCC during active operation, this can indicate that the internal circuits receiving the internal voltage V_IN can ensure sufficient power and perform stable operation during active operation.

[0043] The internal voltage generating circuit 100 may adjust the voltage level of the control voltage DRVP by discharging the control voltage DRVP based on the enable signal EN. Therefore, during active operation, the internal voltage V_IN generated based on the control voltage DRVP may ensure a sufficient amount of power.

[0044] Figure 3 It shows that according to the embodiment Figure 2 A block diagram of a partial configuration of a variation of the internal voltage generating circuit.

[0045] Reference Figure 3 The internal voltage generating circuit may include a drivability control circuit 300A. The drivability control circuit 300A may represent Figure 1 and Figure 2 Furthermore, the internal voltage generating circuit may include an offset control circuit 400A.

[0046] The drivability control circuit 300A may be configured to control a voltage level of the control voltage DRVP based on an enable signal EN enabled during active operation. The deviation control circuit 400A may be configured to adjust a resistance value reflected in the drivability control circuit 300A based on a deviation control signal CTR_S.

[0047] The characteristics of transistors configured in integrated circuits including semiconductor devices and semiconductor memory devices may vary according to process, voltage, and temperature (PVT) deviations. Therefore, the internal voltage generation circuit according to an embodiment can generate a stable internal voltage V_IN by adjusting the drivability of the control voltage DRVP according to PVT deviations.

[0048] Figure 4 It shows Figure 3 FIG. 4 is a circuit diagram of the circuit configuration of the drivability control circuit 300A and the deviation control circuit 400A.

[0049] Reference Figure 4 , the drivability control circuit 300A may include a switch circuit 310A and a load circuit 320A.

[0050] The switch circuit 310A may be configured to perform a switching operation based on an enable signal EN. The switch circuit 310A may include a seventh NMOS transistor N7 coupled to a node outputting a control voltage DRVP and configured to receive the enable signal EN through a gate thereof.

[0051] The load circuit 320A may be configured to reflect the resistance value to the switch circuit 310A. The load circuit 320A may include an eighth NMOS transistor N8 to a tenth NMOS transistor N10, which are connected in parallel to the switch circuit 310A and are commonly connected to the load circuit 320A. Figure 2 The gates of the third NMOS transistor N3 and the fourth NMOS transistor N4 are connected to each other. The eighth NMOS transistor N8 to the tenth NMOS transistor N10 may have different on-resistance values. As described below, the eighth NMOS transistor N8 to the tenth NMOS transistor N10 may be selectively enabled based on the first deviation control signal CTR_S1 to the third deviation control signal CTR_S3 included in the deviation control signal CTR_S. Each of the first deviation control signal CTR_S1 to the third deviation control signal CTR_S3 may have a logic level set according to the PVT deviation "slow", "typical", or "fast".

[0052] The deviation control circuit 400A may be configured to adjust a resistance value reflected in the drivability control circuit 300A based on the first to third deviation control signals CTR_S1 to CTR_S3. The deviation control circuit 400A may include 11th to 13th NMOS transistors N11 to N13.

[0053] The 11th NMOS transistor N11 may be coupled between the eighth NMOS transistor N8 and the ground power supply voltage terminal VSS, and may receive the first deviation control signal CTR_S1 via a gate of the 11th NMOS transistor N11. The 12th NMOS transistor N12 may be coupled between the ninth NMOS transistor N9 and the ground power supply voltage terminal VSS, and may receive the second deviation control signal CTR_S2 via a gate of the 12th NMOS transistor N12. The 13th NMOS transistor N13 may be coupled between the tenth NMOS transistor N10 and the ground power supply voltage terminal VSS, and may receive the third deviation control signal CTR_S3 via a gate of the 13th NMOS transistor N13.

[0054] Therefore, the 11th NMOS transistor N11 can be turned on based on the first deviation control signal CTR_S1, the 12th NMOS transistor N12 can be turned on based on the second deviation control signal CTR_S2, and the 13th NMOS transistor N13 can be turned on based on the third deviation control signal CTR_S3. When the 11th NMOS transistor N11 is turned on, the resistance value of the eighth NMOS transistor N8 can be reflected in the drivability control circuit 300A. When the 12th NMOS transistor N12 is turned on, the resistance value of the ninth NMOS transistor N9 can be reflected in the drivability control circuit 300A. When the 13th NMOS transistor N13 is turned on, the resistance value of the tenth NMOS transistor N10 can be reflected in the drivability control circuit 300A.

[0055] One or more of the first to third deviation control signals CTR_S1 to CTR_S3 input to the deviation control circuit 400A can be enabled based on PVT deviation. In other words, when the characteristics of each transistor are determined to be any of "slow," "typical," and "fast," one or more of the first to third deviation control signals CTR_S1 to CTR_S3 can be enabled. Based on the enabled deviation control signals, one or more of the 11th to 13th NMOS transistors N11 to N13 of the deviation control circuit 400A can be turned on. Consequently, the resistance value of one or more of the 8th to 10th NMOS transistors N8 to N10 of the load circuit 320A can be reflected in the drivability control circuit 300A. That is, the deviation control circuit 400A can adjust the resistance value reflected in the drivability control circuit 300A based on the first to third deviation control signals CTR_S1 to CTR_S3 based on PVT deviation. In an embodiment, the resistance value reflected in the drivability control circuit 300A when the PVT deviation is “fast” may be greater than the resistance value reflected in the drivability control circuit 300A when the PVT deviation is “slow”.

[0056] The internal voltage generating circuit 1000 can adjust the resistance value reflected in the drivability control circuit 300A according to the PVT deviation. Therefore, the internal voltage generating circuit 1000 can generate a stable internal voltage V_IN corresponding to the PVT deviation.

[0057] Figure 5 is a block diagram showing a configuration of a semiconductor memory device according to an embodiment.

[0058] The semiconductor memory device may include a memory cell array circuit (not shown). The memory cell array circuit may store data input from an external source and output the stored data to an external destination. The data input to / output from the memory cell array circuit may be, for example, "1" or "0". Below, as an example, the consumption or use of the internal voltage V_IN during the input / output operation of the data corresponding to "1" is greater than the consumption or use of the internal voltage V_IN during the input / output operation of the data corresponding to "0". Therefore, when the consumption of the internal voltage V_IN is high, the power supply supplied as the internal voltage may be increased to stably generate the internal voltage V_IN. On the other hand, when the consumption of the internal voltage V_IN is low, the power supply supplied as the internal voltage V_IN may be reduced to reduce unnecessary power generation.

[0059] Reference Figure 5 , the semiconductor memory device may include a voltage comparison circuit 100B, a voltage driving circuit 200B, a drivability control circuit 300B, a load control circuit 400B, and a data counting circuit 500B. Figure 5 The voltage comparison circuit 100B, the voltage driving circuit 200B and the drivability control circuit 300B correspond to Figure 1 The voltage comparison circuit 100 and the voltage driving circuit 200 and Figure 3 The drivability control circuit 300A is described in detail here, so its detailed description is omitted.

[0060] The load control circuit 400B may be configured to adjust the resistance value reflected in the drivability control circuit 300B based on the data information INF_D input to / output from the memory cell array circuit. The data information INF_D may be obtained by counting the values (e.g., 0 and / or 1) of the data input to / output from the memory cell array circuit. That is, for example, the data information INF_D may include information about the number of 1s.

[0061] The load control circuit 400B can be operated in accordance with Figure 4 The deviation control circuit 400A is implemented in a similar manner. For example, the data information INF_D may indicate that the number of data corresponding to "1" is high, the number of data corresponding to "1" is normal, and the number of data corresponding to "1" is low. Therefore, the data information INF_D may include any one of the first to third data information. The first data information indicates that the number of "1" is high, the second data information indicates that the number of "1" is normal, and the third data indicates that the number of "1" is low. Similar to Figure 4The load control circuit 400B may include an 11th NMOS transistor N11 to a 13th NMOS transistor N13. The 11th NMOS transistor N11 may receive first data information (not shown) as data information INF_D through its gate, the 12th NMOS transistor N12 may receive second data information (not shown) as data information INF_D through its gate, and the 13th NMOS transistor N13 may receive third data information (not shown) as data information INF_D through its gate.

[0062] In other words, one or more of the 11th to 13th NMOS transistors N11 to N13 of the load control circuit 400B may be turned on based on the first to third data information used as the data information INF_D. Figure 4 As described, when one or more NMOS transistors among the 11th to 13th NMOS transistors N11 to N13 are turned on, the resistance value reflected in the drivability control circuit 300B may be adjusted.

[0063] That is, the semiconductor memory device can adjust the resistance value reflected in the drivability control circuit 300B based on the first to third data information. Therefore, the semiconductor memory device can generate a stable internal voltage V_IN corresponding to the input / output data.

[0064] The semiconductor memory device may further include a data counting circuit 500B configured to generate data information INF_D by counting data values DT (ie, the number of 0s and / or 1s) of data input / output to / from the memory cell array circuit.

[0065] The counting circuit 500B can generate data information INF_D by counting, for example, the number of data corresponding to "1" among the data values DT of the data input to / output from the memory cell array circuit. Therefore, the data information INF_D can include information on whether the number of data corresponding to "1" among the data values DT of the data input to / output from the memory cell array circuit is high, normal, or low.

[0066] The semiconductor memory device can generate data information INF_D by counting the data value DT of data input to / output from the memory cell array circuit. The semiconductor memory device can control the voltage level of the control voltage DRVP based on the data information INF_D during active operation. The semiconductor memory device can then generate a stable internal voltage V_IN based on the control voltage DRVP.

[0067] The data information INF_D may be obtained by counting the number of times the value of previous data stored in the memory cell array circuit is different from the value of current data input to the memory cell array circuit. That is, the data information INF_D may include information obtained by counting the number of times the value of previous data stored in the memory cell array circuit is "1" and the value of current data input to the memory cell array circuit is "0" or the number of times the value of previous data stored in the memory cell array circuit is "0" and the value of current data input to the memory cell array circuit is "1."

[0068] When the value of previous data stored in the memory cell array circuit differs from the value of current data input to the memory cell array circuit, this may indicate higher consumption or usage of the internal voltage V_IN. Therefore, the semiconductor memory device can generate data information INF_D by counting the number of times the value of previous data stored in the memory cell array circuit differs from the value of current data input to the memory cell array circuit based on the data value DT of data input to / output from the memory cell array circuit. The semiconductor memory device can control the voltage level of the control voltage DRVP based on the data information INF_D during active operation. The semiconductor memory device can then generate a stable internal voltage V_IN based on the control voltage DRVP.

[0069] Although various embodiments are described above, those skilled in the art will appreciate that the described embodiments are merely examples and therefore the present invention is not limited to any of the described embodiments.

[0070] Effects of the present disclosure are not limited to those described herein; other effects not described above will be understood by those skilled in the art to which the present disclosure pertains from the above description.

[0071] While various embodiments have been shown and described, it will be apparent to those skilled in the art that various changes and modifications can be made without departing from the spirit and scope of the invention as defined in the following claims.

[0072] CROSS-REFERENCE TO RELATED APPLICATIONS

[0073] This application claims the benefit of Korean Application No. 10-2020-0097903, filed on August 5, 2020, in the Korean Intellectual Property Office, which is hereby incorporated by reference in its entirety.

Claims

1. An internal voltage generating circuit, comprising: a voltage comparison circuit configured to generate a control voltage by comparing a reference voltage with a feedback voltage fed back to the voltage comparison circuit; a voltage driving circuit configured to generate an internal voltage based on the control voltage, wherein the internal voltage is used to generate the feedback voltage; a drivability control circuit directly connected to a node outputting the control voltage and configured to turn on based on activation of an enable signal enabled during active operation and to pull down a voltage level of the control voltage based on activation of the enable signal; as well as A load control circuit is connected in series with the drivability control circuit and is configured to adjust a resistance value reflected in the drivability control circuit based on data information input to a gate of the load control circuit.

2. The internal voltage generating circuit according to claim 1, wherein: The drivability control circuit charges a node outputting the control voltage to a set voltage level based on the enable signal.

3. The internal voltage generating circuit according to claim 1, wherein: The voltage comparison circuit comprises: a comparison circuit configured to compare the reference voltage with the feedback voltage; and A current mirror circuit is configured to generate the control voltage through a current mirror operation according to an output signal of the comparison circuit.

4. The internal voltage generating circuit according to claim 1, wherein: The drivability control circuit discharges the output terminal of the voltage comparison circuit based on activation of the enable signal.

5. The internal voltage generating circuit according to claim 1, wherein: The drivability control circuit comprises: A switching circuit is configured to perform a switching operation based on the enable signal. 6 . The internal voltage generating circuit according to claim 5 , further comprising an offset control circuit configured to adjust a resistance value reflected in the drivability control circuit based on an offset control signal.

7. The internal voltage generating circuit according to claim 6, wherein: The load circuit includes a plurality of resistors having different resistance values, Each of the plurality of resistors is selectively enabled based on the deviation control signal.

8. A semiconductor memory device, comprising: a voltage comparison circuit configured to generate a control voltage by comparing a reference voltage with a feedback voltage fed back to the voltage comparison circuit; a voltage driving circuit configured to generate an internal voltage based on the control voltage, wherein the internal voltage is used to generate the feedback voltage; a drivability control circuit directly connected to a node outputting the control voltage and configured to turn on based on activation of an enable signal enabled during active operation and to pull down a voltage level of the control voltage based on activation of the enable signal; as well as a load control circuit connected in series with the drivability control circuit and configured to adjust a resistance value reflected in the drivability control circuit based on data information input to or output from a memory cell array circuit driven by the internal voltage, the data information being input to a gate of the load control circuit.

9. The semiconductor memory device according to claim 8, further comprising a data counting circuit configured to generate the data information by counting data values of data input to or output from the memory cell array circuit.

10. The semiconductor memory device according to claim 8, further comprising a data counting circuit configured to generate the data information by counting the number of times a value of previous data stored in the memory cell array circuit is different from a value of current data input to the memory cell array circuit.

11. The semiconductor memory device according to claim 8, wherein The drivability control circuit charges a node outputting the control voltage to a set voltage level based on the enable signal.

12. The semiconductor memory device according to claim 8, wherein The drivability control circuit comprises: a switching circuit configured to perform a switching operation based on the enable signal; and A load circuit is configured to reflect a resistance value in the switch circuit.

13. The semiconductor memory device according to claim 12, wherein The load circuit includes a plurality of resistors having different resistance values, The load control circuit selectively enables one or more resistors among the plurality of resistors based on the data information.

14. A semiconductor memory device, comprising: a memory cell array configured to store data; as well as An internal voltage generating circuit, the internal voltage generating circuit comprising: a voltage comparison circuit configured to generate a control voltage by comparing a reference voltage with a feedback voltage; a voltage driving circuit configured to generate an internal voltage based on the control voltage and provide the internal voltage to the memory cell array, the internal voltage being fed back to the voltage comparison circuit as the feedback voltage; a drivability control circuit directly connected to a node outputting the control voltage and configured to adjust a voltage level of the control voltage based on at least one of a process, a voltage, a temperature PVT deviation, and a value in the data to control drivability of the voltage driving circuit; a load control circuit configured to adjust a resistance value reflected in the drivability control circuit based on data information input to or output from the memory cell array driven by the internal voltage; and A data counting circuit is configured to generate the data information by counting the number of times a value of previous data stored in the memory cell array is different from a value of current data input to the memory cell array.

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