Method for manufacturing a semiconductor structure

Abstract

A method for manufacturing a semiconductor structure includes: providing a substrate and a target layer disposed above the substrate, the target layer having a central region and a peripheral region; forming a plurality of linear fin features in the central region, wherein the plurality of linear fin features are parallel to each other and each have an uneven edge portion; and removing the uneven edge portions of the linear fin features to obtain uniform linear fin features, thereby improving the physical properties, material properties, and quality of the semiconductor structure.

Description

Technical Field

[0001] The present invention relates to a method for manufacturing a semiconductor structure. Background Art

[0002] As semiconductor device integration density increases, photolithography processes require higher resolution to meet the precision requirements of semiconductor devices. Photolithography is commonly used to manufacture electronic and optoelectronic components on semiconductor substrates. Therefore, patterning accuracy is a key factor in determining the quality of semiconductor devices.

[0003] However, defects caused by edge non-uniformity are primarily due to the photoloading and etch loading effects after the photolithography process. Optical proximity correction (OPC) is commonly used to address edge defects and pre-correct the pattern on the photoresist. However, performing OPC during the semiconductor structure manufacturing process consumes considerable time and cost.

[0004] From the above description, it can be seen that there is a need to develop more efficient methods to manufacture uniform semiconductor structures. Summary of the Invention

[0005] To solve the above problems, the present invention provides a method for manufacturing a semiconductor structure, which includes: providing a substrate and a target layer arranged above the substrate, the target layer having a central area and a peripheral area; forming a plurality of linear fin features in the central area, wherein the plurality of linear fin features are parallel to each other and have uneven edge portions; and removing the uneven edge portions of the linear fin features to obtain uniform linear fin features.

[0006] In one or more embodiments of the present invention, each linear fin feature has a uniform portion, wherein a width of the non-uniform edge portion is greater than a width of the uniform portion.

[0007] In one or more embodiments of the present invention, the method of manufacturing a semiconductor structure further includes forming a hard mask between the substrate and the target layer.

[0008] In one or more embodiments of the present invention, the target layer includes silicon nitride.

[0009] In one or more embodiments of the present invention, forming a plurality of linear fin features in the central region includes performing a first photolithography and etching process on the central region of the target layer.

[0010] In one or more embodiments of the present invention, removing the uneven edge portion of the linear fin feature and obtaining a uniform linear fin feature includes: forming a patterned photoresist layer covering the target layer, wherein the patterned photoresist layer includes an opening exposing the uneven edge portion; removing the uneven edge portion; and removing the patterned photoresist layer.

[0011] In one or more embodiments of the present invention, the width of the opening is between 100 nm and 1 μm.

[0012] In one or more embodiments of the present invention, the method for fabricating a semiconductor structure further includes etching the uniform linear fin feature so that each uniform linear fin feature is divided into a plurality of fin feature segments, and two adjacent fin feature segments are separated by a trench.

[0013] In one or more embodiments of the present invention, the method of manufacturing a semiconductor structure further includes forming an isolation structure in the trench.

[0014] In one or more embodiments of the present invention, the method of manufacturing a semiconductor structure further includes performing a grinding process on the isolation structure to expose the fin feature segment.

[0015] In one or more embodiments of the present invention, etching the uniform linear fin feature so that each uniform linear fin feature is divided into a plurality of fin feature segments includes performing a second photolithography etching process on each uniform linear fin feature to obtain a plurality of fin feature segments.

[0016] In summary, the present invention provides a method for fabricating a semiconductor structure in which non-uniformities caused by optical loading and etch loading are avoided, thereby producing uniform linear fin features. Subsequently, the uniform linear fin features are etched to form fin feature segments. Because the non-uniform edges of the linear fin features are removed, high-quality fin feature segments can be efficiently produced.

[0017] The above description is only used to illustrate the problems to be solved by the present invention, the technical means for solving the problems, and the effects produced, etc. The specific details of the present invention will be introduced in detail in the following embodiments and related drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] To illustrate how the above and other advantages and features of the present invention are achieved, the principles briefly described above will be more particularly explained with reference to specific embodiments thereof, which are illustrated in the accompanying drawings. These drawings are merely illustrative of the present invention and are not to be considered limiting of its scope. The principles of the present invention will be more clearly explained, and additional features and details will be more fully described through the accompanying drawings, in which:

[0019] Figure 1 A flowchart illustrating steps of a method for manufacturing a semiconductor structure according to one or more embodiments of the present invention is shown;

[0020] Figures 2 to 7 To graphically represent Figure 1 The steps of the method for manufacturing a semiconductor structure;

[0021] Figure 8 is a top view of a semiconductor structure without using the method provided by the present invention; and

[0022] Figure 9 It is a top view of a semiconductor structure using the method provided by the present invention. DETAILED DESCRIPTION

[0023] The present invention can be implemented in many different forms. Representative embodiments are shown in the accompanying drawings and will be described in detail herein. This disclosure includes examples or illustrations of principles, and aspects of the disclosure are not limited to the embodiments shown.

[0024] In addition, relative terms (such as "up" or "down", "top" or "bottom", "left" or "right") can be used to describe the relationship between elements in the drawings. It is understood that in addition to the relationships depicted in the drawings, relative terms cover other relationships of devices. For example, if a device in a drawing is turned over, an element described as "below" other elements will be located "above" the other elements. Therefore, based on the structural relationship in the drawings, the illustrated word "below" can also be interpreted as "above" and "below". Similarly, if the device in the drawing is turned over, when an element is described as "below" or "below" other elements, it will also be interpreted as "above" and "above" other elements. Similarly, relative terms such as "below" or "below" can also be interpreted as "above" or "above" an element.

[0025] Figure 1A step flow chart of a method 100 for manufacturing a semiconductor structure is shown according to one or more embodiments of the present invention. Method 100 begins with step 101, wherein step 101 is to provide a substrate and a target layer thereon, and the target layer includes a central region and a peripheral region. Method 100 then proceeds to step 102, wherein step 102 includes forming a plurality of linear fin features in the central region, wherein the plurality of linear fin features are parallel to each other and have uneven edge portions. Method 100 then proceeds to step 103, wherein step 103 includes removing the uneven edge portions of the linear fin features, thereby obtaining uniform linear fin features. Then, method 100 proceeds to step 104, wherein step 104 includes etching the uniform linear fin features, so that each uniform linear fin feature is divided into a plurality of fin feature segments, and two adjacent fin feature segments are separated by trenches. Method 100 then proceeds to step 105, wherein step 105 includes forming an isolation structure in the trench. Next, method 100 proceeds to step 106, which includes performing a grinding process on the isolation structure to expose the fin features. Although method 100 is depicted as a series of steps in the figures, it should be understood that the order of the steps in the figures is not intended to limit method 100. For example, some steps may be performed in a different order and may be performed concurrently with processes other than those described herein.

[0026] Figures 2 to 7 To graphically represent Figure 1 1 and 2. Various steps of a method 100 for fabricating a semiconductor structure. Figure 2 draw Figure 1 For details on step 101 in Figure 1 and Figure 2 Step 101 includes providing a substrate 210 and a target layer 230, wherein the target layer 230 is disposed on the substrate 210 and includes a central area CA and a peripheral area PA. In some embodiments of the present invention, the material of the substrate 210 is different from the material of the target layer 230. The substrate 210 includes silicon (Si), gallium (Ga), gallium arsenide (GaAs), gallium nitride (GaN), strained silicon, silicon germanium (SiGe), silicon carbide (SiC), diamond, an epitaxial layer, or a combination thereof, while the material of the target layer 230 is actually determined by the type of semiconductor structure. In some embodiments of the present invention, the target layer 230 includes an insulating material (e.g., silicon nitride), a semiconductor material, or a conductive material. The target layer 230 can be formed on the substrate 210 using, for example, physical vapor deposition (PVD), chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), or other suitable deposition processes, but the present invention is not limited thereto.

[0027] In some embodiments of the present invention, the method 100 further includes forming a hard mask between the substrate 210 and the target layer 230 , wherein the hard mask is a single-layer structure or a multi-layer structure, but the present invention is not limited thereto.

[0028] Please refer to Figure 2 and Figure 3 . Figure 2 and Figure 3 Can be used to graphically represent Figure 1 Step 102 in FIG. In some embodiments of the present invention, a first photolithography etching process is performed on the central area CA of the target layer 230, thereby forming a linear fin feature 231 within the central area CA. The photolithography etching process involves transferring a geometric pattern from a mask to a light-sensitive chemical photoresist using light, followed by a series of chemical processes. The exposed pattern is then etched into a desired material, and the desired pattern can be deposited onto the material beneath the photoresist via a deposition process. Specifically, due to the light loading effect and the etching loading effect, the linear fin feature 231 includes an uneven edge portion 231a and a uniform portion 231b, where the width X2 of the uneven edge portion 231a is greater than the width X1 of the uniform portion 231b.

[0029] Please refer to Figures 3 to 5 . Figures 3 to 5 Can be used to graphically represent Figure 1 Step 103 in FIG. In some embodiments of the present invention, step 103 includes removing the uneven edge portion 231a of the linear fin feature 231 to obtain a uniform linear fin feature 233. In some embodiments of the present invention, removing the uneven edge portion 231a of the linear fin feature 231 includes: forming a patterned photoresist layer 250 covering the peripheral area PA and the target layer 230, wherein the patterned photoresist layer 250 includes an opening 251, wherein the opening 251 exposes the uneven edge portion 231a of the linear fin feature 231; and removing the uneven edge portion 231a using the patterned photoresist layer 250 and then removing the patterned photoresist layer 250. Since only the uniform portion 231b of the linear fin feature 231 remains, a uniform linear fin feature 233 is obtained.

[0030] Specifically, the patterned photoresist layer 250 may include a positive photoresist layer or a negative photoresist layer, wherein a patterned mask (not shown) is implemented to cover portions of the patterned photoresist layer 250 and block light, thereby exposing uncovered portions of the patterned photoresist layer 250 to light. A solution may be applied to the patterned photoresist layer 250 to remove either the covered or uncovered portions of the patterned photoresist layer 250. When a positive photoresist layer is used, the uncovered portions of the patterned photoresist layer 250 are degraded and dissolved and removed. When a negative photoresist layer is used, the uncovered portions of the patterned photoresist layer 250 are intensified by light, while the solution dissolves and removes the covered portions of the patterned photoresist layer 250. Through the aforementioned method, the patterned photoresist layer 250 is patterned to have an opening 251. Furthermore, the width W of the opening 251 is between approximately 100 nm and approximately 1 μm to expose the uneven edge portion 231a.

[0031] In some embodiments of the present invention, any suitable etching process can be used to remove the uneven edge portion 231a. The etching process can be an anisotropic etching process (e.g., a dry etching process) or an isotropic etching process (e.g., a wet etching process), but the present invention is not limited thereto. Alternatively, any suitable removal process can be used to remove the patterned photoresist layer 250, such as applying an organic solution or an inorganic solution to the patterned photoresist layer 250, but the present invention is not limited thereto.

[0032] Please refer to Figure 5 and Figure 6 . Figure 5 and Figure 6 Can be used to graphically represent Figure 1 In some embodiments of the present invention, step 104 of the method 100 for forming a semiconductor structure further includes etching the uniform linear fin features 233, whereby each uniform linear fin feature 233 is divided into a plurality of fin feature segments 235, and two adjacent fin feature segments 235 are separated by trenches 237. Specifically, a second photolithography etching process is performed on the uniform linear fin features 233 to obtain the fin feature segments 235, but the present invention is not limited thereto.

[0033] Please refer to Figure 6 and Figure 7 . Figure 6 and Figure 7 Can be used to represent graphically Figure 1In some embodiments of the present invention, the method 100 for forming a semiconductor structure further includes step 106, wherein step 106 includes forming an isolation structure 239 in the trench 237. The isolation structure 239 surrounds the fin feature segment 235 to form a shallow trench isolation (STI) structure between the plurality of fin feature segments 235. Next, the method 100 proceeds to step 107, wherein step 107 includes performing a polishing process on the isolation structure 239, wherein the polishing process may be a chemical mechanical polishing (CMP) process, thereby exposing the top surface of the fin feature segment 235. Thus, a semiconductor structure 200 is formed, wherein the edges of the fin feature segment 235 of the semiconductor structure 200 are relatively uniform. In addition, the semiconductor structure 200 further includes an isolation structure 239, wherein the isolation structure 239 surrounds and exposes the fin feature segment 235.

[0034] Please refer to Figure 8 and Figure 9 . Figure 8 It is a top view of a semiconductor structure without using the method 100 provided by the present invention. Figure 9 FIG. 1 is a top view of a semiconductor structure using the method 100 provided by the present invention. Figure 8 As shown in FIG, the edges of some fin feature segments in the semiconductor structure are not uniform. Figure 9 As shown, the fin feature segments are effectively modified and the edges are relatively uniform, so that a better semiconductor structure can be obtained by implementing the method 100 .

[0035] In summary, the present invention provides a method for fabricating a semiconductor structure in which non-uniformities caused by optical loading and etch loading are avoided, thereby producing uniform linear fin features. Subsequently, the uniform linear fin features are etched to form fin feature segments. Because the non-uniform edges of the linear fin features are removed, high-quality fin feature segments can be efficiently produced.

[0036] While various embodiments of the present invention have been described above, it should be understood that these embodiments are presented as examples only and are not intended to be limiting. Numerous modifications may be made to the embodiments disclosed herein without departing from the spirit and scope of the present invention. Therefore, the breadth and scope of the present invention should not be limited by the embodiments described above.

[0037]

Explanation of symbols

[0038] 100: Method

[0039] 101,102,103,104,105,106,107: Steps

[0040] 200: Semiconductor Structure

[0041] 210: substrate

[0042] 230: Target layer

[0043] 231: Linear fin features

[0044] 231a: Uneven edge

[0045] 231b: Uniform part

[0046] 233: Uniform linear fin features

[0047] 235: Fin feature segment

[0048] 237: Ditch

[0049] 239: Isolation Structure

[0050] 250: Patterned photoresist layer

[0051] 251: Opening

[0052] CA: Central Area

[0053] PA: surrounding area

[0054] W, X1, X2: width.

Claims

1. A method for manufacturing a semiconductor structure, characterized in that: include: Providing a substrate and a target layer disposed above the substrate, wherein the target layer has a central area and a peripheral area; forming a plurality of linear fin features in the central region, wherein the linear fin features are parallel to each other and each have a uniform portion and a non-uniform edge portion; and The uneven edge portions of the linear fin features are removed, and the uniform portions of the linear fin features are retained, wherein the size of the uniform portions remains unchanged, thereby obtaining uniform linear fin features.

2. The method according to claim 1, characterized in that The width of the uneven edge portion is greater than the width of the uniform portion.

3. The method according to claim 1, characterized in that Also includes: A hard mask is formed between the substrate and the target layer.

4. The method according to claim 1, wherein The target layer includes silicon nitride.

5. The method according to claim 1, wherein A plurality of linear fin features are formed in the central region including: A first photolithography etching process is performed on the central region of the target layer.

6. The method according to claim 1, characterized in that Removing the uneven edge portions of the linear fin features and obtaining uniform linear fin features includes: forming a patterned photoresist layer covering the target layer, wherein the patterned photoresist layer includes an opening exposing the uneven edge portion; removing the uneven edge portion; and The patterned photoresist layer is removed.

7. The method according to claim 6, characterized in that The width of the opening is between 100 nm and 1 μm.

8. The method according to claim 1, characterized in that Also includes: The uniform linear fin features are etched so that each of the uniform linear fin features is divided into a plurality of fin feature segments, and two adjacent fin feature segments are separated by a trench.

9. The method according to claim 8, characterized in that Also includes: An isolation structure is formed in the trench.

10. The method according to claim 9, characterized in that Also includes: A grinding process is performed on the isolation structure to expose the fin feature segments.

11. The method according to claim 8, characterized in that Etching the uniform linear fin features so that each of the uniform linear fin features is divided into a plurality of fin feature segments includes: A second photolithography and etching process is performed on each of the uniform linear fin features to obtain the fin feature segments.

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