Line end structure and method for forming the same

Abstract

The present invention discloses a line end structure and a method for forming the same. The line end structure includes a substrate, a plurality of wires, and a first insulating pattern layer. The plurality of wires are located on the substrate. The first insulating pattern layer is located on the substrate. The first insulating pattern layer includes a plurality of first insulating portions and a second insulating portion. The plurality of first insulating portions are located on the plurality of wires. The second insulating portion connects the plurality of first insulating portions.

Description

Technical Field

[0001] The present invention relates to a circuit structure and a method for forming the same, and more particularly to a circuit end structure and a method for forming the same. Background Art

[0002] In the manufacturing process of semiconductors, defects in wire end cuts often cause layout failures. For example, if adjacent wires are unexpectedly connected near their ends, it will cause an unexpected short circuit and affect the quality of the components. Summary of the Invention

[0003] The present invention provides a circuit end structure and a method for forming the same, which have better quality.

[0004] The circuit end structure of the present invention includes a substrate, a plurality of wires, and a first insulating pattern layer. The plurality of wires are located on the substrate. The first insulating pattern layer is located on the substrate. The first insulating pattern layer includes a plurality of first insulating portions and a second insulating portion. The plurality of first insulating portions are respectively located on the plurality of wires. The second insulating portion connects two adjacent plurality of first insulating portions. No wires are formed between the second insulating portion and the substrate.

[0005] In an embodiment of the present invention, the thickness of the plurality of first insulating portions is less than the thickness of the second insulating portion.

[0006] In an embodiment of the present invention, the sum of the thicknesses of the plurality of first insulating portions and the plurality of wires is the same as the thickness of the second insulating portion.

[0007] In an embodiment of the present invention, the top surfaces of the plurality of first insulating portions are coplanar with the top surface of the second insulating portion.

[0008] In an embodiment of the present invention, the plurality of first insulating portions cover the top surfaces of the plurality of wires, and the second insulating portion covers the side surfaces of the ends of the plurality of wires.

[0009] In an embodiment of the present invention, the second insulating portion includes an arc-shaped pattern protruding away from the plurality of wires.

[0010] In an embodiment of the present invention, the width of the second insulating portion is greater than or equal to the width of the plurality of first insulating portions.

[0011] In an embodiment of the present invention, the circuit end structure further includes a second insulating layer. The second insulating layer is at least located between the plurality of wires. The second insulating layer covers the opposite two side surfaces of the wires.

[0012] In an embodiment of the present invention, the second insulating layer also covers the opposite two side surfaces of the first insulating pattern layer.

[0013] The method for forming a line end structure of the present invention includes the following steps: providing a substrate; forming a conductive layer on the substrate; forming a first insulating layer on the substrate, and the first insulating layer at least covers the conductive layer; removing part of the first insulating layer to form a first insulating pattern layer, wherein the first insulating pattern layer includes a plurality of first insulating parts and a second insulating part, and the second insulating part connects two adjacent plurality of first insulating parts; and removing part of the first conductive layer to form a plurality of conductive wires, wherein the plurality of conductive wires are respectively located between the plurality of first insulating parts and the substrate, and a plurality of conductive wires are not formed between the second insulating part and the substrate.

[0014] Based on the above, the conductors of the line end structure can have better quality. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1A , Figure 2A , Figure 3A and Figure 4A is a partial top view schematic diagram of a partial method for forming a line end structure according to a first embodiment of the present invention;

[0016] Figure 1B , Figure 2B , Figure 3B and Figure 4B is a partial cross-sectional schematic diagram of a method for partially forming a line end structure according to a first embodiment of the present invention;

[0017] Figure 1C , Figure 2C , Figure 3C , Figure 3D , Figure 4C and Figure 4D is a partial cross-sectional schematic diagram of a method for partially forming a line end structure according to a first embodiment of the present invention;

[0018] Figure 5A is a partial top view schematic diagram of a line end structure according to a second embodiment of the present invention;

[0019] Figure 5B and Figure 5C It is a partial cross-sectional schematic diagram of a line end structure according to the second embodiment of the present invention.

[0020] Explanation of symbols

[0021] 100, 200: Line end structure

[0022] 110:Substrate

[0023] 111: District 1

[0024] 112: District 2

[0025] 113: Third zone

[0026] 120: Insulating layer

[0027] 121, 122: Film layers

[0028] 139: Conductive layer

[0029] 130, 131, 132: Conductors

[0030] 130h: Thickness

[0031] 130a: First side

[0032] 130b: Second side

[0033] 130c: Third side

[0034] 130d: Top surface

[0035] 140: First insulating layer

[0036] 140d: Top surface

[0037] 141: Part of the first insulating layer

[0038] 141h: Thickness

[0039] 142: Part of the first insulating layer

[0040] 142h: Thickness

[0041] 151, 152, 153: Film layers

[0042] 155: Mask layer

[0043] 160: First insulating pattern layer

[0044] 160b, 160c: Sides

[0045] 160d: Top surface

[0046] 161: First insulating part

[0047] 161d: Top surface

[0048] 161h: Thickness

[0049] 162: Second insulating part

[0050] 162d: Top surface

[0051] 162h: Thickness

[0052] 270: Second insulating layer

[0053] S: Spacing

[0054] L1, L2, L3, L4: Width DETAILED DESCRIPTION

[0055] Some embodiments are listed below and described in detail with the accompanying drawings, but the embodiments provided are not intended to limit the scope of the present invention. In addition, the drawings are for illustration purposes only and are not drawn in original size. For ease of understanding, the same elements in the following description will be described with the same symbols. In addition, the terms "including" or "having" used in the text are open terms; that is, "including" or "having" but not limited to.

[0056] The terms "substantially" or "approximately" used herein may include an acceptable tolerance range. Moreover, the directional terms mentioned herein, such as "upper", "lower", "top", "bottom", etc., are only used to refer to the directions of the drawings. Therefore, the directional terms used are used for explanation, not for limiting the present invention.

[0057] When an element (such as a film layer, a region or other similar terms) is referred to as being "on another element" or "connected to another element", it may be directly on or connected to another element, or other elements may exist in between. Similarly, when a step (such as a manufacturing process or other similar terms) is referred to as being "after another step", it may be performed directly after the other step, or other steps may exist in between.

[0058] Figure 1A , Figure 2A , Figure 3A and Figure 4A 1 is a partial top view schematically showing a partial method for forming a line end structure according to a first embodiment of the present invention. Figure 1B It can be corresponding to Figure 1A Schematic cross-sectional view on the A-A' section line. Figure 1C It can be corresponding to Figure 1A Schematic diagram of the cross-section on the BB' section line or the C-C' section line. Figure 2B It can be corresponding to Figure 2A Schematic cross-sectional view on the D-D' section line. Figure 2C It can be corresponding to Figure 2A Schematic cross-sectional view on the E-E' section line or the F-F' section line. Figure 3B It can be corresponding to Figure 3A Schematic diagram of the cross-section on the G-G' section line. Figure 3C It can be corresponding to Figure 3A Schematic cross-sectional view on the H-H' section line. Figure 3D It can be corresponding to Figure 3ASchematic diagram of the cross-section on the J-J' section line. Figure 4B It can be corresponding to Figure 4A Schematic diagram of the cross-section on the K-K' section line. Figure 4C It can be corresponding to Figure 4A Schematic cross-sectional view on the L-L' section line. Figure 4D It can be corresponding to Figure 4A In addition, the positions of the section lines A-A', D-D', G-G' and / or K-K' corresponding to the substrate 110 may be the same or similar, the positions of the section lines B-B', E-E', H-H' and / or L-L' corresponding to the substrate 110 may be the same or similar, and the positions of the section lines C-C', F-F', J-J' and / or M-M' corresponding to the substrate 110 may be the same or similar.

[0059] Please refer to Figure 1A , Figure 1B and Figure 1C , providing a substrate 110. The substrate 110 may have a first region 111, a second region 112, and a third region 113. The second region 112 is located between the first region 111 and the third region 113. The first region 111 and the third region 113 may be connected to two different sides of the second region 112, respectively.

[0060] In this embodiment, the substrate 110 may include a silicon substrate or other similar semiconductor substrates, but the present invention is not limited thereto. For example, the substrate 110 may include a silicon wafer.

[0061] Please refer to Figure 1A , Figure 1B and Figure 1C , a conductive layer 139 is formed on the first region 111 of the substrate 110. The conductive layer 139 may be formed by sputtering, deposition, plating and / or other suitable manufacturing processes, but the present invention is not limited thereto. In the present embodiment, the conductive layer 139 does not substantially cover the second region 112 or the third region 113 of the substrate 110. Based on conductivity considerations, the material of the conductive layer 139 may include metal, metal alloy, metal silicide, metal nitride or a stack of the above, but the present invention is not limited thereto.

[0062] In this embodiment, the insulating layer 120 may be formed on the substrate 110, and the conductive layer 139 may be formed on the insulating layer 120. In other words, a portion of the insulating layer 120 may be located between the conductive layer 139 and the substrate 110.

[0063] In one embodiment, the insulating layer 120 may be formed by a deposition process or other suitable process, but the present invention is not limited thereto. In one embodiment, the insulating layer 120 may be made of silicon oxide, silicon nitride or a combination thereof, but the present invention is not limited thereto.

[0064] In this embodiment, the insulating layer 120 may include a plurality of film layers 121 and 122, but the present invention is not limited thereto. In one embodiment, the insulating layer 120 may be a single-layer structure.

[0065] In an embodiment not shown, the film layer 121 or the film layer 122 may have other same or different uses in other unshown regions on the substrate 110. For example, the film layer 121 may include silicon dioxide (SiO x ) layer, but the present invention is not limited thereto. For another example, the film layer 122 may include a hard mask (HM) layer.

[0066] In one embodiment, the insulating layer 120 may include a film layer called a buffer layer, but the present invention is not limited thereto.

[0067] Please refer to Figure 2A , Figure 2B and Figure 2C , a first insulating layer 140 is formed at least on the first region 111 and the second region 112 of the substrate 110 . The first insulating layer 140 covers the conductive layer 139 .

[0068] In the present embodiment, the first insulating layer 140 may be further located on the third region 113 of the substrate 110 , but the present invention is not limited thereto.

[0069] In the present embodiment, the top surface 140d of the first insulating layer 140 may be a flat surface, but the present invention is not limited thereto. For example, a first insulating material layer (not shown) may be formed on the substrate 110 in a manner that is the same as or similar to the formation of the insulating layer 120. Then, a chemical-mechanical polishing process (CMP process) or other suitable planarization process may be performed on the first insulating material layer to form the first insulating layer 140 having a flat top surface 140d.

[0070] In this embodiment, the thickness 141h of a part of the first insulating layer 141 covering the conductive layer 139 may be different from the thickness 142h of other parts of the first insulating layer 142 at other locations (e.g., where the conductive layer 139 is not covered). For example, the thickness 141h may be less than the thickness 142h.

[0071] In one embodiment, the first insulating layer 140 may include a film layer called a buffer layer, but the present invention is not limited thereto.

[0072] Please refer to Figure 3A 、 Figure 3B 、 Figure 3C and Figure 3D ,a mask layer 155 may be formed on the substrate 110. The mask layer 155 may overlap a part of the conductive layer 139 and a part of the first insulating layer 140, and the material of the mask layer 155 is substantially different from that of the conductive layer 139 and the first insulating layer 140. For example, the mask layer 155 may include a patterned amorphous silicon layer formed by deposition and photolithographic etching, but the present invention is not limited thereto.

[0073] Please refer to Figures 3A to 4A 、 Figures 3B to 4B 、 Figures 3C to 4C and Figures 3D to 4D ,in one embodiment, parts of the film layers 151, 152, 153 located on the first insulating layer 140 and not covered by the mask layer 155 may be removed by etching or other suitable means.

[0074] In an embodiment not shown, the film layer 151, the film layer 152, or the film layer 153 may have other same or different uses in other areas not shown on the substrate 110.

[0075] Please refer to Figures 3A to 4A 、 Figures 3B to 4B 、 Figures 3C to 4C and Figures 3D to 4D ,a part of the first insulating layer 140 is removed to form a first insulating pattern layer 160. The first insulating pattern layer 160 includes a plurality of first insulating parts 161 and a second insulating part 162. The plurality of first insulating parts 161 are located in the first region 111. The second insulating part 162 is located in the second region 112. The second insulating part 162 connects the plurality of first insulating parts 161.

[0076] In this embodiment, parts of the first insulating layer 140 not covered by the mask layer 155 may be removed by etching (e.g., dry etching, but not limited) or other suitable means, but the present invention is not limited thereto.

[0077] In this embodiment, the pattern of the first insulating pattern layer 160 may be the same as or similar to the pattern of the mask layer 155. That is to say, the pattern of the first insulating pattern layer 160 can be adjusted at least according to the pattern design of the mask layer 155, which is not limited in the present invention.

[0078] Please refer to Figures 3A to 4A , Figures 3B to 4B , Figures 3C to 4C and Figures 3D to 4D , and remove a part of the first conductive layer 139 to form a plurality of conductive lines 130. The plurality of conductive lines 130 are located between the plurality of first insulating portions 161 and the substrate 110. For example, each conductive line 130 is located between each first insulating portion 161 and the substrate 110.

[0079] In this embodiment, the unmasked part of the first conductive layer 139 can be removed by etching (such as dry etching, but not limited thereto) or other suitable means, but the present invention is not limited thereto.

[0080] In this embodiment, the pattern of the conductive lines 130 may be the same as or similar to a part of the pattern of the mask layer 155. That is to say, the pattern of the conductive lines 130 can be adjusted at least according to the pattern design of the mask layer 155, which is not limited in the present invention.

[0081] In one embodiment, after forming the first insulating pattern layer 160 and the plurality of conductive lines 130, the mask layer 155 can be removed. For example, the mask layer 155 can be removed by removing the film layer between the first insulating pattern layer 160 and the mask layer 155 (such as the patterned film layer 151).

[0082] In one embodiment, during the process of removing a part of the first conductive layer 139 or removing the mask layer 155 (such as the process of removing the film layer between the first insulating pattern layer 160 and the mask layer 155), a part of the insulating layer 120 may be slightly removed, but the present invention is not limited thereto.

[0083] After the above forming method, the fabrication of the line end structure 100 of this embodiment can be substantially completed.

[0084] Please refer to Figure 4A , Figure 4B , Figure 4C and Figure 4D, the line end structure 100 includes a substrate 110, a plurality of wires 130, and a first insulating pattern layer 160. The substrate 110 has a first region 111 and a second region 112. The second region 112 is connected to the first region 111. The plurality of wires 130 are located on the first region 111 of the substrate 110. The first insulating pattern layer 160 includes a plurality of first insulating portions 161 and a second insulating portion 162. The first insulating portions 161 are located on the first region 111 of the substrate 110. The plurality of wires 130 are located between the plurality of first insulating portions 161 and the substrate 110. The second insulating portion 162 is located on the second region 112 of the substrate 110. The second insulating portion 162 connects the plurality of first insulating portions 161.

[0085] In this embodiment, the line end structure 100 formed by the above forming method can reduce the possibility that adjacent wires 130 come into unexpected contact with each other. Therefore, the wires 130 have better quality. For example, the plurality of wires 130 may include adjacent wires 131 and 132, and the wires 131 and 132 may be separated from each other.

[0086] In this embodiment, the line end structure 100 formed by the above forming method can be used for electronic components with high-density lines. For example, the wire 130 may be a bit line (BL), and the pitch S between adjacent wires 130 may be less than or equal to 70 nanometers (nm), but the present invention is not limited thereto. In one embodiment, the pitch S between adjacent wires 130 may be less than or equal to 60 nanometers.

[0087] In this embodiment, the first insulating pattern layer 160 can provide good protection for the wires 130, or can reduce the possibility that the wires 130 come into unexpected contact with other conductors.

[0088] In this embodiment, by connecting the plurality of first insulating portions 161 through the second insulating portion 162, the possibility that the first insulating portions 161 are tilted or peeled off can be reduced.

[0089] In this embodiment, the width of the second insulating portion 162 may be greater than or equal to the width L1 of the first insulating portion 161. For example, the width at the connection between the second insulating portion 162 and the first insulating portion 161 may be substantially equal to the width L1 of the first insulating portion 161, and the width of the second insulating portion 162 away from the first insulating portion 161 (such as width L2, width L3, or width L4) may be greater than the width L1 of the first insulating portion 161. In this embodiment, the width L1 of the first insulating portion 161 is substantially equal to the width of the wire 130.

[0090] In this embodiment, the width of the second insulating portion 162 may gradually increase in the extending direction away from the first insulating portion 161 starting from the connection with the first insulating portion 161. For example, the width L4 may be greater than the width L3, and the width L3 may be greater than the width L2. In this way, the possibility of the second insulating portion 162 toppling or peeling off can be reduced.

[0091] In this embodiment, the second insulating portion 162 includes an arc-shaped pattern protruding in a direction away from the plurality of wires. In this way, the possibility of the second insulating portion 162 toppling or peeling off can also be reduced.

[0092] In this embodiment, the substrate 110 may further have a third region 113. The plurality of wires 130 and the first insulating pattern layer 160 may be located on a region outside the third region 113.

[0093] In this embodiment, the thickness 161h of the first insulating portion 161 is less than the thickness 162h of the second insulating portion 162.

[0094] In this embodiment, the sum of the thickness 161h of the first insulating portion 161 and the thickness 130h of the wire 130 is substantially the same as the thickness 162h of the second insulating portion 162. For example, the sum of the thickness 130h of a wire 130 and the thickness 161h of the first insulating portion 161 above the aforementioned wire 130 may be the same as the thickness 162h of the second insulating portion 162.

[0095] In this embodiment, the top surface 161d of the first insulating portion 161 is substantially coplanar with the top surface 162d of the second insulating portion 162.

[0096] In this embodiment, the wire 130 may have a top surface 130d, a first side surface 130a, a second side surface 130b, and a third side surface 130c. The top surface 130d may be the surface of the wire 130 away from the substrate 110. The first side surface 130a may be the side surface at the end of the wire 130. The top surface 130d connects the first side surface 130a, the second side surface 130b, and the third side surface 130c. The first side surface 130a connects the top surface 130d, the second side surface 130b, and the third side surface 130c. The second side surface 130b is opposite to the third side surface 130c. The first insulating portion 161 may cover the top surface 130d of the corresponding wire 130. The second insulating portion 162 may cover the first side surface 130a of the corresponding wire 130. In one embodiment, the second side surface 130b and the third side surface 130c of the wire 130 may not be covered by the first insulating pattern layer 160.

[0097] Figure 5A It is a partial top view schematic diagram of a line end structure according to the second embodiment of the present invention.Figure 5B It may be a cross-sectional schematic diagram corresponding to Figure 5A the cross-section along the N-N’ line in Figure 5B It may be a cross-sectional schematic diagram corresponding to Figure 5A the cross-section along the P-P’ line in

[0098] Please refer to Figure 5A , Figure 5B and Figure 5C , the circuit end structure 200 includes a substrate 110, a plurality of conductive wires 130, a first insulating pattern layer 160, and a second insulating layer 270. The second insulating layer 270 is at least located between the plurality of conductive wires 130. The second insulating layer 270 may cover the second side surface 130b and / or the third side surface 130c of the conductive wire 130.

[0099] In this embodiment, the second insulating layer 270 may be formed on the substrate 110 by a deposition manufacturing process or other suitable manufacturing processes.

[0100] In this embodiment, the second insulating layer 270 may also be located on the third region 113 of the substrate 110.

[0101] In this embodiment, the second insulating layer 270 may cover the opposite side surfaces 160b, 160c of the first insulating pattern layer 160.

[0102] In this embodiment, the second insulating layer 270 may reduce the possibility of the first insulating pattern layer 160 toppling or peeling.

[0103] In this embodiment, the second insulating layer 270 and the first insulating pattern layer 160 may be formed in different steps. Therefore, a corresponding interface may exist between the second insulating layer 270 and the first insulating pattern layer 160.

[0104] In this embodiment, the second insulating layer 270 may further cover the top surface 160d of the first insulating pattern layer 160. In one embodiment, other components or film layers may be formed on the second insulating layer 270.

[0105] In an embodiment not shown, the film layers in the foregoing drawings may have the same, similar, or different patterns on other unshown regions of the substrate 110; or, they may not appear on other unshown regions of the substrate 110. For example, the conductive wire 130 may include curved stripes in other unshown regions.

[0106] In an unillustrated embodiment, there may be other steps that are not shown or described between the two steps. For example, after completing Figure 2A 、 Figure 2B and Figure 2C the structures shown, and before forming Figure 3A 、 Figure 3B 、 Figure 3C and Figure 3D the structures shown, other film layers may be formed, patterned, and / or removed on the substrate 110.

[0107] In an unillustrated embodiment, other film layers or components may be present on other unillustrated regions of the substrate 110. For example, on the other unillustrated regions of the substrate 110 of Figure 4A 、 Figure 4B 、 Figure 4C and Figure 4D there may be included active elements (such as thin film transistors), passive elements (such as capacitors), or other suitable elements composed of one or more conductive layers, semiconductive layers, and / or insulating layers.

[0108] In the foregoing embodiments (including the illustrated embodiments, the described embodiments, or the unillustrated embodiments), the conductive layer may be a single-layer or multi-layer structure. And if the conductive layer is a multi-layer structure, there may be no insulating material between the foregoing multi-layers.

[0109] In the foregoing embodiments (including the illustrated embodiments, the described embodiments, or the unillustrated embodiments), the insulating layer may be a single-layer or multi-layer structure. And if the insulating layer is a multi-layer structure, there may be no conductive material between the foregoing multi-layers.

[0110] In summary, the line end structure of the present invention and its forming method can make the wires have better quality.

Claims

1. A line end structure, characterized in that Comprising: A substrate; A plurality of conductors located on the substrate; And A first insulating pattern layer located on the substrate, and the first insulating pattern layer comprises: A plurality of first insulating portions respectively located on the plurality of conductors; And A second insulating portion connecting two adjacent conductors and connecting the first insulating portions on the two adjacent conductors, and the second insulating portion only covers the side surfaces of the ends of the two adjacent conductors, without covering the side surfaces between the two adjacent conductors, wherein the plurality of conductors are not formed between the second insulating portion and the substrate.

2. The line end structure according to claim 1, wherein the thickness of the plurality of first insulating portions is less than the thickness of the second insulating portion.

3. The line end structure according to claim 2, wherein the sum of the thicknesses of the plurality of first insulating portions and the thicknesses of the plurality of wires is the same as the thickness of the second insulating portion.

4. The line end structure according to claim 1, wherein the top surfaces of the plurality of first insulating portions are coplanar with the top surface of the second insulating portion.

5. The line end structure according to claim 1, wherein the plurality of first insulating portions cover the top surfaces of the plurality of wires.

6. The line end structure according to claim 1, wherein the second insulating portion includes an arc-shaped pattern protruding away from the plurality of wires.

7. The line end structure according to claim 1, wherein the width of the second insulating portion is greater than or equal to the width of the plurality of first insulating portions.

8. The line end structure according to claim 1, further comprising: A second insulating layer at least located between the plurality of conductors, and the second insulating layer covers opposite two side surfaces of the plurality of conductors.

9. The line end structure according to claim 8, wherein the second insulating layer further covers opposite side surfaces of the first insulating pattern layer.

10. A method for forming a line end structure, comprising: Providing a substrate; Forming a conductive layer on the substrate; Forming a first insulating layer on the substrate, and the first insulating layer at least covers the conductive layer; And Removing a part of the first insulating layer to form a first insulating pattern layer, wherein the first insulating pattern layer comprises a plurality of first insulating portions and a second insulating portion; And Removing a part of the conductive layer to form a plurality of conductors, wherein the plurality of conductors are respectively located between the plurality of first insulating portions and the substrate, and the plurality of conductors are not formed between the second insulating portion and the substrate, wherein the second insulating portion connects two adjacent conductors and connects the first insulating portions on the two adjacent conductors, and the second insulating portion only covers the side surfaces of the ends of the two adjacent conductors, without covering the side surfaces between the two adjacent conductors.

Images