Semiconductor structure and method for forming semiconductor structure

Abstract

A semiconductor structure and a method for forming the semiconductor structure, the structure comprising: a substrate, the substrate comprising a first surface and a second surface opposite to each other, the substrate comprising a second region and a first region; a first isolation layer located on the first surface of the substrate; a first connection layer located in the first region of the substrate, the first connection layer extending from the first surface of the substrate to the second surface, and a portion of the first connection layer located in the first isolation layer; a first insulating layer located between the first connection layer and the substrate; a first opening located in the first region of the substrate, the first opening extending from the second surface of the substrate to the first surface of the substrate, the first opening exposing the bottom surface of the first connection layer facing the second surface of the substrate and a portion of the surface of the first insulating layer; a second insulating layer located on the sidewall surface and the bottom surface of the first opening, the second insulating layer exposing the surface of the first connection layer; a second connection layer located on the second insulating layer and the first connection layer. The performance of the semiconductor structure is improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing, and in particular to a semiconductor structure and a method for forming the semiconductor structure. Background Art

[0002] As semiconductor technology nodes continue to shrink, the size of logic semiconductor standard cells also shrinks. It is necessary to increase the density of logic semiconductor circuits to make the size of standard cells extremely small.

[0003] Currently, miniaturization is used to increase the density of logic semiconductor circuits. However, the density of logic semiconductor circuits increased by miniaturization is limited. Therefore, a method of reducing the height of transistor units is proposed to increase the density of logic semiconductor circuits, that is, reducing the number of standard unit fins and embedding power rails (Buried Power Rail, referred to as BPR). The embedded power rail is usually used in conjunction with the back-side power deliver network (back-side PDN) to increase the voltage drop.

[0004] However, the performance of the existing embedded power lines and backside power transmission networks needs to be improved. Summary of the invention

[0005] The technical problem solved by the present invention is to provide a semiconductor structure and a method for forming the semiconductor structure, so as to improve the performance of the semiconductor structure.

[0006] To solve the above technical problems, the technical solution of the present invention provides a semiconductor structure, including: a substrate, the substrate including a first surface and a second surface relative to each other, the substrate including a first region and a second region; a first isolation layer located on the first surface of the substrate; a first connection layer located in the first region of the substrate, the first connection layer extending from the first surface of the substrate to the second surface, and a portion of the first connection layer is located in the first isolation layer; a first insulating layer located between the first connection layer and the substrate; a first opening located in the first region of the substrate, the first opening extending from the second surface of the substrate to the first surface of the substrate, the first opening exposing the bottom surface of the first connection layer facing the second surface of the substrate and a portion of the surface of the first insulating layer; a second insulating layer located on the side wall surface and the bottom surface of the first opening, the second insulating layer exposing the surface of the first connection layer; a second connection layer located on the second insulating layer and the first connection layer.

[0007] Optionally, the second insulating layer exposes a surface of the first connecting layer facing the second surface of the substrate.

[0008] Optionally, the bottom of the first connection layer facing the second surface of the substrate has a first size, and the bottom of the first opening has a second size, and the second size is greater than the first size.

[0009] Optionally, the second size is 1.2 to 6 times the first size.

[0010] Optionally, the material of the second insulating layer includes an insulating material, and the insulating material includes one or more combinations of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbide nitride and silicon carbon nitride oxynitride.

[0011] Optionally, it also includes: a third insulating layer located on the surface of the second side of the substrate.

[0012] Optionally, the material of the third insulating layer includes an insulating material, and the insulating material includes one or more combinations of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbide nitride and silicon carbon nitride oxynitride.

[0013] Optionally, the first surface of the second region also has: a second isolation layer, an active device located in the second isolation layer, and an interconnection structure located in the first isolation layer and the second isolation layer, wherein the interconnection structure is electrically connected to the first connection layer; the second isolation layer is located on the first isolation layer, and the active device is located on the second region.

[0014] Optionally, the active device includes: a plurality of fin structures, wherein the first isolation layer is located on a portion of the side walls of the fin structure, and a top surface of the first isolation layer is lower than a top surface of the fin structure; a plurality of gate structures, wherein the gate structure is located on the first isolation layer and spans the fin structure; source and drain doped regions, wherein the source and drain doped regions are located in the fin structure on both sides of the gate structure, and the gate structure, the source and drain doped regions and a portion of the fin structure are located in a second isolation layer; and the interconnect structure is electrically connected to the gate structure or the source and drain doped regions.

[0015] Optionally, the gate structure includes a gate dielectric layer and a gate layer located on the gate dielectric layer.

[0016] Optionally, the gate structure further includes a work function structure, and the work function structure is located between the gate dielectric layer and the gate layer.

[0017] Optionally, the material of the first connecting layer includes a metal, and the metal includes a combination of one or more of tungsten, copper, cobalt, titanium nitride, titanium, tantalum, tantalum nitride, ruthenium, ruthenium nitride and aluminum; the material of the second connecting layer includes a metal, and the metal includes a combination of one or more of tungsten, copper, cobalt, titanium nitride, titanium, tantalum, tantalum nitride, ruthenium, ruthenium nitride and aluminum.

[0018] Correspondingly, the technical solution of the present invention also provides a method for forming a semiconductor structure, comprising: providing a substrate, the substrate comprising a first surface and a second surface relative to each other, the substrate comprising a first region and a second region; forming a first isolation layer on the first surface of the substrate; forming a first connection layer and a first insulating layer located between the first connection layer and the substrate in the first region of the substrate, the first connection layer extending from the first surface of the substrate to the second surface of the substrate; forming a first opening in the first region of the substrate, the first opening extending from the second surface of the substrate to the first surface of the substrate, the first opening exposing the bottom surface of the first connection layer facing the second surface of the substrate and a portion of the surface of the first insulating layer; forming a second insulating layer on the side wall surface and the bottom surface of the first opening, the second insulating layer exposing a portion of the surface of the first connection layer; after forming the second insulating layer, forming a second connection layer in the first opening, the second connection layer being electrically connected to the first connection layer.

[0019] Optionally, the second insulating layer exposes a surface of the first connecting layer facing the second surface of the substrate.

[0020] Optionally, the method for forming the second insulating layer includes: forming a second insulating material layer on the side wall surface and the bottom surface of the first opening and the surface of the first insulating layer; forming a sacrificial layer on the second insulating material layer at the bottom of the first opening, the sacrificial layer exposing the second insulating material layer on the surface of the first connecting layer facing the second surface of the substrate; using the sacrificial layer as a mask, removing the second insulating material layer and the first insulating layer on the surface of the first connecting layer facing the second surface of the substrate to form the second insulating layer.

[0021] Optionally, the material of the sacrificial layer includes spin-coated silicon oxide, spin-coated carbon or an anti-reflective organic material.

[0022] Optionally, after forming the second insulating layer, the sacrificial layer is removed.

[0023] Optionally, the method for forming the sacrificial layer includes: forming an initial sacrificial layer on the second insulating material layer in the first opening; etching back the initial sacrificial layer until the second insulating material layer on the surface of the first connecting layer facing the second surface of the substrate is exposed to form the sacrificial layer.

[0024] Optionally, the process of removing the second insulating material layer and the first insulating layer on the surface of the first connecting layer facing the second surface of the substrate includes a dry etching process or a wet etching process.

[0025] Optionally, the process of forming the second insulating material layer includes an atomic layer deposition process or a thermal oxidation process.

[0026] Optionally, the method for forming the first opening includes: forming a mask layer on the second surface of the substrate, the mask layer exposing a portion of the substrate surface; etching the substrate using the mask layer as a mask until a portion of the first insulating layer surface of the side wall of the first connecting layer is exposed to form the first opening.

[0027] Optionally, the bottom of the first connection layer facing the second surface of the substrate has a first size, and the bottom of the first opening has a second size, and the second size is greater than the first size.

[0028] Optionally, the second size is 1.2 to 6 times the first size.

[0029] Optionally, the material of the second insulating layer includes an insulating material, and the insulating material includes one or more combinations of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbide nitride and silicon carbon nitride oxynitride.

[0030] Optionally, before forming the first opening in the first region of the substrate, the method further includes: forming a third insulating layer on the surface of the second surface of the substrate.

[0031] Optionally, the material of the third insulating layer includes an insulating material, and the insulating material includes one or more combinations of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbide nitride and silicon carbon nitride oxynitride.

[0032] Optionally, before forming the first isolation layer on the first surface of the substrate, the method further includes: forming a plurality of fin structures on the first surface of the second region; the first isolation layer is located on a partial sidewall of the fin structure, and a top surface of the first isolation layer is lower than a top surface of the fin structure.

[0033] Optionally, before forming the first opening in the first region of the substrate and after forming the first connection layer in the first region of the substrate, the method further includes: forming a plurality of gate structures, source-drain doped regions and a second isolation layer, the gate structure being located on the first isolation layer and spanning the fin structure, the source-drain doped regions being located in the fin structure on both sides of the gate structure, the second isolation layer being located on the first isolation layer, the gate structure, the source-drain doped regions and part of the fin structure being located in the second isolation layer; and forming an interconnect structure in the second isolation layer and in the first isolation layer, the interconnect structure being electrically connected to the first connection layer, and the interconnect structure being electrically connected to the gate structure or the source-drain doped regions.

[0034] Optionally, the gate structure includes a gate dielectric layer and a gate layer located on the gate dielectric layer.

[0035] Optionally, the gate structure further includes a work function structure, and the work function structure is located between the gate dielectric layer and the gate layer.

[0036] Optionally, the material of the first connecting layer includes a metal, and the metal includes a combination of one or more of tungsten, copper, cobalt, titanium nitride, titanium, tantalum, tantalum nitride, ruthenium, ruthenium nitride and aluminum; the material of the second connecting layer includes a metal, and the metal includes a combination of one or more of tungsten, copper, cobalt, titanium nitride, titanium, tantalum, tantalum nitride, ruthenium, ruthenium nitride and aluminum.

[0037] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:

[0038] The semiconductor structure in the technical solution of the present invention has a first opening in the first region of the substrate, and the first opening exposes part of the side wall surface of the first connection layer, so that the second insulating layer formed on the side wall surface and the bottom surface of the first opening can expose the surface of the first connection layer while covering the bottom of the first opening, thereby ensuring that the second connection layer subsequently formed in the first opening can contact the first connection layer, while ensuring that the second connection layer has good electrical isolation from the substrate, so that the semiconductor structure has good performance.

[0039] The method for forming a semiconductor structure in the technical solution of the present invention forms a first opening in a first region of a substrate, wherein the first opening exposes a portion of the side wall surface of the first connection layer, and then forms a second insulating layer on the side wall surface and the bottom surface of the first opening, so that the second insulating layer can expose the surface of the first connection layer while covering the bottom of the first opening, thereby ensuring that the second connection layer subsequently formed in the first opening can contact the first connection layer while ensuring that the second connection layer has good electrical isolation from the substrate, so that the semiconductor structure has good performance.

[0040] Furthermore, the second dimension of the bottom of the first opening is larger than the first dimension of the bottom of the first connection layer toward the second surface of the substrate, thereby making the process window for forming the first opening larger, which is beneficial to improving the production yield.

[0041] Furthermore, the first opening exposes part of the side wall surface of the first connection layer, so that a sacrificial layer exposing the surface of the first connection layer can be self-alignedly formed at the bottom of the first opening, so that the second insulating material layer on the surface of the first connection layer can be removed, so that the formed second insulating layer can expose the surface of the first connection layer while covering the bottom of the first opening. The second connection layer subsequently formed in the first opening can contact the first connection layer, and the second connection layer has good electrical isolation from the substrate, which can avoid the second connection layer directly contacting the substrate and causing a short circuit, thereby improving the performance of the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] Figures 1 to 3 is a schematic cross-sectional structural diagram of a semiconductor structure forming process in one embodiment;

[0043] Figures 4 to 9 It is a schematic cross-sectional structure diagram of the semiconductor structure forming process in an embodiment of the present invention. DETAILED DESCRIPTION

[0044] As described in the background art, the performance of the existing embedded power lines and backside power transmission networks in combination needs to be improved.

[0045] Figures 1 to 3 It is a schematic cross-sectional structure diagram of a semiconductor structure forming process in one embodiment.

[0046] Please refer to Figure 1 , providing a substrate 100, the substrate 100 comprising a first region and a second region, the substrate 100 comprising a first surface 101 and a second surface 102 opposite to each other, the first surface 101 of the substrate 100 having a plurality of fin structures 103, the first surface 101 of the substrate 100 also having a first isolation layer 110, the first isolation layer 110 being located on a portion of the sidewall surface of the fin structure 103 and the top surface of the first isolation layer 110 being lower than the top surface of the fin structure 103; forming a first connection layer 105 in the first region of the substrate 100, the first connection layer 105 extending from the first surface 101 of the substrate to the second surface 102 The fin structure 103 is extended to have a first insulating layer (not shown) between the first connecting layer 105 and the substrate 100; after the first connecting layer 105 is formed, a gate structure 111 and a second insulating layer 104 are formed on the first insulating layer, the gate structure 111 spans the fin structure 103, and the second insulating layer 104 is located on the sidewall surface and the top surface of the gate structure 111; an opening 106 is formed in the first region of the substrate 100, the opening 106 extends from the second surface 102 of the substrate to the first surface 101, and the bottom of the opening 106 exposes the first insulating layer surface and a portion of the substrate 100 at the bottom of the first connecting layer 105.

[0047] Please refer to Figure 2 An insulating material layer 107 is formed on the inner wall surface of the opening 106 .

[0048] Please refer to Figure 3 , remove the insulating material layer 107 and the first insulating layer on the bottom surface of the first connecting layer 105, and form a second insulating layer 108 on the side wall of the opening 106; after forming the second insulating layer 108, form a second connecting layer 109 in the opening 106, and the second connecting layer 109 is electrically connected to the first connecting layer 105.

[0049] During the formation of the semiconductor structure, in consideration of the photolithography accuracy and to ensure that the second connection layer 109 can contact the first connection layer 105, the bottom size of the opening 106 is slightly larger than the bottom size of the first connection layer 105, so that a portion of the substrate 100 is also exposed at the bottom of the opening 106. The material of the second connection layer 109 is metal, and when forming the second connection layer 109 in the opening 106, it is necessary to first form a second insulating layer 108 on the inner wall of the opening 106 to prevent the second connection layer 109 from directly contacting the substrate 100 and causing a short circuit.

[0050] However, after the insulating material layer 107 is formed, while the insulating material layer 107 on the bottom surface of the first connection layer 105 is removed by an etch-back process, the etch-back process also removes the insulating material layer 107 on the bottom substrate 100 of the opening 106, so that the bottom of a portion of the second connection layer 109 formed in the opening 106 is in contact with the substrate 100 (e.g., Figure 3 As shown in the middle area A), the second connection layer 109 and the substrate 100 are short-circuited, affecting the performance of the semiconductor structure.

[0051] In order to solve the above problems, the technical solution of the present invention provides a semiconductor structure and a method for forming a semiconductor structure, by forming a first opening in a first area of ​​a substrate, wherein the first opening exposes a portion of the side wall surface of the first connecting layer, and then forming a second insulating layer on the side wall surface and the bottom surface of the first opening, so that the second insulating layer can expose the surface of the first connecting layer while covering the bottom of the first opening, thereby ensuring that the second connecting layer subsequently formed in the first opening can contact the first connecting layer, while ensuring that the second connecting layer and the substrate have good electrical isolation, so that the semiconductor structure has good performance.

[0052] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0053] Figures 4 to 9 It is a schematic cross-sectional structure diagram of the semiconductor structure forming process in an embodiment of the present invention.

[0054] Please refer to Figure 4 , providing a substrate 200, wherein the substrate 200 includes a first surface 201 and a second surface 202 opposite to each other, and the substrate 200 includes a second region II and a first region I, wherein the first region I is located between adjacent second regions II.

[0055] The second region II is the region where the active device is located, and the active device includes a fin device, a gate structure spanning the fin structure, and a source-drain doped region located in the fin structure on both sides of the gate structure; the second region II and the first region I have an interconnection structure, and the interconnection structure is electrically connected to the gate structure or the source-drain doped region, and the interconnection structure is electrically connected to a first connection layer formed subsequently; the first region I is the region where the first connection layer and the second connection layer formed subsequently are located.

[0056] In this embodiment, the material of the substrate 200 is silicon.

[0057] In other embodiments, the substrate material includes silicon carbide, silicon germanium, a multinary semiconductor material composed of group III-V elements, silicon on insulator (SOI) or germanium on insulator (GOI). Among them, the multinary semiconductor material composed of group III-V elements includes InP, GaAs, GaP, InAs, InSb, InGaAs or InGaAsP.

[0058] Please continue to refer to Figure 4 , a plurality of fin structures 203 are formed on the first surface 201 of the second region II; a first isolation layer 220 is formed on the first surface 201 of the substrate 200, wherein the first isolation layer 220 is located on a portion of the sidewalls of the fin structure 203, and a top surface of the first isolation layer 220 is lower than a top surface of the fin structure 203.

[0059] In this embodiment, the material of the fin structure 203 is silicon.

[0060] Please refer to Figure 5 , a first connection layer 205 is formed in the first region I of the substrate 200 , the first connection layer 205 extends from the first surface 201 to the second surface 202 of the substrate, and a portion of the first connection layer 205 is located in the first isolation layer 220 .

[0061] The method for forming the first connection layer 205 includes: forming an initial isolation structure (not shown) on the first isolation layer 220, wherein the initial isolation structure covers the top surface and side wall surface of the fin structure 203; forming a patterned layer (not shown) on the initial isolation structure, wherein the patterned layer exposes a portion of the surface of the initial isolation structure on the first region I; using the patterned layer as a mask, etching the initial isolation structure and the first isolation layer 220 until the surface of the first region I is exposed, and forming a second opening (not shown) in the initial isolation structure and the first isolation layer 220; etching the first region I exposed by the second opening, and forming a third opening (not shown) in the first region I; forming a first connection layer 205 in the third opening, and a portion of the first connection layer 205 is also located in the second opening; after forming the first connection layer 205, depositing an isolation material in the second opening.

[0062] The process for forming the initial isolation structure is a deposition process, and the deposition process includes a chemical vapor deposition process or an atomic layer deposition process.

[0063] The material of the first connection layer 205 includes metal, and the metal includes one or more combinations of tungsten, copper, cobalt, titanium nitride, titanium, tantalum, tantalum nitride, ruthenium, ruthenium nitride and aluminum. In this embodiment, the material of the first connection layer 205 includes tungsten.

[0064] In this embodiment, a first insulating layer 223 is provided between the first connection layer 205 and the substrate. The first insulating layer 223 is used to electrically isolate the first connection layer 205 from the substrate 200 .

[0065] The material of the first insulating layer 223 includes an insulating material, and the insulating material includes one or more combinations of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbonitride, and silicon carbonitride oxide.

[0066] Please continue to refer to Figure 5 After forming the first connection layer 205, the initial isolation structure is etched back until the surface of the first isolation layer 220 is exposed; a plurality of gate structures, source-drain doped regions (not shown) and a second isolation layer 204 are formed on the first isolation layer 220, the gate structure is located on the first isolation layer 220 and spans the fin structure 203, the source-drain doped regions are located in the fin structure 203 on both sides of the gate structure, the second isolation layer 204 is located on the first isolation layer 220, and the gate structure, source-drain doped regions and part of the fin structure 203 are located in the second isolation layer 204.

[0067] The gate structure includes a gate dielectric layer 221 and a gate layer 222 located on the gate dielectric layer 221 .

[0068] In this embodiment, the gate structure further includes a work function structure (not shown), and the work function structure is located between the gate dielectric layer 221 and the gate layer 222 .

[0069] In this embodiment, the material of the gate dielectric layer 221 includes a high dielectric constant material, the dielectric constant of the high dielectric constant material is greater than 3.9, and the high dielectric constant material includes aluminum oxide or hafnium oxide; the material of the gate layer 222 includes a metal, and the metal includes tungsten; the material of the work function layer includes an N-type work function material or a P-type work function material, the N-type work function material includes titanium aluminum, and the P-type work function material includes titanium nitride or tantalum nitride.

[0070] In other embodiments, the material of the gate dielectric layer includes silicon oxide or a low-K (K is less than 3.9) material; and the material of the gate layer includes polysilicon.

[0071] The material of the second isolation layer 204 includes a dielectric material, and the dielectric material includes a combination of one or more of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbide nitride, and silicon oxycarbon nitride. In this embodiment, the material of the second isolation layer 204 includes silicon oxide.

[0072] The first isolation layer 220 and the second isolation layer 204 constitute an isolation structure on the first surface 201 of the substrate 200 , and the isolation structure is used to electrically isolate the device structure on the first surface 201 of the substrate 200 .

[0073] Please continue to refer to Figure 5 An interconnect structure 224 is formed in the second isolation layer 204 and the first isolation layer 220 , wherein the interconnect structure 224 is electrically connected to the first connection layer 205 , and the interconnect structure 224 is electrically connected to the gate structure or the source-drain doped region.

[0074] The interconnect structure 224 is made of a metal, and the metal includes one or more of copper, aluminum, tungsten, cobalt, and titanium nitride.

[0075] Please continue to refer to Figure 5 , a third insulating layer 206 is formed on the surface of the second surface 202 of the substrate 200 .

[0076] The third insulating layer 206 is used to protect the surface of the second surface 202 of the substrate 200 to prevent the second surface 202 of the substrate 200 from being damaged when the second connecting layer is subsequently formed, and to prevent short circuit problems when other conductive structures electrically connected to the second connecting layer are subsequently formed on the second surface of the substrate and the conductive structures are in direct contact with the second surface 202 of the substrate 200.

[0077] The material of the third insulating layer 206 includes an insulating material, and the insulating material includes one or more combinations of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbonitride, and silicon carbonitride oxynitride.

[0078] The process of forming the third insulating layer 206 includes an atomic layer deposition process or a chemical vapor deposition process.

[0079] Please refer to Figure 6 After forming the third insulating layer 206, a first opening 207 is formed in the first region I of the substrate 200, and the first opening 207 extends from the second surface 202 of the substrate 200 to the first surface 201 of the substrate 200, and the first opening 207 exposes the bottom surface and part of the side wall surface of the first connecting layer 205 facing the second surface 202 of the substrate.

[0080] In this embodiment, since there is a first insulating layer 223 between the first connection layer 205 and the substrate 200 , the first opening 207 exposes the first insulating layer 223 on the surface of the first connection layer 205 .

[0081] The method for forming the first opening 207 includes: forming a mask layer (not shown) on the second surface 202 of the substrate, the mask layer exposing a portion of the surface of the second surface 202 of the substrate; etching the substrate 200 using the mask layer as a mask until the first insulating layer 223 on the bottom surface and a portion of the side wall surface of the first connecting layer 205 facing the second surface of the substrate is exposed, thereby forming the first opening 207.

[0082] The process of etching the substrate 200 to form the first opening 207 includes a dry etching process or a wet etching process.

[0083] In the present embodiment, the process of etching the substrate 200 to form the first opening 207 includes a dry etching process. The dry etching process can form the first opening 207 with good sidewall morphology and good dimensional accuracy.

[0084] The bottom of the first connection layer 205 facing the second surface 202 of the substrate has a first size, and the bottom of the first opening 207 has a second size.

[0085] In this embodiment, the second size is larger than the first size, so that the process window for forming the first opening 207 is larger, which is beneficial to improving the production yield.

[0086] In this embodiment, the second size is 1.2 to 6 times the first size, thereby ensuring that the first opening 207 can completely expose the bottom surface of the first connection layer 205 toward the second surface 202 of the substrate 200, so that the subsequently formed second connection layer has a larger contact area with the first connection layer 205.

[0087] Next, a second insulating layer 210 is formed on the sidewall surface and the bottom surface of the first opening 207, and the second insulating layer 210 exposes a portion of the surface of the first connecting layer 205. The formation process of the second insulating layer 210 can be found in Figure 7 and Figure 8 .

[0088] In this embodiment, the second insulating layer 210 exposes a surface of the first connecting layer 205 facing the second surface 202 of the substrate.

[0089] Please refer to Figure 7 A second insulating material layer 208 is formed on the sidewall surface and the bottom surface of the first opening 207 and the surface of the first insulating layer 223 .

[0090] The process of forming the second insulating material layer 208 includes an atomic layer deposition process or a thermal oxidation process.

[0091] In this embodiment, the process of forming the second insulating material layer 208 includes an atomic layer deposition process. The atomic layer deposition process can form the second insulating material layer 208 with a dense structure and a relatively thin thickness.

[0092] The material of the second insulating material layer 208 includes insulating material, and the insulating material includes one or more combinations of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbide nitride, and silicon carbide nitride.

[0093] Please continue to refer to Figure 7 A sacrificial layer 209 is formed on the second insulating material layer 208 at the bottom of the first opening 207 , and the sacrificial layer 209 exposes the second insulating material layer 208 on the surface of the first connecting layer 205 facing the second surface 202 of the substrate 200 .

[0094] Since the first opening 207 exposes part of the side wall surface of the first connecting layer 205, a sacrificial layer 209 can be self-alignedly formed on the side wall of the first connecting layer 205 to expose the first connecting layer 205 toward the second surface 202 of the substrate 200, so that the second insulating material layer 208 on the surface of the first connecting layer facing the second surface of the substrate can be removed using the sacrificial layer 209 as a mask. The formed second insulating layer can cover the bottom of the first opening 207 and expose the surface of the first connecting layer 205, thereby ensuring that the second connecting layer subsequently formed in the first opening 207 can contact the first connecting layer 205 while ensuring that the second connecting layer and the substrate 200 have good electrical isolation.

[0095] The method for forming the sacrificial layer 209 includes: forming an initial sacrificial layer (not shown) on the second insulating material layer 208 in the first opening 207; etching back the initial sacrificial layer until the second insulating material layer 208 on the surface of the first connecting layer 205 facing the second surface 202 of the substrate is exposed to form the sacrificial layer 209.

[0096] The material of the sacrificial layer 209 includes spin-on silicon oxide, spin-on carbon or an anti-reflective organic material. In this embodiment, the amorphous material includes spin-on carbon.

[0097] Please refer to Figure 8 Using the sacrificial layer 209 as a mask, the second insulating material layer 208 and the first insulating layer 223 on the surface of the first connecting layer 205 facing the second surface 202 of the substrate are removed to form the second insulating layer 210 .

[0098] The second insulating layer 210 is used to electrically isolate a second connecting layer formed subsequently from the substrate 200 .

[0099] The process of removing the second insulating material layer 208 from the surface of the first connecting layer 205 facing the second surface 202 of the substrate includes a dry etching process or a wet etching process.

[0100] After forming the second insulating layer 210 , the sacrificial layer 209 is removed.

[0101] The process of removing the sacrificial layer 209 includes a dry etching process.

[0102] Please refer to Fig. 9 After forming the second insulating layer 210 , a second connection layer 211 is formed in the first opening 207 , and the second connection layer 211 is electrically connected to the first connection layer 205 .

[0103] The material of the second connection layer 211 includes metal, and the metal includes one or more combinations of tungsten, copper, cobalt, titanium nitride, titanium, tantalum, tantalum nitride, ruthenium, ruthenium nitride and aluminum.

[0104] The method for forming the second connection layer 211 includes: forming a connection material layer (not shown) in the first opening 207 and on the surface of the third insulating layer 206 ; and planarizing the connection material layer until the third insulating layer 206 is exposed to form the second connection layer 211 .

[0105] The process of forming the connection material layer includes a physical vapor deposition process, a chemical vapor deposition process or an electroplating process.

[0106] At this point, the second connection layer 211 is formed. Since the second insulating layer 210 can expose the surface of the first connection layer 205 while covering the bottom of the first opening 207, the second connection layer 211 can contact the first connection layer 205 while ensuring good electrical isolation between the second connection layer 211 and the substrate 200, so that the semiconductor structure has good performance.

[0107] Accordingly, the embodiment of the present invention further provides a semiconductor structure, please continue to refer to Fig. 9 ,include:

[0108] A substrate 200, wherein the substrate 200 comprises a first surface 201 and a second surface 202 opposite to each other, and the substrate 200 comprises a second region II (not labeled) and a first region I (not labeled);

[0109] A first isolation layer 220 located on the first surface 201 of the substrate 200;

[0110] A first connection layer 205 located in the first region I of the substrate 200 , wherein the first connection layer 205 extends from the first surface 201 of the substrate to the second surface 202 , and a portion of the first connection layer 205 is located in the first isolation layer 220 ;

[0111] A first insulating layer 223 located between the first connecting layer 205 and the substrate 200;

[0112] A first opening located in the first region I of the substrate 200, the first opening extending from the second surface 202 of the substrate to the first surface 201 of the substrate, the first opening exposing the bottom surface of the first connection layer 205 facing the second surface of the substrate and a portion of the surface of the first insulating layer 223;

[0113] a second insulating layer 210 located on the sidewall surface and the bottom surface of the first opening, wherein the second insulating layer 210 exposes the surface of the first connecting layer 205;

[0114] The second connection layer 211 is located on the second insulating layer 210 and the first connection layer 205 .

[0115] In this embodiment, the second insulating layer 210 exposes a surface of the first connecting layer 205 facing the second surface 202 of the substrate.

[0116] In this embodiment, the bottom of the first connection layer 205 facing the second surface 202 of the substrate has a first size, and the bottom of the first opening has a second size, and the second size is greater than the first size.

[0117] In this embodiment, the second size is 1.2 to 6 times the first size.

[0118] In this embodiment, the material of the second insulating layer 210 includes an insulating material, and the insulating material includes one or more combinations of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbonitride, and silicon carbonitride oxide.

[0119] In this embodiment, it further includes: a third insulating layer 206 located on the surface of the second surface 202 of the substrate.

[0120] In this embodiment, the material of the third insulating layer 206 includes insulating material, and the insulating material includes one or more combinations of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbide nitride and silicon oxycarbon nitride.

[0121] In this embodiment, the first surface 201 of the substrate 200 also has: a second isolation layer 204, an active device located in the second isolation layer 204, and an interconnection structure 224 located in the first isolation layer 220 and the second isolation layer 204, the second isolation layer 204 is located on the first isolation layer 220, and the active device is located on the second region II.

[0122] In this embodiment, the active device includes: a plurality of fin structures 203, the first isolation layer 220 is located on a portion of the side walls of the fin structure 203, and the top surface of the first isolation layer 220 is lower than the top surface of the fin structure 203; a plurality of gate structures, the gate structure is located on the first isolation layer 220 and spans the fin structure 203; source and drain doping regions (not shown), the source and drain doping regions are located in the fin structure 203 on both sides of the gate structure, and the gate structure, the source and drain doping regions and a portion of the fin structure 203 are located in the second isolation layer 204; the interconnection structure 224 is electrically connected to the first connection layer 205, and the interconnection structure 224 is electrically connected to the gate structure or the source and drain doping regions.

[0123] In this embodiment, the gate structure includes a gate dielectric layer 221 and a gate layer 222 located on the gate dielectric layer 221 .

[0124] In this embodiment, the gate structure further includes a work function structure (not shown), and the work function structure is located between the gate dielectric layer and the gate layer.

[0125] In this embodiment, the material of the first connecting layer 205 includes metal, and the metal includes a combination of one or more of tungsten, copper, cobalt, titanium nitride, titanium, tantalum, tantalum nitride, ruthenium, ruthenium nitride and aluminum; the material of the second connecting layer 211 includes metal, and the metal includes a combination of one or more of tungsten, copper, cobalt, titanium nitride, titanium, tantalum, tantalum nitride, ruthenium, ruthenium nitride and aluminum.

[0126] The semiconductor structure has a first opening in the first region I of the substrate, and the first opening exposes part of the side wall surface of the first connecting layer 205, so that the second insulating layer formed on the side wall surface and the bottom surface of the first opening can expose the surface of the first connecting layer 205 while covering the bottom of the first opening, thereby ensuring that the second connecting layer 211 formed in the first opening can contact the first connecting layer 205, and at the same time, the second connecting layer 211 has good electrical isolation from the substrate 200, so that the semiconductor structure has good performance.

[0127] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A semiconductor structure, characterized in that: include: A substrate, the substrate comprising a first surface and a second surface opposite to each other, the substrate comprising a first region and a second region; a first isolation layer located on the first surface of the substrate; A first connection layer located in the first region of the substrate, the first connection layer extending from the first surface to the second surface of the substrate, and a portion of the first connection layer is located in the first isolation layer; a first insulating layer located between the first connecting layer and the substrate; A first opening located in the first region of the substrate, the first opening extending from the second surface of the substrate to the first surface of the substrate, the first opening exposing a first insulating layer surface of a bottom surface and a portion of a sidewall surface of the first connecting layer facing the second surface of the substrate; a second insulating layer located on the sidewall surface and the bottom surface of the first opening, wherein the second insulating layer exposes the surface of the first connecting layer facing the second surface of the substrate; A second connection layer is located on the second insulating layer and the first connection layer, and the second connection layer is electrically connected to the first connection layer.

2. The semiconductor structure according to claim 1, wherein: The second insulating layer exposes a surface of the first connecting layer facing the second surface of the substrate.

3. The semiconductor structure according to claim 1, wherein: The bottom of the first connection layer facing the second surface of the substrate has a first size, and the bottom of the first opening has a second size, and the second size is greater than the first size.

4. The semiconductor structure according to claim 3, characterized in that The second size is 1.2 to 6 times the first size.

5. The semiconductor structure according to claim 1, wherein: The material of the second insulating layer includes an insulating material, and the insulating material includes one or more combinations of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbonitride, and silicon carbonitride oxide.

6. The semiconductor structure according to claim 1, wherein: Also includes: A third insulating layer is located on the surface of the second side of the substrate.

7. The semiconductor structure according to claim 6, wherein: The material of the third insulating layer includes an insulating material, and the insulating material includes one or more combinations of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbide nitride, and silicon oxycarbide nitride.

8. The semiconductor structure according to claim 1, wherein: The first surface of the substrate also has: a second isolation layer, an active device located in the second isolation layer, and an interconnection structure located in the first isolation layer and the second isolation layer, wherein the interconnection structure is electrically connected to the first connection layer; the second isolation layer is located on the first isolation layer, and the active device is located on the second region.

9. The semiconductor structure according to claim 8, characterized in that The active device includes: a plurality of fin structures, wherein the first isolation layer is located on a portion of the side walls of the fin structure, and a top surface of the first isolation layer is lower than a top surface of the fin structure; a plurality of gate structures, wherein the gate structure is located on the first isolation layer and spans the fin structure; source-drain doped regions, wherein the source-drain doped regions are located in the fin structure on both sides of the gate structure, and the gate structure, the source-drain doped regions and a portion of the fin structure are located in a second isolation layer; and the interconnect structure is electrically connected to the gate structure or the source-drain doped regions.

10. The semiconductor structure according to claim 9, wherein: The gate structure includes a gate dielectric layer and a gate layer located on the gate dielectric layer.

11. The semiconductor structure according to claim 10, wherein: The gate structure further includes a work function structure, and the work function structure is located between the gate dielectric layer and the gate layer.

12. The semiconductor structure according to claim 1, wherein: The material of the first connecting layer includes a metal, and the metal includes a combination of one or more of tungsten, copper, cobalt, titanium nitride, titanium, tantalum, tantalum nitride, ruthenium, ruthenium nitride and aluminum; the material of the second connecting layer includes a metal, and the metal includes a combination of one or more of tungsten, copper, cobalt, titanium nitride, titanium, tantalum, tantalum nitride, ruthenium, ruthenium nitride and aluminum.

13. A method for forming a semiconductor structure, characterized in that: include: Providing a substrate, the substrate comprising a first side and a second side opposite to each other, the substrate comprising a first region and a second region; forming a first isolation layer on the first surface of the substrate; forming a first connection layer and a first insulating layer located between the first connection layer and the substrate in the first region of the substrate, wherein the first connection layer extends from the first surface to the second surface of the substrate, and a portion of the first connection layer is located in the first isolation layer; Forming a first opening in the first region of the substrate, the first opening extending from the second surface of the substrate to the first surface of the substrate, the first opening exposing the first insulating layer surface of the bottom surface and a portion of the sidewall surface of the first connecting layer facing the second surface of the substrate; forming a second insulating layer on the sidewall surface and the bottom surface of the first opening, wherein the second insulating layer exposes the surface of the first connecting layer facing the second surface of the substrate; After forming the second insulating layer, a second connection layer is formed in the first opening, and the second connection layer is electrically connected to the first connection layer.

14. The method for forming a semiconductor structure according to claim 13, wherein: The second insulating layer exposes a surface of the first connecting layer facing the second surface of the substrate.

15. The method for forming a semiconductor structure according to claim 14, wherein: The method for forming the second insulating layer includes: forming a second insulating material layer on the side wall surface and the bottom surface of the first opening and the surface of the first insulating layer; forming a sacrificial layer on the second insulating material layer at the bottom of the first opening, the sacrificial layer exposing the second insulating material layer on the surface of the first connecting layer facing the second surface of the substrate; using the sacrificial layer as a mask, removing the second insulating material layer and the first insulating layer on the surface of the first connecting layer facing the second surface of the substrate to form the second insulating layer.

16. The method for forming a semiconductor structure according to claim 15, wherein: The material of the sacrificial layer includes spin-on silicon oxide, spin-on carbon or anti-reflective organic material.

17. The method for forming a semiconductor structure according to claim 15, wherein: After forming the second insulating layer, the sacrificial layer is removed.

18. The method for forming a semiconductor structure according to claim 15, wherein: The method for forming the sacrificial layer includes: forming an initial sacrificial layer on the second insulating material layer in the first opening; etching back the initial sacrificial layer until the second insulating material layer on the surface of the first connecting layer facing the second surface of the substrate is exposed to form the sacrificial layer.

19. The method for forming a semiconductor structure according to claim 15, wherein: The process of removing the second insulating material layer and the first insulating layer on the surface of the first connecting layer facing the second surface of the substrate includes a dry etching process or a wet etching process.

20. The method for forming a semiconductor structure according to claim 15, wherein: The process of forming the second insulating material layer includes an atomic layer deposition process or a thermal oxidation process.

21. The method for forming a semiconductor structure according to claim 13, wherein: The method for forming the first opening includes: forming a mask layer on the second surface of the substrate, the mask layer exposing a portion of the substrate surface; etching the substrate using the mask layer as a mask until a portion of the first insulating layer surface of the first connecting layer side wall is exposed to form the first opening.

22. The method for forming a semiconductor structure according to claim 13, wherein: The bottom of the first connection layer facing the second surface of the substrate has a first size, and the bottom of the first opening has a second size, and the second size is greater than the first size.

23. The method for forming a semiconductor structure according to claim 22, wherein: The second size is 1.2 to 6 times the first size.

24. The method for forming a semiconductor structure according to claim 13, wherein: The material of the second insulating layer includes an insulating material, and the insulating material includes one or more combinations of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbonitride, and silicon carbonitride oxide.

25. The method for forming a semiconductor structure according to claim 13, wherein: Before forming the first opening in the first region of the substrate, the method further includes: forming a third insulating layer on the surface of the second surface of the substrate.

26. The method for forming a semiconductor structure according to claim 25, wherein: The material of the third insulating layer includes an insulating material, and the insulating material includes one or more combinations of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbide nitride, and silicon oxycarbide nitride.

27. The method for forming a semiconductor structure according to claim 13, wherein: Before forming the first isolation layer on the first surface of the substrate, the method also includes: forming a plurality of fin structures on the first surface of the second region; the first isolation layer is located on a partial sidewall of the fin structure, and a top surface of the first isolation layer is lower than a top surface of the fin structure.

28. The method for forming a semiconductor structure according to claim 27, wherein: Before forming the first opening in the first area of ​​the substrate and after forming the first connection layer in the first area of ​​the substrate, the method further includes: forming a plurality of gate structures, source-drain doped regions and a second isolation layer, wherein the gate structure is located on the first isolation layer and spans the fin structure, the source-drain doped regions are located in the fin structure on both sides of the gate structure, the second isolation layer is located on the first isolation layer, and the gate structure, the source-drain doped regions and part of the fin structure are located in the second isolation layer; and forming an interconnection structure in the second isolation layer and in the first isolation layer, wherein the interconnection structure is electrically connected to the first connection layer, and the interconnection structure is electrically connected to the gate structure or the source-drain doped regions.

29. The method for forming a semiconductor structure according to claim 28, wherein: The gate structure includes a gate dielectric layer and a gate layer located on the gate dielectric layer.

30. The method for forming a semiconductor structure according to claim 29, wherein: The gate structure further includes a work function structure, and the work function structure is located between the gate dielectric layer and the gate layer.

31. The method for forming a semiconductor structure according to claim 13, wherein: The material of the first connecting layer includes a metal, and the metal includes a combination of one or more of tungsten, copper, cobalt, titanium nitride, titanium, tantalum, tantalum nitride, ruthenium, ruthenium nitride and aluminum; the material of the second connecting layer includes a metal, and the metal includes a combination of one or more of tungsten, copper, cobalt, titanium nitride, titanium, tantalum, tantalum nitride, ruthenium, ruthenium nitride and aluminum.

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