Semiconductor device with wafer-to-wafer bonding structure and method of manufacturing the same

Abstract

The present disclosure provides a semiconductor device having a wafer-to-wafer bonding structure and a method of manufacturing the same. A semiconductor device includes a lower wafer including a first substrate, a first dielectric layer defined on the first substrate, and a first wiring line defined in the first dielectric layer; an upper wafer including a second substrate, an isolation layer defined in an upper surface of the second substrate, a second dielectric layer bonded to an upper surface of the first dielectric layer, a third dielectric layer defined on the upper surface of the second substrate, and a second wiring line defined on the third dielectric layer, wherein the second dielectric layer covers a lower surface of the second substrate and includes at least a portion defined in the lower surface of the second substrate below and in contact with the isolation layer; and a via through the third dielectric layer, the isolation layer, the second dielectric layer below the isolation layer, and the first dielectric layer below the second wiring line and coupling the second wiring line and the first wiring line.

Description

Technical Field

[0001] Various implementations generally relate to semiconductor technology, and more specifically, to a semiconductor device having a wafer-to-wafer bonding structure and a method of manufacturing the same. Background Technology

[0002] Recently, as a measure to achieve high integration and high capacity in semiconductor devices, a structure has been proposed in which the components included in the semiconductor device are not fabricated on a single wafer, but on at least two wafers, and then the wafers are joined together to connect the components. Summary of the Invention

[0003] Various implementations involve measures that can improve the efficiency of semiconductor device manufacturing processes and help reduce failures that may occur during the manufacturing process.

[0004] In one embodiment, a semiconductor device having a wafer-to-wafer bonding structure includes: a lower wafer including a first substrate, a first dielectric layer defined on the first substrate, and a first wiring line defined in the first dielectric layer; an upper wafer including a second substrate, an isolation layer defined in an upper surface of the second substrate, a second dielectric layer bonded to the upper surface of the first dielectric layer, a third dielectric layer defined on the upper surface of the second substrate, and a second wiring line defined in the third dielectric layer, wherein the second dielectric layer covers a lower surface of the second substrate and includes at least a portion defined in the lower surface of the second substrate located below and in contact with the isolation layer; and a via passing below the second wiring line through the third dielectric layer, the isolation layer, the second dielectric layer below the isolation layer, and the first dielectric layer, and connecting the second wiring line and the first wiring line.

[0005] In one embodiment, a semiconductor device having a wafer-to-wafer bonding structure includes: a lower wafer including a first substrate, a first dielectric layer defined on the first substrate, and a first wiring defined in the first dielectric layer; an upper wafer including a second substrate, an isolation layer defined in an upper surface of the second substrate, a via extending from a lower surface of the second substrate to an upper surface to expose a lower surface of the isolation layer, a second dielectric layer filling the via and covering the lower surface of the second substrate and bonded to the upper surface of the first dielectric layer, a third dielectric layer defined on the upper surface of the second substrate, and a second wiring defined in the third dielectric layer; and a via passing below the second wiring through the third dielectric layer, the isolation layer, the second dielectric layer below the isolation layer, and the first dielectric layer, and connecting the second wiring and the first wiring.

[0006] In one embodiment, a method of manufacturing a semiconductor device having a wafer-to-wafer bonding structure may include the following steps: forming an isolation layer in a front surface of an upper wafer substrate; forming a via that exposes one of the isolation layers by passing through a rear surface of the upper wafer substrate away from the front surface; forming a first dielectric layer that fills the via and covers the rear surface; defining a lower wafer including a lower wafer substrate, a second dielectric layer defined on the lower wafer substrate, and a first wiring disposed in the second dielectric layer; bonding a top surface of the second dielectric layer and a bottom surface of the first dielectric layer of the lower wafer; forming a third dielectric layer on the front surface of the upper wafer substrate; forming a via that passes through the third dielectric layer, the isolation layer, the first dielectric layer below the isolation layer, and the second dielectric layer, and is connected to the first wiring; and forming a second wiring on the third dielectric layer connected to the via. Attached Figure Description

[0007] Figure 1 This is a cross-sectional view showing a semiconductor device according to an embodiment of the present disclosure.

[0008] Figures 2A to 2F This is a cross-sectional view of a semiconductor device according to an embodiment of the present disclosure, explained with the aid of the process sequence.

[0009] Figure 3 This is a cross-sectional view showing the via structure of a semiconductor device according to an embodiment of the present disclosure.

[0010] Figures 4 to 6 This is a cross-sectional view showing a through-hole structure of a semiconductor device according to an embodiment of the present disclosure.

[0011] Figure 7 This is a top view illustrating an example of a semiconductor device according to an embodiment of the present disclosure.

[0012] Figure 8 It is shown Figure 7 A cross-sectional view of the substrate.

[0013] Figure 9 This is a top view showing a representation of a semiconductor device according to an embodiment of the present disclosure.

[0014] Figure 10 It is shown Figure 9 A cross-sectional view of the substrate.

[0015] Figure 11 This is a cross-sectional view showing a semiconductor device according to an embodiment of the present disclosure. Detailed Implementation

[0016] The advantages and features of this disclosure, and methods of implementing them, will become apparent from the following description of exemplary embodiments thereof with reference to the accompanying drawings. However, this disclosure is not limited to the exemplary embodiments disclosed herein, but can be implemented in various different ways. The exemplary embodiments of this disclosure convey the scope of this disclosure to those skilled in the art.

[0017] Because the numerical values, dimensions, ratios, angles, and number of elements given in the accompanying drawings to describe embodiments of this disclosure are merely illustrative, this disclosure is not limited to what is shown. Throughout the specification, the same reference numerals denote the same parts. In describing this disclosure, detailed descriptions of related technologies will be omitted where it is determined that such detailed descriptions may obscure the essential points of this disclosure. It should be understood that the terms “comprising,” “having,” and “including,” as used in the specification and claims, should not be construed as limited to the means listed thereafter, unless otherwise specifically stated. Where an indefinite or definite article (e.g., “a,” “an,” or “the”) is used when referring to a singular noun, the article may include a plurality of that noun, unless otherwise specifically stated.

[0018] When interpreting elements in embodiments of this disclosure, they should be interpreted as including tolerances, even if not explicitly described.

[0019] Furthermore, in describing the components of this disclosure, terms such as first, second, A, B, (a), and (b) may be used. These terms are used only to distinguish one component from another and do not limit the substance, order, sequence, or quantity of the components. Moreover, the components in embodiments of this disclosure are not limited to these terms. These terms are used only to distinguish one component from another. Therefore, as used herein, within the technical spirit of this disclosure, a first component may be a second component.

[0020] When a component is described as "connected," "linked," or "attached" to another component, this can mean that the component can be "connected," "linked," or "attached" not only directly, but also indirectly via a third component. When describing positional relationships, such as "component A on component B," "component A above component B," "component A below component B," and "component A next to component B," one or more other components may be positioned between component A and component B, unless the terms "directly" or "exactly" are explicitly used.

[0021] Features of the various exemplary embodiments of this disclosure may be partially or completely coupled, combined, or separated. Various technical interactions and operations are possible. The various exemplary embodiments may be implemented individually or in combination.

[0022] In the following, various examples of embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0023] Figure 1 This is a cross-sectional view showing a semiconductor device according to an embodiment of the present disclosure.

[0024] Reference Figure 1 The semiconductor device according to embodiments of the present disclosure may include a lower wafer W1, an upper wafer W2 bonded to the lower wafer W1, and a through via VIA passing through the bonding surface between the upper wafer W2 and the lower wafer W1 and connecting the wiring line M2c of the upper wafer W2 and the wiring line M1 of the lower wafer W1.

[0025] The lower chip W1 may include a first substrate 10, a memory cell array MCA, a first dielectric layer ILD1, and wiring lines M1.

[0026] The first substrate 10 may be a single-crystal semiconductor layer. For example, the first substrate 10 may be a bulk silicon substrate, a germanium substrate, a silicon-germanium substrate, or an epitaxial thin film formed by selective epitaxial growth.

[0027] Although not shown, the memory cell array (MCA) may include multiple memory cells. Memory cells can be accessed via word lines and bit lines. Although this embodiment shows the lower chip W1 as a cell chip including the memory cell array (MCA), it should be noted that the spirit of this disclosure is not limited thereto.

[0028] A first dielectric layer ILD1 may be defined on the first substrate 10 to cover the memory cell array MCA. The first dielectric layer ILD1 may include an oxide, such as silicon oxide (SiO2). In one embodiment, the first dielectric layer ILD1 may have a multilayer structure.

[0029] Wiring line M1 can be defined in the first dielectric layer ILD1. Although not shown, wiring line M1 can be connected to the memory cell array MCA.

[0030] The upper wafer W2 may include a second substrate 20, isolation layers ISO1 and ISO2, and a second dielectric layer ILD2. The upper wafer W2 may also include circuit elements CKT, wiring lines M2a to M2c, a third dielectric layer ILD3, and a fourth dielectric layer ILD4.

[0031] The second substrate 20 may be formed of the same material as the first substrate 10. However, the spirit of this disclosure is not limited to embodiments in which the second substrate 20 and the first substrate 10 are formed of the same material. The second substrate 20 may have a front surface 20a and a rear surface 20b opposite to the front surface 20a.

[0032] The semiconductor device may include a first region I and a second region II. The first region I may correspond to a circuit region in which a circuit element CKT is disposed, and the second region II may correspond to a via region in which a via VIA is disposed.

[0033] Isolation layers ISO1 and ISO2 may be formed in the front surface 20a of the second substrate 20. Isolation layers ISO1 and ISO2 may comprise oxides. For example, isolation layers ISO1 and ISO2 may comprise oxides with excellent gap-filling properties, such as flowable oxide (FOX), spin-on-glass (SOG), and high-density plasma (HDP). In some embodiments, isolation layers ISO1 and ISO2 may each have a structure in which nitrides and oxides are stacked.

[0034] The isolation layers ISO1 and ISO2 may include a first isolation layer ISO1 formed in a first region I of the second substrate 20 and a second isolation layer ISO2 formed in a second region II of the second substrate 20.

[0035] To ensure stable operation of the circuit element CKT and pattern uniformity at the boundary between the first region I and the second region II, a dummy isolation layer ISO_DUMMY can be formed at the edge of the second region II adjacent to the first region I. The dummy isolation layer ISO_DUMMY can be formed together with the first isolation layer ISO1 and the second isolation layer ISO2 when the first isolation layer ISO1 and the second isolation layer ISO2 are formed.

[0036] The second substrate 20 can be divided into a field region in which a first isolation layer ISO1, a second isolation layer ISO2, and a dummy isolation layer ISO_DUMMY are formed, and an active region outside the field region. In the second region II, a via TH passing through the second substrate 20 can be formed below the second isolation layer ISO2. The via TH can connect the rear surface 20b of the second substrate 20 and the second isolation layer ISO2.

[0037] The second dielectric layer ILD2 can fill the via TH and cover the rear surface 20b of the second substrate 20. The second dielectric layer ILD2 may include silicon oxide (SiO2). The second dielectric layer ILD2 can contact the second substrate 20 on the inner sidewall defined by the via TH. Due to this fact, compared to a device without via TH, the contact area between the second substrate 20 and the second dielectric layer ILD2 can be increased, thereby increasing the connection force between the second substrate 20 and the second dielectric layer ILD2. The bottom surface of the second dielectric layer ILD2 can be bonded to the top surface of the first dielectric layer ILD1 of the lower wafer W1.

[0038] The circuit element CKT can be formed in the first region I of the front surface 20a of the second substrate 20. For example, the circuit element CKT can constitute logic circuitry for controlling the memory cell array MCA defined in the lower wafer W1.

[0039] Figure 1 An example of a transistor as a circuit element CKT is shown. The transistor may include a gate dielectric layer Gox disposed on the front surface 20a of a second substrate 20, a gate electrode GE disposed on the gate dielectric layer Gox, and junctions Jn1 and Jn2 defined in the active regions on both sides of the gate electrode GE of the second substrate 20. Junctions Jn1 and Jn2 are regions formed by implanting n-type or p-type impurities into the active regions of the second substrate 20. One of junctions Jn1 and Jn2 may serve as the source region of the transistor, and the other of junctions Jn1 and Jn2 may serve as the drain region of the transistor. The transistor is for illustrative purposes, and in some embodiments, the circuit element CKT may include, for example, a diode, a capacitor, or an inductor.

[0040] A third dielectric layer ILD3 may be defined on the front surface 20a of the second substrate 20 to cover the circuit element CKT. The third dielectric layer ILD3 may include oxides, such as borophosphosilicate glass (BPSG), undoped silicate glass (USG), and spin-coated glass (SOG). In one embodiment, the third dielectric layer ILD3 may have a multilayer structure. Wiring lines M2c may be disposed on the third dielectric layer ILD3 and may be connected to the circuit element CKT via wiring lines M2a and M2b defined in the third dielectric layer ILD3 and contacts CNT1 to CNT3. A fourth dielectric layer ILD4 may be defined on the third dielectric layer ILD3 to cover the wiring lines M2c.

[0041] The via VIA can be connected to the wiring line M1 by passing through the third dielectric layer ILD3, the second isolation layer ISO2, the second dielectric layer ILD2, and the first dielectric layer ILD1 beneath the wiring line M2c, and can electrically connect the wiring line M2c and the wiring line M1. Although this embodiment shows one via VIA disposed in a via TH, the present disclosure is not limited thereto. The number of via VIAs disposed in a via TH can be two or more.

[0042] Unlike this embodiment, a method can be used in which pads are formed on the top surface of the first dielectric layer of the lower wafer and on the bottom surface of the second dielectric layer of the upper wafer, and the lower and upper wafers are electrically connected by bonding of the pads. Ideally, the bottom surface of the second dielectric layer of the upper wafer and the top surface of the first dielectric layer of the lower wafer should be flat, but in reality they may not be flat. If the surfaces are not flat, nanogap may be generated at the bonding surface between the upper and lower wafers, and due to the presence of nanogap, a failure may occur in which the pads of the upper wafer and the pads of the lower wafer are not connected to each other.

[0043] According to this embodiment, the wiring lines M2c of the upper wafer W2 and M1 of the lower wafer W1 are electrically connected via vias VIA passing through the bonding surface between the upper wafer W2 and the lower wafer W1. Therefore, even if there is a nanometer gap at the bonding surface between the upper wafer W2 and the lower wafer W1, the failure of the wiring lines M2c of the upper wafer W2 and M1 of the lower wafer W1 not being connected to each other can be prevented.

[0044] Figures 2A to 2F This is a cross-sectional view of a semiconductor device according to an embodiment of the present disclosure, explained with the aid of the process sequence.

[0045] Reference Figure 2A A first isolation layer ISO1 can be formed in the first region I of the second substrate 20, and a second isolation layer ISO2 can be formed in the second region II of the second substrate 20.

[0046] The first isolation layer ISO1 and the second isolation layer ISO2 can be formed using a shallow trench isolation (STI) process. Specifically, after a pad oxide layer and a pad nitride layer are sequentially formed on the front surface 20a of the second substrate 20, the pad nitride layer and the pad oxide layer can be patterned, thereby exposing the portion of the second substrate 20 corresponding to the field region. After etching the exposed portion of the second substrate 20 to form a trench, the trench can be filled with a dielectric material, thereby forming the first isolation layer ISO1 and the second isolation layer ISO2. The dielectric material may include flowable oxide (FOX), spin-on glass (SOG), or high-density plasma (HDP), etc.

[0047] During the process of forming the first isolation layer ISO1 and the second isolation layer ISO2, a dummy isolation layer ISO_DUMMY may be formed at the edge of the second region II adjacent to the first region I.

[0048] Reference Figure 2B In the second region II, a via TH exposing the second isolation layer ISO2 can be formed through the rear surface 20b of the second substrate 20, which is opposite to the front surface 20a, of the second substrate 20. The depth of the via TH can be smaller than the thickness of the second isolation layer ISO2 than the thickness of the second substrate 20. Therefore, compared to forming a via through the entire thickness of the second substrate 20, the etching thickness here is smaller, and the etching process can be relatively reduced.

[0049] Reference Figure 2C A second dielectric layer ILD2 can be formed to fill the via TH and cover the rear surface 20b of the second substrate 20. The second dielectric layer ILD2 may include silicon oxide. Subsequently, the bottom surface of the second dielectric layer ILD2 can be planarized using a chemical mechanical polishing (CMP) process. The second dielectric layer ILD2 can contact the second substrate 20 on the inner sidewall defined by the via TH. This fact increases the contact area between the second substrate 20 and the second dielectric layer ILD2, thereby increasing the bonding force between the second substrate 20 and the second dielectric layer ILD2.

[0050] Reference Figure 2DThe lower wafer W1 can be bonded to the bottom surface of the second dielectric layer ILD2. The lower wafer W1 may include a first substrate 10, a memory cell array MCA defined on the first substrate 10, a first dielectric layer ILD1 defined on the first substrate 10 and covering the memory cell array MCA, and wiring lines M1 defined in the first dielectric layer ILD1. The top surface of the first dielectric layer ILD1 can constitute a surface on which the lower wafer W1 is bonded to the second dielectric layer ILD2. The top surface of the first dielectric layer ILD1 may have a structure planarized by a CMP process. The first dielectric layer ILD1 may be formed of silicon oxide.

[0051] When silicon oxide is planarized using a CMP process, the planarized surface can exhibit hydrophobicity. The top surface of the first dielectric layer ILD1 and the bottom surface of the second dielectric layer ILD2, planarized using the CMP process, can also possess hydrophobic properties. By performing plasma treatment or wet pretreatment on these surfaces, they can be transformed into hydrophilic surfaces, resulting in the adhesion of OH groups to the silicon surface. After the top surface of the first dielectric layer ILD1 and the bottom surface of the second dielectric layer ILD2 are bonded at room temperature by van der Waals forces between the OH groups, heat treatment removes only water molecules, allowing very strong covalent bonds to form between silicon and oxygen atoms. Therefore, the top surface of the first dielectric layer ILD1 and the bottom surface of the second dielectric layer ILD2 can be substantially and firmly bonded together.

[0052] Reference Figure 2E A circuit element CKT can be formed in the front surface 20a of the second substrate 20, and a third dielectric layer ILD3 covering the circuit element CKT can be formed on the front surface 20a of the second substrate 20. The third dielectric layer ILD3 can have a multilayer structure, and wiring lines M2a and M2b, as well as contacts CNT1 to CNT3 connecting the circuit element CKT and the wiring lines M2a and M2b, can be formed in the third dielectric layer ILD3.

[0053] Subsequently, in the second region II, a hole H can be formed through the third dielectric layer ILD3, the second isolation layer ISO2, the second dielectric layer ILD2 and the first dielectric layer ILD1 to expose the wiring line M1 in the first dielectric layer ILD1.

[0054] Reference Figure 2F Conductive material can be filled into hole H to form a via VIA that connects to wiring line M1. Wiring line M2c can be formed on the third dielectric layer ILD3 and connected to contact CNT3 and via VIA. A fourth dielectric layer ILD4 covering wiring line M2c can be formed on the third dielectric layer ILD3.

[0055] The CMP process can be used during the fabrication of at least one of the following: circuit element CKT, wiring lines M2a, M2b and M2c, contacts CNT1 to CNT3, and third dielectric layer ILD3 and fourth dielectric layer ILD4, formed after the lower wafer W1 and the upper wafer W2 are bonded together. During the CMP process, the semiconductor device rotates by contacting a polishing pad, thus subjecting the semiconductor device to shearing stress in the horizontal direction.

[0056] If the bonding force between the second substrate of the upper wafer and the second dielectric layer defined on the rear surface of the second substrate is insufficient, deformation may occur at the interface between the second substrate and the second dielectric layer during the CMP process, and therefore, a failure of misalignment between the lower wafer bonded to the second dielectric layer and the upper wafer may occur.

[0057] According to this embodiment, since the second dielectric layer ILD2 contacts the second substrate 20 along the inner sidewall of the second substrate 20 pre-defined by the via TH, the contact area between the second substrate 20 and the second dielectric layer ILD2 can be increased. As a result, the bonding force between the second substrate 20 and the second dielectric layer ILD2 increases, thereby reducing or preventing deformation at the interface between the second substrate 20 and the second dielectric layer ILD2. Therefore, it can help suppress the occurrence of misalignment faults between the lower wafer W1 and the upper wafer W2 bonded to the second dielectric layer ILD2.

[0058] Figure 3 This is a cross-sectional view showing the via structure of a semiconductor device according to an embodiment of the present disclosure.

[0059] Reference Figure 3 The via VIA may include a first via VIA1 and a second via VIA2. The first via VIA1 may pass through the second isolation layer ISO2, the second dielectric layer ILD2, and the first dielectric layer ILD1, and may be connected to the wiring line M1. The second via VIA2 may pass through the third dielectric layer ILD3 below the wiring line M2c, and may be connected to the first via VIA1.

[0060] The first via VIA1 can be formed by filling the via with a conductive material. The via can also be formed by etching the second isolation layer ISO2, the second dielectric layer ILD2 below the second isolation layer ISO2, and the first dielectric layer ILD1 after the lower wafer W1 and the upper wafer W2 are bonded to expose the wiring line M1.

[0061] The second via VIA2 can be formed by filling the via with a conductive material. The via can also be formed by etching the third dielectric layer ILD3 after its formation.

[0062] According to this embodiment, since the depth of the hole formed by a single etching process can be reduced, it can help reduce or prevent not-open defects of the hole.

[0063] Figures 4 to 6 This is a cross-sectional view showing a through-hole structure of a semiconductor device according to an embodiment of the present disclosure.

[0064] Reference Figure 4 The well region WELL can be defined by doping impurity ions into the second substrate 20. The junction Jn2 of the circuit element CKT can be formed in the well region WELL of the second substrate 20.

[0065] The widths of the first isolation layer ISO1 and the second isolation layer ISO2 can decrease or taper from the front surface 20a to the rear surface 20b of the second substrate 20. The depth of each of the first isolation layer ISO1 and the second isolation layer ISO2 can be shallower than the depth of the well region WELL. Similar to the first isolation layer ISO1 and the second isolation layer ISO2, the dummy isolation layer ISO_DUMMY can also have a width that decreases in the direction from the front surface 20a to the rear surface 20b of the second substrate 20.

[0066] The via TH can have vertical sidewalls. The width A1 of the via TH can be less than the width A2 of the bottom end of the second isolation layer ISO2. Due to the difference between A1 and A2, the inner sidewall of the second substrate 20 defined by the second isolation layer ISO2 and the via TH can have a stepped shape.

[0067] Reference Figure 5 In another embodiment, a via TH can be formed by etching the second substrate 20, exposing the second isolation layer ISO2 from the rear surface 20b of the second substrate 20. Due to the etch loading during the etching process, the width of the via TH can decrease in the direction from the rear surface 20b to the front surface 20a of the second substrate 20. In other words, as the distance from the front surface 20a of the second substrate 20 increases, the width of the second isolation layer ISO2 can gradually become thinner, while the width of the via TH can increase.

[0068] The width A1' of the top end of the via TH that meets the second isolation layer ISO2 can be smaller than the width A2' of the bottom end of the second isolation layer ISO2. Due to the difference between A1' and A2', the inner sidewall of the second substrate 20 defined by the second isolation layer ISO2 and the via TH can have a stepped shape.

[0069] Reference Figure 6 In another embodiment, the width of the second isolation layer ISO2 may decrease as it moves away from the front surface 20a of the second substrate 20. The via TH can be formed by etching trenches for forming the second isolation layer ISO2 and then etching the second substrate 20 below the trenches. Due to the etching load during the etching process, the width of the via TH may decrease as it approaches the rear surface 20b of the second substrate 20.

[0070] After the sacrificial layer (not shown) is filled in the via TH, a second isolation layer ISO2 can be formed in the trench. The sacrificial layer can then be removed, and a second dielectric layer ILD2 can be formed to fill the via TH exposed due to the removal of the sacrificial layer and to cover the rear surface 20b of the second substrate 20.

[0071] The width A1” of the top end of the via TH that meets the second isolation layer ISO2 can be smaller than the width A2” of the bottom end of the second isolation layer ISO2. Due to the difference between A1” and A2”, the inner sidewall of the second substrate 20 defined by the second isolation layer ISO2 and the via TH can have a stepped shape.

[0072] Figure 7 This is a top view showing a representation of a semiconductor device according to an embodiment of the present disclosure, and Figure 8 It is shown Figure 7 A cross-sectional view of the substrate.

[0073] Reference Figure 7 Multiple second isolation layers ISO2 can be defined in the second substrate 20. A dummy isolation layer ISO_DUMMY can be set in a shape surrounding each second isolation layer ISO2.

[0074] Reference Figure 7 and Figure 8 Multiple vias TH can be formed below the second isolation layer ISO2, each connected to the second isolation layer ISO2. Each via TH can be connected to the corresponding second isolation layer ISO2 by passing through the second substrate 20. Each via TH can be formed with a diameter sufficiently larger than the diameter of each via VIA so that multiple via VIAs can be disposed therein.

[0075] Figure 9 This is a top view showing a representation of a semiconductor device according to an embodiment of the present disclosure, and Figure 10 It is shown Figure 9 A cross-sectional view of the substrate.

[0076] Reference Figure 9A second isolation layer ISO2 can be defined in the second substrate 20, which is connected to multiple vias TH. A dummy isolation layer ISO_DUMMY can be defined around the second isolation layer ISO2. For example, in Figure 9 In this context, the virtual isolation layer ISO_DUMMY extends along the long side of the second isolation layer ISO2.

[0077] Reference Figure 9 and Figure 10 Multiple vias TH can be formed below the second isolation layer ISO2. The multiple vias TH can pass through the second substrate 20 and can be connected together to the second isolation layer ISO2.

[0078] Figure 11 This is a cross-sectional view showing a semiconductor device according to an embodiment of the present disclosure.

[0079] Reference Figure 11 The lower chip W1 may include a first substrate 10 and a memory cell array MCA defined on the first substrate 10.

[0080] The memory cell array (MCA) may include a plurality of electrode layers 32 and a plurality of interlayer dielectric layers 34 alternately stacked on the first substrate 10, and a plurality of vertical channels CH passing through the plurality of electrode layers 32 and the plurality of interlayer dielectric layers 34.

[0081] Electrode layer 32 may include a conductive material. For example, electrode layer 32 may include at least one selected from doped semiconductors (e.g., doped silicon), metals (e.g., tungsten, copper, or aluminum), conductive metal nitrides (e.g., titanium nitride or tantalum nitride), and transition metals (e.g., titanium or tantalum). In electrode layers 32, at least one electrode layer 32 starting from the lowest electrode layer 32 may form a source select line. In electrode layers 32, at least one electrode layer 32 starting from the highest electrode layer 32 may form a drain select line. Electrode layers 32 between the source select line and the drain select line may form word lines. Interlayer dielectric layer 34 may include silicon oxide.

[0082] Although not shown, a plurality of first slits may be defined to divide the alternately stacked electrode layers 32 and interlayer dielectric layers 34 into memory block cells. Second slits may be defined between adjacent first slits, dividing at least one of the drain select line and source select line into cells (e.g., sub-block cells) each smaller than the memory block. Therefore, word lines can be divided into memory block cells, and at least one of the drain select line and source select line can be divided into sub-block cells.

[0083] The electrode layers 32 can extend at different lengths to form steps, such as stepped steps. Therefore, the lower electrode layer 32 extends longer than the upper electrode layer 32, and each electrode layer 32 can define a pad area exposed in the upward direction.

[0084] Although not shown, each vertical channel (CH) may include a channel layer and a gate dielectric layer. The channel layer may include polysilicon or monocrystalline silicon, and may include p-type impurities, such as boron (B), in some regions therein. The gate dielectric layer may have a shape surrounding the outer wall of the channel layer. The gate dielectric layer may include a tunnel dielectric layer, a charge storage layer, and a barrier layer sequentially stacked from the outer wall of the channel layer. In some embodiments, the gate dielectric layer may have an oxide-nitride-oxide (ONO) stack structure, wherein oxide layers, nitride layers, and oxide layers are sequentially stacked.

[0085] Source select transistors can be configured in a region or portion of the source select line surrounding the vertical channel CH. Memory cells can be configured in a region or portion of the word line surrounding the vertical channel CH. Drain select transistors can be configured in a region or portion of the drain select line surrounding the vertical channel CH. Drain select transistors, multiple memory cells, and source select transistors arranged along a vertical channel CH can form a cell string.

[0086] Multiple bit lines BL can be disposed above multiple alternating electrode layers 32, multiple interlayer dielectric layers 34, and multiple vertical channels CH. The bit lines BL can be connected to the vertical channels CH through bit line contacts BLC1 and BLC2.

[0087] A first dielectric layer ILD1 can be defined on the first substrate 10 to cover a plurality of alternately stacked electrode layers 32 and a plurality of interlayer dielectric layers 34, a vertical channel CH and a bit line BL. The top surface of the first dielectric layer ILD1 can form a surface on which the lower wafer W1 is bonded to the upper wafer W2.

[0088] Wiring line M1 can be defined in the first dielectric layer ILD1. Wiring line M1 can be connected to the memory cell array MCA via contacts 40a to 40c. Figure 11 Wiring line M1 connected to electrode layer 32 of memory cell array MCA is shown. Although only one wiring line M1 connected to one electrode layer 32 of memory cell array MCA is shown for simplicity, it should be understood that multiple wiring lines connected to electrode layer 32 can be defined in the first dielectric layer ILD1.

[0089] The upper wafer W2 may include a second substrate 20 and circuit elements CKT defined within the second substrate 20. The circuit elements CKT may control the memory cell array MCA. For example, the circuit elements CKT may include a row decoder. As another example, the circuit elements CKT may include page buffer circuitry and peripheral circuitry.

[0090] Although not shown, the row decoder can select any memory block from the memory blocks included in the memory cell array (MCA) in response to a row address provided from the external circuitry. The row decoder can transmit an operating voltage provided from the external circuitry to the word line connected to the memory block selected from the memory blocks included in the MCA.

[0091] Page buffer circuitry may include multiple page buffers, each connected to a bit line BL. The page buffer can receive page buffer control signals from external circuitry, and can send and receive data signals to and from external circuitry. The page buffer can control the bit line BL in response to the page buffer control signals. For example, the page buffer can detect data stored in a memory cell of the memory cell array (MCA) by sensing a signal on the bit line BL in response to the page buffer control signals, and can send a data signal to the external circuitry based on the detected data. The page buffer can apply a signal to the bit line BL based on the data signal received from the external circuitry in response to the page buffer control signals, and accordingly, can write data to a memory cell of the MCA. The page buffer can write data to or read data from a memory cell connected to an active word line.

[0092] Peripheral circuitry can receive command signals, address signals, and control signals from devices outside the semiconductor device (e.g., a memory controller), and can send data to and receive data from these devices. Based on the command, address, and control signals, peripheral circuitry can output signals for writing data to or reading data from the memory cell array (MCA), such as row address and page buffer control signals. Peripheral circuitry can generate various voltages required by the semiconductor device, including operating voltages.

[0093] A third dielectric layer ILD3 can be defined on the front surface 20a of the second substrate 20 to cover the circuit element CKT. Wiring lines M2c can be formed on the third dielectric layer ILD3, and the circuit element CKT can be connected by the wiring lines M2a and M2b defined in the third dielectric layer ILD3 and the contacts CNT1 to CNT3.

[0094] Wiring lines M2a to M2c of the upper wafer W2 can be formed after the lower wafer W1 and the upper wafer W2 are bonded together. Wiring lines M2a to M2c can be formed from a conductive material with low resistivity but likely to cause process failure at the highest temperature (hereinafter referred to as the "process critical temperature") during the process of forming the lower wafer W1. For example, wiring lines M2a to M2c can be formed from copper or aluminum.

[0095] Because the upper wafer W2 and the lower wafer W1 are formed separately, materials with low melting points and low resistivity can be used as conductive materials for forming wiring lines M2a to M2c. Since wiring lines M2a to M2c are formed of materials with low resistivity, the load on wiring lines M2a to M2c can be reduced, thereby improving signal transmission speed.

[0096] Below wiring line M2c, via VIA can be connected to wiring line M1 by passing through the third dielectric layer ILD3, the second isolation layer ISO2, the second dielectric layer ILD2 below the second isolation layer ISO2, and the first dielectric layer ILD1. Via VIA can electrically connect wiring line M2c and wiring line M1. Although this embodiment shows via VIA electrically connected to the line decoder and electrode layer 32, this disclosure is not limited thereto. For example, via can electrically connect page buffer circuitry and bit line BL.

[0097] According to embodiments of this disclosure, since the via TH formed in the substrate of the upper wafer to provide space for providing vias for electrically connecting the upper and lower wafers can be formed to overlap with the isolation layer, the etching thickness in the etching process for forming the via can be reduced. As a result, the etching process time for forming the via can be shortened, thus helping to reduce manufacturing costs and increase productivity.

[0098] According to embodiments of this disclosure, vias connected to an isolation layer are formed in the rear surface of the substrate of the upper wafer, and a dielectric layer is formed on the rear surface of the substrate of the upper wafer including the vias. As a result, the contact area between the dielectric layer and the substrate of the upper wafer can be increased, and the bonding force therebetween can be improved. Therefore, it can help suppress in subsequent processes the occurrence of misalignment between the lower wafer and the upper wafer due to insufficient bonding force at the interface between the substrate of the upper wafer and the dielectric layer.

[0099] The exemplary embodiments described above can be implemented not only by devices and methods, but also by programs that implement functions corresponding to the configurations of the exemplary embodiments of this disclosure, or by recording media on which the programs are recorded, and can be readily implemented by those skilled in the art based on the description of the foregoing exemplary embodiments.

[0100] Although exemplary embodiments of this disclosure have been described for illustrative purposes, those skilled in the art will understand that various modifications, additions, and substitutions can be made without departing from the scope and spirit of this disclosure. Therefore, the embodiments disclosed above and in the accompanying drawings should be considered descriptive only and not intended to limit the scope of the technology. The scope of this disclosure is not limited by the embodiments and the accompanying drawings. The spirit and scope of this disclosure should be interpreted through the appended claims and include all equivalents falling within the scope of the appended claims.

[0101] Cross-references to related applications

[0102] This application claims priority to Korean Patent Application No. 10-2020-0097352, filed on August 4, 2020, with the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference.

Claims

1. A semiconductor device, the semiconductor device comprising: The lower wafer includes a first substrate, a first dielectric layer defined on the first substrate, and a first wiring line defined in the first dielectric layer; A wafer is mounted, the wafer comprising a second substrate, an isolation layer defined in an upper surface of the second substrate, a via, a second dielectric layer bonded to an upper surface of a first dielectric layer, a third dielectric layer defined in the upper surface of the second substrate, and a second wiring defined in the third dielectric layer, wherein the via extends vertically from a lower surface of the second substrate to expose a lower surface of the isolation layer defined in the second substrate, the second dielectric layer covers the lower surface of the second substrate and includes at least a portion defined in the via and in contact with the isolation layer; as well as A via passes beneath the second wiring line through the third dielectric layer, the isolation layer, the second dielectric layer below the isolation layer, and the first dielectric layer, and connects the second wiring line and the first wiring line.

2. The semiconductor device according to claim 1, further comprising: A dummy isolation layer is defined in the upper surface of the second substrate and disposed around the isolation layer. The isolation layer and the at least portion of the second dielectric layer that are in contact with the isolation layer extend together through the second substrate from the upper surface of the second substrate to the lower surface of the second substrate.

3. The semiconductor device according to claim 1, wherein, At least a portion of the second dielectric layer extends upward from the lower surface of the second substrate to the lower surface of the insulating layer.

4. The semiconductor device according to claim 1, wherein, The width of the lower surface of the isolation layer is greater than the width of the top surface of at least a portion of the second dielectric layer.

5. The semiconductor device according to claim 4, wherein, The inner sidewall of the second substrate, defined by at least a portion of the isolation layer and the second dielectric layer, has a stepped shape.

6. The semiconductor device according to claim 4, wherein, The at least portion of the second dielectric layer has a constant width from the lower surface of the second substrate to the lower surface of the isolation layer.

7. The semiconductor device according to claim 1, wherein, The isolation layer has a width that narrows from the upper surface of the isolation layer to the lower surface of the isolation layer.

8. The semiconductor device according to claim 7, wherein, The at least portion of the second dielectric layer has a width that widens from the lower surface of the isolation layer to the lower surface of the second substrate.

9. The semiconductor device according to claim 7, wherein, The at least portion of the second dielectric layer has a width that narrows from the lower surface of the isolation layer to the lower surface of the second substrate.

10. The semiconductor device according to claim 1, wherein, The second dielectric layer includes at least two portions defined in the lower surface of the second substrate and spaced apart from each other, located below the isolation layer and in contact with the isolation layer.

11. The semiconductor device of claim 10, further comprising: A dummy isolation layer is defined in the upper surface of the second substrate and disposed around the isolation layer.

12. The semiconductor device of claim 10, further comprising: A dummy isolation layer is defined in the upper surface of the second substrate and disposed along opposite sides of the isolation layer.

13. The semiconductor device according to claim 11, wherein, The through hole includes: A first via, the first via passing through the isolation layer, the second dielectric layer below the isolation layer, and the first dielectric layer; and The second via passes through the third dielectric layer beneath the second wiring line and is connected to the first via.

14. The semiconductor device according to claim 1, wherein, The lower wafer includes a memory cell array defined on the first substrate, and the upper wafer includes logic circuitry defined on the second substrate that controls the memory cell array.

15. The semiconductor device according to claim 14, in, The first wiring line is electrically connected to the memory cell array. The second wiring line is electrically connected to the logic circuit, and The memory cell array is electrically connected to the logic circuit through the first wiring line, the second wiring line, and the via.

16. A semiconductor device comprising: The lower wafer includes a first substrate, a first dielectric layer defined on the first substrate, and a first wiring line defined in the first dielectric layer; The wafer includes a second substrate, an isolation layer defined in an upper surface of the second substrate, a via extending from a lower surface of the second substrate to the upper surface of the second substrate to expose a lower surface of the isolation layer, a second dielectric layer filling the via and covering the lower surface of the second substrate and bonded to an upper surface of a first dielectric layer, a third dielectric layer defined on the upper surface of the second substrate, and a second wiring line defined on the third dielectric layer. as well as A via, which passes beneath the second wiring line through the third dielectric layer, the isolation layer, the second dielectric layer below the isolation layer, and the first dielectric layer, and connects the second wiring line and the first wiring line. The through-hole has a vertical height that is less than the thickness of the second substrate.

17. A method for manufacturing a semiconductor device, the method comprising the following steps: An isolation layer is formed on the front surface of the upper wafer substrate; A via is formed, the via exposing one of the isolation layers by passing through the upper wafer substrate from a rear surface opposite to the front surface; A first dielectric layer is formed, which fills the via and covers the rear surface; The lower wafer is defined as a lower wafer substrate, a second dielectric layer defined on the lower wafer substrate, and a first wiring line disposed in the second dielectric layer. The top surface of the second dielectric layer of the lower wafer and the bottom surface of the first dielectric layer are joined together; A third dielectric layer is formed on the front surface of the upper wafer substrate; A via is formed, the via passing through the third dielectric layer, the isolation layer, the first dielectric layer below the isolation layer, and the second dielectric layer, and is connected to the first wiring line; as well as A second wiring line connected to the via is formed on the third dielectric layer.

18. The method of claim 17, further comprising the step of: Before bonding the top surface of the second dielectric layer and the bottom surface of the first dielectric layer, the bottom surface of the first dielectric layer and the top surface of the second dielectric layer are planarized by CMP process; as well as Plasma treatment or wet pretreatment is performed on the planarized bottom surface of the first dielectric layer and the planarized top surface of the second dielectric layer.

19. The method of claim 17, further comprising the step of: After bonding the top surface of the second dielectric layer and the bottom surface of the first dielectric layer and before forming the third dielectric layer, circuit elements are formed on the front surface of the upper wafer substrate.

20. The method according to claim 19, in, The lower wafer includes a memory cell array connected to the first wiring line, and The circuit element includes logic circuitry connected to the second wiring line and controlling the memory cell array.

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