Semiconductor storage device

Abstract

According to one embodiment, a semiconductor memory device includes: a stack in which a plurality of conductive layers are separated from each other and stacked; a pillar that extends in a stacking direction and includes memory cells to be formed at intersection points with at least some of the plurality of conductive layers; an upper insulating layer disposed on the stack; a plug that extends in the stacking direction inside the upper insulating layer and is connected to an upper end portion of the pillar; and a spacer insulating layer that surrounds the plug and has a dielectric constant lower than that of the upper insulating layer.

Description

[0001] Cross - Reference to Related Applications

[0002] This application claims the benefit of priority based on Japanese Patent Application No. 2020-135031, filed on Aug. 7, 2020; the entire contents of the application are incorporated herein by reference. Technical Field

[0003] Embodiments described herein generally relate to semiconductor memory devices. Background Art

[0004] For example, in a three-dimensional non-volatile memory, a pillar penetrates a stack in which a plurality of conductive layers are stacked, and memory cells are formed at intersections between the pillar and at least some of the conductive layers. A plug connecting the pillar and an upper wiring is connected to an upper surface of the pillar. For example, if the pillar and the plug, both having a columnar shape, are misaligned, there is a possibility that the plug and the conductive layer in the stack come into contact with each other. Summary of the Invention

[0005] A semiconductor memory device according to an embodiment includes: a stack in which a plurality of conductive layers are separated from each other and stacked; a pillar extending in a stacking direction of the plurality of conductive layers inside the stack and including memory cells to be formed at intersections with at least some of the plurality of conductive layers; an upper insulating layer disposed on the stack; a plug extending in the stacking direction inside the upper insulating layer and connected to an upper end portion of the pillar; and a spacer insulating layer surrounding the plug inside the upper insulating layer and having a dielectric constant lower than that of the upper insulating layer.

[0006] According to an embodiment, contact between the plug on the upper layer of the pillar and the conductive layer in the stack can be prevented. Brief Description of the Drawings

[0007] Figures 1A to 1D is a cross-sectional view of a semiconductor memory device according to an embodiment;

[0008] Figures 2A to 2D is a cross-sectional view illustrating an example of a procedure of a method for manufacturing a semiconductor memory device according to an embodiment;

[0009] Figures 3A to 3D is a cross-sectional view illustrating an example of a procedure of a method for manufacturing a semiconductor memory device according to an embodiment;

[0010] Figures 4A to 4D is an enlarged cross-sectional view illustrating an example of a procedure of a method for forming a plug of a semiconductor memory device according to an embodiment;

[0011] Figure 5A and 5B is an enlarged cross-sectional view of an example of a procedure for a method of forming a plug for a semiconductor memory device according to an embodiment;

[0012] Figure 6A and 6B is a schematic view illustrating the alignment of a pillar and a plug of a semiconductor memory device according to an embodiment;

[0013] Figures 7A to 7D is an enlarged cross-sectional view of an example of a procedure for a method of forming a plug for a semiconductor memory device according to an embodiment;

[0014] Figures 8A to 8D is a view illustrating the relationship between the layer thickness of an insulating layer and the hole diameter and pillar diameter of a semiconductor memory device according to an embodiment; and

[0015] Figures 9A to 9D is an enlarged cross-sectional view of an example of a configuration near a plug of a modified semiconductor memory device according to an embodiment. DETAILED DESCRIPTION

[0016] Hereinafter, the present invention will be described in detail with reference to the drawings. It should be noted that the present invention is not limited to the embodiments below. In addition, the constituent elements in the following embodiments include constituent elements that can be easily adopted by those skilled in the art or substantially the same constituent elements.

[0017] (Example Configuration of Semiconductor Memory Device)

[0018] Figures 1A to 1D is a cross-sectional view of a semiconductor memory device 1 according to an embodiment. Figure 1A is a cross-sectional view illustrating the overall configuration of a pillar PL of the semiconductor memory device 1. Figure 1B is an enlarged cross-sectional view of a pillar PL near select gate lines SGD0 and SGD1, Figure 1C is an enlarged cross-sectional view of a pillar PL near a word line WL, and Figure 1D is an enlarged cross-sectional view of a pillar PL near select gate lines SGS0 and SGS1.

[0019] As Figure 1A illustrated, the semiconductor memory device 1 includes a stack body LM, insulating layers 51, 52, and the like on a substrate SB.

[0020] The substrate SB is a semiconductor substrate, such as a silicon substrate. The substrate SB has an n-well 11 in a surface layer portion, a p-well 12 inside the n-well 11, and a plurality of n + diffusion regions 13 inside the p-well 12.

[0021] The stacked body LM has a structure in which a plurality of conductive layers and insulating layers are stacked alternately one by one. For example, the conductive layer is a tungsten layer or a molybdenum layer. For example, the insulating layer is a SiO2 layer or the like.

[0022] Among the plurality of conductive layers of the stacked body LM, the conductive layers on the lowermost layer and the second lowermost layer are the selection gate lines SGS1 and SGS0, respectively. Among the plurality of conductive layers, the conductive layers on the second uppermost layer and the uppermost layer are the selection gate lines SGD1 and SGD0, respectively. The other conductive layers of the stacked body LM are word lines WL.

[0023] However, the number of selection gate lines SGS is arbitrary, and the number of selection gate lines SGS can be one or less or three or more. In addition, the number of selection gate lines SGD is arbitrary, and the number of selection gate lines SGD can be one or less or three or more. The number of word lines WL is also arbitrary.

[0024] In this way, the plurality of conductive layers of the stacked body LM can include a predetermined number of selection gate lines SGS and SGD and a predetermined number of word lines WL. It should be noted that different conductive materials can be used to configure the selection gate lines SGS and SGD and the word lines WL.

[0025] The plurality of word lines WL and the selection gate lines SGS1, SGS0, SGD1, and SGD0 are separated from each other, and the insulating layer OL is disposed among the plurality of word lines WL and the selection gate lines SGS1, SGS0, SGD1, and SGD0.

[0026] Insulating layers 51a and 51b, which serve as the upper insulating layer 51, are disposed on the stacked body LM, and an etch stop layer ES, which serves as an intermediate insulating layer of the upper insulating layer 51, is inserted between the insulating layers 51a and 51b. That is, in the upper insulating layer 51, the etch stop layer ES, which serves as an intermediate insulating layer, is made of a material different from the other parts of the upper insulating layer 51. Here, for example, the other parts of the upper insulating layer 51 are the insulating layers 51a and 51b. A bit line BL, which serves as an upper layer wiring, is disposed on the insulating layer 51b, and an insulating layer 52 is interposed between the bit line BL and the insulating layer 51b.

[0027] For example, the insulating layers 51a, 51b, and 52 are SiO2 layers or the like. For example, the etch stop layer ES is a SiN layer or the like and has higher etch resistance than the insulating layers 51a and 51b under predetermined etching conditions. In addition, for example, the etch stop layer ES is a layer having a higher dielectric constant than the dielectric constants of the insulating layers 51a and 51b. The bit line BL is a metal layer or the like.

[0028] In the stack body LM, a plurality of contacts LI are arranged, each of which has a longitudinal direction in a predetermined direction along the surface of each layer of the stack body LM, penetrates the insulating layer 51a and the stack body LM, and reaches the n of the substrate SB + diffusion region 13. The stack body LM is divided into a plurality of parts by a plurality of contacts LI in a direction intersecting the predetermined direction.

[0029] An insulating layer 54 such as a SiO2 layer is arranged on the side wall of the contact LI. The inside of the insulating layer 54 is filled with a conductive layer 21 such as a tungsten layer. The conductive layer 21 of the contact LI is connected to the upper layer wiring through a plug or the like (not shown).

[0030] With the above configuration, for example, the contact LI serves as a source line contact. However, instead of the contact LI, an insulating layer or the like that does not serve as a source line contact may divide the stack body LM.

[0031] A separation layer SHE is arranged between two contacts LI. The separation layer SHE has a longitudinal direction in a direction along the longitudinal direction of the contact LI, and penetrates the insulating layer 51a and the select gate lines SGD0 and SGD1 of the stack body LM. The separation layer SHE is filled with an insulating layer such as a SiO2 layer, and between the two contacts LI, the conductive layers on the topmost layer and the second topmost layer of the stack body LM are respectively divided into patterns of two select gate lines SGD0 and SGD1.

[0032] In addition, for example, between two contacts LI, a plurality of columns PL extending in the stacking direction of a plurality of word lines WL inside the stack body LM are arranged in a matrix to be separated from each other by a predetermined distance. The stacking direction of the plurality of word lines WL is a direction intersecting the direction in which the individual word lines WL extend and stretch in the layer. It should be noted that the direction in which the word lines WL extend and stretch in the layer is substantially the same as the direction in which the insulating layer OL included in the stack body LM extends and stretches in the layer. Therefore, in this specification, the stacking direction of the plurality of word lines WL may be simply referred to as the stacking direction of the stack body LM.

[0033] The column PL penetrates the stack body LM from a predetermined depth position of the insulating layer 51a and reaches the inside of the p-well 12 of the substrate SB. For example, the column PL has a columnar shape, and the cross section orthogonal to the longitudinal direction of the column PL is a circle.

[0034] The column PL includes an epitaxial layer EP at the lower end portion that protrudes from the inside of the p-well 12 of the substrate SB to the insulating layer OL on the lowermost layer of the stack body LM. For example, the epitaxial layer EP is a crystalline silicon layer or the like.

[0035] On the epitaxial layer EP in the pillar PL, a memory layer ME, a channel layer CN, and a core layer CR are sequentially arranged starting from the outer peripheral portion of the pillar PL so as to penetrate the stack body LM. The memory layer ME is a layer in which a block insulating layer BK, a charge storage layer CT, and a tunnel insulating layer TN are stacked in this order starting from the outer peripheral side of the pillar PL. The channel layer CN is also arranged on the upper surface of the epitaxial layer EP.

[0036] For example, the block insulating layer BK, the tunnel insulating layer TN, and the core layer CR are SiO2 layers or the like. For example, the charge storage layer CT is a SiN layer or the like. For example, the channel layer CN is an amorphous silicon layer or a polysilicon layer.

[0037] A capping layer CP, which is an amorphous silicon layer or a polysilicon layer, is arranged at the upper end portion of the core layer CR and is connected to the channel layer CN on the outer periphery. The capping layer CP is connected to a plug CH, which penetrates an etch stop layer ES and extends vertically inside the insulating layers 51a and 51b. The plug CH is connected to a bit line BL via a plug V1 embedded in an insulating layer 52 arranged on the insulating layer 51b.

[0038] It should be noted that in this specification, the vertical direction of the semiconductor memory device 1 is defined with reference to the pillar PL. Specifically, one of the two end portions in the longitudinal direction of the pillar PL to which the plug CH is connected is referred to as the upward direction of the semiconductor memory device 1. In this specification, the vertical direction of the semiconductor memory device 1 is sometimes used to mean the same as the stacking direction of the plurality of word lines WL described above.

[0039] The plug CH has a columnar shape, the cross section orthogonal to the longitudinal direction of the plug CH is circular, and is configured to be filled with a metal layer, such as a tungsten layer. For example, the diameter of the plug CH is smaller than the diameter of the pillar PL. That is, when viewed from the stacking direction of the stack body LM, the plug CH has an area smaller than the area of the upper end portion of the pillar PL. For example, the plug V1 has an elliptical cross section orthogonal to the longitudinal direction of the plug V1 and is configured to be filled with a metal layer, such as a tungsten layer.

[0040] It should be noted that since the plurality of pillars PL are separated from each other by a predetermined distance as described above, it is possible to prevent the plug CH connected to one pillar PL from being too close to the adjacent pillar PL and making physical or electrical contact therewith. In other words, for example, the interval between the plurality of pillars PL is maintained at a distance that can prevent physical and electrical contact between the adjacent plug CH and pillar PL.

[0041] An insulating layer 53 serving as a spacer insulating layer is disposed around the plug CH. The insulating layer 53 surrounds the plug CH with a predetermined thickness and is interposed between the plug CH and the upper insulating layer 51 including the insulating layers 51a and 51b and the etch stop layer ES. For example, the diameter of the outer edge of the insulating layer 53 is larger than the diameter of, for example, the pillar PL.

[0042] The insulating layer 53 extends inside the insulating layer 51a to a position below the upper surface of the pillar PL. For example, the lower end of the insulating layer 53 may reach the upper surface of the select gate line SGD0 to contact the select gate line SGD0. Accordingly, the insulating layer 53 covers at least a part of the outer peripheral portion of the upper end portion of the pillar PL protruding into the insulating layer 51a.

[0043] The insulating layer 53 is a layer having a dielectric constant lower than that of the insulating layers 51a and 51b and is, for example, a low dielectric constant layer (low-k layer) containing SiOC or the like. Since the etch stop layer ES is a layer having a dielectric constant higher than that of the insulating layers 51a and 51b described above, it can also be said that the insulating layer 53 generally has a dielectric constant lower than that of the upper insulating layer 51.

[0044] It should be noted that the insulating layer 53 may be a low-k layer containing a material other than SiOC. For example, as the insulating layer 53, a low-k layer containing at least any low-k material such as SiOC, SiOF, SiOCN, SiCOH, SiBCN, hydrogen-containing SiO (HSQ: hydrogen silsesquioxane), and methyl-containing SiO (MSQ: methyl silsesquioxane) can be used. The insulating layer 53 may contain a low-k material other than these. The insulating layer 53 may contain one or more materials or may be composed of a plurality of sub-layers, at least one of which contains a low-k material. One or more of the materials contained in the low-k layer may be porous.

[0045] Here, there is a case where the pillar PL is also disposed at the disposition position of the separation layer SHE to maintain a regular array of a plurality of pillars PL. In this case, the upper portion of the pillar PL interferes with the separation layer SHE, and the plug CH, V1, and the like are not disposed on this pillar PL. Accordingly, this pillar PL can be used as a dummy pillar where an effective memory cell for reading and writing data is not formed even at the intersection with the word line WL.

[0046] As illustrated in Figure 1C a plurality of memory cells MC arranged in the height direction are formed at the intersection of the pillar PL connected to the bit line BL via the plug CH and V1 and the corresponding word line WL. That is, assuming that a plurality of conductive layers include the select gate lines SGS and SGD and the word line WL, the memory cells MC are formed at the intersections with the plurality of word lines WL which are some of the plurality of conductive layers.

[0047] When a predetermined charge is stored in the charge storage layer CT of each memory cell MC or the like, data is stored in each of the memory cells MC. When a predetermined voltage such as a read voltage and a write voltage is applied through each of the word lines WL arranged at the same height position as each of the memory cells MC, data is read from each of the memory cells MC and data is written to each of the memory cells MC.

[0048] As described in Figure 1B the select gates STD0 and STD1 are respectively formed at the intersection points between each of the pillars PL and each of the select gate lines SGD0 and SGD1. In addition, the select gates STS0 and STS1 are respectively formed at the intersection points between the pillar PL and each of the select gate lines SGS0 and SGS1, as described in Figure 1D When a predetermined voltage is applied through the select gate lines SGD0, SGD1, SGS0, and SGS1, the select gates STD0, STD1, STS0, and STS1 are turned on or off, and the memory cells MC of the pillar PL to which the select gates STD0, STD1, STS0, and STS1 belong become in a selected state or an unselected state.

[0049] For example, the stack body LM includes a stepped region (not shown), in which a plurality of word lines WL and select gate lines SGD0, SGD1, SGS0, and SGS1 are led out in a staircase shape. The individual word lines WL and select gate lines SGD0, SGD1, SGS0, and SGS1 in the stepped region are connected to a peripheral circuit (not shown).

[0050] For example, the peripheral circuit includes transistors (not shown) arranged on the substrate SB, arranged around the stack body LM, and promotes the operation of the memory cells MC and the select gates STD0, STD1, STS0, and STS1 by controlling the voltage to be applied to the word lines WL and the select gate lines SGD0, SGD1, SGS0, and SGS1.

[0051] (Method for manufacturing a semiconductor memory device)

[0052] Next, an example of a method for manufacturing the semiconductor memory device 1 according to an embodiment will be described with reference to Figures 2A to 7D FIG. is a cross-sectional view showing an example of a procedure for manufacturing the semiconductor memory device 1 according to an embodiment. It should be noted that it is assumed that a peripheral circuit (not shown) has been formed on the substrate SB before the process described in Figures 2A to 3D FIG. Figure 2A is performed.

[0053] As described in Figure 2AAs described, a stack body LM in which a plurality of sacrificial layers NL and insulating layers OL are stacked alternately one by one is formed on a substrate SB. The substrate SB has an n-well 11 in a surface layer portion and a p-well 12 in the n-well 11. For example, the sacrificial layer NL is a SiN layer or the like and is a layer that will later be replaced with a conductive material to form a word line WL or select gate lines SGD1, SGD0, SGS1, and SGS0. An insulating layer 51a is formed on the stack body LM.

[0054] In addition, at this time sequence, a stepped region (not shown) is formed in which the individual sacrificial layers NL of the stack body LM are led out in a staircase shape.

[0055] As described in Figure 2B a plurality of columns PL are formed that penetrate the insulating layer 51a and the stack body LM and reach the p-well 12 of the substrate SB.

[0056] That is, a plurality of memory holes are formed that penetrate the insulating layer 51a and the stack body LM and reach the p-well 12 of the substrate SB. For example, crystalline silicon compatible with the silicon constituting the substrate SB is epitaxially grown on the hole bottom of the memory hole to form an epitaxial layer EP. In addition, a memory layer ME, a channel layer CN, and a core layer are formed in this order from the outer peripheral side of the memory hole in the memory hole. The channel layer CN is also formed on the epitaxial layer EP at the bottom of the memory hole. In addition, a recess formed by etching back the upper end portion of the core layer CR is filled with an amorphous silicon layer, a polysilicon layer, or the like to form a cover layer CP.

[0057] Therefore, a plurality of columns PL arranged in a matrix are formed in the stack body LM.

[0058] As described in Figure 2C the insulating layer 51a is stacked to bury the upper surface of the column PL in the insulating layer 51a. In addition, a plurality of slits ST are formed, each of which has a longitudinal direction in a predetermined direction along the surface of each layer of the stack body LM, penetrates the insulating layer 51a and the stack body LM, and reaches the p-well 12 of the substrate SB. In addition, a groove having a longitudinal direction along the longitudinal direction of the slit ST and penetrating the insulating layer 51a and the sacrificial layer NL on the topmost layer and the second topmost layer of the stack body LM is formed at a position between two slits ST, and the groove is filled with an insulating layer to form a separation layer SHE.

[0059] As described in Figure 2D the sacrificial layer NL included in the stack body LM is replaced with a conductive material to form a word line WL and select gate lines SGD0, SGD1, SGS0, and SGS1.

[0060] That is, the sacrificial layer NL in the stacked body LM is removed through the slit ST penetrating the stacked body LM. Additionally, the slit ST is used to fill the gap between the insulating layers OL formed by removing the sacrificial layer NL with a conductive material. Thus, a stacked body LM including the word line WL and the select gate lines SGD0, SGD1, SGS0, and SGS1 is formed.

[0061] It should be noted that the process of replacing the sacrificial layer NL of the stacked body LM with the word line WL or the like is called the replacement process.

[0062] In addition, n + The diffusion region 13 is formed on the substrate SB and is exposed on the bottom surface of the slit ST.

[0063] As described in Figure 3A An insulating layer 54 is formed on the sidewall of the slit ST, and the inside of the insulating layer 54 is filled with a conductive layer 21 to form a contact LI. However, the inside of the slit ST may be completely filled with an insulating layer or the like so as not to serve as a source line contact.

[0064] As described in Figure 3B An etch stop layer ES is formed on the insulating layer 51a, and an insulating layer 51b is formed on the etch stop layer ES.

[0065] As described in Figure 3C A hole HLc is formed above the pillar PL, penetrating the insulating layer 51b and the etch stop layer ES and reaching a position deeper than the upper surface of the pillar PL in the insulating layer 51a. For example, the bottom surface of the hole HLc may reach the upper surface of the select gate line SGD0.

[0066] As Figure 3D described in, an insulating layer 53 is formed on the sidewall of the hole HLc, and the inside of the insulating layer 53 is filled with a conductive layer to form a plug CH connected to the capping layer CP of the pillar PL.

[0067] Thereafter, an insulating layer 52 is formed on the insulating layer 51b, and a plug V1 connected to the plug CH is formed in the insulating layer 52. A bit line BL connected to the plug V1 is formed on the insulating layer 52.

[0068] In addition, the contact LI is connected to the upper layer wiring through a plug or the like (not shown), and connects the stepped region (not shown) of the stacked body LM and the peripheral circuit (not shown) on the substrate SB.

[0069] As described above, the semiconductor memory device 1 of the manufacturing example is manufactured.

[0070] Here, a method for forming the plug CH and the insulating layer 53 will be described in more detail with reference to Figures 4A to 7D Figures 4A to 5BFIGS. 7A to 7D are enlarged cross-sectional views illustrating an example of a procedure for forming a plug CH of the semiconductor memory device 1 according to an embodiment. Figure 6A and 6B is a schematic view illustrating the alignment of the pillar PL and the plug CH of the semiconductor memory device 1 according to an embodiment.

[0071] As illustrated in Figure 4A , after the replacement process, an etch stop layer ES and an insulating layer 51b are formed on the stack LM, and then a mask pattern 61 is formed on the insulating layer 51b. The mask pattern 61 has an opening above the pillar PL. It should be noted that Figure 4A the plug position CHt where the plug CH will be formed later is illustrated by a dashed line. The opening 61c of the mask pattern 61 has a shape such as a circle in a top view, and has a diameter / circular opening area larger than the diameter / circular cross-sectional area of, for example, the plug CH to be formed and the diameter / circular cross-sectional area of the upper end portion of the pillar PL to be connected. It should be noted that "in a top view" means a case where it is observed from the stacking direction of the stack LM.

[0072] As illustrated in Figure 4B , the insulating layers 51a and 51b and the etch stop layer ES are etched using the mask pattern 61 as a mask to form a hole HLc that reaches the upper surface of the pillar PL and has a diameter / open area larger than the diameter / cross-sectional area of the plug CH and the diameter / cross-sectional area of the pillar PL.

[0073] It should be noted that there is a case where the height at which the upper end portion of the pillar PL protrudes from the select gate line SGD0 into the insulating layer 51a and the height difference between the pillar PL and the contact LI vary, so that the distance from the upper surface of the insulating layer 51b to the upper surface of the pillar PL varies during the manufacturing process of the semiconductor memory device 1.

[0074] Therefore, when the hole HLc is formed by etching, it is desirable to penetrate the insulating layer 51b under etching conditions with high selectivity with respect to the etch stop layer ES so that the arrival position of the hole HLc is aligned at once on the upper surface of the etch stop layer ES. In addition, when the insulating layer 51a is etched after penetrating the etch stop layer ES under different etching conditions, it is desirable to set the etching time so that a predetermined overetch amount is added to the theoretical etching amount until the bottom of the hole HLc reaches the upper surface of the pillar PL.

[0075] Therefore, the holes HLc formed separately on the plurality of pillars PL can reach the upper surfaces of the corresponding pillars PL more reliably. Accordingly, a part of the bottom of the hole HLc that departs from the upper surface of the pillar PL reaches a position deeper than the upper surface of the pillar PL in some or all of the pillars PL in the insulating layer 51a. In some or all of the pillars PL, a state may be formed in which the bottom of the hole HLc reaches the upper surface of the select gate line SGD0, and the upper surface of the select gate line SGD0 is exposed at the bottom of the hole HLc.

[0076] Through this etching process, the upper end portion of the pillar PL protruding into the insulating layer 51a protrudes into the hole HLc, and a gap portion HLg is formed between the pillar PL and the insulating layer 51a in the outer peripheral portion of the pillar PL. In principle, with respect to the entire diameter of the hole HLc in a predetermined cross section of the hole HLc, the total width of the gap portions HLg on both sides of the pillar PL is approximately the difference between the diameter of the hole HLc and the diameter of the pillar PL.

[0077] As illustrated in Figure 4C an insulating layer 53 is formed on the side walls of the hole HLc. The insulating layer 53 is also formed on the upper surface of the pillar PL and the upper surface of the insulating layer 51b. At this time, the thickness of the insulating layer 53 is adjusted such that the hole HLc is not completely filled, and a hole 53c serving as a space for forming the plug CH is left.

[0078] In addition, preferably, the insulating layer 53 is adjusted to have a certain thickness such that the gap portion HLg on the outer periphery of the pillar PL is substantially completely filled with the insulating layer 53. In the gap portion HLg, the insulating layer 53 is formed from both the side wall of the pillar PL and the side wall of the insulating layer 51a. Therefore, if the insulating layer 53 is formed to have a thickness of 1 / 2 or more of the difference between the diameter of the hole HLc and the diameter of the pillar PL, then even considering the misalignment between the pillar PL and the plug CH (which will be described later), the gap portion HLg can be almost completely filled.

[0079] Here, when viewed in the stacking direction of the stack LM, the area of the region surrounded by the outer edge of the insulating layer 53, that is, the region defined by the outer edge of the insulating layer 53, is larger than the cross-sectional area of the plug CH and the area of the upper end portion of the pillar PL.

[0080] It should be noted that in the semiconductor memory device 1 of the embodiment, the outer edge of the insulating layer 53, the plug CH, and the upper end portion of the pillar PL are, for example, circular. Therefore, since the hole HLc is formed as described in Figure 4B the outer edge of the insulating layer 53 also has a diameter larger than the diameter of the plug CH and the diameter of the upper end portion of the pillar PL, which is similar to the magnitude relationship in the corresponding regions.

[0081] However, at least any one of the outer edge of the insulating layer 53 (the opening of the hole HLc), the plug CH, and the upper end portion of the pillar PL may be oval or have an oval shape or the like. Even in this case, preferably, the area defined by the outer edge of the insulating layer 53 is larger than the cross-sectional area of the plug CH and the area of the upper end portion of the pillar PL as viewed from the stacking direction of the stack LM, so that the outer edge of the insulating layer 53 can surround the plug CH and the upper end portion of the pillar PL.

[0082] As illustrated in Figure 4D the insulating layer 53 on the upper surface of the pillar PL and the upper surface of the insulating layer 51b is removed by etch-back.

[0083] As illustrated in Figure 5A the inside of the hole 53c is filled with a conductive layer 22 such as a tungsten layer. The conductive layer 22 is also formed on the upper surface of the insulating layer 51b.

[0084] As illustrated in Figure 5B the conductive layer 22 on the upper surface of the insulating layer 51b is removed by chemical mechanical polishing (CMP) or the like.

[0085] As described above, the plug CH connected to the capping layer CP of the pillar PL is formed. In addition, the insulating layer 53 surrounding the periphery of the plug CH and desirably surrounding the periphery of the upper end portion of the pillar PL is formed.

[0086] However, there is also a case where the plug CH and the insulating layer 53 are formed in a state where the positional relationship between the pillar PL and each of the plug CH and the insulating layer 53 is different from Figures 4A to 5B the positional relationship in the above example. This is because there is a case where the opening 61c is displaced from the arrangement position of the pillar PL depending on the alignment accuracy of lithography when forming the mask pattern 61 having the opening 61c.

[0087] Figure 6A The positional relationship between the pillar PL, the plug CH, and each of the outer edges of the insulating layer 53 is described when the opening 61c is misaligned with respect to the pillar PL. In this case, the outer edges of the pillar PL, the plug CH, and the insulating layer 53 are arranged to be concentric with each other. Therefore, the periphery of the plug CH and the periphery of the pillar PL are surrounded by the insulating layer 53, as in Figures 4A to 5B the above example.

[0088] However, at least any one of the outer edge of the insulating layer 53, the plug CH, and the upper end portion of the pillar PL may have a shape other than the circle described above. Even in this case, if there is no misalignment of the opening 61c with respect to the pillar PL, then the periphery of the plug CH and the periphery of the pillar PL are surrounded by the outer edge of the insulating layer 53, and the outer edge of the insulating layer 53 has the same center as the plug CH and the upper end portion of the pillar PL.

[0089] Figure 6B Describe the positional relationship between the column PL and each of the plug CH and the insulating layer 53 when the opening 61c is misaligned with respect to the column PL. Even in this case, the outer edges of the plug CH and the insulating layer 53 are in principle concentric with each other. However, the plug CH and the insulating layer 53 are arranged to be biased to one side of the column PL. Thus, for example, only the outer periphery on one side of the column PL is covered with the insulating layer 53, and the insulating layer 53 is not formed on the outer periphery on the other side of the column PL. Additionally, for example, a state is formed in which a part of the plug CH is separated from the upper surface of the column PL.

[0090] Figures 7A to 7D Describe an example in which the plug CH and the insulating layer 53 are formed in the positional relationship as described in Figure 6B the example.

[0091] For example, since the mask pattern 61 described above is misaligned as described in Figure 7A the example, the hole HLc is formed in a state where the axial center of the hole HLc is deviated from the axial center of the column PL. Thus, in the cross section described in Figure 7A the example, the gap portion HLg is formed only on one side of the column PL.

[0092] At this time, the maximum width of the gap portion HLg is considered to fall within the difference between the diameter of the hole HLc and the diameter of the column PL, for example, according to the positioning accuracy of the mask pattern 61. That is, most of the lower surface of the plug position CHt where the plug CH will be formed later is maintained on the upper surface of the column PL.

[0093] As described in Figure 7B the example, the insulating layer 53 is formed on the side wall of the hole HLc so that the hole 53c serving as a space for forming the plug CH remains. The insulating layer 53 is also formed on the upper surface of the column PL and the upper surface of the insulating layer 51b. Additionally, if the maximum width of the gap portion HLg is, for example, about twice or less the layer thickness of the insulating layer 53, then the gap portion HLg can be completely filled. The above conditions are generally satisfied from the alignment accuracy of the mask pattern 61, and the gap portion HLg is almost completely filled with the insulating layer 53.

[0094] As described in Figure 7CAs described in [reference], the insulating layer 53 on the upper surface of the column PL and the upper surface of the insulating layer 51b is removed by etchback. At this time, a part of the lower surface of the hole 53c that is separated from the upper surface of the column PL is over-etched along the sidewall of the column PL to reach a predetermined depth of the insulating layer 53 in the gap portion HLg. However, the thickness of the insulating layer 53 that fills the gap portion HLg is thick enough compared to the amount of over-etching to remove the insulating layer 53 on the upper surface of the column PL, and thus prevents the lower surface of the hole 53c from penetrating the insulating layer 53 in the gap portion HLg and reaching, for example, the select gate line SGD0.

[0095] As described in Figure 7D the inside of the hole 53c is filled with a conductive layer 22 such as a tungsten layer, and the conductive layer 22 formed on the upper surface of the insulating layer 51b is removed to form a plug CH connected to the upper surface of the column PL. A part of the lower end portion of the plug CH is separated from the upper surface of the column PL and reaches a position deeper than the upper surface of the column PL in the insulating layer 53, but is prevented from contacting the select gate line SGD0.

[0096] Therefore, even if each of the column PL, the plug CH, and the insulating layer 53 is displaced within the alignment accuracy range of photolithography, the plug CH that will be connected to the capping layer CP of the column PL is formed while preventing contact with the select gate line SGD0. In addition, the insulating layer 53 is formed to surround the periphery of the plug CH and cover at least a part of the outer peripheral portion of the upper end portion of the column PL. At this time, if the misalignment amount between the column PL and the plug CH is large, then a lower end portion of a part of the plug CH is inserted between the insulating layer covering a part of the outer periphery of the upper end portion of the column PL and the column PL.

[0097] Meanwhile, it is desirable to satisfy some conditions for the layer thickness of the insulating layer 53 formed on the sidewall of the hole HLc. Conditions required for the layer thickness of the insulating layer 53 will be described hereinafter with reference to Figures 8A to 8D FIG. [reference] describes the conditions required for the layer thickness of the insulating layer 53.

[0098] Figures 8A to 8D FIG. [reference] is a view showing the relationship between the layer thickness of the insulating layer 53 of the semiconductor memory device 1 according to the embodiment and each of the diameter of the hole HLc and the diameter of the column PL. Figure 8A The horizontal axis of the graph in [reference] represents the layer thickness X (nm) of the insulating layer 53. Figure 8A The vertical axis of the graph in [reference] represents the difference Y (nm) between the radius R Dh of the bottom surface of the hole HLc and the radius R Dp of the upper end portion of the column PL, which is obtained by subtracting the radius R Dp of the upper end portion of the column PL from the radius R Dh of the bottom surface of the hole HLc. In other words, Figure 8A the vertical axis of the graph in [reference] represents 1 / 2 of the difference between the diameter of the bottom surface of the hole HLc and the diameter of the upper end portion of the column PL.

[0099] It should be noted that the radius R Dh of the bottom surface of the hole HLc can be considered to be the same as the radius of the lower end of the outer edge of the insulating layer 53. That is to say, the difference Y (nm) between the radius R Dh of the bottom surface of the hole HLc and the radius R Dp of the upper end portion of the column PL can be reformulated as the difference Y (nm) between the radius of the lower end of the outer edge of the insulating layer 53 and the radius R Dp of the upper end portion of the column PL.

[0100] The line segment SGxl indicates the lower limit of the layer thickness X of the insulating layer 53 and is expressed, for example, by the following formula (1).

[0101] Y = 2X - 10…(1)

[0102] That is to say, it is desirable that the layer thickness X (nm) of the insulating layer 53 is not Figure 8A a value in the region AR(CH - SGD) above the line segment SGxl in the graph of. Specifically, as described in Figure 8B , there is a possibility that the gap portion HLg in the region AR(CH - SGD) is not sufficiently filled with the insulating layer 53. That is to say, when considering the possible misalignment between each of the column PL, the plug CH, and the insulating layer 53, there is a possibility that the maximum width of the gap portion HLg is greater than twice the layer thickness of the insulating layer 53. If the gap portion HLg is not sufficiently filled with the insulating layer 53, then a situation may occur in which when the insulating layer 53 is removed from the upper surface of the column PL, the insulating layer 53 is also removed from the bottom surface of the gap portion HLg, such that, for example, the select gate line SGD0 is exposed inside the gap portion HLg. Therefore, if the conductive layer 22 of the plug CH is filled, then contact with the select gate line SGD0 occurs, such that there is a possibility of a short circuit occurring between the plug CH and the select gate line SGD0.

[0103] In this way, the possible misalignment amounts between each of the column PL, the plug CH, and the insulating layer 53 are added to formula (1), and the y - intercept value (-10) in formula (1) depends, for example, on the alignment accuracy of the mask pattern 61.

[0104] The line segment Sgxu indicates the upper limit of the layer thickness X of the insulating layer 53 and is expressed, for example, by the following formula (2).

[0105] Y = 2X - 40…(2)

[0106] That is to say, it is desirable that the layer thickness X (nm) of the insulating layer 53 is not Figure 8A a value in the region AR(CH - PL) below the line segment SGxu in the graph of. Specifically, as in Figure 8CAs described, the inside of the hole HLc may be blocked by the insulating layer 53, making it difficult to sufficiently fix the diameter of the plug CH in the region AR(CH-PL). If it is difficult to sufficiently fix the diameter of the plug CH, there is a possibility that conduction between the plug CH and the column PL is not achieved or the resistance value increases.

[0107] In this way, the target value or design value of the diameter of the plug CH has been added to formula (2), and the y-intercept value (-40) of formula (2) depends on, for example, the diameter of the plug CH.

[0108] The line segment SGyu indicates the upper limit of the difference Y between the radius R Dh of the bottom surface of the hole HLc and the radius R Dp of the upper end portion of the column PL, and is expressed, for example, by the following formula (3).

[0109] Y = 25 nm…(3)

[0110] It is desirable that the difference Y between the radius R Dh of the bottom surface of the hole HLc and the radius R Dp of the upper end portion of the column PL is not Figure 8A a value in the region AR(PL-PL) above the line segment SGyu in the graph.

[0111] The above formula (3) represents a condition based on the fact that a plurality of columns PL are arranged at a predetermined distance apart. Specifically, as described in Figure 8D there is a possibility that in the region AR(PL-PL), the plug CH is too close to the column PL adjacent to the column PL to which the plug CH is connected or the lower end portion of the plug CH contacts the adjacent column PL. If the adjacent column PL and the plug CH are too close to each other, there is a possibility of a short circuit or leakage current occurring between the adjacent column PL and the plug CH.

[0112] In this way, the design value of the distance between the corresponding columns PL has been added to formula (3), and the upper limit value (25) of the difference Y between the radius R Dh of the bottom surface of the hole HLc and the radius R Dp of the upper end portion of the column PL in formula (3) depends on, for example, the distance between the columns PL.

[0113] As described above, in the Figure 8A example illustrated in the graph, the desired layer thickness of the insulating layer 53 is within the range that satisfies the following formula (4).

[0114] 2X - 40 ≤ Y ≤ 2X - 10 and 0 nm < Y < 25 nm…(4)

[0115] That is, the ideal layer thickness of the insulating layer 53 is a value in the region AR(CHbv) surrounded by the line segments SGxl, SGxu, and SGyu obtained by formulas (1) to (3).

[0116] In other words, the desired layer thickness of the insulating layer 53 has a lower limit value determined by the maximum width that the gap portion HLg can take depending on the alignment accuracy of the mask pattern 61 and an upper limit value determined by the diameter of the plug CH and the diameter of the hole HLc, and further, is also affected by the distance between the pillars PL. As described above, since both the pillar PL and the plug CH have a columnar shape, there is an ideal condition as expressed by Equation (4) with respect to the layer thickness of the insulating layer 53.

[0117] For example, in a semiconductor memory device such as a three-dimensional non-volatile memory, a plurality of pillars are formed to penetrate a stack body in which word lines and the like are stacked, and memory cells are formed at the intersection points with the word lines. The upper surfaces of these pillars are connected to an upper layer wiring, such as a bit line, via plugs. Since both the pillar and the plug having a columnar shape are connected, high alignment accuracy is required for the pillar and the plug.

[0118] In the semiconductor memory device 1 according to the embodiment, plugs CH extending in the vertical direction are provided inside the insulating layers 51a and 51b, and an insulating layer 53 surrounding the periphery of the plugs CH and having a dielectric constant lower than that of the insulating layers 51a and 51b. That is, a hole HLc having a diameter larger than that of the plug CH is formed, and after the insulating layer 53 is formed inside the hole HLc, the plug CH is formed so as to surround the plug position CHt where the plug CH will be formed later.

[0119] Therefore, contact between the plug CH on the upper layer of the pillar PL and the selection gate line SGD0 can be prevented. In other words, even if a part of the lower end portion of the plug CH is separated from the upper surface of the pillar PL due to misalignment between the pillar PL and the plug CH, the insulating layer 53 is interposed between the lower end portion of the plug CH and the selection gate line SGD0. Therefore, it is possible to prevent the plug CH and the selection gate line SGD0 from contacting each other and causing a short circuit.

[0120] In addition, since the insulating layer 53 having a low dielectric constant surrounds the periphery of the plug CH, the parasitic capacitance that may occur in the periphery of the plug CH can be reduced.

[0121] In the semiconductor memory device 1 according to the embodiment, the diameter of the outer edge of the insulating layer 53 is larger than the diameter of the upper end portion of the pillar PL, and the insulating layer 53 covers at least a part of the outer periphery of the upper end portion of the pillar PL. In this way, by increasing the diameter of the outer edge of the insulating layer 53, it is easy to fix the diameter of the hole 53c for forming the plug CH after the insulating layer 53 is formed.

[0122] In addition, if the misalignment amount between the pillar PL and the plug CH is small enough, the entire outer periphery of the upper end portion of the pillar PL is covered with the insulating layer 53. In addition, even if the pillar PL and the plug CH are misaligned, at least a part of the outer periphery of the upper end portion of the pillar PL is covered with the insulating layer 53. Therefore, the withstand voltage between adjacent pillars PL can be improved.

[0123] In the semiconductor memory device 1 according to the embodiment, in the vertical direction inside the insulating layer 51, that is, at a predetermined position in the stacking direction of the stacked body LM, an etch stop layer ES is provided which is inserted between the insulating layers 51a and 51b and surrounds the periphery of the plug CH, and the insulating layer 53 is inserted between the etch stop layer ES and the plug CH at this vertical position. Since the insulating layer 53 having a low dielectric constant is inserted between the etch stop layer ES having a high dielectric constant and the plug CH, the parasitic capacitance that may occur in the periphery of the plug CH can be further reduced.

[0124] It should be noted that considering the above-described function of the etch stop layer ES (i.e., the position of the bottom surface of the hole HLc is aligned at one time during etching), the predetermined position in the insulating layer 51 where the etch stop layer ES is inserted can be arbitrarily determined. Specifically, for example, any position above the upper end portion of the pillar PL located inside the insulating layer 51 can be set as the predetermined position where the etch stop layer ES is inserted.

[0125] In the semiconductor memory device 1 according to the embodiment, the layer thickness of the insulating layer 53 has a desired lower limit value derived from the maximum width that may occur between the outer edge of the insulating layer 53 and the outer periphery of the pillar PL. For example, it depends on the misalignment accuracy between the pillar PL and the plug CH. Since the layer thickness of the insulating layer 53 is determined based on this lower limit value, the gap portion HLg can be more reliably filled with the insulating layer 53, and a short circuit between the plug CH and the select gate line SGD0 can be prevented.

[0126] In the semiconductor memory device 1 according to the embodiment, the layer thickness of the insulating layer 53 has a desired upper limit value determined by, for example, the diameter of the plug CH and the diameter of the outer edge of the insulating layer 53. Since the layer thickness of the insulating layer 53 is determined based on this upper limit value, the diameter of the hole 53c for forming the plug CH can be ensured after the inner surface of the hole HLc is lined with the insulating layer 53.

[0127] In the semiconductor memory device 1 according to the embodiment, for example, the required layer thickness of the insulating layer 53 is also affected by the distance between the pillars PL. Since the layer thickness of the insulating layer 53 is determined in consideration of this influence, for example, the plug CH can be prevented from being too close to the pillar PL adjacent to the pillar PL to which the plug is connected.

[0128] Note that, in the embodiment described above, the diameter of the outer edge of the insulating layer 53 is larger than the diameter of the pillar PL. However, the diameter of the outer edge of the insulating layer 53 may be substantially equal to the diameter of the pillar PL, or may be smaller than the diameter of the pillar PL. Even with this configuration, a short circuit between the plug CH and the select gate line SGD0 can be prevented. In addition, when the misalignment amount between the pillar PL and the plug CH is small enough, the outer peripheral portion of the upper end portion of the pillar PL is not covered with the insulating layer 53, but the periphery of the plug CH is surrounded by the insulating layer 53, so that the parasitic capacitance in the periphery of the plug CH is reduced.

[0129] In addition, the insulating layer 53 is a low-k layer having a dielectric constant lower than that of the insulating layers 51a and 51b in the embodiment described above. However, the insulating layer 53 may be a layer having a dielectric constant similar to that of the insulating layers 51a and 51b, and may be, for example, a SiO2 layer, a SiON layer, or the like of the same type as the insulating layers 51a and 51b. Even with this configuration, a short circuit between the plug CH and the select gate line SGD0 can be prevented.

[0130] (Modification)

[0131] Next, a modified semiconductor memory device of the embodiment will be described with reference to Figure 9A and 9D The modified semiconductor memory device does not have an etch stop layer, which is different from the embodiment described above.

[0132] Figures 9A to 9D is an enlarged cross-sectional view showing a configuration example in the vicinity of the plug CH of the modified semiconductor memory device according to the embodiment. Figure 9A An example in which the insulating layer 53 surrounds the periphery of the plug CH as in the embodiment described above is illustrated. For comparison, Figure 9B An example in which an etch stop layer ES is provided between the insulating layers 51a and 51b and the insulating layer 53 surrounds the periphery of the plug CH as in the embodiment described above is illustrated. Figure 9C An example in which an insulating layer 53d (e.g., a SiO2 layer) surrounds the periphery of the plug CH is illustrated. For comparison, Figure 9D An example in which an etch stop layer ES is provided between the insulating layers 51a and 51b and the insulating layer 53d surrounds the periphery of the plug CH is illustrated.

[0133] As will be described later, in the configuration illustrated in Figures 9A to 9D a technique for preventing a short circuit between the plug CH and the select gate line SGD0 is employed, which is similar to the embodiment described above. Therefore, it is not necessary to strictly align the etch depth of the hole for forming the plug CH, and, for example, as in Figure 9A and 9CThe configuration without an etch stop layer described therein.

[0134] As described in Figure 9A As an example of a modified semiconductor memory device, an etch stop layer is not disposed inside the insulating layer 51 which is the upper layer of the select gate line SGD0. The insulating layer 51 as the upper insulating layer has a configuration corresponding to the insulating layers 51a and 51b of the embodiments described above, and is, for example, a SiO2 layer or the like.

[0135] Similar to the embodiments described above, the periphery of the plug CH is surrounded by the insulating layer 53 which is a low-k layer. The insulating layer 53 is a layer having a different material type from that of the insulating layer 51. Therefore, it is possible to discriminate that a layer different from the insulating layer 51 surrounds the periphery of the plug CH by some analysis means. Examples of the analysis means include detecting the interface between the insulating layer 53 and the insulating layer 51, detecting a component different from the component of the insulating layer 51 in the periphery of the plug CH, and the like.

[0136] Even in Figure 9B the configuration of the embodiments described above as described in Figure 9A , it is also possible to determine that a layer different from the insulating layers 51a and 51b surrounds the periphery of the plug CH by using the same analysis means as in Figure 9B . In addition, as described above, the outer edges of the plug CH and the insulating layer 53 are arranged so as to be substantially concentric with each other. Therefore, the etch stop layer ES is also arranged so as to substantially concentrically surround the periphery of the plug CH in the

[0137] configuration. This can also prove that a layer different from the insulating layers 51a and 51b surrounds the periphery of the plug CH. Figure 9A and 9B In both cases, the periphery of the plug CH is surrounded by a layer different from the insulating layers 51a and 51b, and therefore, it is assumed that the above-described technique for preventing a short circuit between the plug CH and the select gate line SGD0 has been used to form the plug CH.

[0138] As described in Figure 9C , as another example of the modified semiconductor memory device, in the configuration where an etch stop layer is not disposed in the insulating layer 51 which is the upper layer of the select gate line SGD0, the insulating layer 53d may be disposed around the periphery of the plug CH instead of around the insulating layer 53.

[0139] The insulating layer 53d is, for example, a layer having a dielectric constant similar to that of the insulating layer 51, and is, for example, a SiO2 layer of the same type as the insulating layer 51. Therefore, there are cases where it is difficult to discriminate that a layer separately formed from the insulating layer 51 surrounds the periphery of the plug CH by some analysis means.

[0140] In the case where, as described in Figure 9D , an etch stop layer ES is included, even if it is difficult to discriminate the insulating layer 53d itself, it is possible to discriminate that the periphery of the plug CH is surrounded by a layer formed indirectly separated from the insulating layer 51 by the etch stop layer ES. That is, the etch stop layer ES does not contact the plug CH, and the etch stop layer ES is arranged so as to be separated from the plug CH and, for example, substantially concentrically surrounds the periphery of the plug CH. In addition, the etch stop layer ES causes separation from the plug CH at substantially the same distance throughout the periphery of the plug CH. Therefore, it is possible to discriminate that the layer interposed between the etch stop layer ES and the plug CH and separating the etch stop layer ES from the plug CH layer is formed separately from the insulating layers 51a and 51b with a thickness corresponding to the separation distance therebetween.

[0141] In this way, at least in Figure 9D , the periphery of the plug CH is surrounded by a layer different from the insulating layers 51a and 51b, and thus, it is assumed that the above-described technique for preventing a short circuit between the plug CH and the select gate line SGD0 has been used to form the plug CH.

[0142] According to the modified semiconductor memory device, a plug CH extending in the vertical direction inside the insulating layer 51 and an insulating layer 53 or an insulating layer 53d surrounding the periphery of the plug CH are provided. In this way, the modified semiconductor memory device also uses a technique for preventing a short circuit between the plug CH and the select gate line SGD0, whereby the etch stop layer in the insulating layer 51 can be eliminated. In this way, the modified semiconductor memory device also uses a technique for preventing a short circuit between the plug CH and the select gate line SGD0, whereby the etch stop layer in the insulating layer 51 can be eliminated. Therefore, it is possible to reduce the manufacturing process of the modified semiconductor memory device and lower the cost.

[0143] (Other modifications)

[0144] In the above-described embodiments and modifications, the semiconductor memory device includes a stack LM including a word line WL as a metal layer (e.g., a tungsten layer) and select gate lines SGD0, SGD1, SGS0, and SGS1 as conductive layers. However, the conductive layer of the stack may be a layer of a silicon material containing, for example, a polysilicon layer or the like. In this case, a stack in which a layer containing a silicon material is stacked is formed from the beginning, and the semiconductor memory device is manufactured without a replacement process.

[0145] In the above-described embodiments and modifications, the semiconductor memory device has a single-layer structure including a single stack LM. However, the semiconductor memory device may have a structure of two or more layers.

[0146] In the embodiments and modifications described above, the semiconductor memory device includes a stack body LM stacked on a substrate SB and includes a peripheral circuit disposed on the substrate SB outside the stack body LM. However, the stack body LM of the semiconductor memory device may be stacked above the peripheral circuit via a source line such as a polysilicon layer or the like. Alternatively, by forming the stack body LM and the peripheral circuit on different substrates and attaching these substrates, the peripheral circuit may be disposed above the stack body LM.

[0147] Although certain embodiments have been described, these embodiments are presented by way of example only and are not intended to limit the scope of the invention. In fact, the novel embodiments described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes may be made to the forms of the embodiments described herein without departing from the spirit of the invention. The appended claims and their equivalents are intended to cover forms or modifications that fall within the spirit and scope of the invention.

Claims

1. A semiconductor memory device, comprising: A stack body, in which a plurality of conductive layers are separated from each other and stacked; A column, which extends in the stacking direction of the plurality of conductive layers inside the stack body and includes memory cells to be formed at intersection points with at least some of the plurality of conductive layers; An upper insulating layer, which is disposed on the stack body; A plug, which extends in the stacking direction inside the upper insulating layer and is connected to the upper end portion of the column; and A spacer insulating layer, which surrounds the plug inside the upper insulating layer and has a dielectric constant lower than that of the upper insulating layer.

2. The semiconductor memory device according to claim 1, wherein When viewed from the stacking direction, the region defined by the outer edge of the spacer insulating layer is larger than the region of the upper end portion of the column, and the spacer insulating layer covers at least a part of the outer periphery of the upper end portion of the column.

3. The semiconductor memory device according to claim 2, wherein When the layer thickness of the spacer insulating layer is X nm and the difference obtained by subtracting the radius of the upper end portion of the column from the radius of the lower end of the outer edge of the spacer insulating layer is Y nm, the following formula is satisfied: 2X - 40 ≤ Y ≤ 2X - 10.

4. The semiconductor memory device according to claim 3, wherein The column includes a plurality of columns, which are arranged to be separated from each other by a predetermined distance, and The difference obtained by subtracting the radius of the upper end portion of the column from the radius of the lower end of the outer edge of the spacer insulating layer is greater than 0 nm and less than 25 nm.

5. The semiconductor memory device according to claim 1, wherein The spacer insulating layer is a low-k layer containing at least one of low-k materials such as SiOC, SiOF, SiOCN, SiCOH, SiBCN, hydrogen-containing SiO, and methyl-containing SiO.

6. The semiconductor memory device according to claim 5, wherein At least one of the low-k materials contained in the low-k layer is porous.

7. The semiconductor memory device according to claim 1, wherein The upper insulating layer includes an intermediate insulating layer, which is inserted at a predetermined position in the upper insulating layer in the stacking direction and surrounds the periphery of the plug interposed by the spacer insulating layer at the predetermined position in the stacking direction.

8. The semiconductor memory device according to claim 7, wherein The intermediate insulating layer substantially concentrically surrounds the periphery of the plug.

9. The semiconductor memory device according to claim 7, wherein The intermediate insulating layer has a dielectric constant higher than that of other parts of the upper insulating layer.

10. The semiconductor memory device according to claim 1, wherein When viewed from the stacking direction, the plug has a region smaller than the region of the upper end portion of the column.

11. A semiconductor memory device, comprising: A stack body, in which a plurality of conductive layers are separated from each other and stacked; A column that extends in the stacking direction of the plurality of conductive layers inside the stack and includes memory cells to be formed at intersections with at least some of the plurality of conductive layers; An upper insulating layer disposed on the stack, the upper insulating layer including an intermediate insulating layer made of a material different from other portions of the upper insulating layer at a predetermined position in the stacking direction; And A plug that extends in the stacking direction inside the upper insulating layer and is connected to an upper end portion of the column, wherein The intermediate insulating layer is separated from the plug and surrounds the periphery of the plug at the predetermined position in the stacking direction.

12. The semiconductor memory device according to claim 11, wherein The intermediate insulating layer substantially concentrically surrounds the periphery of the plug.

13. The semiconductor memory device according to claim 11, wherein The intermediate insulating layer has a higher dielectric constant than other portions of the upper insulating layer.

14. The semiconductor memory device according to claim 13, wherein The intermediate insulating layer is a SiN layer.

15. A semiconductor memory device comprising: A stack in which a plurality of conductive layers are separated from each other and stacked; A column that extends in the stacking direction of the plurality of conductive layers inside the stack and includes memory cells to be formed at intersections with at least some of the plurality of conductive layers; An upper insulating layer disposed on the stack, the upper insulating layer including an intermediate insulating layer made of a material different from other portions of the upper insulating layer at a predetermined position in the stacking direction; A plug that extends in the stacking direction inside the upper insulating layer and is connected to an upper end portion of the column; and A spacer insulating layer that surrounds the plug inside the upper insulating layer, has a diameter defined by its outer edge that is larger than the diameter of the upper end portion of the column, and is interposed between the plug and the intermediate insulating layer at the predetermined position in the stacking direction.

16. The semiconductor memory device according to claim 15, wherein The spacer insulating layer covers at least a part of the outer periphery of the upper end portion of the column.

17. The semiconductor memory device according to claim 15, wherein The spacer insulating layer is a low-k layer containing at least one of low-k materials such as SiOC, SiOF, SiOCN, SiCOH, SiBCN, hydrogen-containing SiO, and methyl-containing SiO.

18. The semiconductor memory device according to claim 17, wherein At least one of the low-k materials contained in the low-k layer is porous.

19. The semiconductor memory device according to claim 15, wherein The intermediate insulating layer substantially concentrically surrounds the periphery of the plug.

20. The semiconductor memory device according to claim 15, wherein When viewed from the stacking direction, the plug has a smaller area than the area of the upper end portion of the column.

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