Semiconductor capacitor structure and method of manufacture

Abstract

The application discloses a semiconductor capacitor structure and a manufacturing method. The semiconductor capacitor structure comprises a bottom layer, a lower electrode, a dielectric layer and an upper electrode. The bottom layer comprises a plurality of spacers. The lower electrode comprises a bottom and a sidewall on both sides of the bottom. The bottom is located on the top surface of the spacers. The dielectric layer is formed along the inner sidewall of the lower electrode. The upper electrode is filled in the space contained by the dielectric layer. The support layer is arranged between at least one pair of adjacent sidewalls of the lower electrode. The semiconductor capacitor structure provided by the application has a plurality of support layers between two adjacent electrodes along the direction perpendicular to the bottom layer. The upper limit of the capacitor height caused by the insufficient tilt margin is solved, more etching margin is obtained, and the capacitor height required by the storage capacitor can be ensured.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, specifically to a semiconductor capacitor structure and manufacturing method. Background Technology

[0002] DRAM (Dynamic Random Access Memory) capacitors (CAPs) are high aspect ratio structures. Currently, the manufacturing process for high aspect ratio capacitors primarily employs an oxide removal process based on LAL (Low Alkali) chemical etching solution to form a support layer that prevents capacitor tilting. Existing technology uses two support layers, top and middle, for tilt protection. The structure of semiconductor capacitors manufactured using existing technology is as follows: Figure 1 As shown, there are only two support layers 2 between the sidewalls of two adjacent lower electrodes 8.

[0003] As integration density increases, aspect ratios further increase, leading to insufficient learning margin. Increasing the number of support layers is one important technical choice. However, in conventional processes, support layers require dry etching to open. The more support layers there are, the more etching steps there will be, which will increase plasma etching damage to the bottom electrode, thereby increasing the storage capacitance and reducing device performance. Summary of the Invention

[0004] The purpose of this application is to provide a semiconductor capacitor structure and manufacturing method. To provide a basic understanding of some aspects of the disclosed embodiments, a brief summary is given below. This summary is not intended as a general description, nor is it intended to identify key / important components or describe the scope of protection of these embodiments. Its sole purpose is to present some concepts in a simple form as a prelude to the detailed description that follows.

[0005] According to one aspect of the embodiments of this application, a semiconductor capacitor structure is provided, comprising:

[0006] The bottom layer includes a plurality of spaced-apart pads;

[0007] The lower electrode includes a bottom and sidewalls on both sides of the bottom, the bottom being located on the top surface of the solder pad;

[0008] A dielectric layer is formed along the bottom wall and inner sidewall of the lower electrode;

[0009] The upper electrode fills the space contained in the dielectric layer;

[0010] The support layer comprises three or more support layers between at least one pair of adjacent sidewalls of the lower electrode.

[0011] According to another aspect of the embodiments of this application, a method for manufacturing a semiconductor capacitor structure is provided, comprising:

[0012] A base layer is provided, the base layer comprising a plurality of spaced-apart pads;

[0013] Multiple sacrificial layers and multiple support layers are sequentially deposited on the bottom layer to form a stacked layer, wherein each of the sacrificial layer and the support layer comprises at least three layers.

[0014] A plurality of first trenches are fabricated that extend longitudinally through the stacked layers; wherein the first trenches expose the solder pads;

[0015] The lower electrode of the capacitor is formed on the bottom wall and inner surface of the first trench;

[0016] The sacrificial layer between two adjacent lower electrodes is completely removed to obtain a semiconductor capacitor structure.

[0017] According to another aspect of the embodiments of this application, an electronic device is provided, including the semiconductor capacitor structure described above.

[0018] One aspect of the technical solution provided in this application embodiment may include the following beneficial effects:

[0019] The semiconductor capacitor structure provided in this application embodiment has multiple support layers between two adjacent electrodes along a direction perpendicular to the bottom layer. This solves the problem of the upper limit of capacitor height caused by insufficient tilt margin, obtains more etching process margin, and can ensure that the capacitor height required for storage capacitor is obtained.

[0020] Other features and advantages of this application will be set forth in the following description and will be apparent in part from the description, or some features and advantages may be inferred from the description or determined without question, or may be learned by practicing embodiments of this application. The objectives and other advantages of this application may be realized and obtained by means of the structures particularly pointed out in the written description, claims, and drawings. Attached Figure Description

[0021] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0022] Figure 1 A schematic diagram of a prior art semiconductor capacitor structure is shown;

[0023] Figure 2 A schematic diagram of a semiconductor capacitor structure according to an embodiment of this application is shown;

[0024] Figure 3 A flowchart illustrating a method for manufacturing a semiconductor capacitor structure according to an embodiment of this application is shown;

[0025] Figure 4 This illustration shows a structural diagram of an embodiment of the present application after a stacked layer has been formed on the bottom layer;

[0026] Figure 5 This illustration shows a schematic diagram of the structure after filling the second trench with oxide, according to one embodiment of this application.

[0027] Figure 6 This illustration shows a schematic diagram of the structure after deposition of a first mask layer, a mask layer, and an oxide layer according to an embodiment of this application.

[0028] Figure 7 This illustration shows a schematic diagram of the structure after removing the oxide layer and part of the mask layer from an embodiment of the present application and fabricating a plurality of first trenches;

[0029] Figure 8 A schematic diagram of the structure after removing the residual mask layer according to an embodiment of this application is shown;

[0030] Figure 9 This illustration shows a schematic diagram of the structure after forming an electrode and separating the remaining first mask layer according to an embodiment of this application;

[0031] Figure 10 This illustration shows a schematic diagram of the structure after all the oxide between two adjacent electrodes has been removed, according to an embodiment of this application.

[0032] Figure 11 A schematic diagram of a semiconductor capacitor structure according to an embodiment of this application is shown. Detailed Implementation

[0033] Embodiments of the present disclosure will now be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the disclosure. Furthermore, descriptions of well-known structures and technologies are omitted in the following description to avoid unnecessarily obscuring the concepts of the present disclosure.

[0034] The accompanying drawings illustrate various structural schematics according to embodiments of the present disclosure. These drawings are not to scale, and some details have been enlarged for clarity, and some details may have been omitted. The shapes of the various regions and layers shown in the drawings, as well as their relative sizes and positional relationships, are merely exemplary and may deviate from reality due to manufacturing tolerances or technical limitations. Furthermore, those skilled in the art can design regions / layers with different shapes, sizes, and relative positions as needed.

[0035] In the context of this disclosure, when a layer / element is referred to as being "above" another layer / element, the layer / element may be directly above the other layer / element, or there may be an intermediate layer / element between them. Additionally, if a layer / element is "above" another layer / element in one orientation, then when the orientation is reversed, the layer / element may be "below" the other layer / element.

[0036] like Figure 2 As shown, one embodiment of this application provides a semiconductor capacitor structure, including:

[0037] The bottom layer includes a plurality of spaced solder pads 9;

[0038] The lower electrode 8 includes a bottom and two sidewalls on both sides of the bottom. Each lower electrode 8 corresponds to a solder pad 9. The bottom of the lower electrode 8 is located on the top surface of the solder pad 9.

[0039] A dielectric layer 11 is formed along the inner sidewall of the lower electrode 8;

[0040] The upper electrode 12 fills the space contained in the dielectric layer 11;

[0041] The support layer 2 has three or more layers between at least one pair of adjacent sidewalls of the lower electrode 8.

[0042] In some embodiments, the bottom layer further includes a nitride layer 10, with each of the solder pads 9 located within the nitride layer 10 and spaced apart, and the top surface of the solder pads 9 exposed from the top surface of the nitride layer 10.

[0043] The materials of the lower electrode 8 and the upper electrode 12 can be TiN. x ,TaN or WN x The material of solder pad 9 can be tungsten.

[0044] The number of support layers 2 provided between the sidewalls of two adjacent lower electrodes 8 is more than three, such as three, five, eight or ten.

[0045] In some embodiments, the thickness of the support layer 2 is

[0046] In other embodiments of the present invention, a capacitor dielectric layer and an upper electrode are formed between adjacent lower electrode 8 sidewalls, and this dielectric layer and upper electrode share a lower electrode with the dielectric layer 11 and upper electrode 12 inside the lower electrode 8.

[0047] One embodiment of this application also provides a DRAM that includes the capacitor structure described above.

[0048] Another embodiment of this application provides an electronic device including the semiconductor capacitor structure described above. The electronic device includes a smartphone, computer, tablet computer, wearable smart device, artificial intelligence device, and power bank.

[0049] Another embodiment of this application also provides a method for manufacturing a semiconductor capacitor structure, including:

[0050] 1. A substrate is provided, the substrate comprising a plurality of spaced solder pads 9;

[0051] 2. A plurality of sacrificial layers and a plurality of support layers 2 are sequentially deposited on the bottom layer to form a stacked layer; the sacrificial layer can be an oxide layer, such as silicon dioxide; the stacked layer is composed of the plurality of sacrificial layers and the plurality of support layers 2; the sacrificial layer and the support layer 2 each include at least three layers;

[0052] 3. Fabricate a plurality of first trenches that extend longitudinally through the stacked layers; wherein the first trenches expose the solder pads 9;

[0053] 4. The lower electrode of the capacitor is formed on the bottom wall and inner surface of the first trench;

[0054] 5. Remove all the sacrificial layers between the two adjacent lower electrodes 8 to obtain a semiconductor capacitor structure.

[0055] Before fabricating multiple first trenches that extend longitudinally through the stacked layers, the method further includes the following steps:

[0056] 3-1. A second trench extending to the bottom layer is formed by photolithography and etching of the stacked layers to form a support structure pattern;

[0057] 3-2. Fill the second trench with a sacrificial layer material and flatten it to serve as a penetration path for the wet etching solution; the sacrificial layer material can be an oxide, such as silicon dioxide; the etching solution can be an HF solution or VHF (vapor HF); VHF can prevent the structure from collapsing due to liquid tension.

[0058] 3-3. A first mask layer, a second mask layer, and an oxide layer are sequentially deposited on top of the stacked layers;

[0059] 3-4. Remove part of the second mask layer;

[0060] 3-5. Multiple first trenches are formed longitudinally through the stacked layers by photolithography and etching processes.

[0061] Before depositing a lower electrode on the inner surface of the first trench, the method further includes removing any remaining second mask layer.

[0062] The removal of the sacrificial layer between two adjacent electrodes includes: removing the sacrificial layer between two adjacent lower electrodes through the path of the corrosive liquid penetration.

[0063] According to one embodiment of the present invention, after etching the sacrificial layer, the dielectric layer and the upper electrode are formed, thereby completing the construction of the capacitor.

[0064] like Figure 3 As shown, another embodiment of this application provides a method for manufacturing a semiconductor capacitor structure, comprising:

[0065] S1. Provide a substrate, the substrate comprising a pad 9 formed by a plurality of spaced-apart tungsten structures.

[0066] In some embodiments, the underlying layer may include a nitride layer and a plurality of solder pads 9 spaced apart within the nitride layer. The material of the solder pads 9 is not limited to tungsten, but may also be other conductive materials, such as cobalt.

[0067] S2. Multiple mold oxide layers 1 and multiple support layers 2 are sequentially deposited on the bottom layer to form a stacked layer, such as... Figure 1 As shown.

[0068] The silicon nitride layer can be deposited in multiple layers, with the silicon nitride layer serving as the support layer 2. During subsequent LAL (Low Alloy Metal) oxide wet etching operations, the silicon nitride layer acts as the support layer. The support layer 2 can have more than three layers. The thickness of the support layer 2 is...

[0069] S3, photolithography and etching form two second trenches 3.

[0070] Specifically, photolithography and etching are performed on the stacked layer to create two second trenches 3 on the stacked layer. The second trenches 3 extend from the top surface of the stacked layer to the top surface of the bottom layer, as shown below. Figure 5 As shown.

[0071] S4. Fill the second trench 3 with oxide (the oxide being the sacrificial layer material) and level it to form a path for subsequent corrosion liquid penetration, such as... Figure 6 As shown.

[0072] The oxide can be silicon dioxide.

[0073] S5, a first mask layer 5, a second mask layer 4 and an oxide layer 6 are deposited sequentially; the oxide layer 6 is used as a sacrificial layer.

[0074] A first mask layer 5, a second mask layer 4, and an oxide layer 6 are deposited sequentially from bottom to top on the filled stacked layers.

[0075] Specifically, a first mask layer 5 is deposited on the filled stacked layers, a mask layer 4 is deposited on the first mask layer 5, and an oxide layer 6 (which may be silicon dioxide) is deposited on the second mask layer 4. Figure 7 As shown.

[0076] The mask layer can be polysilicon.

[0077] S6. Remove the oxide layer 6 and part of the second mask layer 4;

[0078] In some implementations, step S6 is achieved through photolithography and etching processes.

[0079] S7. Photolithography and etching form a plurality of first trenches 7; wherein each first trench 7 corresponds to one of the solder pads 9, and the first trench 7 extends upward from the top surface of the solder pad 9 to the top surface of the remaining second mask layer 4, as shown. Figure 8 As shown, the number of the first trenches 7 is the same as the number of the solder pads 9. The first trenches 7 expose the solder pads 9.

[0080] S8. Remove the remaining second mask layer 4, as shown. Figure 9 As shown.

[0081] The residual mask layer is removed by dry or wet etching processes.

[0082] S9. A capacitor is formed on the inner surface of the first trench 7, the capacitor including a lower electrode 8, a dielectric layer 11, and an upper electrode 12, as shown below. Figure 10 As shown.

[0083] Specifically, step S9 includes:

[0084] S91. A nitride (e.g., titanium nitride) is deposited on the inner surface of the first trench 7 to form the lower electrode 8, such as... Figure 10 As shown, the lower electrode 8 has a groove.

[0085] S92. A dielectric layer 11 is formed inside the groove of the lower electrode 8, and the dielectric layer 11 has a groove.

[0086] S93. Deposit an upper electrode 12 in the groove of the dielectric layer 11.

[0087] S10. Perform an oxide wet etching process to remove all oxide between the two adjacent lower electrodes 8, such as... Figure 11 As shown, the semiconductor capacitor structure is obtained.

[0088] For example, wet etching chemicals are penetrated between the two lower electrodes 8 to remove all oxides up to the bottom layer.

[0089] Specifically, the oxide path is located between two adjacent electrodes, and a wet etching chemical penetrates into the oxide path to remove all oxide up to the bottom.

[0090] like Figure 11 As shown, after oxide wet etching, a semiconductor capacitor structure is obtained, with residual support layer patterns for supporting electrodes. These support layer patterns improve the leaning margin. Furthermore, regarding the overall thickness of support layer 2, the original top support layer thickness is allocated and used in the lower part. This process ensures consistent storage capacitor height, preventing loss and achieving leaning margin. To prevent storage capacitor loss, the thickness of each support layer is...

[0091] The semiconductor capacitor structure manufacturing method provided in this application adds multiple support layers between two adjacent electrodes in a direction perpendicular to the bottom layer, creating a capacitor (CAP) without tilting defects. This solves the problem of the upper limit of capacitor height caused by insufficient tilt margin, obtains more etch margin, and can ensure that the capacitor height required for storage capacitor is obtained.

[0092] The semiconductor capacitor structure provided in this application embodiment has multiple support layers between two adjacent electrodes, which reduces tilt defects, solves the problem of insufficient tilt margin leading to an upper limit of capacitor (CAP) height, obtains more etch margin, and can ensure that the capacitor (CAP) height required for storage capacitor is obtained.

[0093] The above description does not provide detailed explanations of the technical aspects of each layer's patterning, etching, etc. However, those skilled in the art should understand that various technical means can be used to form layers and regions of the desired shape. Furthermore, to form the same structure, those skilled in the art can also design methods that are not entirely identical to those described above. Additionally, although various embodiments have been described above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination.

[0094] The embodiments of this disclosure have been described above. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of this disclosure. The scope of this disclosure is defined by the appended claims and their equivalents. Various substitutions and modifications can be made by those skilled in the art without departing from the scope of this disclosure, and all such substitutions and modifications should fall within the scope of this disclosure.

Claims

1. A method for manufacturing a semiconductor capacitor structure, characterized in that, include: A base layer is provided, the base layer comprising a plurality of spaced-apart pads; Multiple sacrificial layers and multiple support layers are sequentially deposited on the bottom layer to form a stacked layer, wherein each of the sacrificial layer and the support layer comprises at least three layers. A plurality of first trenches are fabricated that extend longitudinally through the stacked layers; wherein the first trenches expose the solder pads; The lower electrode of the capacitor is formed on the bottom wall and inner surface of the first trench; The sacrificial layer between two adjacent lower electrodes is completely removed to obtain a semiconductor capacitor structure. Prior to manufacturing the first trenches that extend longitudinally through the stacked layers, the method further includes: A second trench extending to the bottom layer is formed by photolithography and etching of the stacked layers, forming a support structure pattern; The second trench is filled with a sacrificial layer material, which serves as the penetration path for the subsequent formation of wet etching solution; The fabrication of a plurality of first trenches extending longitudinally through the stacked layers includes: A first mask layer and a second mask layer are sequentially deposited on top of the stacked layers; Multiple first trenches are formed longitudinally through the stacked layers using photolithography and etching processes.

2. The method according to claim 1, characterized in that, Before depositing a lower electrode on the inner surface of the first trench, the method further includes removing any remaining second mask layer.

3. The method according to claim 1, characterized in that, The removal of the sacrificial layer between two adjacent electrodes includes: removing the sacrificial layer between two adjacent electrodes through the path of the corrosive liquid penetration.

Images