Semiconductor device and method for manufacturing semiconductor device

Abstract

The present application relates to a semiconductor device and a method for manufacturing the semiconductor device. A semiconductor device includes: a first bit line extending in a first direction; a first word line extending in a second direction intersecting the first direction; a first transistor located at a first intersection of the first word line and the first bit line, the first transistor being connected to the first word line and the first bit line; a first capacitor electrically connected to the first transistor, the first capacitor being located at a first portion of the first intersection; a second capacitor electrically isolated from the first transistor, the second capacitor being located at a second portion of the first intersection; and a second transistor electrically connected to the second capacitor, the first capacitor and the second capacitor being located between the first transistor and the second transistor.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of Korean Patent Application No. 10-2020-0097001 filed on August 3, 2020, in the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present disclosure relates generally to electronic devices and, more particularly, to semiconductor devices and methods of fabricating semiconductor devices. Background Art

[0004] The integration density of semiconductor devices is primarily determined by the area occupied by a unit memory cell. As the integration density of semiconductor devices in which memory cells are formed as a single layer on a substrate has reached its limit, three-dimensional semiconductor devices have recently been proposed, in which memory cells are stacked on a substrate. Various structures and manufacturing methods have been developed to improve the operational reliability of such three-dimensional semiconductor devices. Summary of the Invention

[0005] Embodiments provide a semiconductor device having a stable structure and improved characteristics, and a method of manufacturing the semiconductor device.

[0006] According to one aspect of the present disclosure, a semiconductor device is provided, comprising: a first bit line extending in a first direction; a first word line extending in a second direction intersecting the first direction; a first transistor located at a first intersection of the first word line and the first bit line, the first transistor being connected to the first word line and the first bit line; a first capacitor electrically connected to the first transistor, the first capacitor being located at a first portion of the first intersection; a second capacitor electrically isolated from the first transistor, the second capacitor being located at a second portion of the first intersection; and a second transistor electrically connected to the second capacitor, the first capacitor and the second capacitor being located between the first transistor and the second transistor.

[0007] According to another aspect of the present disclosure, a semiconductor device is provided, comprising: a first vertical transistor arranged in a first direction and in a second direction intersecting the first direction; a second vertical transistor located on the first vertical transistor, the second vertical transistor being arranged in the first direction and the second direction; a first capacitor located between the first vertical transistor and the second vertical transistor, the first capacitor being electrically connected to the first vertical transistor; and a second capacitor located between the first vertical transistor and the second vertical transistor, the second capacitor being electrically connected to the second vertical transistor, wherein the second capacitor is arranged between the first capacitors.

[0008] According to another aspect of the present disclosure, a method for manufacturing a semiconductor device is provided, the method including: forming a first array, the first array including a first bit line extending in a first direction, a first word line extending in a second direction intersecting the first direction, and a first transistor located at a first intersection of the first word line and the first bit line, the first transistor being connected to the first word line and the first bit line; forming a first capacitor electrically connected to the first transistor, the first capacitor being located at a first portion of the first intersection; and forming a second capacitor, the second capacitor being located at a second portion of the first intersection. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Hereinafter, example embodiments will be described more fully with reference to the accompanying drawings; however, embodiments of the present disclosure may be implemented in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these example embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the example embodiments to those skilled in the art.

[0010] In the accompanying drawings, dimensions may be exaggerated for clarity. It will be understood that when an element is referred to as being "between" two elements, this element can be the only element between the two elements, or one or more intervening elements may also be present. The same reference numerals represent the same elements throughout.

[0011] Figures 1A to 1C is a view showing the structure of a semiconductor device according to an embodiment of the present disclosure.

[0012] Figure 2A and Figure 2B is a view showing the structure of a semiconductor device according to an embodiment of the present disclosure.

[0013] Figure 3A and Figure 3B is a view showing the structure of a semiconductor device according to an embodiment of the present disclosure.

[0014] Figure 4A 、 Figure 4B 、 Figure 5A 、 Figure 5B 、 6A to 6D 、 7A to 7E 、 Figures 8A to 8C 、 Figure 9A 、 Figure 9B 、 Figure 10A and Figure 10B are views illustrating a method of manufacturing a semiconductor device according to an embodiment of the present disclosure.

[0015] Figure 11A 、 Figure 11B 、 Figure 12A 、 Figure 12B 、 Figure 13A 、 Figure 13B 、 Figure 14A and Figure 14B are views illustrating a method of manufacturing a semiconductor device according to an embodiment of the present disclosure.

[0016] Figure 15A and Figure 15B are views illustrating a method of manufacturing a semiconductor device according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0017] The specific structural or functional descriptions disclosed herein are only illustrative for the purpose of describing the embodiments according to the concepts of the present disclosure. The embodiments according to the concepts of the present disclosure can be implemented in various forms and should not be interpreted as being limited to the embodiments set forth herein.

[0018] Figures 1A to 1C is a view showing the structure of a semiconductor device according to an embodiment of the present disclosure.

[0019] Reference Figures 1A to 1C , from a perspective perpendicular to a plane formed by the first direction I and the second direction II, the semiconductor device may include a bit line BL, a word line WL, a transistor TR, and a first capacitor C1.

[0020] The bit line BL may extend in a first direction I. The word line WL may extend in a second direction II intersecting the first direction I. The bit line BL and the word line WL may be located at different heights. For example, the word line WL may be located above the bit line BL or below the bit line BL.

[0021] An intersection IP may be defined in an area where the bit line BL and the word line WL intersect each other. Transistors TR may be located at the intersection IP and connected between the bit line BL and the word line WL. In an embodiment, the transistor TR may be a vertical transistor including a vertical channel layer passing through the WL or the bit line BL.

[0022] According to this structure, the bit lines BL, word lines WL, and transistors TR can form a first array. In addition, first capacitors C1 can be electrically connected to the transistors TR, respectively. The first capacitors C1 can be located at a different height than the first array. For example, the first capacitors C1 can be located above or below the first array.

[0023] The first capacitor C1 can be arranged in a first direction I and a second direction II. The first capacitor C1 is positioned relative to its corresponding intersection IP. For example, the first capacitor C1 can be displaced toward one or more sides of the intersection IP. In an embodiment, the first capacitor C1 can be displaced from the intersection IP in a positive third direction +III. The third direction III can be a direction that intersects the first direction I and the second direction II in a plane formed by the first direction I and the second direction II.

[0024] The semiconductor device may further include a second capacitor C2, which may be located between the first capacitors C1. The second capacitor C2 may be electrically isolated from the transistor TR and may be electrically connected to a transistor included in another array.

[0025] The second capacitor C2 may be arranged in the first direction I and the second direction II. The first capacitor C1 and the second capacitor C2 may be located at substantially the same height. For example, the first capacitor C1 and the second capacitor C2 may be located on a plane defined by the first direction I and the second direction II. The first capacitor C1 and the second capacitor C2 may be adjacent to each other in the third direction III.

[0026] The first capacitor C1 and the second capacitor C2 may be positioned such that the pair of first capacitors C1 and second capacitors C2 share an intersection IP. Each intersection IP may include a first portion P1 and a second portion P2. The first capacitor C1 may be located at or near the first portion P1, and a portion of the first capacitor C1 may overlap with the first portion P1. The second capacitor C2 may be located at or near the second portion P2, and a portion of the second capacitor C2 may overlap with the second portion P2.

[0027] The first portion P1 and the second portion P2 of the intersection IP may be adjacent to each other in the third direction III. The center PC of the intersection IP may be located between the first portion P1 and the second portion P2. The first center C1C of the first capacitor C1 may be positioned so as to be displaced from the center PC of the intersection IP in the positive third direction +III. The second center C2C of the second capacitor C2 may be positioned so as to be displaced from the center PC of the intersection IP in the negative third direction -III.

[0028] According to the above structure, the first capacitor C1 and the second capacitor C2 connected to different arrays can be located at substantially the same height. Therefore, the stack height of the semiconductor device can be reduced and the integration degree can be improved.

[0029] Figure 2A and Figure 2B is a view showing the structure of a semiconductor device according to an embodiment of the present disclosure. Figure 2A is a plan view, and Figure 2BShown along Figure 2A The cross section is taken along the line AA' shown in FIG. Figures 1A to 1C Description of elements that are substantially similar.

[0030] Reference Figure 2A and Figure 2B The semiconductor device may include a first array AR1, a first capacitor C1 electrically connected to the first array AR1, a second array AR2, and a second capacitor C2 electrically connected to the second array AR2. The semiconductor device may also include a first contact structure CT1 and a second contact structure CT2.

[0031] The first array AR1 may include first bit lines BL1 corresponding to the first word lines WL1, respectively. The first array AR1 may also include first transistors TR1 connecting the corresponding first bit lines BL1 and the first word lines WL1. Figure 2A In the embodiment, the first transistors TR1 may be located at first intersections IP1 of the first word line WL1 and the first bit line BL1, respectively. Each first transistor TR1 may include a first channel layer CH1. The first channel layer CH1 may pass through the first word line WL1, and the first word line WL1 may surround the sidewalls of the first channel layer CH1. In a cross-sectional view, such as in FIG. Figure 2B In the embodiment, the first transistor TR1 may be located at substantially the same height as the first word line WL1. Although not shown in the figure, the semiconductor device may further include a first gate insulating layer surrounding the first channel layer CH1. The first gate insulating layer may be interposed between the first channel layer CH1 and the first word line WL1.

[0032] The second array AR2 may include second bit lines BL2 corresponding to the second word lines WL2. The second array AR2 may also include second transistors TR2 connecting the corresponding second bit lines BL2 and the second word lines WL2. Figure 2A In the embodiment, the second transistors TR2 may be located at the second intersection IP2 of the second word line WL2 and the second bit line BL2, respectively. Each second transistor TR2 may include a second channel layer CH2. The second channel layer CH2 may pass through the second word line WL2, and the second word line WL2 may surround the sidewall of the second channel layer CH2. In a cross-sectional view, such as in Figure 2B In the embodiment, the second transistor TR2 may be located at substantially the same height as the second word line WL2. Although not shown in the figure, the semiconductor device may further include a second gate insulating layer surrounding the second channel layer CH2. The second gate insulating layer may be disposed between the second channel layer CH2 and the second word line WL2.

[0033] The first array AR1 and the second array AR2 may be stacked or arranged along a fourth direction IV. The fourth direction IV may be a direction extending from a plane defined by the first direction I and the second direction II. For example, the fourth direction IV may be a vertical direction.

[0034] The first array AR1 and the second array AR2 may have a structure in which the first array AR1 and the second array AR2 are symmetrical to each other, or a structure in which the first array AR1 and the second array AR2 are asymmetrical to each other. The first bit line BL1 and the second bit line BL2 may extend in a first direction I, and the corresponding first bit line BL1 and the second bit line BL2 may overlap in a fourth direction IV. The first word line WL1 and the second word line WL2 may extend in a second direction II, and the corresponding first word line WL1 and the second word line WL2 may overlap in a fourth direction IV. The corresponding first intersection IP1 and the second intersection IP2 may overlap in the fourth direction IV. The corresponding first transistor TR1 and the second transistor TR2 may overlap in the fourth direction IV.

[0035] The first capacitor C1 and the second capacitor C2 may be located between the first array AR1 and the second array AR2. The first capacitor C1 may be connected to the first channel layer CH1 via a first contact structure CT1. The first capacitor C1 may be electrically connected to the first transistor TR1 and may be electrically isolated from the second transistor TR2. The second capacitor C2 may be connected to the second channel layer CH2 via a second contact structure CT2. The second capacitor C2 may be electrically connected to the second transistor TR2 and may be electrically isolated from the first transistor TR1.

[0036] For ease of description, Figure 2B "C1" shown in the figure represents the configuration of the first capacitor, such as the electrodes included in the first capacitor. The first capacitor may include a cylindrical first electrode, a plate-shaped second electrode, and a dielectric layer between the first electrode and the second electrode. The first capacitor and the second capacitor may each independently include a first electrode, but may share the second electrode with each other. Therefore, "C1" may represent the first electrode of the first capacitor. Similarly, for ease of description, "C2" represents the configuration of the second capacitor, such as the first electrode included in the second capacitor.

[0037] According to the above structure, the first capacitors C1 of the first array AR1 and the second capacitors C2 of the second array AR2 can be located at substantially the same height. Therefore, the stack height of the semiconductor device can be reduced and the integration density can be improved.

[0038] Figure 3A and Figure 3B is a view showing the structure of a semiconductor device according to an embodiment of the present disclosure. Figure 3A is a plan view, and Figure 3B Shown along Figure 3A The cross section is taken along the line BB' shown in FIG. Figures 1A to 2B Description of elements that are substantially similar.

[0039] Reference Figure 3A and Figure 3B The semiconductor device may include a first array AR1, a first capacitor C1 electrically connected to the first array AR1, a second array AR2, a second capacitor C2 electrically connected to the second array AR2, a third array AR3, a third capacitor C3 electrically connected to the third array AR3, a fourth array AR4, and a fourth capacitor C4 electrically connected to the fourth array AR4. The semiconductor device may further include a first contact structure CT1, a second contact structure CT2, a third contact structure CT3, and a fourth contact structure CT4.

[0040] The third array AR3 may be located above the second array AR2 and share the second bit line BL2 with the second array AR2. The third array AR3 may include the second bit line BL2, the third word line WL3, and the third transistor TR3. The fourth array AR4 may include the third bit line BL3, the fourth word line WL4, and the fourth transistor TR4.

[0041] According to the above structure, the second array AR2 and the third array AR3 can share the second bit line BL2 with each other. Therefore, the stack height of the semiconductor device can be reduced and the integration degree can be improved.

[0042] Figure 4A 、 Figure 4B 、 Figure 5A 、 Figure 5B 、 6A to 6D 、 7A to 7E 、 Figures 8A to 8C 、 Figure 9A 、 Figure 9B 、 Figure 10A and Figure 10B are views illustrating a method of manufacturing a semiconductor device according to an embodiment of the present disclosure. Figure 4A 、 Figure 5A 、 Figure 6A 、 Figure 7A 、 Figure 8A 、 Figure 9A and Figure 10A It's the layout. Figure 4B 、 Figure 5B and Figures 6B to 6D is a cross-sectional view taken along line C-C', and Figures 7B to 7E 、 Figure 8B 、 Figure 8C 、 Figure 9B and Figure 10BIt is a cross-sectional view taken along the line D-D'. Figures 1A to 3B Description of elements that are substantially similar.

[0043] Reference Figure 4A and Figure 4B A first conductive layer 41 is formed on a substrate 40, and a first channel material layer 42 is formed on the first conductive layer 41. The substrate 40 may be a semiconductor substrate and include a lower structure such as a peripheral circuit.

[0044] The first conductive layer 41 is used to form a bit line or a word line. The first conductive layer 41 may include polysilicon, a metal such as tungsten, etc. The first conductive layer 41 may be deposited by a sputtering process, a chemical vapor deposition (CVD) process, an atomic layer deposition (ALD) process, etc.

[0045] The first channel material layer 42 is used to form a channel layer in which a channel of the transistor is generated. The first channel material layer 42 may include a semiconductor material such as polysilicon or silicon germanium, or may include an oxide semiconductor such as indium gallium zinc oxide (IGZO). The first channel material layer 42 may include a junction. The first channel material layer 42 may be deposited by a sputtering process, a chemical vapor deposition (CVD) process, an atomic layer deposition (ALD) process, or the like.

[0046] Reference Figure 5A and Figure 5B , forming the first bit line 41A and the first channel layer 42A. In an embodiment, the first channel material layer 42 and the first conductive layer 41 are formed by using Figure 5A , the first channel material layer 42 is patterned using a linear mask pattern extending in the first direction I. Subsequently, the first channel material layer 42 is patterned using a linear mask pattern extending in the second direction II. Thus, a first bit line 41A extending in the first direction I can be formed. In addition, a first channel layer 42A can be formed, which is located on the first bit line 41A and arranged in the first direction I and the second direction II.

[0047] Subsequently, a first gate insulating layer 43 is formed around the first channel layer 42A. The first gate insulating layer 43 may be conformally formed on the substrate 40 along the contours of the first channel layer 42A and the first bit line 41A. Subsequently, a portion of the first gate insulating layer 43 formed on the substrate 40 may be etched. The first gate insulating layer 43 may include oxide.

[0048] Reference 6A to 6D , a first word line 44A is formed, which surrounds the sidewall of the first channel layer 42A and extends in the second direction II. Hereinafter, a method of forming the first word line 44A will be described for each process.

[0049] First, refer to Figure 6A and Figure 6B A second conductive layer 44 is formed on the first gate insulating layer 43. The second conductive layer 44 can be conformally formed along the contour of the first gate insulating layer 43. The second conductive layer 44 is used to form a bit line or a word line. The second conductive layer 44 may include polysilicon, tungsten, metal, etc. The second conductive layer 44 may be deposited by a sputtering process, a chemical vapor deposition (CVD) process, an atomic layer deposition (ALD) process, etc.

[0050] Subsequently, a protection layer 45 is formed on the second conductive layer 44. The protection layer 45 may be conformally formed along the contour of the second conductive layer 44. The protection layer 45 may include a material having an etching selectivity relative to the second conductive layer 44. The protection layer 45 may include an insulating material such as oxide or nitride.

[0051] Reference Figure 6A and Figure 6C , a protection pattern 45A is formed by etching the protection layer 45 to partially expose the second conductive layer 44. The protection pattern 45A may be formed to surround the sidewalls of the first channel layer 42A. In an embodiment, the protection pattern 45A may be formed by etching the protection layer 45 through an anisotropic etching process. The anisotropic etching process may be a dry etching process. Therefore, a portion of the protection layer 45 corresponding to the upper surface and sidewalls of the first channel layer 42A and the upper surface of the first bit line 41A may be etched. In addition, a portion of the second conductive layer 44 corresponding to the upper surface and sidewalls of the first channel layer 42A and the upper surface of the first bit line 41A may be exposed.

[0052] Reference Figure 6A and Figure 6D The second conductive layer 44 is etched using the protection pattern 45A as an etch barrier. Thus, a first word line 44A extending in the second direction II is formed, and a first transistor is formed at a portion where the first channel layer 42A and the first word line 44A intersect each other.

[0053] Subsequently, an interlayer insulating layer 46 is formed. In an embodiment, after forming an insulating material to fill the space between the first word lines 44A, the insulating material is planarized until the upper surface of the first gate insulating layer 43 is exposed. The interlayer insulating layer 46 may include an insulating material such as oxide.

[0054] Thus, a first array including the first bit line 41A, the first word line 44A, and the first transistor may be formed.

[0055] Reference 7A to 7E , forming the first electrode layer 57 of the first capacitor and the first electrode layer 58 of the second capacitor. Hereinafter, a method of forming the first electrode layers 57 and 58 will be described for each process.

[0056] Reference Figure 7A and Figure 7B A sacrificial structure SC of the capacitor is formed on the interlayer insulating layer 46 and the first gate insulating layer 43. The sacrificial structure SC may include at least one capping layer and at least one sacrificial layer alternately stacked. The sacrificial layer may include a material having a higher etching selectivity than the capping layer. In an embodiment, the capping layer may include a nitride-based material, and the sacrificial layer may include an oxide-based material. 7A to 7E is a representative diagram, and the numbers of capping layers and sacrificial layers included in the sacrificial structure SC may vary in other embodiments.

[0057] In an embodiment, the sacrificial structure SC is formed by forming a first capping layer 51, a first sacrificial layer 52, a second capping layer 53, a second sacrificial layer 54, and a third capping layer 55 on the interlayer insulating layer 46 and the first gate insulating layer 43. The first capping layer 51, the second capping layer 53, or the third capping layer 55 can serve as a support in subsequent processes or can serve as an etch stop layer. The first capping layer 51, the second capping layer 53, or the third capping layer 55 may include a nitride. The first sacrificial layer 52 and the second sacrificial layer 54 are used to secure the positions of the electrodes to be formed for the first and second capacitors, and may include an oxide.

[0058] Reference Figure 7A and 7C , forming first openings OP1 through the sacrificial structure. Each first opening OP1 may be formed to have a depth such that the first opening OP1 passes through the third capping layer 55, the second sacrificial layer 54, the second capping layer 53, the first sacrificial layer 52, and the first capping layer 51. The first opening OP1 may be used to form a first electrode layer of the first capacitor. The first gate insulating layer 43 may be exposed through the first opening OP1, and the interlayer insulating layer 46 may be further exposed.

[0059] Subsequently, a second opening OP2 exposing the first channel layer 42A is formed by selectively etching the first gate insulating layer 43. The second opening OP2 may be connected to the first opening OP1 and may be used to form a first contact structure connecting the first capacitor and the first transistor.

[0060] Reference Figure 7A and Figure 7D , forming a first contact structure 56 in the second opening OP2 and a first electrode layer 57 in the first opening OP1. In an embodiment, the first contact structure 56 and the first electrode layer 57 may be a single layer. The first contact structure 56 and the first electrode layer 57 may include the same material.

[0061] After forming a conductive material in the first and second openings OP1 and OP2, a first electrode layer 57 and a first contact structure 56 may be formed by planarizing the conductive material until the third capping layer 55 is exposed. The first contact structure 56 may pass through the first gate insulating layer 43 and be electrically connected to the first channel layer 42A. The first electrode layer 57 may be electrically connected to the first channel layer 42A through the first contact structure 56.

[0062] The first contact structure 56 or the first electrode layer 57 may include a conductive material such as a metal, a metal compound, or polysilicon. In embodiments, the first contact structure 56 or the first electrode layer 57 may include iridium (Ir), ruthenium (Ru), rhodium (Rh), palladium (Pd), aluminum (Al), silver (Ag), platinum (Pt), titanium (Ti), tantalum (Ta), tungsten (W), aluminum nitride (AlNx), titanium nitride (TiNx), tantalum nitride (TaNx), tungsten nitride (WNx), or doped polysilicon, or a combination thereof.

[0063] The first contact structure 56 and the first electrode layer 57 can be formed by separate processes. In an embodiment, the first contact structure 56 can be formed before the sacrificial structure SC is formed. After forming the second opening OP2 through the first gate insulating layer 43 and exposing the first channel layer 42A, the first contact structure 56 is formed in the second opening OP2. Subsequently, the sacrificial structure SC is formed. In another embodiment, the first contact structure 56 can be formed before the first sacrificial layer 52 is formed. After forming the second opening OP2 through the first cap layer 51 and the first gate insulating layer 43 and exposing the first channel layer 42A, the first contact structure 56 is formed in the second opening OP2. Subsequently, the remaining portion of the sacrificial structure SC is formed by forming the first sacrificial layer 52, the second cap layer 53, the second sacrificial layer 54, and the third cap layer 55. Subsequently, the first opening OP1 can be formed to have a depth such that the first opening OP1 passes through the sacrificial structure SC and exposes the first contact structure 56.

[0064] Reference Figure 7A and Figure 7E , forming a third opening OP3 passing through the sacrificial structure SC. Figure 7AAs shown in , the third opening OP3 may be located between the first openings OP1. Each third opening OP3 may have a depth in which the third opening OP3 passes through the third cap layer 55, the second sacrificial layer 54, the second cap layer 53, and the first sacrificial layer 52. The third opening OP3 may be used to form a first electrode layer of a second capacitor. The second capacitor is formed to be electrically isolated from the first transistor, so that the third opening OP3 is formed to have a depth in which the third opening OP3 does not expose the first transistor. For example, the third opening OP3 may be formed to have a depth in which the third opening OP3 does not expose the first cap layer 51, exposes the first cap layer 51, or partially passes through the first cap layer 51, but in all cases, the third opening OP3 does not expose the first channel layer 42A. In an embodiment, Figure 7E A third opening OP3 exposing the top surface of the first capping layer 51 is shown.

[0065] Subsequently, a first electrode layer 58 is formed in the third opening OP3. The first electrode layer 58 may be spaced apart from the first channel layer 42A and may be electrically isolated from the first channel layer 42A. The height of the first electrode layer 58 of the second capacitor in the fourth direction IV may be substantially the same as the height of the first electrode layer 57 of the first capacitor, or may be different from the height of the first electrode layer 57 of the first capacitor. In an embodiment, the upper surface of the first electrode layer 58 and the upper surface of the first electrode layer 57 may be located at substantially the same height, and the lower surface of the first electrode layer 58 and the lower surface of the first electrode layer 57 may be located at different heights. For example, the lower surface of the first electrode layer 58 may be located at a height higher than the lower surface of the first electrode layer 57.

[0066] The first electrode layer 58 may have substantially the same material as the first electrode layer 57, or may have a different material from the first electrode layer 57. The first electrode layer 58 may include a conductive material such as a metal, a metal compound, or polysilicon. In embodiments, the first electrode layer 57 may include iridium (Ir), ruthenium (Ru), rhodium (Rh), palladium (Pd), aluminum (Al), silver (Ag), platinum (Pt), titanium (Ti), tantalum (Ta), tungsten (W), aluminum nitride (AlNx), titanium nitride (TiNx), tantalum nitride (TaNx), tungsten nitride (WNx), or doped polysilicon, or a combination thereof.

[0067] Subsequently, an interlayer insulating layer 59 is formed on the first electrode layer 58, the first electrode layer 57, and the third capping layer 55. The interlayer insulating layer 59 may include an insulating material such as oxide.

[0068] Reference Figures 8A to 8C , forming the first capacitor CAP1 and the second capacitor CAP2. The method of forming the first capacitor CAP1 and the second capacitor CAP2 will be described below for each process.

[0069] Reference Figure 8A and Figure 8B , forming a slit SL passing through the sacrificial structure SC. The slit SL serves as a path through which the first sacrificial layer 52 and the second sacrificial layer 54 are replaced with the electrode layer, and may have a depth at which the slit SL exposes the first sacrificial layer 52 and the second sacrificial layer 54. For example, in a plan view, the slit SL may have various shapes such as a circular shape, an elliptical shape, a polygonal shape, and a linear or rectangular shape.

[0070] After forming the slit SL, the first sacrificial layer 52 is removed through the slit SL to form a fifth opening OP5. The first electrode layer 57, the first electrode layer 58, the first cap layer 51, and the second cap layer 53 can be exposed through the fifth opening OP5. The second sacrificial layer 54 is removed through the slit SL to form a fourth opening OP4. The first electrode layer 57, the first electrode layer 58, the second cap layer 53, and the third cap layer 55 can be exposed through the fourth opening OP4. When the first sacrificial layer 52 is removed, the second sacrificial layer 54 can be removed, and when the fifth opening OP5 is formed, the fourth opening OP4 can be formed.

[0071] Reference Figure 8A and Figure 8C , a first dielectric layer 61 and a second electrode layer 63 may be formed in the fifth opening OP5. The first dielectric layer 61 may be formed in the fifth opening OP5, and the second electrode layer 63 may be formed on the first dielectric layer 61. The second electrode layer 63 may substantially include the same material as the first electrode layers 57 and 58, or include a material different from the first electrode layers 57 and 58. The second electrode layer 63 may include a conductive material such as a metal, a metal compound, or polysilicon. In an embodiment, the second electrode layer 63 may include iridium (Ir), ruthenium (Ru), rhodium (Rh), palladium (Pd), aluminum (Al), silver (Ag), platinum (Pt), titanium (Ti), tantalum (Ta), tungsten (W), aluminum nitride (AlNx), titanium nitride (TiNx), tantalum nitride (TaNx), tungsten nitride (WNx), or doped polysilicon, or include a combination thereof.

[0072] The second dielectric layer 62 and the third electrode layer 64 are formed in the fourth opening OP4. The second dielectric layer 62 may be formed in the fourth opening OP4, and the third electrode layer 64 may be formed on the second dielectric layer 62. When the first dielectric layer 61 is formed, the second dielectric layer 62 may be formed. The first dielectric layer 61 and the second dielectric layer 62 may include substantially the same material.

[0073] When the second electrode layer 63 is formed, the third electrode layer 64 may be formed. The third electrode layer 64 may include substantially the same material as the second electrode layer 63, or may include a material different from the second electrode layer 63. The third electrode layer 64 may include a conductive material such as a metal, a metal compound, or polysilicon. In an embodiment, the third electrode layer 64 may include iridium (Ir), ruthenium (Ru), rhodium (Rh), palladium (Pd), aluminum (Al), silver (Ag), platinum (Pt), titanium (Ti), tantalum (Ta), tungsten (W), aluminum nitride (AlNx), titanium nitride (TiNx), tantalum nitride (TaNx), tungsten nitride (WNx), or doped polysilicon, or a combination thereof.

[0074] Thus, a first capacitor CAP1 including the first electrode layer 57, the first dielectric layer 61, the second dielectric layer 62, the second electrode layer 63, and the third electrode layer 64 can be formed. A second capacitor CAP2 including the first electrode layer 58, the first dielectric layer 61, the second dielectric layer 62, the second electrode layer 63, and the third electrode layer 64 can be formed. The first capacitor CAP1 and the second capacitor CAP2 can share the second electrode layer 63 or the third electrode layer 64, or each capacitor may include the second electrode layer 63 and the third electrode layer 64.

[0075] Reference Figure 9A and Figure 9B , second contact structures 71 are formed through the interlayer insulating layer 59. The second contact structures 71 may be electrically connected to the first electrode layers 58, respectively.

[0076] Subsequently, a second channel layer 72 is formed. The second channel layer 72 can be formed by forming a second channel material layer on the interlayer insulating layer 59 and then patterning the second channel material layer. The second channel layer 72 can be formed at a position corresponding to the first channel layer 42A in the first direction I and the second direction II. The second channel layer 72 can be connected to the second contact structure 71 respectively. The second channel layer 72 can be electrically connected to the first electrode layer 58 through the second contact structure 71.

[0077] The second channel layer 72 may include substantially the same material as the first channel layer 42A, or may include a material different from the first channel layer 42A. The second channel layer 72 may include a semiconductor material such as polysilicon or silicon, or an oxide semiconductor such as indium gallium zinc oxide (IGZO). The second channel layer 72 may include a junction.

[0078] Subsequently, a second gate insulating layer 73 is formed on the second channel layer 72. The second gate insulating layer 73 may include substantially the same material as the first gate insulating layer 43, or include a material different from the first gate insulating layer 43. The second gate insulating layer 73 may include oxide.

[0079] Subsequently, a second word line 74 is formed. The second word line 74 may be formed to surround a sidewall of the second channel layer 72. The second word line 74 may be formed at a position corresponding to the first word line 44A, and the second word line 74 may extend in the second direction II.

[0080] Subsequently, an interlayer insulating layer 75 is formed. In an embodiment, after forming an insulating material to fill the spaces between the second word lines 74, the insulating material is planarized until the upper surface of the second gate insulating layer 73 is exposed. The interlayer insulating layer 75 may include an insulating material such as oxide.

[0081] Reference Figure 10A and Figure 10B , forming a second bit line 81. The second bit line 81 may be formed at a position corresponding to the first bit line 41A and may extend in the first direction I. In an embodiment, a trench may be formed by etching the interlayer insulating layer 75, and the second bit line 81 may be formed by filling the trench with a conductive material. Alternatively, a conductive material layer may be formed, the second bit line 81 may be formed by etching the conductive material layer, and the interlayer insulating layer 75 may be formed between the second bit lines 81. Thus, a second array including the second bit line 81, the second word line 74, and the second transistor may be formed.

[0082] According to the above manufacturing method, first and second capacitors CAP1 and CAP2 can be formed between the first and second arrays, sharing the second and third electrode layers 63 and 64. In addition, the first capacitor CAP1 can be electrically connected to the first array, and the second capacitor CAP2 can be electrically connected to the second array.

[0083] Figure 11A 、 Figure 11B 、 Figure 12A 、 Figure 12B 、 Figure 13A 、 Figure 13B 、 Figure 14A and Figure 14B is a view showing a method for manufacturing a semiconductor device according to an embodiment of the present disclosure. Figures 1A to 10B The elements described are the same as or similar to the description of the elements.

[0084] Reference Figure 11A and Figure 11B , a first conductive layer 91 is formed on a substrate 90 , and a first channel material layer 92 is formed on the first conductive layer 91 .

[0085] Reference Figure 12A and Figure 12BA first channel material layer 92A and a first bit line 91A are formed by etching the first channel material layer 92 and the first conductive layer 91. The first bit line 91A and the first channel material layer 92A may extend in the first direction I.

[0086] Subsequently, a gap-filling insulating layer 98 is formed to fill between the first bit lines 91A and between the first channel material layers 92A. The gap-filling insulating layer 98 may include an insulating material such as oxide.

[0087] Reference Figure 13A and Figure 13B , by etching the gap-filling insulating layer 98 and the first channel material layer 92A, a first channel layer 92B and a gap-filling insulating pattern 98A are formed. The gap-filling insulating pattern 98A may be arranged in the first direction I and the second direction II. The gap-filling insulating pattern 98A may be located between first channel layers 92B adjacent to each other in the second direction II. The gap-filling insulating pattern 98A and the first channel layer 92B may be alternately arranged along the second direction II.

[0088] Subsequently, a first gate insulating layer 93 is formed. The first gate insulating layer 93 may be formed to surround the first channel layer 92B and the gap-filling insulating pattern 98A.

[0089] Reference Figure 14A and Figure 14B , forming a first word line 94 surrounding the sidewall of the first channel layer 92B and the sidewall of the gap-filling insulating pattern 98A. The first word line 94 may extend in the second direction II. 6A to 6D The depicted embodiment forms a first word line 94 and subsequently an interlayer insulating layer 96 .

[0090] Thus, a first array including a first bit line 91A, a first word line 94 and a first transistor can be formed. 7A to 7E as well as Figures 8A to 8C The embodiment described above forms the first capacitor C1 and the second capacitor C2. Figure 9A 、 Figure 9B 、 Figure 10A and Figure 10B Alternatively, the second array may be formed according to the embodiment described. Figure 11A 、 Figure 11B 、 Figure 12A 、 Figure 12B 、 Figure 13A 、 Figure 13B 、 Figure 14A and Figure 14B The described embodiment forms a second array.

[0091] According to the above-described manufacturing method, the first channel layer 92B may be supported by the gap-filling insulating pattern 98 A. Therefore, the semiconductor device may have a stable structure during the manufacturing process.

[0092] Figure 15A and Figure 15B is a view showing a method for manufacturing a semiconductor device according to an embodiment of the present disclosure. Figures 1A to 14B The elements described are substantially the same as those described above.

[0093] Reference Figure 15A After forming the first channel layer 42A on the substrate 40, the first gate insulating layer 43, the first word line 44A and the interlayer insulating layer 46 are formed. Subsequently, the first capping layer 51 is formed on the first gate insulating layer 43 and the interlayer insulating layer 46. Figures 4A to 7B The manufacturing method is described.

[0094] Subsequently, the second opening OP2' is formed by etching the first capping layer 51 and the first gate insulating layer 43. For example, the second opening OP2' can be formed by etching the first capping layer 51 and the first gate insulating layer 43 using a mask pattern that partially exposes the first gate insulating layer 43 as an etch barrier. The second opening OP2' can have a depth at which the second opening OP2' exposes the first channel layer 42A. Subsequently, the first contact structure 56' is formed in the second opening OP2'.

[0095] Reference Figure 15B , a sacrificial structure SC is formed by forming a first sacrificial layer 52, a second capping layer 53, a second sacrificial layer 54, and a third capping layer 55. Subsequently, a first opening OP1' and a third opening OP3' are formed through the sacrificial structure SC. The first opening OP1' may be formed to have a depth at which the first opening OP1' exposes the first contact structure 56'. The third opening OP3' may be formed to have a depth at which the third opening OP3' exposes the first capping layer 51 without exposing the first channel layer 42A. When forming the third opening OP3', the first capping layer 51 may serve as an etch stop layer.

[0096] Subsequently, a first electrode layer 57' of a first capacitor is formed in the first opening OP1', and a first electrode layer 58' of a second capacitor is formed in the third opening OP3'. 8A to 10B The described manufacturing method can be applied to subsequent processes.

[0097] According to the above manufacturing method, when the first opening OP1 ′ is formed, the third opening OP3 ′ may be formed. In addition, when the first electrode layer 57 ′ is formed, the first electrode layer 58 ′ may be formed.

[0098] According to the present disclosure, transistors and capacitors are three-dimensionally stacked, so that the integration density of the semiconductor device can be improved. In addition, the semiconductor device can have a stable structure and improved reliability.

[0099] The exemplary embodiments of the present disclosure have been described in the drawings and the specification. Although specific terms are used herein, these terms are only used to illustrate the embodiments of the present disclosure. Therefore, the present disclosure is not limited to the above-described embodiments, and many modifications can be made within the spirit and scope of the present disclosure. It will be apparent to those skilled in the art that, in addition to the embodiments disclosed herein, various modifications can be made based on the technical scope of the present disclosure.

[0100] Unless otherwise defined, all terms used herein, including technical or scientific terms, have the meanings commonly understood by those skilled in the art to which this disclosure relates. Terms with definitions as defined in dictionaries should be understood so that their meanings are consistent with the context of the relevant art. Unless otherwise clearly defined in this application, terms should not be understood in an idealized or overly formal manner.

Claims

1. A semiconductor device comprising: a first bit line extending in a first direction; a first word line extending in a second direction intersecting the first direction; a first transistor located at a first intersection of the first word line and the first bit line, the first transistor being connected to the first word line and the first bit line; a first capacitor electrically connected to the first transistor, the first capacitor overlapping a first portion of the first intersection; a second capacitor electrically isolated from the first transistor, the second capacitor overlapping a second portion of the first intersection; as well as A second transistor is electrically connected to the second capacitor, the first capacitor and the second capacitor being located between the first transistor and the second transistor.

2. The semiconductor device according to claim 1, wherein The first capacitor and the second capacitor are located at substantially the same height.

3. The semiconductor device according to claim 1, wherein The first capacitor and the second capacitor are located together on a plane defined by the first direction and the second direction.

4. The semiconductor device according to claim 3, wherein The first capacitor and the second capacitor are adjacent to each other in a third direction that intersects the first direction and the second direction on a plane defined by the first direction and the second direction. The semiconductor device according to claim 1 , wherein The first transistor includes: a first channel layer passing through the first word line; and A first gate insulating layer surrounds the first channel layer.

6. The semiconductor device according to claim 5 , further comprising a gap-filling insulating pattern formed between the first channel layers adjacent to each other in the second direction, in, The first gate insulating layer surrounds the first channel layer and the gap-filling insulating pattern. 7 . The semiconductor device according to claim 5 , further comprising a first contact structure passing through the first gate insulating layer, the first contact structure connecting the first channel layer and the first capacitor.

8. The semiconductor device according to claim 1, wherein The first capacitor comprises: a second electrode layer formed on the first transistor; a third electrode layer formed on the second electrode layer; a capping layer formed between the second electrode layer and the third electrode layer; a first electrode layer passing through the third electrode layer, the cap layer, and the second electrode layer, the first electrode layer being connected to the first channel layer of the first transistor; a first dielectric layer disposed between the first electrode layer and the second electrode layer; and A second dielectric layer is disposed between the first electrode layer and the third electrode layer.

9. The semiconductor device according to claim 1, wherein An upper surface of the first capacitor and an upper surface of the second capacitor are located at substantially the same height, and a lower surface of the first capacitor and a lower surface of the second capacitor are located at different heights.

10. The semiconductor device according to claim 1, further comprising: Second bit line; as well as a second word line intersecting the second bit line, The second transistor is located at a second intersection of the second word line and the second bit line, and is connected to the second bit line and the second word line.

11. The semiconductor device according to claim 10, wherein The second transistor includes: a second channel layer passing through the second word line; and A second gate insulating layer surrounds the second channel layer.

12. The semiconductor device according to claim 11, further comprising: an interlayer insulating layer formed between the second capacitor and the second transistor; A second contact structure passes through the interlayer insulating layer, and the second contact structure connects the second channel layer and the second capacitor.

13. The semiconductor device according to claim 10, further comprising: a third word line intersecting the second bit line; a third transistor located at a third intersection of the second bit line and the third word line, the third transistor being connected to the second bit line and the third word line; a third capacitor electrically connected to the third transistor, the third capacitor overlapping a first portion of the third intersection; a fourth capacitor overlapping the second portion of the third intersection; as well as A fourth transistor is electrically connected to the fourth capacitor, the third capacitor and the fourth capacitor being located between the third transistor and the fourth transistor.

14. A semiconductor device comprising: first vertical transistors arranged in a first direction and in a second direction intersecting the first direction; a second vertical transistor located above the first vertical transistor in a vertical direction, the second vertical transistor being arranged in a first direction and a second direction; a first capacitor located between the first vertical transistor and the second vertical transistor, the first capacitor being electrically connected to the first vertical transistor; as well as a second capacitor located between the first vertical transistor and the second vertical transistor, the second capacitor being electrically connected to the second vertical transistor, wherein the second capacitor is arranged between the first capacitors, Wherein, the first capacitor and the second capacitor both include: a first electrode layer extending in the vertical direction; a second electrode layer provided between each of the first vertical transistors and each of the second vertical transistors; a third electrode layer disposed between the second electrode layer and each of the second vertical transistors, the third electrode layer being spaced apart from the second electrode layer; a first dielectric layer disposed between the first electrode layer and the second electrode layer; and A second dielectric layer is disposed between the first electrode layer and the third electrode layer.

15. The semiconductor device according to claim 14, wherein The first capacitor and the second capacitor are located at substantially the same height.

16. The semiconductor device according to claim 14, wherein The first capacitor and the second capacitor are adjacent to each other in a third direction that intersects the first direction and the second direction on a plane defined by the first direction and the second direction.

17. A method for manufacturing a semiconductor device, the method comprising: forming a first array including a first bit line extending in a first direction, a first word line extending in a second direction intersecting the first direction, and a first transistor located at a first intersection of the first word line and the first bit line, the first transistor being connected to the first word line and the first bit line; forming a first capacitor electrically connected to the first transistor, the first capacitor overlapping a first portion of the first intersection; as well as A second capacitor is formed that overlaps a second portion of the first intersection.

18. The method according to claim 17, wherein Forming the first array includes: forming the first bit line and a first channel layer located on the first bit line; forming a first gate insulating layer surrounding the first channel layer; and A first word line surrounding the first channel layer is formed on the first gate insulating layer.

19. The method according to claim 17, wherein Forming the first capacitor includes: forming a first sacrificial layer on the first array; forming a capping layer on the first sacrificial layer; forming a second sacrificial layer on the capping layer; and A first opening is formed through the second sacrificial layer, the capping layer, and the first sacrificial layer.

20. The method according to claim 19, further comprising: forming a second opening connected to the first opening, the second opening exposing the first channel layer of the first transistor; A first contact structure connected to the first channel layer is formed in the second opening.

21. The method according to claim 19, wherein Forming the first capacitor further includes: forming a first electrode layer in the first opening; forming a second opening by removing the first sacrificial layer; forming a third opening by removing the second sacrificial layer; forming a first dielectric layer in the second opening; forming a second electrode layer in the first dielectric layer; forming a second dielectric layer in the third opening; and A third electrode layer is formed in the second dielectric layer. 22 . The method according to claim 21 , wherein the third opening is formed when the second opening is formed, the second dielectric layer is formed when the first dielectric layer is formed, and the third electrode layer is formed when the second electrode layer is formed.

23. The method according to claim 19, wherein Forming the second capacitor includes: forming a first opening through the second sacrificial layer, the capping layer, and the first sacrificial layer; forming a first electrode layer in the first opening; forming a second opening by removing the first sacrificial layer; forming a third opening by removing the second sacrificial layer; forming a first dielectric layer in the second opening; forming a second electrode layer in the first dielectric layer; forming a second dielectric layer in the third opening; and A third electrode layer is formed in the second dielectric layer.

24. The method according to claim 23, wherein A bottom surface of the second opening is located between a bottom surface and a top surface of the first sacrificial layer.

25. The method of claim 17, further comprising forming a second contact structure connected to the second capacitor.

26. The method of claim 17 , further comprising forming a second array over the first capacitor and the second capacitor, wherein the second array comprises a second bit line, a second word line intersecting the second bit line, and a second transistor located at a second intersection of the second word line and the second bit line, the second transistor being connected between the second word line and the second bit line.

27. The method according to claim 26, wherein Forming the second array includes: forming a second channel layer connected to the second capacitor; forming a second gate insulating layer surrounding the second channel layer; forming the second word line surrounding the sidewall of the second channel layer on the second gate insulating layer; and The second bit line connected to the second channel layer is formed on the second word line.

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