Multi-finger gate non-volatile memory primitives

Abstract

The present disclosure relates to a multi-finger gate non-volatile memory cell. A non-volatile memory device is provided. The device includes a floating gate having a first finger and a second finger, and an active region located below the floating gate finger. A first doped region is located in the active region and laterally displaced from the first floating gate finger on a first side of the first floating gate finger. A second doped region is located in the active region and laterally displaced from the first floating gate finger on a second side of the first floating gate finger. A third doped region is located in the active region and laterally displaced from the second floating gate finger and the second doped region.

Description

Technical Field

[0001] The disclosed embodiments relate generally to semiconductor memory devices, and more particularly, to nonvolatile memories with improved programming efficiency, larger program / erase windows, and improved reliability. Background Art

[0002] Nonvolatile memory devices retain stored data even when the power is turned off. Multi-time programmable (MTP) nonvolatile memories include electrically erasable programmable read-only memory (EEPROM) and flash EEPROM. The memory device includes a memory transistor having a gate electrode separated from an active area by a dielectric layer.

[0003] Programming a memory device may result in charge being injected into the gate electrode of the memory transistor to change the threshold voltage of the transistor. Erasing the memory device may drain the injected charge from the gate electrode of the memory transistor. During programming, a high voltage may be applied to the gate and drain terminals of the memory transistor. A lower voltage may be applied to the source terminal while the substrate terminal of the memory transistor is grounded. The bias condition creates a strong vertically oriented electric field in the channel region between the source and drain of the memory transistor, causing hot electrons to be injected from the channel region near the drain through the dielectric layer into the edge portion of the gate electrode. The term "hot electron" may refer to electrons that have acquired high kinetic energy after being accelerated by a strong electric field within a semiconductor device. For a typical gate length of 0.55 μm, programming is inefficient, resulting in slow programming speeds, because only a small fraction of the electrons may acquire sufficiently high kinetic energy to be injected into the gate electrode.

[0004] During erase, a high voltage can be applied to the drain terminal while the gate electrode, source terminal, and substrate terminal are grounded. Electron-hole pairs can be generated in the drain region through band-to-band (BTB) tunneling. The generated holes can be injected from the drain region to the gate electrode through the dielectric layer. The injection of hot electrons and holes into the gate electrode during programming and erase operations can cause degradation of the dielectric layer near the drain region of the memory device, thereby shortening the device life. Therefore, there is an urgent need for an improved non-volatile memory device to overcome the above challenges. Summary of the Invention

[0005] In one aspect of the present disclosure, a nonvolatile memory device is provided. The device includes a floating gate having a first finger and a second finger. An active region may be disposed below the floating gate finger. A first doped region may be disposed in the active region and laterally displaced from the first floating gate finger on a first side of the first floating gate finger. A second doped region may be disposed in the active region and laterally displaced from the first floating gate finger on a second side of the first floating gate finger. A third doped region may be disposed in the active region and laterally displaced from the second floating gate finger and the second doped region.

[0006] In another aspect of the present disclosure, a nonvolatile memory device is provided. The device includes a floating gate having a first finger and a second finger. The first floating gate finger of the device may have a width less than or equal to the width of the second floating gate finger. A spacer structure may be disposed adjacent to a sidewall of the floating gate. An active region may be disposed below the floating gate finger. A first doped region may be disposed in the active region and laterally displaced from the first floating gate finger on a first side of the first floating gate finger. A second doped region may be disposed in the active region and laterally displaced from the first floating gate finger on a second side of the first floating gate finger. A third doped region may be disposed in the active region and laterally displaced from the second floating gate finger and the second doped region.

[0007] In another aspect of the present disclosure, a method for manufacturing a memory device is provided. The method includes providing an active region and providing a floating gate having a first finger and a second finger above the active region. A first doped region may be formed in the active region and laterally displaced from the first floating gate finger on a first side of the first floating gate finger. A second doped region may be formed in the active region and laterally displaced from the first floating gate finger on a second side of the first floating gate finger. A third doped region may be formed in the active region and laterally displaced from the second floating gate finger and the second doped region.

[0008] The embodiments described below provide many advantages. The narrow width of the first floating gate finger results in improved programming efficiency and faster programming speed because impact ionization is enhanced and the generation rate of hot electrons is increased. The small active area below the first floating gate finger results in a higher coupling ratio, which further improves programming efficiency. The improved programming efficiency results in a larger program / erase window. The term "coupling ratio" can refer to the voltage transfer capability from the coupled n-well capacitor to the floating gate. The term "floating gate" can refer to a gate electrode surrounded by an insulator. The term "program / erase window" can refer to the difference between the device threshold voltage after the program and erase cycles.

[0009] Programming can include injecting hot electrons into the first floating gate finger, while erasing can include injecting hot holes into the second floating gate finger. Because hot electrons and holes are injected into different locations of the memory device during programming and erasing, device degradation is minimized and device lifetime and reliability are increased. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The disclosed embodiments will be better understood by reading the following detailed description in conjunction with the accompanying drawings:

[0011] Figure 1A is a top view of a nonvolatile memory device according to an embodiment of the present disclosure.

[0012] Figure 1B is a circuit diagram of a nonvolatile memory device according to an embodiment of the present disclosure.

[0013] Figure 1C According to the embodiment of the present disclosure Figure 1A 1 is a cross-sectional view of the memory transistor taken along the section line AA'.

[0014] Figure 1D According to the embodiment of the present disclosure Figure 1A FIG. 5 is a cross-sectional view of the n-well capacitor taken along the section line BB′.

[0015] Figure 2 is a schematic diagram of a nonvolatile memory device according to an embodiment of the present disclosure.

[0016] Figure 3 is a top view of a nonvolatile memory device array according to an embodiment of the present disclosure.

[0017] Figure 4 is a top view of a nonvolatile memory device array according to an embodiment of the present disclosure, showing a portion of the active region below the floating gate.

[0018] Figure 5 is a top view of a nonvolatile memory device array according to other embodiments of the present disclosure, showing a portion of an active region below a floating gate.

[0019] Figure 6 is a top view of a nonvolatile memory device array according to other embodiments of the present disclosure, showing a portion of an active region below a floating gate.

[0020] 7A to 9A The embodiment according to the present disclosure is shown Figure 1C The manufacturing process flow of the memory transistor is shown.

[0021] Figures 7B to 9B The embodiment according to the present disclosure is shown Figure 1D The manufacturing process flow of the n-well capacitor is shown.

[0022] Figure 10A and 10B Other embodiments according to the present disclosure are shown Figure 5The manufacturing process flow of the non-volatile memory device array is shown.

[0023] Figure 11A and 11B Other embodiments according to the present disclosure are shown Figure 6 The manufacturing process flow of the non-volatile memory device array is shown.

[0024] For simplicity and clarity of illustration, the drawings illustrate general construction methods, and specific descriptions and details of well-known features and technologies may be omitted to avoid unnecessary confusion in the discussion of the embodiments of the described devices. In addition, the elements in the drawings are not necessarily drawn to scale. For example, the dimensions of some elements in the drawings may be exaggerated relative to other elements to help improve understanding of the embodiments of the device. The same reference numerals in different drawings represent the same elements, and similar reference numerals may, but do not necessarily, represent similar elements. DETAILED DESCRIPTION

[0025] The following detailed description is exemplary in nature and is not intended to limit the device or its application and uses. Furthermore, no one is bound by any theory presented in the preceding background of these devices or the following detailed description.

[0026] Figure 1A 1 is a top view of a nonvolatile memory device 100 according to an embodiment of the present disclosure. The nonvolatile memory device 100 may be an MTP EEPROM device. Figure 1A, the non-volatile memory device 100 may include a memory transistor 118 connected to an n-well capacitor 120. The memory transistor 118 may include a floating gate 190 having at least two floating gate fingers 132 and 138 located above an active region 110. The floating gate 190 may be made of a conductive material such as doped polysilicon. Doped regions may be formed in the active region 110. For example, a first doped region 162 may be formed in a portion of the active region 110 that is adjacent to the portion of the active region 110 below the first floating gate finger 132. A second doped region 166 may be formed in another portion of the active region 110 that is between the first floating gate finger 132 and the portion of the active region 110 below the second floating gate finger 138. A third doped region 168 may be formed in a portion of the active region 110 that is adjacent to the portion of the active region 110 below the second floating gate finger 138. The third doped region 168 and the second doped region 166 may be formed on different sides of the second floating gate finger 138. Contact 18 may be formed on the first doped region 162 and may be connected to a bit line. In an embodiment, the first doped region 162 may be the drain of the memory transistor 118. Contacts 20 and 22 may be formed on the second doped region 166 and the third doped region 168, respectively. Contact 20 may be connected to a first source line and contact 22 may be connected to a second source line. The second and third doped regions 166 and 168 may be the first source and the second source of the memory transistor 118, respectively. The first, second, and third doped regions 162, 166, and 168 may be connected to separate input terminals for independently controlling the drain, the first source, and the second source of the memory transistor 118.

[0027] The width x1 of the first floating gate finger 132 may be less than or equal to the width x2 of the second floating gate finger 138. The first floating gate finger 132 and the second floating gate finger 138 may be connected to a portion of the floating gate 136 that constitutes an electrode of the n-well capacitor 120. An n-well region 112 may be disposed below the floating gate portion 136. Doped regions 152 or 156 in the n-well region 112 may be formed in a portion of the n-well region 112 that is adjacent to the portion of the n-well region located below the floating gate portion 136. Doped regions 152 or 156 may be connected to separate input terminals from the first, second, and third doped regions 162, 166, and 168 in the active region 110. Contacts 26 may be formed on the doped regions 152 and may be connected to the input terminals to bias the floating gate 190.

[0028] In an embodiment, the active region 110 may be p-doped. The first, second, and third doped regions 162, 166, and 168 in the active region 110 may be n+ doped. The doped region 152 or 156 in the n-well region 112 may be n+ doped.

[0029] Figure 1B 1 is a circuit diagram of a nonvolatile memory device 100 according to an embodiment of the present disclosure. Figure 1B , the memory device 100 may include a memory transistor 118 connected to an n-well capacitor 120. The memory transistor 118 may include a first transistor 118a having a first floating gate finger 132 and a second transistor 118b having a second floating gate finger 138. The first floating gate finger 132 and the second floating gate finger 138 may be electrically connected to a portion of a floating gate 136 that constitutes an electrode of the n-well capacitor 120. The first transistor 118a and the second transistor 118b may share a first source. Contacts 18, 20, 22, and 26 may be connected to separate input terminals to provide independent control of the drain, first source, second source, and floating gate of the memory transistor 118, respectively.

[0030] Figure 1C According to the embodiment of the present disclosure Figure 1A The cross-sectional view of the memory transistor 118 is taken along the section line AA'. Figure 1C Memory transistor 118 may include dielectric layers 128 and 130 located between floating gate finger 132 and active region 110 and between floating gate finger 138 and active region 110, respectively. Dielectric layers 128 and 130 may be made of silicon dioxide. Spacer structure 102 may be formed adjacent to sidewalls of floating gate fingers 132 and 138. Active region 110 may be formed in semiconductor substrate 108. Isolation structures 116 and 106 may be formed adjacent to active region 110 to thereby define the area of ​​active region 110. Isolation structures 116 and 106 may be shallow trench isolation (STI) structures.

[0031] Figure 1D According to the embodiment of the present disclosure Figure 1A The cross-sectional view of the n-well capacitor 120 is taken along the section line BB'. Figure 1D A dielectric layer 158 may be formed between floating gate portion 136 and n-well region 112. Dielectric layer 158 may be made of silicon dioxide. Spacer structure 102 may be formed adjacent to the sidewalls of floating gate portion 136. N-well region 112 may be formed in semiconductor substrate 108. Isolation structure 170 may be formed adjacent to n-well region 112 to thereby define the area of ​​n-well region 112. Isolation structure 170 may be an STI structure.

[0032] Figure 2 FIG is a schematic diagram of a nonvolatile memory device 100 according to an embodiment of the present disclosure. Figure 2Isolation structure 176 can separate active region 110 from n-well region 112. Isolation structure 176 can be an STI structure. Line 178 indicates electrical connections between first floating gate finger 132, second floating gate finger 138, and floating gate portion 136.

[0033] Table 1

[0034]

[0035] Table 1 shows the Figure 2 An exemplary set of bias conditions for nonvolatile memory device 100 is shown. During programming, a bias of approximately 9V may be applied to n-well capacitor 120 via doped region 156. A bias of approximately 9V may be applied to the drain or first doped region 162 of memory transistor 118. A bias of approximately 4V may be applied to the first source or second doped region 166 of memory transistor 118. The second source or third doped region 168 of memory transistor 118 is unselected or floating. Active region 110 may be grounded. The bias conditions create a strong vertically oriented electric field in the channel region between first source 166 and drain 162 of memory transistor 118. Hot electrons may be generated by impact ionization and injected into edge portions of first floating gate fingers 132 near drain 162. The narrow width of first floating gate fingers 132 results in improved hot electron generation and better programming efficiency. First floating gate fingers 132 may have a width ranging from approximately 10 nm to approximately 10 μm.

[0036] During erase, a bias of approximately 9V can be applied to the second source 168 of the memory transistor 118. The drain 162 of the memory transistor 118 is unselected or floating. The n-well capacitor 120, the first source 166, and the active region 110 can be grounded. The bias conditions generate electron-hole pairs near the second source 168 through BTB tunneling. The generated holes are injected into the edge portion of the second floating gate finger 138 near the second source 168 region. Because hot electrons and holes are injected into different portions of the memory transistor 118 during programming and erase operations, the reliability and device life of the memory transistor 118 are improved.

[0037] During a read operation, a bias between 0 and 3.5 V can be applied to n-well capacitor 120. A bias of approximately 1.2 V can be applied to second source 168 of memory transistor 118. Drain 162 of memory transistor 118 is unselected or floating. First source 166 of memory transistor 118 and active area 110 can be grounded. Depending on the threshold voltage value of memory transistor 118, current can be detected at second source 168 of memory transistor 118. For example, after an erase operation, the threshold voltage of memory transistor 118 is low, and current can be detected at second source 168 of memory transistor 118. A programming operation may result in a high threshold voltage of memory transistor 118, and low or negligible current may be detected at second source 168 of memory transistor 118. A read operation detects current generated in the channel region beneath second floating gate finger 138. The longer width of second floating gate finger 138 reduces leakage current and improves readout during a read operation. The second floating gate finger 138 may have a width in a range of about 10 nm to about 10 μm.

[0038] Figure 3 is a top view of a nonvolatile memory device array 100 according to an embodiment of the present disclosure. There are no minimum design rule restrictions for MTP devices, and therefore, the area of ​​a nonvolatile memory device array 100 including memory transistors 118 having first and second sources 166 and 168, respectively, may be only approximately 20% larger than an array including memory transistors having a single source. The term "minimum design rule" may refer to the minimum separation between device features. Reference Figure 3 Although not shown, contact 20 may be connected to the first source line, and contact 22 may be connected to the second source line. Contact 18 may be connected to the bit line. Contact 26 may be connected to an input terminal to bias the floating gate.

[0039] Figure 4 FIG1 is a top view of a nonvolatile memory device array 100 according to an embodiment of the present disclosure, showing a portion of the active region 110 below the floating gate 190. Due to the higher coupling ratio, the nonvolatile memory device 100 has improved programming efficiency. Since only the first transistor 118a is selected, the coupling ratio of the nonvolatile memory device 100 is equal to A during the programming operation. C0 / (A TP +A C0 ). A C0 A refers to the area of ​​portion 186 of n-well region 112 located below floating gate portion 136. TP A refers to the area of ​​the portion 180 of the active region 110 located below the first floating gate finger 132. TP Less than AC0 , whereby the programming coupling ratio can be in the range of about 60% to about 80%, which is an improvement of about 20% to 30% compared to conventional nonvolatile memory devices. Figure 4 The sum of the width x1 of the first floating gate finger 132 and the width x2 of the second floating gate finger 138 is smaller than the width x3 of the floating gate portion 136 .

[0040] Figure 1 to Figure 4 The embodiments shown may be modified to form alternative embodiments without departing from the scope of the present disclosure. For example, Figure 5 FIG1 is a top view of a nonvolatile memory device array 200 according to another embodiment of the present disclosure, showing a portion of the active region 210 below the floating gate 190. Figure 4 The same reference numerals used in Figure 5 are used to indicate the same features. Figure 4 In contrast to the nonvolatile memory device array 100 shown, the active area 210 has a varying width along its length. For example, a portion 280 of the active area 210 located below the first floating gate finger 132 has a first width w1 that is smaller than its second width w2. Figure 4 The portion 180 of the nonvolatile memory device 100 shown is small in area, resulting in a larger programming coupling ratio and higher programming efficiency. Although not shown, an isolation structure may be formed adjacent to the active region 210 to define the active region 210.

[0041] Figure 6 FIG. 1 is a top view of a nonvolatile memory device array 300 according to another embodiment of the present disclosure, showing a portion of an active region 310 below a floating gate 190. Figure 6 , the width y1 of the portion 380 of the active area 310 located below the first floating gate finger 132 is narrower than the width y2 of the portion 182 of the active area 310 located below the second floating gate finger 138. The area of ​​the portion 380 of the nonvolatile memory device 300 is smaller than Figure 5 The area of ​​portion 280 of the non-volatile memory device 200 is shown, resulting in a larger programming coupling ratio and higher programming efficiency.

[0042] 7A to 9A The embodiment according to the present disclosure is shown Figure 1C The manufacturing process flow of memory transistor 118 is shown. Figure 7A is a cross-sectional view of a partially completed memory transistor 118 according to an embodiment of the present disclosure. Figure 7A, a semiconductor substrate 108 is provided. In an embodiment, the semiconductor substrate 108 may be p-doped. Isolation structures 116 and 106 may be formed in the substrate 108. Formation of the isolation structures 116 and 106 may include etching isolation trenches in the substrate 108 and filling the isolation trenches with a suitable dielectric material, such as silicon dioxide. An active region 110 may be formed in the substrate 108 between the isolation structures 116 and 106. Formation of the active region 110 may include doping with a suitable p-type dopant, such as boron, followed by activation annealing.

[0043] Figures 7B to 9B The embodiment according to the present disclosure is shown Figure 1D The manufacturing process flow of the n-well capacitor 120 is shown. Figure 7B is a cross-sectional view of a partially completed n-well capacitor 120 according to an embodiment of the present disclosure. Figure 7B , an isolation structure 170 may be formed in the substrate 108. An n-well region 112 may be formed in the substrate 108 adjacent to the isolation structure 170. The formation of the n-well region 112 may include doping with a suitable n-type dopant such as phosphorus or arsenic.

[0044] Figure 8A is a cross-sectional view of a partially completed memory transistor 118 after forming a floating gate 190 according to an embodiment of the present disclosure. Figure 8A A dielectric layer may be formed over active area 110. A floating gate layer comprising a doped polysilicon layer may be deposited over the dielectric layer. The floating gate layer may be patterned to form a floating gate 190 having at least two fingers 132 and 138 located over active area 110. A wet or dry etching process may be used to remove portions of the dielectric layer not covered by floating gate 190, leaving dielectric layers 128 and 130 beneath floating gate fingers 132 and 138, respectively.

[0045] Figure 8B is a cross-sectional view of a partially completed n-well capacitor 120 after forming a floating gate 190 according to an embodiment of the present disclosure. Figure 8B A dielectric layer may be formed on n-well region 112 and a floating gate layer may be deposited on the dielectric layer. The formation of the dielectric layer and the floating gate layer over n-well region 112 of n-well capacitor 120 and active area 110 of memory transistor 118 may be completed simultaneously. The floating gate layer may be patterned to form floating gate portion 136. Portions of the dielectric layer not covered by floating gate portion 136 may be removed to leave dielectric layer 158 below floating gate portion 136.

[0046] Figure 9Ais a cross-sectional view of the memory transistor 118 after forming the doped regions 162, 166, and 168 and the spacer structure 102 according to an embodiment of the present disclosure. Figure 9A , spacer structures 102 may be formed adjacent to sidewalls of floating gate fingers 132 and 138. Formation of spacer structures 102 may include depositing a suitable spacer dielectric layer, such as silicon nitride, silicon dioxide, silicon oxynitride, silicon oxycarbonitride, or any other suitable dielectric material, over floating gate fingers 132 and 138, followed by an anisotropic etch. The term "anisotropic etch" may refer to an etching process that is directional in nature. A first doped region 162 may be formed in a portion of active area 110 that is adjacent to the portion of active area 110 below first floating gate finger 132, and a second doped region 166 may be formed in another portion of active area 110 that is between the first floating gate finger 132 and the portion of active area 110 below second floating gate finger 138. A third doped region 168 may be formed in a portion of active area 110 that is adjacent to the portion of active area 110 below second floating gate finger 138. The third doped region 168 and the second doped region 166 may be formed on different sides of the second floating gate finger 138. The first doped region 162, the second doped region 166, and the third doped region 168 may be formed by doping with a suitable n+ dopant, such as phosphorus or arsenic. Due to the doping process, portions of the first doped region 162 and the second doped region 166 may partially overlap with the first floating gate finger 132. Portions of the third doped region 168 may partially overlap with the second floating gate finger 138.

[0047] Figure 9B is a cross-sectional view of n-well capacitor 120 after forming doped regions 152 and 156 and spacer structure 102. Spacer structure 102 of n-well capacitor 120 may be formed along with spacer structure 102 of memory transistor 118. Doped regions 152 and 156 of n-well capacitor 120 are formed in portions of n-well region 112 adjacent to portions of n-well region 112 underlying floating gate portion 136 and may be formed along with doped regions 162, 166, and 168 of memory transistor 118.

[0048] Figure 10A and Figure 10B Other embodiments according to the present disclosure are shown Figure 5 The manufacturing process flow of the non-volatile memory device array 200 is shown. Figure 10A FIG. 2 shows a partially completed nonvolatile memory device array 200 after forming active regions 210 and n-well regions 112 according to an embodiment of the present disclosure. Figure 10A, a semiconductor substrate 108 is provided. An isolation structure 270 may be formed in the semiconductor substrate 108, as shown by the dashed outline. An active region 210 and an n-well region 112 may be formed in the semiconductor substrate 108 and surrounded by the isolation structure 270. A portion of the isolation structure 270 having a varying width along its length may separate the active region 210 and the n-well region 112. A width L1 of the portion of the isolation structure 270 may be wider than a width L2 of the portion of the isolation structure. The isolation structure 270 thus defines the area of ​​the active region 210 and the n-well region 112.

[0049] Figure 10B 1 shows the nonvolatile memory device array 200 after forming the memory transistor 218 and the n-well capacitor 120 according to an embodiment of the present disclosure. Figure 10B The isolation structure 270 and the semiconductor substrate 108 are not shown. The formation of the memory transistor 218 may follow Figure 8A and Figure 9A The formation of the n-well capacitor 120 can follow the manufacturing process flow shown in FIG. Figure 8B and Figure 9B The manufacturing process flow is shown. Figure 10B A floating gate 190 having at least two fingers 132 and 138 may be formed over the active region 210. A floating gate portion 136 connecting the floating gate fingers 132 and 138 may be formed over the n-well region 112. A first doped region 162 may be formed in a portion of the active region 210 that is adjacent to the portion of the active region 210 below the first floating gate finger 132. A second doped region 166 may be formed in a portion of the active region 210 that is between the first floating gate finger 132 and the portion of the active region 210 below the second floating gate finger 138. A third doped region 168 may be formed in a portion of the active region 210 that is adjacent to the portion of the active region 210 below the second floating gate finger 138. The third doped region 168 and the second doped region 166 may be formed on different sides of the second floating gate finger 138. Doped regions 152 and 156 may be formed in a portion of n-well region 112 that is adjacent to the portion of n-well region 112 below floating gate portion 136. Contacts 18, 20, and 22 may be formed on first doped region 162, second doped region 166, and third doped region 168, respectively. Contact 26 may be formed on n-well region 112. The formation of contacts 18, 20, 22, and 26 is well known in the art and will not be described in further detail.

[0050] Figure 11A and 11B Other embodiments according to the present disclosure are shown Figure 6 The manufacturing process flow of the non-volatile memory device array 300 is shown. Figure 11AFIG. 3 shows a partially completed nonvolatile memory device array 300 after forming active regions 310 and n-well regions 112 according to an embodiment of the present disclosure. Figure 11A , a semiconductor substrate 108 is provided. An isolation structure 370 may be formed in the semiconductor substrate 108. An active region 310 and an n-well region 112 may be formed in the semiconductor substrate 108 and surrounded by the isolation structure 370. A portion of the isolation structure 370 having a width L1 may separate a central portion of the active region 310 from the n-well region 112. A portion of the isolation structure 370 having a width L2 narrower than L1 may separate an upper portion and a lower portion of the active region 310 from the n-well region 112. The central portion of the active region 310 may be narrower than the upper portion and the lower portion of the active region 310.

[0051] Figure 11B 1 shows a nonvolatile memory device array 300 after forming memory transistors 318 and n-well capacitors 120 according to an embodiment of the present disclosure. Figure 11B The substrate 108 and the isolation structure 370 are not shown. The formation of the memory transistor 318 may follow Figure 8A and Figure 9A The formation of the n-well capacitor 120 can follow the manufacturing process flow shown in FIG. Figure 8B and Figure 9B The manufacturing process flow is shown. Figure 11B A floating gate 190 having at least two fingers 132 and 138 may be formed over the active region 310. A floating gate portion 136 connecting the floating gate fingers 132 and 138 may be formed over the n-well region 112. A first doped region 162 may be formed in a portion of the active region 310 that is adjacent to the portion of the active region 310 below the first floating gate finger 132. A second doped region 166 may be formed in a portion of the active region 310 that is between the first floating gate finger 132 and the portion of the active region 310 below the second floating gate finger 138. A third doped region 168 may be formed in a portion of the active region 310 that is adjacent to the portion of the active region 310 below the second floating gate finger 138. The third doped region 168 and the second doped region 166 may be formed on different sides of the second floating gate finger 138. Doped regions 152 and 156 may be formed in a portion of n-well region 112 that is adjacent to the portion of n-well region 112 below floating gate portion 136. Contacts 18, 20, and 22 may be formed on first doped region 162, second doped region 166, and third doped region 168, respectively. Contact 26 may be formed on n-well region 112.

[0052] The terms "first", "second", "third", etc. (if any) in the description and claims are used to distinguish between similar elements and are not necessarily used to describe a particular order or chronological sequence. It should be understood that the terms used in this way are interchangeable where appropriate so that embodiments of the devices described herein can, for example, be operated in an order other than the order shown or otherwise described herein. The terms "left", "right", "front", "rear", "top", "bottom", "above", "below", etc. (if any) in the description and claims are used for descriptive purposes only and are not necessarily used to describe permanent relative positions. It should be understood that the terms used in this way are interchangeable where appropriate so that embodiments of the devices described herein can, for example, be operated in an orientation other than the orientation shown or otherwise described herein. Similarly, if the method described herein includes a series of steps, the order of the steps presented herein is not necessarily the only order in which the steps can be performed, some of the steps may be omitted and / or some other steps not described herein may be added to the method. Furthermore, the terms "comprises," "comprising," "including," "having," and any variations thereof are intended to cover a non-exclusive inclusion such that a process, method, article, or apparatus that comprises a list of elements is not necessarily limited to those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus.

[0053] Although several exemplary embodiments have been presented in the above detailed description of the device, it should be understood that many variations exist. It should be further understood that the embodiments are merely examples and are not intended to limit the scope, applicability, size, or configuration of the device in any way. Rather, the above detailed description will provide those skilled in the art with a convenient guide to implementing exemplary embodiments of the device, and it will be understood that various changes may be made to the function and arrangement of the elements described in the exemplary embodiments and their methods of manufacture without departing from the scope of the present disclosure as set forth in the appended claims.

Claims

1. A nonvolatile memory device comprising: a floating gate having a first floating gate finger and a second floating gate finger; an active region underlying the first floating gate finger and the second floating gate finger, wherein a portion of the active region underlying the first floating gate finger has a narrower width than a portion of the active region underlying the second floating gate finger; a first doped region located in the active area and laterally displaced from the first floating gate finger on a first side of the first floating gate finger; a second doped region located in the active area and laterally displaced from the first floating gate finger on a second side of the first floating gate finger; and A third doped region is located in the active area and is laterally displaced from the second floating gate fingers and the second doped region.

2. The nonvolatile memory device according to claim 1, wherein: The first floating gate finger has a smaller width than the second floating gate finger.

3. The nonvolatile memory device according to claim 1, wherein: The first doping region, the second doping region, and the third doping region are connected to separate input terminals.

4. The nonvolatile memory device according to claim 1, wherein: The portion of the active region below the first floating gate finger has a first width that is less than a second width.

5. The nonvolatile memory device according to claim 1 , further comprising: A capacitor includes a portion of the floating gate connected to the first floating gate finger and the second floating gate finger.

6. The nonvolatile memory device according to claim 5, further comprising: An n-well region is located below the floating gate portion.

7. The nonvolatile memory device according to claim 6, further comprising: a doped region in the n-well region and laterally displaced from the floating gate portion, wherein the doped region in the n-well region is connected to separate input terminals from the first, second, and third doped regions in the active area.

8. The nonvolatile memory device according to claim 1, wherein: The active region is p-doped.

9. The nonvolatile memory device according to claim 6, further comprising: An isolation structure separates the active region from the n-well region.

10. The nonvolatile memory device according to claim 8, wherein: The first doping region, the second doping region and the third doping region are n+ doped.

11. The nonvolatile memory device according to claim 7, wherein: The doped region in the n-well region is n+ doped.

12. The nonvolatile memory device according to claim 1, further comprising: A dielectric layer is located between the first floating gate finger, the second floating gate finger and the active area.

13. The nonvolatile memory device according to claim 6, further comprising: A dielectric layer is located between the floating gate portion and the n-well region.

14. A non-volatile memory device comprising: a floating gate having a first floating gate finger and a second floating gate finger, wherein the first floating gate finger has a width less than or equal to a width of the second floating gate finger; a spacer structure adjacent to a sidewall of the floating gate; an active region underlying the first floating gate finger and the second floating gate finger, wherein a portion of the active region underlying the first floating gate finger has a narrower width than a portion of the active region underlying the second floating gate finger; a first doped region located in the active area and laterally displaced from the first floating gate finger on a first side of the first floating gate finger; a second doped region located in the active area and laterally displaced from the first floating gate finger on a second side of the first floating gate finger; and A third doped region is located in the active area and is laterally displaced from the second floating gate fingers and the second doped region.

15. The nonvolatile memory device according to claim 14, further comprising: A capacitor includes a portion of the floating gate connected to the first floating gate finger and the second floating gate finger.

16. The nonvolatile memory device according to claim 15, wherein: A sum of a width of the first floating gate finger and a width of the second floating gate finger is smaller than a width of the floating gate portion.

17. A method of manufacturing a non-volatile memory device, comprising: providing an active area; providing a floating gate having a first floating gate finger and a second floating gate finger over the active area, wherein a portion of the active area below the first floating gate finger has a narrower width than a portion of the active area below the second floating gate finger; forming a first doped region in the active area at a first side of the first floating gate finger and laterally displaced from the first floating gate finger; forming a second doped region in the active area at a second side of the first floating gate finger laterally displaced from the first floating gate finger; and A third doped region is formed in the active area laterally displaced from the second floating gate fingers and the second doped region.

18. The method according to claim 17, wherein: Providing an active area also includes: providing a substrate; forming an isolation structure in the substrate; and An active region is formed in the substrate adjacent to the isolation structure.

19. The method according to claim 18, wherein Providing a floating gate having a first floating gate finger and a second floating gate finger over the active area further comprises: forming a floating gate layer over the active area; and The floating gate layer is patterned to form a floating gate having a first floating gate finger and a second floating gate finger over the active area.

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