Package structure and method of manufacturing the same

Abstract

The application provides a packaging structure and a manufacturing method thereof. The packaging structure includes a first chip, a second chip, a mold encapsulation, a blocking structure, a light-transmissive sheet, a conductive connecting piece, a circuit layer, and a conductive terminal. The first chip includes a first active surface. The first active surface has a sensing area. The second chip is configured in a manner that a second back surface thereof faces the first chip. The mold encapsulation covers the second chip. The mold encapsulation has a first mold surface and a second mold surface. The blocking structure is located on the first mold surface and exposes the sensing area. The light-transmissive sheet is located on the blocking structure. The conductive connecting piece penetrates through the mold encapsulation. The circuit layer is located on the second mold surface. The first chip is electrically connected to the second chip via the conductive connecting piece and the circuit layer. The conductive terminal is configured on the circuit layer.

Description

Technical Field

[0001] This invention relates to a packaging structure and its manufacturing method, and more particularly to a packaging structure integrating multiple chips and its manufacturing method. Background Technology

[0002] To enable electronic products to achieve thin, light, and compact designs, semiconductor packaging technology has also advanced rapidly, developing products that meet the requirements of small size, light weight, high density, and high market competitiveness. Therefore, how to integrate multiple chips to improve the performance of the packaging structure has become one of the important issues. Summary of the Invention

[0003] This invention provides a packaging structure with better quality.

[0004] This invention provides a method for manufacturing a packaging structure that has better yield or lower cost.

[0005] The packaging structure of this invention includes a bridging chip, a through-silicon via (TSV) chip, a first mold enclosure, a first active chip, a second active chip, a second mold enclosure, and a redistribution structure. The first mold enclosure covers the TSV chip and the bridging chip. The first active chip is electrically connected to the bridging chip and the TSV chip. The second active chip is electrically connected to the bridging chip. The second mold enclosure covers the first active chip and the second active chip. The redistribution structure is electrically connected to the TSV chip. The TSV chip is located between the first active chip and the redistribution structure.

[0006] The method for manufacturing the packaging structure of the present invention includes the following steps: Providing a through-silicon via (TSV) chip and a bridging chip. Forming a first mold covering the TSV chip and the bridging chip. Forming a redistribution circuit structure electrically connected to the TSV chip. Configuring a first active chip electrically connected to the bridging chip and the TSV chip. Configuring a second active chip electrically connected to the bridging chip. Forming a second mold covering the first active chip and the second active chip. After the steps of forming the redistribution circuit structure and configuring the first active chip, the TSV chip is positioned between the first active chip and the redistribution circuit structure.

[0007] Based on the above, the packaging structure of the present invention can integrate multiple active chips. These active chips can be electrically connected to each other via bridging chips, and can also be electrically connected to a redistribution structure via through-silicon via (TSV) chips. This improves the quality of the packaging structure. Furthermore, in the manufacturing method of the packaging structure, the bridging chips and TSV chips can be encapsulated in a first mold first, and then the active chips electrically connected to the bridging chips or TSV chips can be configured. This improves the manufacturing yield of the packaging structure and may reduce its manufacturing cost.

[0008] This invention provides a packaging structure and its manufacturing method, which can have better performance.

[0009] The packaging structure of the present invention includes a first chip, a second chip, a mold enclosure, a barrier structure, a light-transmitting sheet, a conductive connector, a first circuit layer, and conductive terminals. The first chip includes a first active surface and a first back surface opposite to the first active surface. The first active surface has a sensing area. The second chip includes a second active surface and a second back surface opposite to the second active surface. The second chip is configured such that its second back surface faces the first back surface of the first chip. The mold enclosure covers the second chip. The mold enclosure has a first mold cover and a second mold cover opposite to the first mold cover. The barrier structure is located on the first mold cover and exposes the sensing area of ​​the first chip. The light-transmitting sheet is located on the barrier structure. The conductive connector penetrates the mold enclosure. The first circuit layer is located on the second mold cover. The first chip is electrically connected to the second chip via the conductive connector and the first circuit layer. The conductive terminals are disposed on the first circuit layer.

[0010] The manufacturing method of the packaging structure of the present invention includes the following steps: providing a wafer including an active surface, wherein the active surface has a sensing area; forming a barrier structure on the active surface of the wafer; disposing a light-transmitting sheet on the barrier structure; forming a through-silicon via (TSV) on the wafer, and forming a circuit layer electrically connecting the TSV on the back side of the wafer opposite to the active surface; forming a dielectric layer covering the TSV; forming a conductive connector on the dielectric layer; disposing a second chip on the dielectric layer; forming a mold covering the second chip on the dielectric layer; forming a first circuit layer on the mold, wherein the first chip is electrically connected to the second chip via the conductive connector and the first circuit layer; and forming a conductive terminal on the first circuit layer.

[0011] The manufacturing method of the packaging structure of the present invention includes the following steps: forming a conductive connector on a carrier substrate; disposing a first chip on the carrier substrate, the chip including a first active surface and a first back surface opposite to the first active surface, wherein the first active surface has a sensing area, and the first chip is disposed with its first active surface facing the carrier substrate; disposing a second chip on the first chip, the chip including a second active surface and a second back surface opposite to the second active surface, and the second chip is disposed with its second back surface facing the first back surface of the first chip; forming a molding compound on the carrier substrate, which covers the first chip and the second chip; forming a second circuit layer on the molding compound; after forming the molding compound, separating the carrier substrate from the first chip to expose the first active surface; forming a barrier structure on the molding compound, wherein the barrier structure exposes the sensing area; and disposing a light-transmitting sheet on the barrier structure.

[0012] Based on the above, the manufacturing method and corresponding structure of the present invention can integrate a first chip suitable for sensing and a second chip suitable for data processing into a package structure. This improves the sensing and processing performance of the package structure. Attached Figure Description

[0013] The accompanying drawings are included to further illustrate the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.

[0014] Figures 1A to 1H This is a partial cross-sectional schematic diagram of a method for manufacturing a packaging structure according to a first embodiment of the present invention;

[0015] Figures 2A to 2H This is a partial cross-sectional schematic diagram of a method for manufacturing a packaging structure according to a second embodiment of the present invention.

[0016] Explanation of icon numbers

[0017] 100, 200: Package structure;

[0018] 119, 119': wafer;

[0019] 110, 120, 210: Chips;

[0020] 110a, 110b, 110c, 120a, 120b, 120c, 210a, 210b: surface;

[0021] 110d, 210d: Sensing area;

[0022] 111, 111', 121: Substrate;

[0023] 112, 122, 212: Chip connection pads;

[0024] 123: Chip insulating layer;

[0025] 124: Chip connector;

[0026] 124a: Surface;

[0027] 115: Through-silicon via;

[0028] 115e: Insulation layer;

[0029] 115f, 162f: conductive layers;

[0030] 116: Air gap;

[0031] 130: Molded body;

[0032] 130a, 130b: Mold cover;

[0033] 136: Conductive connector;

[0034] 145: Barrier structure;

[0035] 146: Translucent sheet;

[0036] 150: Dielectric layer;

[0037] 170: Re-layout circuit structure;

[0038] 171: Circuit layer or conductive layer;

[0039] 175: Insulation layer;

[0040] 162, 262: Line layer;

[0041] 181, 281: Adhesive material;

[0042] 186: Conductive terminal;

[0043] R1, R2: Enclosed spaces;

[0044] 91, 93: Carrier plates;

[0045] 92, 94: Release layer. Detailed Implementation

[0046] Unless otherwise expressly stated, directional terms used herein (e.g., up, down, right, left, front, back, top, bottom) are for reference only and are not intended to imply absolute orientation. Additionally, for clarity, portions of membranes or components may be omitted from the accompanying drawings.

[0047] Unless otherwise expressly stated, no method described herein is intended to be construed as requiring its steps to be performed in a particular order.

[0048] Reference will now be made in detail to exemplary embodiments of the invention, examples of which are illustrated in the accompanying drawings. However, the invention may be embodied in various different forms and should not be limited to the embodiments described herein. The thickness, dimensions, or sizes of layers or regions in the drawings are enlarged for clarity. The same or similar reference numerals denote the same or similar components, which will not be described again in the following paragraphs.

[0049] Figures 1A to 1H This is a partial cross-sectional schematic diagram of a method for manufacturing a packaging structure according to a first embodiment of the present invention.

[0050] Please refer to Figure 1A A wafer 119' is provided. The wafer 119' may be placed on a carrier plate (not shown), but the invention is not limited thereto.

[0051] The wafer 119' may include a silicon substrate 111' and a plurality of die pads 112. The die pads 112 may be, for example, aluminum pads, copper pads or other suitable metal pads, but the invention is not limited thereto.

[0052] One side of the substrate 111' has a component region (not shown), and the surface on which the component region is located can be referred to as the active surface 110a. Chip connection pads 112 can be located on the active surface 110a. In a typical chip design, components within the component region (e.g., components within the component region of wafer 119') can be electrically connected to corresponding chip connection pads (e.g., some chip connection pads 112 in wafer 119') via corresponding back end of line interconnects (BEOL interconnects). The active surface 110a has a sensing region 110d. The sensing region 110d can have corresponding sensing components. The sensing components are, for example, complementary metal-oxide-semiconductor image sensors (CMOS image sensors; CIS), but the invention is not limited thereto.

[0053] Please continue to refer to Figure 1A An insulating barrier structure 145 is formed on the active surface 110a of the wafer 119'. The barrier structure 145 can be formed by coating, printing, photolithography or other suitable methods, and is not limited thereto in this invention.

[0054] Please refer to Figures 1A to 1B A light-transmitting sheet 146 is configured on the blocking structure 145.

[0055] In this embodiment, the step of configuring the light-transmitting sheet 146 on the blocking structure 145 can be performed under a first ambient air pressure. For example, the step of configuring the light-transmitting sheet 146 on the blocking structure 145 can be performed inside a cavity (not shown) with a corresponding first ambient air pressure.

[0056] In one embodiment, the first ambient air pressure is less than one atmosphere. In this way, in subsequent steps or structures, the pressure difference can make the contact between the light-transmitting sheet 146 and the blocking structure 145 more intimate.

[0057] Please refer to Figures 1B to 1C For wafer 119 (marked as Figure 1C A through silicon via (TSV) 115 is formed, and a circuit layer 162 for electrically connecting the TSV 115 is formed on the back side 110b of the wafer 119 opposite to the active surface 110a.

[0058] In this embodiment, the silicon substrate 111' (denoted as 111') of wafer 119' can be... Figure 1B The thinning process is performed on the silicon substrate 111 (marked as...). Figure 1CA through-silicon via 115 and a corresponding circuit layer 162 (which can be referred to as the second circuit layer) are formed on the back side 110b.

[0059] For example, one can first work on the silicon substrate 111' (marked as...). Figure 1B The thinning process is then performed on the thinned silicon substrate 111 (marked as shown in the image). Then, the thinned silicon substrate 111 can be removed by etching or other suitable methods. Figure 1C An opening is formed on the back side 110b of the substrate 111 to expose the chip connection pad 112. A corresponding insulating layer 115e can then be formed by deposition, etching, and / or other suitable methods. The insulating layer 115e can cover the back side 110b of the substrate 111 and the sidewalls of the opening, and the insulating layer 115e can expose the chip connection pad 112. Corresponding conductive layers 115f and 162f can then be formed by deposition, plating, etching, and / or other suitable methods. Conductive layers 115f and 162f may include, for example, corresponding seed layers and corresponding plating layers, but the invention is not limited thereto. The portion of conductive layer 115f and the corresponding insulating layer 115e located within the opening can be referred to as a through-silicon via 115. The portion of conductive layer 162f located on the back side 110b of the substrate 111 can be referred to as a circuit layer 162. That is, the conductive portion in the through-silicon via 115 and the conductive portion in the circuit layer 162 can be the same film layer. Furthermore, the layout design in the circuit layer 162 can be adjusted according to design requirements, and is not limited in this invention.

[0060] In this embodiment, the insulating layer 115e and the conductive layer 115f do not completely fill the openings of the exposed chip connection pad 112.

[0061] Please refer to Figures 1C to 1D A dielectric layer 150 is formed. The dielectric layer 150 may cover the through-silicon via 115 and expose a portion of the circuit layer 162. In this embodiment, a corresponding organic dielectric material (such as polyimide (PI), but not limited thereto) may be formed on the back side 110b of the substrate 111 by coating. Then, the aforementioned organic dielectric material may be used to form a patterned dielectric layer 150 by a suitable curing method (such as light exposure, heating, and / or standing for a period of time).

[0062] In this embodiment, the patterned dielectric layer 150 may partially fill but not completely fill the opening in the substrate 111. That is, at least one gas gap 116 is embedded within the through-silicon via 115. For example, the step of forming the dielectric layer 150 covering the through-silicon via 115 (e.g., the step of forming an organic dielectric material on the back side of the substrate) can be performed under a second ambient pressure, such as room pressure (e.g., about one atmosphere). In this way, the dielectric layer 150 can be formed more easily and / or quickly. That is, by the above method, the pressure of the gas gap 116 is also approximately the second ambient pressure.

[0063] In one embodiment, the organic dielectric material used to form the dielectric layer 150 may be dissolved in a suitable solvent; or, it may be formed by a suitable reaction (e.g., condensation polymerization) in a suitable solvent. The aforementioned solvent is, for example, dimethylformamide, dimethyl sulfoxide (DMSO), or other suitable organic solvents. Therefore, during the formation of the dielectric layer 150 (e.g., during the aforementioned curing step), some organic solvent molecules may remain within the air gap 116.

[0064] In one embodiment, the dielectric layer 150 may be referred to as a passivation layer, but the invention is not limited thereto.

[0065] Please continue to refer to Figure 1D Conductive connectors 136 are formed on dielectric layer 150. Conductive connectors 136 can be electrically connected to corresponding lines in circuit layer 162.

[0066] In one embodiment, the conductive connector 136 may be formed by a suitable method (e.g., photolithography and plating, but not limited thereto), but the invention is not limited thereto. In one embodiment, the conductive connector 136 may be a pre-formed conductive element.

[0067] Please refer to Figure 1EA second chip 120 is disposed on a dielectric layer 150. In this embodiment, the second chip 120 may include a silicon substrate 121, a plurality of chip connection pads 122, a chip insulating layer 123, and a plurality of chip connectors 124. One side of the silicon substrate 121 has a component region (not shown), and the surface on which the component region is located may be referred to as a second active surface 120a. The surface relative to the second active surface 120a may be referred to as a second back surface 120b. The second chip 120 is disposed with its second back surface 120b facing the wafer 119. The chip connection pads 122 may be located on the second active surface 120a. The chip connectors 124 are, for example, metal bumps, but the invention is not limited thereto. The chip connectors 124 are located on and electrically connected to the corresponding chip connection pads 122. The chip insulating layer 123 may cover the chip connection pads 122, and the chip insulating layer 123 exposes a portion of the chip connection pads 122. In chip design, components within a component area (e.g., components within the component area of ​​the second chip 120) can be electrically connected to corresponding chip connection pads (e.g., some chip connection pads 122 of the second chip 120) via corresponding back-end metal interconnects.

[0068] In one embodiment, the second chip 120 may include an image signal processor (ISP), but the invention is not limited thereto.

[0069] It is worth noting that in the illustrated embodiment, the conductive connector 136 is formed on the dielectric layer 150 first, and then the second chip 120 is disposed on the dielectric layer 150; however, the present invention is not limited thereto. In an embodiment not shown, the second chip 120 may be disposed on the dielectric layer 150 first, and then the conductive connector 136 may be formed on the dielectric layer 150.

[0070] In one embodiment, the second back surface 120b of the second chip 120 may have an adhesive material 181. The adhesive material 181 may include a die-attached film (DAF), but the invention is not limited thereto.

[0071] Please refer to Figures 1E to 1F A molding compound 130 is formed on the dielectric layer 150. The molding compound 130 can cover the second chip 120.

[0072] In one embodiment, a molding material (not shown) may be formed on the dielectric layer 150. After curing the molding material, a planarization process may be performed to form the mold body 130. The planarization process may include, for example, grinding, polishing, or other suitable planarization steps. The mold body 130 may expose the upper surface 124a of the chip connector 124 of the second chip 120. That is, the mold cover 130b of the mold body 130 may be coplanar with the upper surface 124a of the chip connector 124 of the second chip 120.

[0073] In one embodiment, since the second active surface 120a of the second chip 120 has a chip connector 124, the possibility of damage to the second active surface 120a of the second chip 120 can be reduced when the aforementioned planarization step is performed.

[0074] Please refer to Figures 1F to 1G A redistributed circuit structure 170 is formed on the molding body 130. The redistributed circuit structure 170 includes a corresponding conductive layer 171 (which may be referred to as a first circuit layer) and a corresponding insulating layer 175. The portion of the conductive layer 171 that penetrates the insulating layer 175 may be referred to as a conductive via. The layout design of the circuit formed by the conductive layer 171 can be adjusted according to design requirements and is not limited in this invention. The electronic components in the wafer 119 and the second chip 120 can be electrically connected via the corresponding lines in the redistributed circuit structure 170, the corresponding conductive connectors 136, and the corresponding lines in the first circuit layer 171.

[0075] Please refer to Figures 1G to 1H Conductive terminals 186 are formed on the first circuit layer 171 and electrically connected to corresponding lines in the first circuit layer 171. The conductive terminals 186 may include solder balls, but the invention is not limited thereto.

[0076] Please continue to refer to Figures 1G to 1H This allows for a singulation process to obtain multiple first chips 110. The dicing process includes, for example, using a rotating blade or laser beam to diced wafer 119 (labeled as...). Figure 1G The aforementioned standardization process can also be applied to the redistribution circuit structure 170, the molded enclosure 130, the blocking structure 145, and / or the light-transmitting sheet 146.

[0077] It is worth noting that after the standardization process, similar component symbols will be used for the standardized components. For example, the corresponding structure in wafer 119 (such as...) Figure 1GThe sensing area 110d, silicon via 115, air gap 116, or other similar elements in the first chip 110 can be the corresponding structures in multiple first chips 110 after being monolithically assembled (e.g., Figure 1H The sensing area 110d, silicon via 115, air gap 116 or other similar elements, and the second chip 120 (such as...) Figure 1G As shown, after being monolithically processed, it can be used to create multiple second chips 120 (such as...). Figure 1H As shown), mold body 130 (as shown) Figure 1G As shown, after monomerization, it can be made into multiple mold bodies 130 (e.g. Figure 1H As shown), the blocking structure 145 (as shown) Figure 1G As shown, after being monolithized, it can be used to create multiple barrier structures 145 (such as...). Figure 1H As shown), light-transmitting sheet 146 (as shown) Figure 1G As shown, after monomerization, it can be made into multiple light-transmitting sheets 146 (e.g. Figure 1H (As shown), and so on. Other monolithic components will follow the same component notation rules as described above, and will not be elaborated upon here. Additionally, for clarity, in Figure 1H Not all components are listed in the text.

[0078] It is worth noting that in the illustrated embodiment, the conductive terminal 186 is formed first, and then the aforementioned standardization process is performed; however, the present invention is not limited thereto. In an embodiment not shown, the aforementioned standardization process may be performed first, and then the conductive terminal 186 may be formed.

[0079] Please refer to Figure 1HAfter the above-described process, the packaging structure 100 of this embodiment can be largely completed. The packaging structure 100 includes a first chip 110, a second chip 120, a mold body 130, a barrier structure 145, a light-transmitting sheet 146, a conductive connector 136, a first circuit layer 171, and conductive terminals 186. The first chip 110 includes a first active surface 110a, a first back surface 110b, and a first side surface 110c. The first back surface 110b is opposite to the first active surface 110a. The first side surface 110c connects the first active surface 110a and the first back surface 110b. The first active surface 110a has a sensing area 110d. The second chip 120 includes a second active surface 120a, a second back surface 120b, and a second side surface 120c. The second back surface 120b is opposite to the second active surface 120a. The second side surface 120c connects the second active surface 120a and the second back surface 120b. The second chip 120 is configured such that its second back surface 120b faces the first back surface 110b of the first chip 110. A molding compound 130 covers the second side surface 120c and / or a portion of the second active surface 120a of the second chip 120. The molding compound 130 has a first mold cover 130a and a second mold cover 130b relative to the first mold cover 130a. A blocking structure 145 is located on the first mold cover 130a, or also on the first active surface 110a of the first chip 110. The blocking structure 145 exposes the sensing area 110d of the first chip 110. A light-transmitting sheet 146 is located on the blocking structure 145. A conductive connector 136 penetrates the molding compound 130. A first circuit layer 171 is located on the second mold cover 130b. The first chip 110 is electrically connected to the second chip 120 via the conductive connector 136 and the first circuit layer 171. A conductive terminal 186 is disposed on the first circuit layer 171.

[0080] In this embodiment, the second active surface 120a of the second chip 120 also has a chip connector 124. The surface 124a of the chip connector 124 is coplanar with the second mold cover 130b.

[0081] In this embodiment, the packaging structure 100 further includes a second circuit layer 162. The second circuit layer 162 is located on the first mold cover 130a. The first chip 110 is electrically connected to the second chip 120 via the second circuit layer 162, the conductive connector 136, and the first circuit layer 171.

[0082] In this embodiment, the first chip 110 further includes a through-silicon via 115, and the through-silicon via 115 of the first chip 110 is electrically connected to the second circuit layer 162.

[0083] In this embodiment, the second circuit layer 162 is also located between the first chip 110 and the second chip 120.

[0084] In this embodiment, the package structure 100 further includes a dielectric layer 150. The dielectric layer 150 is located on the circuit layer and covers the through-silicon via 115. At least one air gap 116 is embedded in the through-silicon via 115. In one embodiment, the air gaps 116 located in different through-silicon vias 115 may have different sizes and / or morphologies.

[0085] In this embodiment, the first chip 110, the blocking structure 145, and the light-transmitting sheet 146 constitute a closed space R1. In one embodiment, the air pressure in the air gap 116 is greater than or equal to the air pressure in the closed space R1. In another embodiment, the air pressure in the closed space R1 is less than one atmosphere.

[0086] Figures 2A to 2H This is a partial cross-sectional schematic diagram of a method for manufacturing a packaging structure according to a second embodiment of the present invention.

[0087] Please refer to Figure 2A The invention provides a first carrier plate 91. The invention does not impose any particular limitations on the first carrier plate 91, as long as the first carrier plate 91 is suitable for carrying a film layer formed thereon or components disposed thereon.

[0088] In this embodiment, the first carrier plate 91 may have a release layer 92, but the invention is not limited thereto. The release layer 92 may be, for example, a light-to-heat conversion (LTHC) adhesive layer or other similar film layer, but the invention is not limited thereto.

[0089] Please continue to refer to Figure 2A Conductive connector 136 is formed on the first carrier plate 91.

[0090] Please continue to refer to Figure 2A A first chip 210 is disposed on a first carrier board 91. The first chip 210 includes a first active surface 210a and a first back surface 210b opposite to the first active surface 210a. The first active surface 210a has a sensing area 210d. The first chip 210 may include a silicon substrate 211 and a plurality of chip connection pads 212. The chip connection pads 212 may be located on the active surface 210a. The first chip 210 is disposed with its first active surface 210a facing the first carrier board 91.

[0091] It is worth noting that the present invention does not limit the order of the steps of forming the conductive connector 136 and configuring the first chip 210.

[0092] Please refer to Figures 2A to 2B A second chip 120 is configured on the first chip 210. The second chip 120 is configured such that its second back surface 120b faces the first back surface 210b of the first chip 210.

[0093] In one embodiment, an adhesive material 281 may be present between the first back surface 210b of the first chip 210 and the second back surface 120b of the second chip 120. The adhesive material 281 may include a die-attachment film, but the invention is not limited thereto.

[0094] It is worth noting that the present invention does not limit the order of the steps of forming the conductive connector 136 and configuring the second chip 120.

[0095] It is worth noting that in the illustrated embodiment, the conductive connector 136 is formed first, and then the second chip 120 is disposed on the first chip 210, but the present invention is not limited thereto. In an embodiment not shown, the second chip 120 may be disposed on the first chip 210 first, and then the conductive connector 136 may be formed.

[0096] Please refer to Figures 2B to 2C A mold 130 is formed on the first carrier 91, which covers the first chip 210 and the second chip 120. The mold 130 can expose the upper surface 124a of the chip connector 124 of the second chip 120.

[0097] It is worth noting that in the illustrated embodiment, the conductive connector 136 is formed first, and then the molded enclosure 130 covering the first chip 210 and the second chip 120 is formed; however, the present invention is not limited thereto. In an embodiment not shown, the molded enclosure 130 covering the first chip 210 and the second chip 120 may be formed first, and then the conductive connector 136 penetrating the molded enclosure 130 may be formed, for example, by drilling / etching and plating.

[0098] Please refer to Figures 2C to 2D A redistribution circuit structure 170 is formed on the mold enclosure 130. The corresponding circuits in the redistribution circuit structure 170 can be electrically connected to the corresponding conductive connector 136 and / or the second chip 120.

[0099] Please refer to Figures 2D to 2E After forming the mold body 130, the order in which the components are assembled can be unlimited. Figure 2D The structure shown is flipped up and down and placed on the second carrier plate 93 (marked as follows). Figure 2E Then, place the first carrier plate 91 (marked on) onto the first carrier plate 91. Figure 2D The first active surface 210a of the first chip 210 is separated from the first chip 210 to expose the first active surface 210a of the first chip 210, thus forming a structure as shown in the figure. Figure 2E The structure shown.

[0100] The present invention does not impose any particular limitation on the second carrier plate 93, as long as the second carrier plate 93 is suitable for carrying the film layer formed thereon or the components disposed thereon. In this embodiment, the second carrier plate 93 may have a release layer 94, but the present invention is not limited thereto.

[0101] Please continue to refer to Figure 2E A second circuit layer 262 is formed on the mold body 130. Corresponding lines of the second circuit layer 262 can be electrically connected to corresponding chip connection pads 212. Therefore, the first chip 210 and the second chip 120 can be electrically connected via corresponding lines in the redistributed circuit structure 170, conductive connectors 136, and the second circuit layer 262.

[0102] Please refer to Figures 2E to 2F A barrier structure 145 is formed on the mold body 130. The barrier structure 145 exposes the sensing region 210d in the first active surface 210a.

[0103] Please refer to Figures 2F to 2G The light-transmitting sheet 146 is placed on the blocking structure 145, and then the second carrier board 93 is separated from the redistribution circuit structure.

[0104] It is worth noting that in the illustrated embodiment, the light-transmitting sheet 146 is first placed on the blocking structure 145, and then the second carrier board 93 is separated from the redistribution circuit structure, but the present invention is not limited thereto.

[0105] Please refer to Figures 2G to 2H Conductive terminals 186 are formed on the first circuit layer 171 and electrically connected to the corresponding lines in the first circuit layer 171.

[0106] Please refer to Figures 2G to 2H It can at least be for Figure 2G The structure shown undergoes a standardization process. It is worth noting that after standardization, similar component symbols will be used for the standardized components; this will not be elaborated upon here. Additionally, for clarity, in... Figure 2H Not all components are listed in the text.

[0107] It is worth noting that the present invention does not limit the steps for forming the conductive terminal 186 or the order of performing the standardization process.

[0108] It is worth noting that in the illustrated embodiment, the second carrier board 93 may be separated from the redistribution circuit structure first, and then a standardization process may be performed; however, the present invention is not limited thereto. In an embodiment not shown, a standardization process may be performed first, and then the second carrier board 93 may be separated from the standardized multiple structures.

[0109] Please refer to Figure 2HAfter the above-described process, the packaging structure 200 of this embodiment can be largely completed. The packaging structure 200 includes a first chip 210, a second chip 120, a mold 130, a barrier structure 145, a light-transmitting sheet 146, a conductive connector 136, a first circuit layer 171, and conductive terminals 186. The first chip 210 includes a first active surface 210a, a first back surface 210b, and a first side surface 210c. The first back surface 210b is opposite to the first active surface 210a. The first side surface 210c connects the first active surface 210a and the first back surface 210b. The first active surface 210a has a sensing area 210d. The second chip 120 is configured such that its second back surface 120b faces the first back surface 210b of the first chip 210. The mold 130 covers the first chip 210 and the second chip 120. The barrier structure 145 exposes the sensing area 210d of the first chip 210. The first chip 210 is electrically connected to the second chip 120 via a conductive connector 136 and a first circuit layer 171. A conductive terminal 186 is disposed on the first circuit layer 171.

[0110] In this embodiment, the packaging structure 200 further includes a second circuit layer 262. The second circuit layer 262 is located on the first mold cover 130a. The barrier structure 145 can further expose the second circuit layer 262. The first chip 210 is electrically connected to the second chip 120 via the second circuit layer 262, the conductive connector 136, and the first circuit layer 171. The first chip 210, the second circuit layer 262, the barrier structure 145, and the light-transmitting sheet 146 constitute a closed space R2.

[0111] In summary, the manufacturing method and corresponding structure of the present invention can integrate a first chip suitable for sensing and a second chip suitable for data processing into a single package structure. This improves the sensing and processing performance of the package structure.

[0112] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A packaging structure, characterized in that, include: The first chip includes a silicon substrate and a chip connection pad, and has a first active surface and a first back surface relative to the first active surface, wherein the first active surface has a sensing area, and the chip connection pad is located on the first active surface. The second chip includes a second active surface and a second back surface relative to the second active surface, and the second chip is configured such that its second back surface faces the first back surface of the first chip. A molded enclosure covering the second chip and having a first molded cover and a second molded cover relative to the first molded cover; A blocking structure is located on the first mold cover and exposes the sensing area of ​​the first chip; A light-transmitting sheet is located on the blocking structure; A conductive connector penetrates the molded body; The first circuit layer is located on the cover of the second module. An insulating layer is located on the first back side of the first chip and extends through the silicon substrate to directly cover a portion of the chip connection pad; A conductive layer, situated on the insulating layer, extends through the silicon substrate to contact a portion of the chip connection pad exposed by the insulating layer, wherein: A portion of the conductive layer located on the first back side of the first chip constitutes a second circuit layer located on the first mold cover; A portion of the insulating layer penetrating the silicon substrate and a portion of the conductive layer penetrating the silicon substrate constitute a through-silicon via; and The chip connection pad of the first chip is electrically connected to the second chip via the through-silicon via, the second circuit layer, the conductive connector, and the first circuit layer; A dielectric layer, located on the second circuit layer and covering the through-silicon via, wherein: A portion of the dielectric layer is embedded in the silicon substrate; The portion of the dielectric layer embedded in the silicon substrate forms an air gap with the portion of the insulating layer constituting the through-silicon via; and The first chip, the blocking structure, and the light-transmitting sheet constitute a closed space, and the air pressure in the air gap is greater than or equal to the air pressure in the closed space; and Conductive terminals are disposed on the first circuit layer.

2. The packaging structure according to claim 1, characterized in that, The second active surface of the second chip also has a chip connector, and the surface of the chip connector is coplanar with the second mold cover.

3. The packaging structure according to claim 1, characterized in that, The second circuit layer is located between the first chip and the second chip.

4. The packaging structure according to claim 1, characterized in that, The air pressure in the enclosed space is less than one atmosphere.

5. A method for manufacturing a packaging structure, characterized in that, include: A wafer is provided, comprising a silicon substrate and a chip connection pad, and having a first active surface and a first back surface relative to the first active surface, wherein the first active surface has a sensing area and the chip connection pad is located on the first active surface; A barrier structure is formed on the active surface of the wafer; A light-transmitting sheet is disposed on the blocking structure, wherein the wafer, the blocking structure, and the light-transmitting sheet constitute a closed space; A through-silicon via (TSV) is formed on the wafer, and a second circuit layer electrically connecting the TSV is formed on the first back side of the wafer, comprising: An opening is formed from the first back side that penetrates the silicon substrate and exposes the chip connection pad; An insulating layer is formed on the first back side of the wafer and extends from the opening through the silicon substrate to directly cover a portion of the chip connection pad; A conductive layer is formed on the insulating layer and extends from the opening through the silicon substrate to contact a portion of the chip connection pad exposed by the insulating layer, wherein: A portion of the conductive layer located on the first back side constitutes the second circuit layer; and A portion of the insulating layer penetrating the silicon substrate and a portion of the conductive layer penetrating the silicon substrate constitute the through-silicon via; A dielectric layer is formed on the second circuit layer and covering the through-silicon via, wherein: A portion of the dielectric layer is embedded in the silicon substrate; and The portion of the dielectric layer embedded in the silicon substrate forms an air gap with the portion of the insulating layer constituting the through-silicon via; Conductive connectors are formed on the dielectric layer; A second chip is disposed on the dielectric layer, which includes a second active surface and a second back surface relative to the second active surface, and the second chip is disposed such that its second back surface faces the first back surface; A molded enclosure covering the second chip is formed on the dielectric layer, and the conductive connector penetrates the molded enclosure; A first circuit layer is formed on the mold enclosure, and the chip connection pad of the wafer is electrically connected to the second chip via the through-silicon via, the second circuit layer, the conductive connector, and the first circuit layer; and Conductive terminals are formed on the first circuit layer, wherein: The step of configuring the light-transmitting sheet on the blocking structure to form the enclosed space is performed under a first ambient air pressure. The step of forming the air gap by forming the dielectric layer covering the through-silicon via is performed under a second ambient pressure; and The second ambient air pressure is greater than or equal to the first ambient air pressure, so that the air pressure in the air gap is greater than or equal to the air pressure in the enclosed space.

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