Magnetoresistive random access memory structure and method of making same

Abstract

This invention discloses a magnetoresistive random access memory (MRAM) structure and its fabrication method. The MRAM structure includes a dielectric layer, and a first MRAM, a second MRAM, and a third MRAM are disposed on the dielectric layer from right to left. The second MRAM includes a magnetic tunneling junction. Two gaps are located between the first MRAM and the second MRAM, and between the second MRAM and the third MRAM, respectively. Two tensile stress material blocks are disposed in each gap. A first compressive stress layer surrounds and contacts all sidewalls of the magnetic tunneling junction, and a second compressive stress layer covers the openings of each gap and contacts the tensile stress material blocks.

Description

Technical Field

[0001] This invention relates to a magnetoresistive random access memory structure and its fabrication method, and particularly to a memory structure and its fabrication method that avoids deformation of the magnetic tunneling junction. Background Technology

[0002] Many modern electronic devices incorporate electronic memory. Electronic memory can be either volatile or non-volatile. Non-volatile memory retains its stored data even without power, while volatile memory loses its stored data when power is lost. Magnetoresistive random access memory (MRAM) is highly anticipated as the next generation of non-volatile memory technology due to its superior characteristics compared to current electronic memory.

[0003] Magnetoresistive random access memory (MRAM) does not store bit information using traditional electric charge; instead, it stores data using the effect of magnetic impedance. Structurally, MRAM includes a data layer and a reference layer. The data layer is made of a magnetic material, and during a write operation, an external magnetic field switches the data layer between two opposite magnetic states to store bit information. The reference layer is typically made of a magnetic material with a fixed magnetic state, making it difficult to change with an external magnetic field.

[0004] However, existing magnetoresistive random access memory (RAM) fabrication processes still have many drawbacks that require further improvement. For example, the magnetic tunneling junction deforms due to stress in the surrounding material layers. Therefore, the field still needs improved fabrication methods and structures for magnetoresistive RAM devices to address these issues. Summary of the Invention

[0005] According to a preferred embodiment of the present invention, a magnetoresistive random access memory (MRAM) structure includes a dielectric layer, a first MRAM, a second MRAM, and a third MRAM disposed on the dielectric layer, wherein the second MRAM is located between the first MRAM and the third MRAM, the second MRAM includes a magnetic tunneling junction, two gaps are respectively located between the first MRAM and the second MRAM and between the second MRAM and the third MRAM, two tensile stress material blocks are respectively disposed in each gap, a first compressive stress layer surrounds and contacts all sidewalls of the magnetic tunneling junction, and a second compressive stress layer covers the openings of each gap and contacts the tensile stress material blocks.

[0006] According to another preferred embodiment of the present invention, a method for fabricating a magnetoresistive random access memory (MRAM) structure includes: providing a dielectric layer, and disposing of a first magnetoresistive random access memory (MRAM), a second magnetoresistive random access memory (MRAM), and a third magnetoresistive random access memory (MRAM) on the dielectric layer, wherein the second magnetoresistive MRAM is located between the first and third MRAMs, and two gaps are respectively located between the first and second MRAMs and between the second and third MRAMs. Between the three magnetoresistive random access memories, the second magnetoresistive random access memory includes a magnetic tunneling junction, and then a first compressive stress layer is formed to cover the first magnetoresistive random access memory, the second magnetoresistive random access memory, the third magnetoresistive random access memory and the dielectric layer. Then, a tensile stress material layer is formed to cover the first compressive stress layer and fill the gaps. Next, the tensile stress material layer outside the gaps is removed to form two tensile stress material blocks respectively disposed in the gaps. Finally, a second compressive stress layer is formed to cover the openings of each gap and contact the tensile stress material blocks.

[0007] According to another preferred embodiment of the present invention, a magnetoresistive random access memory (MRAM) structure includes a dielectric layer, a plurality of magnetoresistive random access memories (MRAMs) disposed on the dielectric layer and arranged in a column, wherein the magnetoresistive MRAMs include a last magnetoresistive MRAM disposed at the end of the aforementioned column, a dummy magnetoresistive MRAM disposed on the dielectric layer and located on one side of the last magnetoresistive MRAM, a gap located between the dummy magnetoresistive MRAM and the last magnetoresistive MRAM, a first compressive stress layer contacting the sidewall of the gap, a tensile stress material block disposed in the gap, a second compressive stress layer covering the opening of the gap and contacting the tensile stress material block, wherein the second compressive stress layer has compressive stress, and a plurality of metal interconnect structures electrically connecting each magnetoresistive MRAM.

[0008] To make the above-mentioned objects, features, and advantages of the present invention more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. However, the following preferred embodiments and drawings are for reference and illustration only and are not intended to limit the present invention. Attached Figure Description

[0009] Figures 1 to 6 This is a schematic diagram illustrating a method for fabricating a magnetoresistive random access memory structure according to a preferred embodiment of the present invention;

[0010] Figure 7 A schematic diagram illustrating the etch-back step according to another preferred embodiment of the present invention;

[0011] Figure 8 This is a schematic diagram illustrating the etch-back step according to another preferred embodiment of the present invention;

[0012] Figure 9 A schematic diagram illustrating a magnetoresistive random access memory structure according to another preferred embodiment of the present invention;

[0013] Figure 10 This is a schematic diagram illustrating a magnetoresistive random access memory structure according to another preferred embodiment of the present invention.

[0014] Explanation of main component symbols

[0015] 10: Dielectric layer

[0016] 12: Upper electrode

[0017] 14: Magnetic tunnel junction

[0018] 15: Lower electrode

[0019] 16: Lower conductor

[0020] 18: Gap

[0021] 20: Metal interconnects

[0022] 22: First compressive stress layer

[0023] 24: Tensile stress material layer

[0024] 26: Tensile stress material block

[0025] 28: Second compressive stress layer

[0026] 30: Photoresist

[0027] 32: Interlayer dielectric layer

[0028] 34: Metal interconnects

[0029] 36: Metal interconnect structure

[0030] 100: Magnetoresistive Random Access Memory Structure

[0031] A: Memory area

[0032] B: Peripheral Circuit Area

[0033] M1: First Magnetoresistive Random Access Memory

[0034] M2: Second Magnetoresistive Random Access Memory

[0035] M3: Third Magnetoresistive Random Access Memory

[0036] DM: Virtual Magnetoresistive Random Access Memory Detailed Implementation

[0037] Figures 1 to 6 This is a method for fabricating a magnetoresistive random access memory structure according to a preferred embodiment of the present invention. Figure 7 The etch-back step is illustrated according to another preferred embodiment of the present invention. Figure 8 The back etching step is illustrated according to another preferred embodiment of the present invention.

[0038] like Figure 1 As shown, a dielectric layer 10 is first provided, which is divided into a memory region A and a peripheral circuit region B. Multiple magnetoresistive random access memories (RAMs) are arranged in an array on the dielectric layer 10 within memory region A. For example, a first magnetoresistive RAM M1, a second magnetoresistive RAM M2, and a third magnetoresistive RAM M3 are arranged in a column from right to left on the dielectric layer 10. The second magnetoresistive RAM M2 is located between the first magnetoresistive RAM M1 and the third magnetoresistive RAM M3. Furthermore, the first magnetoresistive RAM M1 is located at the end of the column, making it the last magnetoresistive RAM in the column. Additionally, a dummy magnetoresistive RAM DM is disposed on the dielectric layer 10 and located to one side of the first magnetoresistive RAM M1.

[0039] Furthermore, the first magnetoresistive random access memory M1, the second magnetoresistive random access memory M2, the third magnetoresistive random access memory M3, and the dummy magnetoresistive random access memory DM are each composed of an upper electrode 12, a magnetic tunneling junction 14, and a lower electrode 15. Several gaps 18 are located between two adjacent magnetoresistive random access memories, for example, gaps 18 may be located between the dummy magnetoresistive random access memory DM and the first magnetoresistive random access memory M1, between the first magnetoresistive random access memory M1 and the second magnetoresistive random access memory M2, and between the second magnetoresistive random access memory M2 and the third magnetoresistive random access memory M3.

[0040] In addition, a plurality of metal interconnects 20 are provided in the dielectric layer 10. The metal interconnects 20 are electrically connected to the lower electrode 15 of the first magnetoresistive random access memory M1, the lower electrode 15 of the second magnetoresistive random access memory M2, the lower electrode 15 of the third magnetoresistive random access memory M3 and the lower electrode 15 of the dummy magnetoresistive random access memory DM through the lower conductor 16.

[0041] Next, a first compressive stress layer 22 is formed to cover the first magnetoresistive random access memory M1, the second magnetoresistive random access memory M2, the third magnetoresistive random access memory M3, the dummy magnetoresistive random access memory DM, and the dielectric layer 10. The first compressive stress layer 22 has compressive stress. Because the pores in the material layer with compressive stress are smaller, water vapor or oxygen can be blocked outside the first compressive stress layer 22. Therefore, when the first compressive stress layer 22 is covered on the first magnetoresistive random access memory M1, the second magnetoresistive random access memory M2, the third magnetoresistive random access memory M3, and the dummy magnetoresistive random access memory DM, it can prevent water vapor and oxygen from entering the first magnetoresistive random access memory M1, the second magnetoresistive random access memory M2, the third magnetoresistive random access memory M3, and the dummy magnetoresistive random access memory DM. According to a preferred embodiment of the present invention, the first compressive stress layer 22 preferably has a thickness of 50 angstroms or more to effectively prevent water vapor and oxygen intrusion. Furthermore, the first compressive stress layer 22 comprises silicon nitride, silicon oxide, silicon oxynitride, or other insulating materials. According to a preferred embodiment of the present invention, the first compressive stress layer 22 is silicon nitride.

[0042] like Figure 2 As shown, etching back the first compressive stress layer 22 thins the first compressive stress layer 22 and removes a portion of the first compressive stress layer 22. Furthermore, the degree of back etching can be adjusted according to product requirements, for example, in... Figure 2 In the process, after the etch-back process, the first compressive stress layer 22 still completely covers the first magnetoresistive random access memory M1, the second magnetoresistive random access memory M2, the third magnetoresistive random access memory M3, and the dummy magnetoresistive random access memory DM. That is to say, the first compressive stress layer 22 covers the entire sidewall and top surface of the first magnetoresistive random access memory M1, the entire sidewall and top surface of the second magnetoresistive random access memory M2, the entire sidewall and top surface of the third magnetoresistive random access memory M3, and the entire sidewall and top surface of the dummy magnetoresistive random access memory DM. In addition, all gaps 18 are completely covered by the first compressive stress layer 22.

[0043] like Figure 7 As shown, according to another preferred embodiment of the present invention, the first compressive stress layer 22 is etched back until the top surface of the first magnetoresistive random access memory M1, the top surface of the second magnetoresistive random access memory M2, the top surface of the third magnetoresistive random access memory M3 and the top surface of the dummy magnetoresistive random access memory DM are exposed. The top surface includes the upper electrode 12 of the first magnetoresistive random access memory M1, the upper electrode 12 of the second magnetoresistive random access memory M2, the upper electrode 12 of the third magnetoresistive random access memory M3 and the upper electrode 12 of the dummy magnetoresistive random access memory DM.

[0044] like Figure 8 As shown, according to another preferred embodiment of the present invention, the first compressive stress layer 22 is etched back until the top surface of the first magnetoresistive random access memory M1, the top surface of the second magnetoresistive random access memory M2, the top surface of the third magnetoresistive random access memory M3, the top surface of the dummy magnetoresistive random access memory DM, and the bottom of the gap 18 are exposed. Figure 2 , Figures 7 to 8 The key point of the back etching is that after back etching, at least a portion of the first compressive stress layer 22 is retained to surround and contact all sidewalls of the magnetic tunnel junction 14 of the first magnetoresistive random access memory M1, the second magnetoresistive random access memory M2, the third magnetoresistive random access memory M3, and the dummy magnetoresistive random access memory DM. This effectively prevents moisture and oxygen from entering the magnetic tunnel junction 14.

[0045] Although the first compressive stress layer 22 can prevent water vapor and oxygen from entering the magnetic tunneling junction, the structure in the magnetic tunneling junction 14, including the free layer, reference layer, IEC material layer used to adjust the interlayer exchange coupling (IEC) between the free layer and reference layer, and the perpendicular magnetic anisotropic (PMA) material layer that forms the perpendicular magnetic moment, are all made of pure metal films. Because pure metals have a relatively low elastic modulus, the free layer, reference layer, IEC material layer, PMA material layer, or other pure metal material layers located on the sidewalls of the magnetic tunneling junction 14 will deform due to contact with the first compressive stress layer 22. However, the free layer, reference layer, IEC material layer, PMA material layer, or other pure metal material layers in the middle of the magnetic tunneling junction 14 will not deform because they are not contacted by the first compressive stress layer 22. Such an asymmetrical shape will cause the performance of the magnetoresistive random access memory to be unstable.

[0046] Therefore, the present invention will subsequently provide a method for solving deformation, and the following steps will be described in detail. Figure 2 The following explanation will use the results of etch-back as an example. Figure 3 As shown, a tensile stress material layer 24 is formed to cover the first compressive stress layer 22 and fill the gaps 18. The tensile stress material layer 24 comprises silicon nitride, silicon oxide, silicon oxynitride, or other insulating materials. According to a preferred embodiment of the present invention, the tensile stress material layer 24 is silicon oxide. Figure 4As shown, the tensile stress material layer 24 outside each gap 18 is removed, and the remaining tensile stress material layer 24 in each gap 18 becomes the tensile stress material block 26. The material of the tensile stress material block 26 is the same as that of the tensile stress material layer 24. Furthermore, the absolute value of the tensile stress in the tensile stress material block 26 is the same as the absolute value of the compressive stress of the first compressive stress layer 22, or the difference is less than a predetermined value, which will depend on the deformation resistance of the metal material in the magnetic tunneling junction 14. The tensile stress in the tensile stress material block 26 can reduce or offset the compressive stress of the first compressive stress layer 22 on the sidewall of the magnetic tunneling junction 14, preventing the deformation problem of the pure metal film.

[0047] Please continue reading. Figure 4 A second compressive stress layer 28 is formed, covering the openings of each gap 18 and contacting each tensile stress material block 26, as well as covering the first magnetoresistive random access memory M1, the second magnetoresistive random access memory M2, the third magnetoresistive random access memory M3, the dummy magnetoresistive random access memory DM, and the first compressive stress layer 22 located in the peripheral circuit area B. Similar to the first compressive stress layer 22, the second compressive stress layer 28, due to its compressive stress, can block water vapor or oxygen from entering the tensile stress material block 26. Because when the tensile stress material block 26 absorbs water vapor and oxygen, its tensile stress decreases or even transforms into compressive stress, it is necessary to protect the tensile stress material block 26 using the second compressive stress layer 28. Furthermore, the thickness of the second compressive stress layer 28 is less than or equal to the thickness of the first compressive stress layer 22. According to a preferred embodiment of the present invention, the thickness of the second compressive stress layer 28 is approximately 10 angstroms.

[0048] like Figure 5 As shown, a photoresist 30 is formed to cover the memory region A, and then an etching process is performed to remove the first compressive stress layer 22 and the second compressive stress layer 28 located on the peripheral circuit region B. Depending on different product requirements, this step can be omitted. Figure 5 The step of removing the first compressive stress layer 22 and the second compressive stress layer 28 on the peripheral circuit area B is equivalent to retaining the first compressive stress layer 22 and the second compressive stress layer 28 on the peripheral circuit area B. Subsequent steps will be explained using the removal of the first compressive stress layer 22 and the second compressive stress layer 28 on the peripheral circuit area B as an example.

[0049] like Figure 6As shown, after removing the photoresist 30, an interlayer dielectric layer 32 is formed to cover the memory region A and the peripheral circuit region B. Then, multiple metal interconnects 34 are formed passing through the interlayer dielectric layer 32. Each metal interconnect 34 contacts the upper electrode 12 of the first magnetoresistive random access memory M1, the upper electrode 12 of the second magnetoresistive random access memory M2, and the upper electrode 12 of the third magnetoresistive random access memory M3. Furthermore, the metal interconnects 34 are also located in the peripheral circuit region B. It is worth noting that the dummy magnetoresistive random access memory DM lacks a tensile stress material block 26 on one side. Therefore, one side of the magnetic tunnel junction 14 sidewall of the dummy magnetoresistive random access memory DM is still under compressive stress, while the other side is stress-free, causing a stress mismatch. This prevents the dummy magnetoresistive random access memory DM from conducting in actual operation, thus avoiding electrical instability of the dummy magnetoresistive random access memory DM and its impact on the overall performance of the magnetoresistive random access memory. Therefore, in this embodiment, the dummy magnetoresistive random access memory (DM) is de-conductive by not providing a metal interconnect 34 above the upper electrode 14. According to another preferred embodiment of the present invention, the dummy magnetoresistive random access memory (DM) can also be de-conductive by not providing a metal interconnect 20 below the lower electrode 15.

[0050] like Figure 6 As shown, according to a preferred embodiment of the present invention, a magnetoresistive random access memory (MRAM) structure 100 includes a dielectric layer 10. Multiple magnetoresistive MRAMs are arranged in a column on the dielectric layer 10. For example, a first magnetoresistive MRAM M1, a second magnetoresistive MRAM M2, and a third magnetoresistive MRAM M3 are arranged in a column from right to left on the dielectric layer 10. The second magnetoresistive MRAM M2 is located between the first magnetoresistive MRAM M1 and the third magnetoresistive MRAM M3. Furthermore, the first magnetoresistive MRAM M1 is located at the last position in the column, thus it is also the last magnetoresistive MRAM in the column. Additionally, a dummy magnetoresistive MRAM DM is disposed on the dielectric layer 10 and located to one side of the first magnetoresistive MRAM M1. The first magnetoresistive random access memory (M1), the second magnetoresistive random access memory (M2), the third magnetoresistive random access memory (M3), and the dummy magnetoresistive random access memory (DM) are each composed of an upper electrode 12, a magnetic tunneling junction 14, and a lower electrode 15. Several gaps 18 are located between the dummy magnetoresistive random access memory (DM) and the first magnetoresistive random access memory (M1), between the first magnetoresistive random access memory (M1) and the second magnetoresistive random access memory (M2), and between the second magnetoresistive random access memory (M2) and the third magnetoresistive random access memory (M3), respectively.

[0051] In addition, multiple metal interconnect structures 36 are electrically connected to each magnetoresistive random access memory. Specifically, the metal interconnect structure 36 includes metal interconnects 20 and metal interconnects 34. The metal interconnects 20 are disposed in the dielectric layer 10. For example, multiple metal plugs contact and electrically connect to the lower electrode 15 of the first magnetoresistive random access memory M1, the lower electrode 15 of the second magnetoresistive random access memory M2, the lower electrode 15 of the third magnetoresistive random access memory M3, and the lower electrode 15 of the dummy magnetoresistive random access memory DM.

[0052] Multiple metal interconnects 34 each contact and electrically connect to the upper electrode 12 of the first magnetoresistive random access memory M1, the upper electrode 12 of the second magnetoresistive random access memory M2, and the upper electrode 12 of the third magnetoresistive random access memory M3. It is worth noting that there are no metal interconnects 34 on the upper electrode 12 of the dummy magnetoresistive random access memory DM.

[0053] like Figure 8 As shown, a first compressive stress layer 22 surrounds and contacts all sidewalls of the magnetic tunneling junction 14 of the first magnetoresistive random access memory M1, the second magnetoresistive random access memory M2, the third magnetoresistive random access memory M3, and the dummy magnetoresistive random access memory DM. At this time, the top surface of the first magnetoresistive random access memory M1 may not be covered by the first compressive stress layer 22. Similarly, the top surfaces of the second magnetoresistive random access memory M2, the third magnetoresistive random access memory M3, and the dummy magnetoresistive random access memory DM may also not be covered by the first compressive stress layer 22. Additionally, the bottom of the gap 18 may also not be covered by the first compressive stress layer 22.

[0054] According to another preferred embodiment of the present invention, such as Figure 7 As shown, the first compressive stress layer 22, in addition to... Figure 8 In addition to covering all the sidewalls of the magnetic tunnel junction 14, the bottom of the gap 18 is also covered.

[0055] Please refer again to another preferred embodiment of the present invention. Figure 6 In addition to Figure 7 In addition to covering all the sidewalls surrounding the magnetic tunnel junction 14 and the bottom of the gap 18, the first compressive stress layer 22 may also cover the top surface of the first magnetoresistive random access memory M1, the top surface of the second magnetoresistive random access memory M2, the top surface of the third magnetoresistive random access memory M3, and the top surface of the dummy magnetoresistive random access memory DM.

[0056] Please continue reading. Figure 6 Several tensile stress material blocks 26 are respectively disposed in each gap 18. The tensile stress of the tensile stress material blocks 26 can reduce or offset the compressive stress on the sidewall of the magnetic tunneling junction 14 by the first compressive stress layer 22, preventing deformation of the sidewall of the magnetic tunneling junction 14. The first compressive stress layer 22 covers the bottom of the tensile stress material blocks 26. The absolute value of the tensile stress in the tensile stress material blocks 26 is the same as the absolute value of the compressive stress in the first compressive stress layer 22, or the difference is less than a predetermined ratio, which depends on the deformation resistance of the metal material in the magnetic tunneling junction 14. For example, if the stress value of the first compressive stress layer 22 is -100 MPa, the stress value of the tensile stress material blocks 26 can be 70 to 130 MPa, and the difference is less than 30%. Depending on the deformation resistance of the metal materials in the magnetic tunneling junction 14, the upper electrode 12, and the lower electrode 15, the difference can be between 0% and 50%. According to a preferred embodiment of the present invention, when the stresses of the first compressive stress layer 22 and the tensile stress material block 26 are neutralized, the sidewalls of the magnetic tunnel junction 14 do not deform due to stress.

[0057] A second compressive stress layer 28 covers the openings of each gap 18 and contacts each tensile stress material block 26. The thickness of the second compressive stress layer 28 is preferably no greater than the thickness of the first compressive stress layer 22. The thickness of the first compressive stress layer 22 is preferably no less than 50 angstroms, and the thickness of the second compressive stress layer 28 is preferably 10 angstroms. The materials of the first compressive stress layer 22, the second compressive stress layer 28, and the tensile stress material blocks 26 may include silicon nitride, silicon oxide, silicon oxynitride, or other insulating materials. According to a preferred embodiment of the invention, the tensile stress material block 26 is silicon oxide, and both the first compressive stress layer 22 and the second compressive stress layer 28 are silicon nitride.

[0058] Please see Figure 9 , Figure 9 A magnetoresistive random access memory structure is illustrated according to another preferred embodiment of the present invention, wherein elements having the same function and location will use and Figure 6 The same labels in the text. Figure 9 Magnetoresistive random access memory structure and Figure 6 The only difference in the structure of the magnetoresistive random access memory is that the first compressive stress layer 22 does not cover the top surface of the first magnetoresistive random access memory M1, the top surface of the second magnetoresistive random access memory M2, the top surface of the third magnetoresistive random access memory M3, and the top surface of the dummy magnetoresistive random access memory DM. The positions and materials of the other components are the same, and will not be described in detail here.

[0059] Please see Figure 10 , Figure 10A magnetoresistive random access memory structure is illustrated according to another preferred embodiment of the present invention, wherein elements having the same function and location will use and Figure 6 The same labels in the text. Figure 10 Magnetoresistive random access memory structure and Figure 6 The only difference in the structure of the magnetoresistive random access memory is that the first compressive stress layer 22 surrounds all the sidewalls of the magnetic tunnel junction 14. The positions and materials of the other components are the same, and will not be described in detail here.

[0060] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made in accordance with the claims of the present invention should be included within the scope of the present invention.

Claims

1. A magnetoresistive random access memory structure, characterized by, Include: Dielectric layer; A first magnetoresistive random access memory, a second magnetoresistive random access memory, and a third magnetoresistive random access memory are disposed on the dielectric layer, wherein the second magnetoresistive random access memory is located between the first magnetoresistive random access memory and the third magnetoresistive random access memory, and the second magnetoresistive random access memory includes a magnetic tunneling junction. Two gaps are located between the first magnetoresistive random access memory and the second magnetoresistive random access memory, and between the second magnetoresistive random access memory and the third magnetoresistive random access memory, respectively. Two tensile stress material blocks are respectively placed in each of the gaps; The first compressive stress layer surrounds and contacts all sidewalls of the magnetic tunneling junction; and The second compressive stress layer covers the openings of each gap and contacts the two tensile stress material blocks, wherein the absolute value of the tensile stress in each tensile stress material block is the same as the absolute value of the compressive stress of the first compressive stress layer, or the difference between them is less than a predetermined ratio.

2. The magnetoresistive random access memory structure as described in claim 1, wherein the predetermined ratio is 30%.

3. The magnetoresistive random access memory structure as claimed in claim 1, wherein the first compressive stress layer covers the entire sidewall of the first magnetoresistive random access memory, the entire sidewall of the second magnetoresistive random access memory, and the entire sidewall of the third magnetoresistive random access memory.

4. The magnetoresistive random access memory structure as claimed in claim 1, wherein the first compressive stress layer covers the top surface of the first magnetoresistive random access memory, the top surface of the second magnetoresistive random access memory, and the top surface of the third magnetoresistive random access memory.

5. The magnetoresistive random access memory structure as claimed in claim 1, wherein there is no compressive stress on the sidewalls of the magnetic tunnel junction.

6. The magnetoresistive random access memory structure as claimed in claim 1, wherein the two tensile stress material blocks comprise silicon oxide.

7. The magnetoresistive random access memory structure as claimed in claim 1, wherein the first compressive stress layer covers the bottom of each of the tensile stress material blocks.

8. The magnetoresistive random access memory structure as claimed in claim 1, wherein the thickness of the second compressive stress layer is not greater than the thickness of the first compressive stress layer.

9. The magnetoresistive random access memory structure as claimed in claim 1, wherein the thickness of the first compressive stress layer is not less than 50 angstroms.

10. A method for fabricating a magnetoresistive random access memory structure, comprising: A dielectric layer is provided, on which a first magnetoresistive random access memory, a second magnetoresistive random access memory, and a third magnetoresistive random access memory are disposed. The second magnetoresistive random access memory is located between the first magnetoresistive random access memory and the third magnetoresistive random access memory. Two gaps are located between the first magnetoresistive random access memory and the second magnetoresistive random access memory, and between the second magnetoresistive random access memory and the third magnetoresistive random access memory, respectively. The second magnetoresistive random access memory includes a magnetic tunneling junction. A first compressive stress layer is formed to cover the first magnetoresistive random access memory, the second magnetoresistive random access memory, the third magnetoresistive random access memory, and the dielectric layer; A tensile stress material layer is formed to cover the first compressive stress layer and fill the two gaps; Remove the tensile stress material layer outside the two gaps to form two tensile stress material blocks respectively disposed in each of the gaps; as well as A second compressive stress layer is formed to cover the openings of each of the gaps and to contact the two tensile stress material blocks, wherein the absolute value of the tensile stress in each tensile stress material block is the same as the absolute value of the compressive stress of the first compressive stress layer, or the difference between them is less than a predetermined ratio.

11. The method for fabricating a magnetoresistive random access memory structure as claimed in claim 10, further comprising etching back the first compressive stress layer before forming the tensile stress material layer.

12. The method of fabricating a magnetoresistive random access memory structure as claimed in claim 11, wherein the first compressive stress layer is etched back to remove the first compressive stress layer from the top surface of the first magnetoresistive random access memory, the top surface of the second magnetoresistive random access memory, and the top surface of the third magnetoresistive random access memory.

13. The method of fabricating a magnetoresistive random access memory structure as claimed in claim 12, wherein the first compressive stress layer is etched back to remove the first compressive stress layer at the bottom of each of the gaps.

14. The method for manufacturing a magnetoresistive random access memory structure as described in claim 10, wherein the predetermined ratio is 30%.

15. The method for manufacturing a magnetoresistive random access memory structure as described in claim 10, wherein after the two tensile stress material blocks are formed, there is no compressive stress on the sidewalls of the magnetic tunnel junction.

16. The method for manufacturing a magnetoresistive random access memory structure according to claim 10, wherein the thickness of the second compressive stress layer is not greater than the thickness of the first compressive stress layer.

17. The method for manufacturing the magnetoresistive random access memory structure of claim 10, wherein the thickness of the first compressive stress layer is not less than 50 angstroms.

18. A magnetoresistive random access memory structure, characterized in that, Include: Dielectric layer; Multiple magnetoresistive random access memories are disposed on the dielectric layer and arranged in a column, wherein the multiple magnetoresistive random access memories include a last magnetoresistive random access memory disposed at the end of the column. A virtual magnetoresistive random access memory is disposed on the dielectric layer and located on one side of the last magnetoresistive random access memory. A gap is located between the dummy magnetoresistive random access memory and the last magnetoresistive random access memory; The first compressive stress layer contacts the sidewall of the gap; A tensile stress material block is placed in this gap; A second compressive stress layer covers the opening of the gap and contacts the tensile stress material block, wherein the absolute value of the tensile stress in each of the tensile stress material blocks is the same as the absolute value of the compressive stress in the first compressive stress layer, or the difference between them is less than a predetermined proportion; and Multiple metal interconnect structures are electrically connected to each of the magnetoresistive random access memories.

19. The magnetoresistive random access memory structure as claimed in claim 18, wherein each of the metal interconnect structures includes a first metal interconnect and a second metal interconnect that respectively contact the upper electrode and lower electrode of the corresponding magnetoresistive random access memory, and the dummy magnetoresistive random access memory is electrically connected only to one of the first metal interconnect and the second metal interconnect.

20. The magnetoresistive random access memory structure of claim 18, wherein the tensile stress material block comprises silicon oxide.

21. The magnetoresistive random access memory structure as claimed in claim 18, wherein the predetermined ratio is 30%.

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