Phase-locked loop circuit, corresponding radar sensor, vehicle and operating method

Abstract

Embodiments of this disclosure relate to phase-locked loop (PLL) circuits, corresponding radar sensors, vehicles, and operating methods. The PLL has a tunable resonator including an inductor and a variable capacitor coupled between a first node and a second node, and a capacitor coupled between the nodes. A control node is coupled to the variable capacitor and receives a control signal for tuning the resonator. A bias circuit biases the resonator to generate an output. A PFD circuit senses a timing offset of the output relative to a reference and asserts a first digital signal or a second digital signal based on the sign of the timing offset. A charge pump generates a control signal based on the first and second digital signals. A timer asserts a timing signal in response to a pulse sensed in a reset signal and deasserts the timing signal after a time interval. A calibrator, in response to the assertion of the timing signal, couples a selected capacitor between the first and second nodes according to the second digital signal.

Description

[0001] Priority requirements

[0002] This application claims priority to Italian Patent Application No. 102020000019765, filed on 7 August 2020, the contents of which are hereby incorporated in their entirety by reference to the fullest extent permitted by law. Technical Field

[0003] This disclosure relates to phase-locked loop (PLL) circuits. The embodiments described herein can be used, for example, in radar detection systems, such as those increasingly used in advanced driver assistance systems (ADAS) for automobiles. Background Technology

[0004] Short-range and / or long-range radar sensors can be placed around a vehicle (e.g., a car) to detect objects near and / or around the vehicle. Radar sensor data can be processed (e.g., by a processing unit within the vehicle) and used by systems within the vehicle to prevent accidents, prepare the vehicle for accidents, or take action to mitigate the severity of accidents. By way of example only, possible applications of advanced driver assistance systems include adaptive cruise control, pre-collision safety systems, blind spot detection, lane change assist, etc.

[0005] The standard (e.g., standard) operating frequency bands for short-range and long-range radar sensors are 77 GHz to 81 GHz and 76 GHz to 77 GHz, respectively. These bands correspond to wavelengths on the order of millimeters (millimeters, 1 mm = 10⁻¹⁰). -3 rice).

[0006] Frequency modulated continuous wave (FMCW) radar systems can be used in millimeter-wave radar applications in the automotive industry. The working principle of FMCW radar is as follows: Figure 1 exemplified, Figure 1 This is an example diagram illustrating the possible time-frequency relationship of radar signals in an FMCW radar system.

[0007] like Figure 1 As shown, the FMCW radar system can transmit (e.g., periodically) signals TX (such as...). Figure 1 (As shown by the solid line in the image), also known as "linear frequency modulation," its frequency sweeps (e.g., linearly) over a certain time interval T. m (For example, its duration T) m In the range of 10 μs to 40 μs, 1 μs = 10 -6The frequency range F above s). For example, for short-range radar, the frequency range F can be the 4-GHz range between 77GHz and 81GHz, or for long-range radar, the frequency range F can be the 1-GHz range between 76GHz and 77GHz.

[0008] The FMCW radar system can then receive the corresponding echo signal RX generated by the reflection of the transmitted signal TX at the target object. Figure 1 (As shown by the dotted line in the text).

[0009] like Figure 1 As shown, when the frequency of the transmitted signal TX equals the reference value f1, the FMCW radar system can detect the first instant t1, where f1 is included in the frequency range F. When the frequency of the echo signal RX equals the reference value f1, the FMCW radar system can then detect the second instant t2, and at the second instant t2, detect the frequency f2 of the transmitted signal TX. Therefore, the FMCW radar system can calculate the frequency value f. R It is the difference between frequency f2 and reference frequency f1.

[0010] According to the following equation, the time interval t between the first instant t1 and the second instant t2 is... R It is a function of (e.g., proportional to) the distance R between the radar sensor and the target object, where c is the propagation speed of the radar signals TX and RX:

[0011]

[0012] like Figure 1 As shown, the slope of the "linear frequency modulation" of the radar signal TX can be calculated using the following equation:

[0013]

[0014] Therefore, the distance R between the radar sensor and the target object can be calculated as follows:

[0015]

[0016] A phase-locked loop (PLL) circuit, including a voltage-controlled oscillator (VCO), can be used in an FMCW radar detection system to generate a variable-frequency signal (e.g., a "linear frequency modulation" signal). The VCO may include a tunable LC resonant circuit.

[0017] The use of calibration techniques in PLL circuits to adjust the tuning curve within the target frequency bandwidth F is well known in the art.

[0018] For example, known calibration techniques may include adjusting the VCO output frequency by applying a control voltage from a voltage-controlled oscillator to an LC resonant circuit under closed-loop conditions to compensate for frequency variations caused by process, voltage, and temperature (PVT) variations. For example, known calibration techniques may include sensing the VCO control voltage and selectively enabling / disabling one or more cell capacitors of a capacitor array for the LC resonant circuit based on the sensed VCO control voltage. The resulting calibration time can be lengthy, potentially requiring a delay equal to (at least) the PLL settling time in each calibration step (e.g., one PLL settling time for each insertion or activation of a cell capacitor in the capacitor array). Therefore, in conventional automotive radar applications, calibration routines can only be performed when the radar system is started.

[0019] Therefore, an improved calibration strategy for the voltage-controlled oscillator in the PLL circuit is expected. Summary of the Invention

[0020] The purpose of one or more embodiments is to facilitate the provision of such improved solutions.

[0021] According to one or more embodiments, such an object can be achieved by a circuit having the features set forth in the appended claims.

[0022] One or more embodiments may involve a corresponding radar sensor.

[0023] One or more embodiments may relate to corresponding vehicles.

[0024] One or more embodiments may relate to methods of operating corresponding circuits.

[0025] According to one or more embodiments, a circuit (e.g., a PLL circuit) is provided, which may include: a tunable resonant circuit having a first node and a second node and including an inductor coupled between the first node and the second node, a variable capacitor coupled between the first node and the second node, and a set of capacitors selectively coupled between the first node and the second node; a control node coupled to the variable capacitor, the control node being configured to receive a control signal, wherein the tunable resonant circuit is tunable according to the control signal; a bias circuit coupled to the tunable resonant circuit and configured to bias the tunable resonant circuit to generate a variable frequency output signal between the first node and the second node; and a phase frequency detector circuit sensitive to an input reference signal and the variable frequency output signal, and configured to generate a first digital control signal based on a timing offset of the variable frequency output signal relative to the input reference signal. The system includes a first digital control signal asserted to indicate a first operating state in which the timing offset has a first sign, and a second digital control signal asserted to indicate a second operating state in which the timing offset has a second sign opposite to the first sign; a charge pump circuit and a filter circuit configured to generate control signals based on the first and second digital control signals; a timer circuit sensitive to a reset signal and configured to generate a timing signal, wherein the timing signal is asserted in response to a pulse sensed in the reset signal, and the timing signal is deasserted after a time interval from the start of the sensed pulse; and a calibration circuit configured to selectively couple a selected capacitor from the group of capacitors between a first node and a second node in response to the timing signal being asserted.

[0026] Therefore, one or more embodiments can facilitate rapid calibration of the PLL circuitry, for example, suitable for performing between subsequent linear frequency modulation signals during the operation of an automotive radar sensor. Attached Figure Description

[0027] One or more embodiments will now be described by way of example only with reference to the accompanying drawings, wherein:

[0028] The above description Figure 1 This is an example diagram illustrating the possible time-frequency relationships of radar signals in a frequency-modulated continuous wave (FMCW) radar system.

[0029] Figure 2 This is an exemplary circuit block diagram of a PLL circuit that may be used in a radar sensor.

[0030] Figure 3 This is an exemplary circuit block diagram of a voltage-controlled oscillator circuit that may be used in a PLL circuit.

[0031] Figure 4A and Figure 4BThis is an example diagram illustrating possible time-frequency relationships of signals in one or more embodiments of this specification.

[0032] Figure 5 This is an exemplary circuit block diagram of a PLL circuit according to one or more embodiments of this description.

[0033] Figure 6 This is an exemplary circuit block diagram of another PLL circuit according to one or more embodiments of this description.

[0034] Figures 7A to 7E This is an exemplary diagram illustrating the possible behavior of signals in one or more embodiments of this specification.

[0035] Figure 8 This is an exemplary circuit block diagram illustrating possible implementation details of one or more embodiments of this specification, and

[0036] Figure 9 This is an exemplary circuit block diagram of a radar architecture in a vehicle according to one or more embodiments of this description. Specific Implementation

[0037] In the following description, one or more specific details are shown to provide a thorough understanding of examples of embodiments of this specification. Embodiments may be obtained without one or more specific details, or by utilizing other methods, components, materials, etc. In other instances, certain structures, materials, or operations have not been shown or described in detail so as not to obscure certain aspects of the embodiments.

[0038] References to "an embodiment" or "one embodiment" within the framework of this specification are intended to indicate that a particular configuration, structure, or feature described with respect to that embodiment is included in at least one embodiment. Therefore, phrases such as "in one embodiment" or "in one embodiment" that may appear at one or more points in this specification do not necessarily refer to the same embodiment. Furthermore, in one or more embodiments, particular conformations, structures, or features may be combined in any suitable manner.

[0039] The headings / references used herein are provided for convenience only and therefore do not limit the scope of protection or the scope of embodiments.

[0040] For simplicity, similar parts or elements are indicated by similar reference numerals / numbers throughout the accompanying figures. For the sake of brevity, the corresponding descriptions of each figure will not be repeated.

[0041] As a detailed description of exemplary embodiments, reference can be made first to... Figure 2 .

[0042] Figure 2This is an exemplary circuit block diagram of a PLL circuit 20 that may be used in a radar sensor. For example, the PLL circuit 20 may rely on a suitable calibration strategy.

[0043] PLL circuit 20 may include: an input node 200 configured to receive an input reference signal f ref Phase frequency detector (PFD) circuit 202, configured to receive input reference signal f ref The first input; a charge pump (CP) circuit 204, coupled to the output of the phase frequency detector circuit 202; a low-pass filter circuit 206, coupled to the output of the charge pump circuit 204, and configured to generate a control signal V at the corresponding output node 208. C Voltage-controlled oscillator (VCO) circuit 210, coupled at node 208 and controlled by signal V C The voltage-controlled oscillator circuit 210 is configured to generate an output signal f at the output node 212. O ; and a feedback loop configured to provide an output signal f at the second input of the phase frequency detector circuit 202. O .

[0044] The feedback loop may optionally include a frequency divider circuit 214.

[0045] like Figure 2 As shown, the voltage-controlled oscillator circuit 210 may include an active core 216 (e.g., a bias circuit) coupled to the LC resonant circuit 218.

[0046] The active core 216 may include a pair of transistors M1 and M2, such as metal-oxide-semiconductor (MOS) field-effect transistors. Figure 2 As shown, the first transistor M1 may have a source terminal coupled to a voltage reference node (e.g., ground GND) and a drain terminal coupled to a first terminal 219a of the LC resonant circuit 218, and the second transistor M2 may have a source terminal coupled to the voltage reference node GND and a drain terminal coupled to a second terminal 219b of the LC resonant circuit 218. The control (gate) terminal of the first transistor M1 may be coupled to the drain terminal of the second transistor M2, and the control (gate) terminal of the second transistor M2 may be coupled to the drain terminal of the first transistor M1.

[0047] like Figure 2 As shown, the LC resonant circuit 218 may include an inductor and a capacitor coupled between the first terminal 219a and the second terminal 219b.

[0048] As shown herein, an inductor assembly may include an inductor L, and a capacitor assembly may include one or more (e.g., a pair) variable capacitors or transformers C.V For example, a variable capacitor or variable capacitor is connected in series between terminals 219a and 219b.

[0049] As shown in this article, the control signal V C It can be applied to two variable containers C V The middle node is at position 224.

[0050] like Figure 2 As shown, the LC resonant circuit 218 may further include components coupled in parallel to one or more transformers C. V A capacitor array (or capacitor bank) 220. The capacitor array 220 can be configured to receive a set of configuration signals from an analog-to-digital converter circuit 222. The analog-to-digital converter 222 can be coupled to node 208 to receive control signals V. C For example, analog-to-digital converter 222 may include an N-bit ADC, and capacitor array 220 may include 2 N Individual capacitors.

[0051] A configuration signal (e.g., an N-bit binary signal generated by ADC 222) can be used to activate and deactivate a set of switches that are respectively coupled to capacitors in capacitor array 220, so that the total capacitance of the capacitor assembly of LC resonant circuit 218 can be changed to tune the output frequency of voltage-controlled oscillator 210.

[0052] In such Figure 2 In the PLL circuit 20 shown, the analog-to-digital converter 222 and capacitor array 220 can be used to perform adjustments (e.g., calibration) to the tuning curve of the LC resonant circuit 218 to compensate for the effects of process, voltage, and / or temperature variations. This calibration strategy can advantageously avoid the use of large capacitors that may result in high power consumption and high phase noise.

[0053] like Figure 3 As shown, Figure 3 This is an exemplary circuit block diagram detailing possible implementations of the voltage-controlled oscillator circuit 210 used in the PLL circuit 20. The analog-to-digital converter 222 may include a successive approximation analog-to-digital converter (SA-ADC) configured to calibrate an LC resonant circuit.

[0054] A successive approximation analog-to-digital converter may include a comparator circuit 300 having a connection to node 208 to receive a control signal V. C The first (e.g., non-inverting) input is coupled to node 302 to receive the reference voltage signal V. R The second (e.g., inverting) input. For example, the reference voltage signal V. R It can be equal to the power supply voltage V of PLL circuit 20. CC Half of (i.e., V)R =V CC / 2). The successive approximation analog-to-digital converter may further include a successive approximation register (SAR) 304, which is configured to receive the output signal from the comparator circuit 300 and provide an N-bit configuration signal to the capacitor array 220.

[0055] like Figure 3 As shown, the first switch S FT It can be arranged at the configuration node of LC resonant circuit 218 (here, in variable capacitor C). V In the propagation path between the intermediate node 224 and the first input (e.g., node 208) of the comparator circuit 300, and the second switch S CT It can be arranged in the propagation path between the configuration node of the LC resonant circuit 218 and the second input (e.g., node 302) of the comparator circuit 300.

[0056] Therefore, as Figure 3 The calibration and tuning of the voltage-controlled oscillator circuit 210 shown can be performed in two steps to avoid instability.

[0057] In the calibration procedure, the first switch S FT Disconnect, and the second switch S CT Close. (One or more) variable containers C V A constant capacitance value (e.g., an average value) is provided, and the ADC converter 222 calibrates the LC resonant circuit 218 by enabling a selected subset of capacitors in the capacitor array 220.

[0058] During the tuning process, the first switch S FT Close, and the second switch S CT Disconnect. (One or more) variable containers C V Connected to control voltage V C And change its capacitance value to provide frequency tuning within the calibrated tuning curve.

[0059] The solution described above may not be satisfactory because the calibration steps may take a long time (e.g., N times the setup time of the PLL circuit), and therefore, calibration may only be performed when the radar system is started.

[0060] Therefore, one or more embodiments may be intended to provide an improved calibration system for PLL circuits used, for example, in automotive radar applications.

[0061] In this regard, one or more embodiments may rely on dynamic calibration performed during the dead time DT between subsequent "linear frequency modulation" signals, such as Figure 4A and Figure 4B As shown.

[0062] Figure 4A This is an example diagram illustrating possible time-frequency relationships of radar transmitted signals TX in one or more embodiments. As previously mentioned, the transmitted signal TX may include multiple "linear frequency modulations" (i.e., at a lower frequency f). min With higher frequency f max The frequency scan between the two frequencies has a duration of T. m (For example, approximately 10 μs, 1 μs = 10) -6 The duration of the dead time DT separating the subsequent linear frequency modulation can be, for example, approximately 2 μs.

[0063] The duration of the dead time DT, or "inter-linear modulation idle time" (which may include a calibration phase), can depend on the setup time of the PLL circuit. In other words, during the dead time, before starting a new frequency scan (e.g., a new linear modulation), the operating frequency of the LC resonant circuit can be reduced from its maximum value f. max to the minimum value f min This is to stabilize the PLL circuit.

[0064] Figure 4B The output signal f generated by the voltage-controlled oscillator during the dead time DT in one or more embodiments O Example diagram of possible time-frequency relationships (note, Figure 4A and Figure 4B The time scales are therefore different. For example... Figure 4B As shown, the output signal f O The frequency can be quantized or stepped from f max Reduce to f min For example, by activating the capacitors in the capacitor array 220 progressively (or sequentially).

[0065] Figure 5 This is an exemplary circuit block diagram of certain components of a PLL circuit 50 according to one or more embodiments, such as for a radar sensor.

[0066] In one or more embodiments, the PLL circuit 50 may include: an input node 500 configured to receive an input reference signal f ref (For example, at a frequency of 100MHz); Phase Frequency Detector (PFD) circuit 502, configured to receive input reference signal f refThe first inputs, the phase frequency detector circuit 502, are configured (in a conventional manner) to generate digital control signals UP and DOWN; the charge pump (CP) circuit 504, coupled to the output of the phase frequency detector circuit 502 and configured to receive the digital control signals UP and DOWN from the output of the phase frequency detector circuit 502; and the low-pass filter circuit 506, coupled to the output of the charge pump circuit 504 and configured to generate control signals V at the corresponding output node 508. C Voltage-controlled oscillator (VCO) circuit 510, coupled to node 508 and controlled by signal V C The voltage-controlled oscillator circuit 510 is configured to generate an output signal f. O (For example, between nodes 519a and 519b); and a feedback loop configured to provide an output signal f at the second input of the phase frequency detector circuit 502. O .

[0067] The feedback loop may optionally include a frequency divider circuit 514.

[0068] like Figure 5 As shown, the low-pass filter circuit 506 may include a filter capacitor C coupled between node 508 and the reference voltage node GND. F .

[0069] like Figure 5 As shown, the voltage-controlled oscillator circuit 510 may include an active core 516 (e.g., a bias circuit) coupled to the LC resonant circuit 518.

[0070] The active core 516 may include a pair of transistors M1 and M2, such as MOS field-effect transistors. Figure 5 As shown, the first transistor M1 may have a source terminal coupled to a reference voltage node GND (e.g., ground) and a drain terminal coupled to a first terminal 519a of the LC resonant circuit 518, and the second transistor M2 may have a source terminal coupled to the reference voltage node GND and a drain terminal coupled to a second terminal 519b of the LC resonant circuit 518. The control (gate) terminal of the first transistor M1 may be coupled to the drain terminal of the second transistor M2, and the control (gate) terminal of the second transistor M2 may be coupled to the drain terminal of the first transistor M1.

[0071] like Figure 5 As shown, the LC resonant circuit 518 may include an inductor and a capacitor coupled between a first terminal 519a and a second terminal 519b of the LC resonant circuit 518.

[0072] like Figure 5As shown, an inductor assembly may include one or more inductors L'. For example, an inductor assembly may include a pair of inductors L', with a power supply voltage V. DD It is applied at the node between the two inductors L'. As an example, the supply voltage V... DD It can be the power supply voltage used for logic circuits, for example, equal to about 1V.

[0073] like Figure 5 As shown, a capacitor assembly may include one or more (e.g., a pair) variable capacitors or transformers C coupled in series. V As shown in this article, the control signal V C It can be applied to two variable containers C V The middle node is at position 524.

[0074] like Figure 5 As shown, the LC resonant circuit 518 may further include components coupled in parallel to one or more transformers C. V 520 capacitor arrays (or capacitor banks).

[0075] The capacitor array 520 can be configured to receive a set of configuration signals from the calibration circuit 52. The configuration signals can be used to activate and deactivate a set of switches respectively coupled to the capacitors in the capacitor array 520, such that the total capacitance of the capacitor assembly of the LC resonant circuit 518 can be changed to tune the output frequency of the voltage-controlled oscillator 510.

[0076] In one or more embodiments, calibration circuitry 52 may include register 522 (e.g., a 12-bit register). Register 522 may include a serial-in parallel-out (SIPO) register. SIPO register 522 may have a data input D configured to be coupled to a voltage signal that provides a high logic value, such as a power supply voltage V. DD The SIPO register 522 may have a reset input R configured to receive a reset signal R. The SIPO register 522 may also have a clock input ck configured to receive a digital (e.g., pulse) signal generated by an integrator circuit.

[0077] In one or more embodiments, the reset signal R may include a pulse corresponding to the start of the dead time interval DT between the transmitted linear frequency modulated signals.

[0078] like Figure 5 As shown, the integrator circuit may include a digital integrator implemented by counter circuit 526. Counter circuit 526 may have a reset input R configured to receive a reset signal R and a clock input ck configured to receive a digital (e.g., pulse) signal generated at the output of logic gate 528. For example, counter circuit 526 may have a counter modulo 2... 3That is, it can generate at its output the number 2 of pulses received at the corresponding clock input ck. 3 The pulse resulting from =8.

[0079] like Figure 5 As shown, logic gate 528 may have a first input configured to receive an output signal from edge-triggered D flip-flop circuit 530. D flip-flop circuit 530 may have a data input D configured to be coupled to a voltage signal providing a high logic value, such as a power supply voltage V. DD The D flip-flop circuit 530 may have a clock input ck, which is configured to receive a digital control signal DOWN generated by the phase frequency detector circuit 502. The D flip-flop circuit 530 may have a reset input R, which is configured to receive a reset signal R' from the output of the OR logic gate 532.

[0080] like Figure 5 As shown, the OR logic gate 532 may have a first input configured to receive a digital control signal UP generated by the phase frequency detector circuit 502 and a second input configured to receive a reset signal R. Therefore, the reset signal R' may include pulses corresponding to the pulses in the reset signal R and the pulses in the control signal UP.

[0081] like Figure 5 As shown, logic gate 528 may have a second input configured to receive a timing signal TS from timer circuit 54.

[0082] For example, the timing signal TS can be generated as a transformed copy of the output signal from the counter circuit 536 (by the converter circuit 534).

[0083] like Figure 5 As shown, the counter circuit 536 may have a reset input R configured to receive a reset signal R and a clock input ck configured to receive a digital (e.g., pulse) signal generated at the output of logic gate 538. For example, the counter circuit 536 may have a counter modulo 2 7 That is, it can generate at its output the number 2 of pulses received at the corresponding clock input ck. 7 =128 is the result of the pulse.

[0084] like Figure 5 As shown, the AND logic gate 538 can be configured to receive a reference signal f. ref A first input (e.g., via coupling to node 500) and a second input configured to receive a timing signal TS (e.g., via a feedback loop of timer circuit 54).

[0085] like Figure 5As shown, the PLL circuit 50 may include a switch S V The switch is configured to selectively couple the control node 508 of the voltage-controlled oscillator 510 to a reference control voltage V. C,min Node 540.

[0086] Switch S V It can be controlled by a timing signal TS. For example, switch S. V It can be closed during the calibration phase of PLL circuit 50 (e.g., during the dead time DT between linear frequency modulation signals) and can be opened during the transmission phase of signal TX.

[0087] Therefore, in one or more embodiments, counter circuit 536 can be used to set the timing of the calibration phase. Calibration can begin with a reset pulse in reset signal R at the start of the dead time. Dynamic calibration can rely on the (digital) integration of control signal DOWN, for example, using pulses in signal DOWN to advance counter 526 (e.g., 2). 3 (A counter). The output signal from counter 526 can be used to trigger a shift in register 522, thereby generating a thermometer code (e.g., a 12-bit thermometer code) for activating (e.g., via a corresponding switch insertion) the capacitors in capacitor array 520. For example, each shift of the value of register 522 can cause a variable capacitor C in the capacitor array 520 to be coupled in parallel to the LC resonant circuit 518. V .

[0088] In one or more embodiments, the counter circuit 536 (e.g., 2) 7 (A counter) can define the entire calibration time.

[0089] Figure 6 This is an exemplary circuit block diagram of another PLL circuit 60 according to one or more embodiments, such as for a radar sensor.

[0090] and Figure 5 The circuits shown are different. Figure 6 The circuit shown can rely on analog calibration circuit 62. Therefore, Figure 6 The circuit shown may include a main charge pump circuit 504a and an auxiliary charge pump circuit 504b, which are coupled to a PFD circuit 502 to receive signals UP and DOWN. Note that, although for ease of illustration... Figure 5 The main charge pump circuit 504a and the auxiliary charge pump circuit 504b are shown in different locations, but they can be coupled to the output of the same PFD circuit 502.

[0091] like Figure 6As shown, register 522 may include a serial-in parallel-out (SIPO) register. SIPO register 522 may have a data input D, which is configured to be coupled to a voltage signal providing a high logic value, such as a power supply voltage V. DD SIPO register 522 may have a reset input R configured to receive a reset signal R. SIPO register 522 may have a clock input ck configured to receive a digital (e.g., pulse) signal generated by AND logic gate 600.

[0092] like Figure 6 As shown, the AND logic gate 600 may have a first input configured to receive the output signal from the comparator circuit 602. The comparator circuit 602 may be configured to receive the threshold voltage signal V received at the corresponding first (e.g., non-inverting) input 604. TH The voltage signal V received at the corresponding second (e.g., inverting) input 606 CP Compare them.

[0093] like Figure 6 As shown, the auxiliary charge pump circuit 504b can provide an auxiliary pulse current I to node 606. CP,A Auxiliary current I CP,A It can be used to couple to node 606 and provide power supply voltage V DD The integrator capacitor C between the power supply voltage nodes C Charging. Switch S C It can be used with integrator capacitor C C Parallel configuration to selectively adjust the integrator capacitor C C Discharge.

[0094] Switch S C It can be controlled by the integral signal IS generated at the output of timer circuit 64.

[0095] like Figure 6 As shown, the timer circuit 64 may include an OR logic gate 608 configured to generate an integral signal IS. The OR logic gate 608 may have a first input configured to receive a reset signal R and a signal f generated at the output of the frequency divider circuit 610. ck The second input.

[0096] Frequency divider circuit 610 (e.g., factor 2) 3 A frequency divider of 8 can have a reset input R configured to receive a reset signal R and a reference signal f. ref The clock input ck (e.g., the same reference signal for the PLL circuit). In one or more embodiments, a reference signal f is provided at the clock input ck of the frequency divider circuit 610.ref This could be advantageous because it may not require an internal clock generator.

[0097] like Figure 6 As shown, the AND logic gate 600 may have a second input configured to receive a timing signal TS, for example, a transformed copy of the output signal from the counter circuit 614 (e.g., generated by the converter circuit 612).

[0098] like Figure 6 As shown, the counter circuit 614 may have a reset input R configured to receive a reset signal R and a clock input ck configured to receive a signal fck generated at the output of the frequency divider circuit 610. For example, the counter circuit 614 may have a counter modulo 2 4 That is, it can generate at its output the number 2 of pulses received at the corresponding clock input ck. 4 =16 results in a pulse.

[0099] like Figure 6 As shown, the PLL circuit 60 may include a switch S V The switch is configured to selectively couple the control node 508 of the voltage-controlled oscillator 510 to a reference control voltage V. C,min Node 540.

[0100] Switch S V It can be controlled by a timing signal TS. For example, switch S. V It can be closed during the calibration phase of PLL circuit 60 (e.g., during the dead time between linear frequency modulation signals) and can be opened during the transmission phase of signal TX.

[0101] Therefore, in one or more embodiments, the counter circuit 614 can be used to set the timing of the calibration phase. Calibration can begin with a reset pulse at the start of the dead time.

[0102] like Figure 6 The dynamic calibration based on analog integration shown can utilize the current I generated by the auxiliary charge pump circuit 504b. CP,A The sign is used to trigger the comparator circuit 602 of the drive register 522.

[0103] In such Figure 6 In one or more embodiments shown, in the auxiliary current I CP,AThe commutation of comparator circuit 602 after integrating a specific number of current pulses can trigger a shift in register 522, thereby generating a thermometer code (e.g., a 12-bit thermometer code) for activating the capacitors in capacitor array 520. For example, each shift of the value of register 522 can cause a single capacitor in capacitor array 520 to be coupled in parallel to a variable capacitor C in LC resonant circuit 518. V .

[0104] The speed of the analog integrator can benefit from the reliance on the auxiliary charge pump circuit 504b, as long as the current I... CP,A Capacitor C C and threshold voltage V TH The size can be adjusted appropriately to set the switching time T of comparator 602. SW Consistent with the linear frequency modulation dead time DT. For example, based on the following equation, once the switching time T is defined... SW Then the current I can be adjusted. CP,A and capacitor C C Size:

[0105]

[0106] In such Figure 6 In one or more embodiments shown, the frequency divider circuit 610 can define a clock signal f ck The clock cycle. Clock signal f ck The first half-cycle can be used to discharge capacitor C C And the clock signal f ck The second half of the cycle can be used for charge integration until comparator 602 switches.

[0107] In such Figure 6 In one or more embodiments shown, the counter circuit 614 (e.g., 2) 4 (A counter) can define the entire calibration time.

[0108] Figures 7A to 7E This is an exemplary diagram illustrating the possible temporal evolution of various signals in one or more embodiments. Specifically, Figure 7A This example illustrates the time-frequency relationship of the radar's transmitted signal TX. Figure 7B This example illustrates the time-amplitude relationship of the reset signal R. Figure 7C Example of a reference signal f received at input node 500 of PLL circuit 50 or 60 ref The temporal relationship, Figure 7D Example of auxiliary current I provided by auxiliary charge pump circuit 504B CP,A The temporal relationship, and Figure 7E Example of a clock signal f generated at the output of frequency divider circuit 610 ckThe temporal and amplitude relationship. Note that... Figure 7A The time scale is different Figures 7B to 7E The time scale is shown in the following figure, which provides a magnified view of the dead time interval DT between two subsequent linear frequency modulated signals.

[0109] like Figure 7A As shown, the duration T of the linear frequency modulated signal ramp m It can be in the range of 10μs to 40μs, and the duration of the dead time DT can be in the range of 2μs to 10μs.

[0110] like Figure 7B As shown, a reset pulse can be generated in the reset signal R at the start of the dead time DT or shortly thereafter to trigger (or enable) the calibration phase.

[0111] like Figure 7C As shown, the reference signal f provided at input node 500 of the PLL circuit ref A reference time can be provided. This is only by way of a non-limiting example; the reference signal f... ref It can have 10ns (1ns = 10) -9 The period of s), that is, the frequency of 100MHz.

[0112] like Figure 7D As shown, the auxiliary current I generated by the auxiliary charge pump circuit 504b CP,A This can include a duration of, for example, 2 ns and a reference signal f. ref Pulses with the same period.

[0113] like Figure 7E As shown, the clock signal f generated at the output of the frequency divider circuit 610 ck Period T ck It can be equal to 80ns (i.e., the reference signal f). ref The frequency divider circuit 610 has a modulo 2 period of 8 times, provided that the frequency divider circuit 610 has a modulo 2 period. 3 Period T ck Half of it (e.g., 40 ns) can be used for the integrator capacitor C. C Discharge, and the period T ck The other half (e.g., another 40 ns) can be used for integration.

[0114] Therefore, by way of a non-limiting example only, in the case of the reference signal f ref The frequency is 100MHz, and assuming the auxiliary current I... CP,A With four pulses, each lasting 2 ns, the total calibration time can be equal to 1.28 μs. The total calibration time can also be equal to the clock signal f. ck16 times the period, as long as the counter circuit 614 has modulo 2 4 .

[0115] Both digital and analog calibration techniques (e.g., as referenced separately) Figure 5 and Figure 6 (As shown) can all be applied to cellular applications. The first case may involve adjusting the filter capacitor C. F and (one or more) variable containers C V Precharge to control voltage V C The average value (e.g., choosing V) C,min (equal to the average value).

[0116] For example, to achieve a higher response speed, another solution can be adopted. This second case could involve adjusting the filter capacitor C. F and (one or more) variable containers C V Precharged to near control voltage V C The final value of .

[0117] This second solution can be achieved by replacing switch S with an A / D flash memory converter. V To achieve, such as Figure 8 As shown.

[0118] like Figure 8 As shown, one or more embodiments may include a voltage divider network or voltage ladder, the voltage divider network or voltage ladder including components connected in series with the supply voltage V. DD A set of resistors R0, ..., R1 between the resistor and ground GND N To generate a set of increasing voltage levels V C1 ... V CN .

[0119] Control node 508 of voltage-controlled oscillator 510 (filter capacitor C) F and variable container C V (Coupled to it) can be done through the corresponding switch S V1 S VN Selectively coupled to voltage level V C1 ... V CN Any one of them. Switch S V1 S VN It can be controlled by a corresponding control signal generated by decoding the most significant bit of the divider programming word (or coarse divider word) CDW of the divider circuit 514 in the feedback loop of PLL circuit 50 or 60 at decoder circuit 800.

[0120] For example, if a change in the communication channel is desired, the frequency divider 514 can modify its division ratio by changing the "frequency divider programming word" and can return the bit sequence to the decoder circuit 800. Therefore, the decoder can pass a portion of the voltage step through switch S. V1 S VN So that (one or more) variable containers C V and filter capacitor C F It can be preloaded to a value close to the final value of the control voltage. Once the (one or more) variable capacitors and filter capacitors are preloaded, the PLL loop can be closed, and the (one or more) variable capacitors can be connected via the compensation signal f. ref with f O The remaining frequency difference between them is used to perform "fine-tuning".

[0121] Therefore, in one or more embodiments, the filter capacitor C F and (one or more) variable containers C V It can be connected to one of the voltage levels generated by a series of resistors, which corresponds to the transition of the most significant bit (MSB) of the divider programming word.

[0122] Note that, without departing from the scope of this disclosure, the inductor and capacitor components in the LC resonant circuit 518 can be arranged in various other ways (e.g., compared to) Figure 2 , Figure 5 and Figure 6 (Different arrangements are shown). For example, one or more embodiments may include one of a Hartley oscillator, a Colpitts oscillator, and a Clap oscillator.

[0123] Note that while applicable to performing the calibration phase during the dead time between linear frequency modulation signals, one or more embodiments may involve performing the calibration phase when the PLL circuit is started.

[0124] like Figure 9 As shown, one or more embodiments can be applied to a vehicle V. The vehicle V may include a power system 900, a control unit 902 (e.g., a microcontroller unit, MCU), and a radar sensor 904.

[0125] The radar sensor 904 may include a PLL circuit 906, a transmitter circuit 908, a receiver circuit 910, a transmitter antenna 912, and a receiver antenna 914.

[0126] The power supply system 900 can provide a power supply voltage (e.g., equal to 1V or 3.3V) to the radar sensor 904 and a power supply voltage (e.g., equal to 3.3V or 5V) to the control unit 902.

[0127] Control unit 902 can provide input reference signal f ref To control the PLL circuit 906. The PLL circuit 906 can provide a variable frequency signal f O This drives the transmitter circuit 908 (e.g., according to an FMCW driving scheme). The transmitter circuit can therefore bias the transmitter antenna 912 to transmit the transmitted signal TX.

[0128] The receiver antenna 914 can receive the echo signal RX and provide it to the receiver circuit 910, which processes information about the transmitted and received signals to provide information about the distance to the target object.

[0129] Therefore, one or more embodiments can provide one or more of the following advantages: rapid dynamic calibration suitable for use in automotive radar sensors, provided that one or more embodiments do not require a delay equal to N times the PPL circuit set-up time; dynamic compensation for temperature changes; and adjustment of the filter capacitor C during the dead time. F Perform rapid pre-charging (via switch S) V Or switch S V1 S VN This can lead to a faster response from the PLL circuit; accuracy is improved by performing dynamic calibration during the dead time between subsequent linear frequency modulation signals; and accuracy is improved at the minimum frequency value f after sweeping the full frequency ramp during the linear frequency modulation signal. min It enables rapid relocation and faster data acquisition due to the reduced dead time duration between subsequent linear frequency modulation signals.

[0130] Note that temperature variations can cause deviations in the PLL output frequency. The calibration technique disclosed herein facilitates the compensation process and addresses power supply and temperature variations by inserting capacitance into the capacitor array of the LC resonant circuit. Specifically, the calibration technique disclosed herein can be dynamic, i.e., it can be performed between one linear frequency modulation (LFM) cycle and another. By acquiring hundreds of LFM cycles for each radar scan, one or more embodiments facilitate constant compensation for temperature variations, a characteristic not found in conventional systems, which perform calibration at startup and cannot compensate for variations occurring after and throughout the operating time. In one or more embodiments, temperature compensation can be precise, provided it is performed at the same period as the LFM cycle (e.g., 10 μs to 40 μs). Temperature variations occurring within a single LFM cycle are negligible.

[0131] As illustrated herein, a circuit such as a PLL circuit (e.g., 50, 60) may include: a tunable resonant circuit (e.g., 518) having a first node (e.g., 519a) and a second node (e.g., 519b) and including an inductor (e.g., L') coupled between the first node and the second node, and a variable capacitor (e.g., C) coupled between the first node and the second node. V ) and a set of capacitors (e.g., 520) selectively coupled between the first node and the second node; a control node (e.g., 508) coupled to the variable capacitor, the control node being configured to receive a control signal (e.g., V C The tunable resonant circuit is tunable according to the control signal; a bias circuit (e.g., 516) is coupled to the tunable resonant circuit and configured to bias the tunable resonant circuit to generate a variable frequency output signal (e.g., f) between the first node and the second node. O ); Phase frequency detector circuit (e.g., 502), for input reference signal (e.g., f ref The variable frequency output signal is sensitive to and configured to generate a first digital control signal (e.g., UP) and a second digital control signal (e.g., DOWN) based on a timing offset of the variable frequency output signal relative to the input reference signal. The first digital control signal is asserted to indicate a first operating state in which the timing offset has a first sign (e.g., indicating that the variable frequency output signal is phase-delayed relative to the input reference signal), and the second digital control signal is asserted to indicate a second operating state in which the timing offset has a sign consistent with the first digital control signal. A second symbol corresponding to the input reference signal (e.g., indicating that the input reference signal is phase-delayed relative to the variable frequency output signal); a charge pump circuit (e.g., 504; 504a) and a filter circuit (e.g., 506) are configured to generate the control signal according to the first digital control signal and the second digital control signal; a timer circuit (e.g., 54; 64) is sensitive to a reset signal (e.g., R) and is configured to generate a timing signal (e.g., TS), wherein the timing signal is asserted in response to a pulse sensed in the reset signal and a time interval (e.g., T) begins from the sensed pulse. ck / 2) is then deasserted; and calibration circuitry (e.g., 52; 62) is configured to selectively couple a selected capacitor in the capacitor bank between the first node and the second node according to the second digital control signal in response to the timing signal being asserted.

[0132] As shown herein, the circuit can be configured to: generate the variable frequency output signal comprising a frequency scan separated by dead time (e.g., DT); and generate a pulse in the reset signal at the start of the dead time.

[0133] As shown in this document, the circuit may include a switch (e.g., S). V The switch is configured to selectively couple the control node to a reference control voltage (e.g., V) in response to an assertion of the timing signal. C,min ).

[0134] As shown herein, the circuit may include: a feedback loop configured to provide the variable frequency output signal to the phase frequency detector circuit, wherein the feedback loop includes a frequency divider circuit (e.g., 514); and a voltage divider network (e.g., V...). DD R0, ..., R N ), configured to generate a different set of reference control voltages (e.g., V C1 ... V CN ); and a set of switches (e.g., S ... V1 S VN The control node is configured to selectively couple the control node to a corresponding reference control voltage from the set of different reference control voltages based on the divider programming word (e.g., CDW) of the divider circuit.

[0135] As shown herein, the calibration circuit can be configured to count the number of pulses generated during the second digital control signal, and in response to the number of counted pulses in the second digital control signal reaching a threshold, to couple the set of capacitors between the first node and the second node.

[0136] As shown herein, the calibration circuit may include a digital counter circuit (e.g., 526) configured to count the number of pulses occurring in the second digital control signal.

[0137] As shown herein, the calibration circuit may include: a further charge pump circuit (e.g., 504b) configured to generate a pulsed current signal (e.g., I0) based on the first digital control signal and the second digital control signal. CP,A ); Integrator circuit (e.g., S C C C ), configured to generate a signal (e.g., V) indicating the integral value of the pulse current signal over time. CP ); and a comparator circuit (e.g., 602), configured to compare the signal indicating the integral value of the pulse current signal over time with a threshold voltage (e.g., V). THThe number of counted pulses in the second digital control signal that reach the threshold is compared to detect the number of pulses in the second digital control signal.

[0138] As shown herein, a radar sensor (e.g., 904) may include circuitry (e.g., 906) according to one or more embodiments and transmitter circuitry (e.g., 908) coupled to an antenna (e.g., 912). This circuitry may be configured to receive the input reference signal from a microcontroller unit (e.g., 902) and provide the variable-frequency output signal to the transmitter circuitry.

[0139] As shown herein, a vehicle (e.g., V) may include a radar sensor according to one or more embodiments.

[0140] As shown herein, a method of operating a circuit according to one or more embodiments may include: biasing a tunable resonant circuit to generate a variable-frequency output signal between a first node and a second node; generating a first digital control signal and a second digital control signal based on an input reference signal and the variable-frequency output signal, wherein the first digital control signal is asserted to indicate a first operating state in which the timing offset has a first sign, and the second digital control signal is asserted to indicate a second operating state in which the timing offset has a second sign opposite to the first sign; generating a control signal based on the first digital control signal and the second digital control signal; receiving the control signal at the control node coupled to the variable capacitor and tuning the tunable resonant circuit according to the control signal; sensing a reset signal and generating a timing signal, wherein the timing signal is asserted in response to a pulse sensed in the reset signal and is deasserted after a time interval from the sensed pulse; and, in response to the timing signal being asserted, selectively coupling a selected capacitor of the set of capacitors between the first node and the second node according to the second digital control signal.

[0141] Without prejudice to the fundamental principles, details and embodiments may be changed, even significantly changed, relative to what has been described, by way of example only, without departing from the scope of protection.

[0142] The scope of protection is determined by the appended claims.

Claims

1. A circuit comprising: A tunable resonant circuit includes: First node; Second node; An inductor is coupled between the first node and the second node; A variable capacitor is coupled between the first node and the second node; A set of capacitors, selectively coupled between the first node and the second node; and A control node, coupled to the variable capacitor, is configured to receive a control signal, wherein the tunable resonant circuit is tunable according to the control signal. A bias circuit is coupled to the tunable resonant circuit, and the bias circuit is configured to bias the tunable resonant circuit to generate a variable frequency output signal between the first node and the second node. A phase frequency detector circuit is sensitive to an input reference signal and to the variable frequency output signal, and the phase frequency detector circuit is configured to generate a first digital control signal and a second digital control signal based on a timing offset of the variable frequency output signal relative to the input reference signal, wherein an assertion of the first digital control signal indicates a first operating state in which the timing offset has a first sign, and wherein an assertion of the second digital control signal indicates a second operating state in which the timing offset has a second sign opposite to the first sign; The charge pump circuit and the filter circuit are configured to generate the control signal to the control node based on the first digital control signal and the second digital control signal; A timer circuit sensitive to a reset signal, and the timer circuit is configured to generate a timing signal, wherein the timing signal is asserted in response to a pulse sensed in the reset signal, and the timing signal is deasserted after a time interval from the start of the sensed pulse; and A calibration circuit is configured to selectively couple a capacitor selected from the set of capacitors between the first node and the second node, the selected capacitor being chosen according to the second digital control signal, the calibration circuit performing the selective coupling in response to an assertion of the timing signal.

2. The circuit of claim 1, wherein the bias circuit is configured to: generate the variable frequency output signal comprising a frequency scan separated by dead time, and generate a pulse in the reset signal at the start of the dead time.

3. The circuit according to claim 1, further comprising: A switch is configured to selectively couple the control node to a reference control voltage in response to an assertion of the timing signal.

4. The circuit according to claim 1, comprising: A feedback loop is configured to provide the variable frequency output signal to the phase frequency detector circuit, wherein the feedback loop includes a frequency divider circuit. A voltage divider network is configured to generate a set of different reference control voltages; as well as A set of switches is configured to selectively couple the control node to a corresponding reference control voltage among the set of different reference control voltages, based on the divider programming word of the divider circuit.

5. The circuit of claim 1, wherein the calibration circuit is configured to count the number of pulses occurring in the second digital control signal, and in response to the number of counted pulses in the second digital control signal reaching a threshold, to couple a capacitor from the set of capacitors between the first node and the second node.

6. The circuit of claim 5, wherein the calibration circuit includes a digital counter circuit configured to count the number of pulses occurring in the second digital control signal.

7. The circuit of claim 5, wherein the calibration circuit comprises: A further charge pump circuit is configured to generate a pulse current signal based on the first digital control signal and the second digital control signal; An integrator circuit is configured to generate a signal indicating the integral value of the pulse current signal as a function of time; as well as A comparator circuit is configured to compare a signal indicating the integral value of the pulse current signal as a function of time with a threshold voltage to detect the number of counted pulses in the second digital control signal that reach the threshold.

8. A radar sensor, comprising: The circuit includes: A tunable resonant circuit having a first node and a second node, and comprising: An inductor is coupled between the first node and the second node; A variable capacitor is coupled between the first node and the second node; A set of capacitors, selectively coupled between the first node and the second node; and A control node, coupled to the variable capacitor, is configured to receive a control signal, wherein the tunable resonant circuit is tunable according to the control signal. A bias circuit is coupled to the tunable resonant circuit, and the bias circuit is configured to bias the tunable resonant circuit to generate a variable frequency output signal between the first node and the second node. A phase frequency detector circuit is sensitive to an input reference signal and the variable frequency output signal, and the phase frequency detector circuit is configured to generate a first digital control signal and a second digital control signal based on a timing offset of the variable frequency output signal relative to the input reference signal, wherein an assertion of the first digital control signal indicates a first operating state in which the timing offset has a first sign, and wherein an assertion of the second digital control signal indicates a second operating state in which the timing offset has a second sign opposite to the first sign; The charge pump circuit and the filter circuit are configured to generate the control signal to the control node based on the first digital control signal and the second digital control signal; A timer circuit sensitive to a reset signal, and the timer circuit is configured to generate a timing signal, wherein the timing signal is asserted in response to a pulse sensed in the reset signal, and the timing signal is deasserted after a time interval from the start of the sensed pulse; and A calibration circuit is configured to selectively couple a capacitor selected from the set of capacitors between the first node and the second node, the selected capacitor being chosen according to a second digital control signal, the calibration circuit performing the selective coupling in response to an assertion of the timing signal; and The transmitter circuit is coupled to the antenna; The circuit is further configured to receive the input reference signal from the microcontroller unit and provide the variable frequency output signal to the transmitter circuit.

9. The radar sensor of claim 8, wherein the bias circuit is configured to generate the variable frequency output signal comprising a frequency scan separated by dead time, and to generate a pulse in the reset signal at the start of the dead time.

10. The radar sensor according to claim 8, further comprising: A switch is configured to selectively couple the control node to a reference control voltage in response to an assertion of the timing signal.

11. The radar sensor according to claim 8, comprising: A feedback loop is configured to provide the variable frequency output signal to the phase frequency detector circuit, wherein the feedback loop includes a frequency divider circuit. A voltage divider network is configured to generate a set of different reference control voltages; as well as A set of switches is configured to selectively couple the control node to a corresponding reference control voltage among the set of different reference control voltages, based on the divider programming word of the divider circuit.

12. The radar sensor of claim 8, wherein the calibration circuit is configured to count the number of pulses occurring in the second digital control signal, and in response to the number of pulses counted in the second digital control signal reaching a threshold, a capacitor from the set of capacitors is coupled between the first node and the second node.

13. The radar sensor of claim 12, wherein the calibration circuit includes a digital counter circuit configured to count the number of pulses occurring in the second digital control signal.

14. The radar sensor according to claim 12, wherein, The calibration circuit includes: A further charge pump circuit is configured to generate a pulse current signal based on the first digital control signal and the second digital control signal; An integrator circuit is configured to generate a signal indicating the integral value of the pulse current signal over time; and A comparator circuit is configured to compare a signal indicating the integral value of the pulse current signal as a function of time with a threshold voltage to detect the number of counted pulses in the second digital control signal that reach the threshold.

15. A means of transportation comprising the radar sensor according to claim 8.

16. A method of operating a circuit according to any one of claims 1-7, the method comprising: A biased tunable resonant circuit is used to generate a variable frequency output signal between the first node and the second node; A first digital control signal and a second digital control signal are generated based on an input reference signal and the variable frequency output signal, wherein the first digital control signal is asserted to indicate a first operating state, in which the timing offset of the variable frequency output signal relative to the input reference signal has a first sign, and wherein the second digital control signal is asserted to indicate a second operating state, in which the timing offset has a second sign opposite to the first sign. A control signal is generated based on the first digital control signal and the second digital control signal; The control signal is received at the control node coupled to the variable capacitor, and the tunable resonant circuit is tuned according to the control signal. A reset signal is sensed, and a timing signal is generated, wherein the timing signal is asserted in response to a pulse sensed in the reset signal, and is deasserted after a time interval from the start of the sensed pulse; as well as In response to the timing signal being asserted, a capacitor selected from a set of capacitors is selectively coupled between the first node and the second node according to the second digital control signal.

17. The method of claim 16, wherein the variable frequency output signal is generated by biasing the tunable resonant circuit to perform a frequency scan separated by a dead time, and a pulse is generated in the reset signal at the start of the dead time.

18. The method of claim 16, further comprising: In response to the assertion of the timing signal, the control node is selectively coupled to a reference control voltage.

19. The method of claim 16, further comprising: The number of pulses occurring in the second digital control signal is counted, and in response to the number of pulses counted in the second digital control signal reaching a threshold, a capacitor from the set of capacitors is coupled between the first node and the second node.

20. The method of claim 19, wherein the calibration circuit includes a digital counter circuit configured to count the number of pulses occurring in the second digital control signal.

21. The method of claim 20, further comprising: A pulse current signal is generated based on the first digital control signal and the second digital control signal; Generate a signal indicating the integral value of the pulse current signal as a function of time; as well as The signal indicating the integral value of the pulse current signal changing over time is compared with a threshold voltage to detect the number of counted pulses in the second digital control signal that reach the threshold.

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