III-V semiconductor device with integrated power transistor and startup circuit

Abstract

Disclosed is a heterojunction power device based on a group III nitride semiconductor, comprising: a first heterojunction transistor formed on a substrate (4) and a second heterojunction transistor formed on the substrate. The first heterojunction transistor comprises: a first group III nitride semiconductor region formed on the substrate, wherein the first group III nitride semiconductor region comprises a first heterojunction, wherein the first heterojunction comprises at least one two-dimensional carrier gas; a first terminal (8) operatively connected to the first group III nitride semiconductor region; a second terminal (9) laterally spaced from the first terminal and operatively connected to the first group III nitride semiconductor region; and a first gate region (10) on the first group III nitride semiconductor region between the first terminal and the second terminal. The second heterojunction transistor includes: a second III-nitride semiconductor region formed on a substrate, wherein the second III-nitride semiconductor region includes a second heterojunction, the second heterojunction including at least one two-dimensional carrier gas; a third terminal (19) operatively connected to the second III-nitride semiconductor region; a fourth terminal (16) laterally spaced apart from the third terminal in a first dimension and operatively connected to the second III-nitride semiconductor region; a first plurality of highly doped semiconductor regions (18) of a first conductivity type formed on the second III-nitride semiconductor region, the first plurality of highly doped semiconductor regions formed between the third terminal and the fourth terminal; and a second gate region (17) operatively connected to the first plurality of highly doped semiconductor regions. One of the first heterojunction transistor and the second heterojunction transistor is an enhancement mode field effect transistor, and the other of the first heterojunction transistor and the second heterojunction transistor is a depletion mode field effect transistor.

Description

Technical Field

[0001] The present disclosure relates to power semiconductor devices. In particular, but not exclusively, the present disclosure relates to the use of heterostructure AlGaN / GaN high electron mobility transistors for integrated startup circuits of switch-mode power supplies. Background Art

[0002] A power semiconductor is a semiconductor device that can be used as a switch or rectifier in power electronics. A power semiconductor is typically used in a "commutation mode" (i.e., it is either in the on or off state, or switches between these two states) and therefore has a design optimized for this use.

[0003] Silicon bipolar junction transistors (BJTs), metal oxide semiconductor field effect transistors (MOSFETs), and insulated gate bipolar transistors (IGBTs) are common types of power semiconductor switching devices. Their applications include switch-mode power supplies in consumer electronics, inverters and converters in hybrid and electric vehicles, motor controllers, RF and microwave circuits, and telecommunications systems.

[0004] A switched-mode power supply (SMPS) is an electronic power supply that utilizes switching devices, such as MOSFETs, that are continuously turned on and off at high frequencies in order to efficiently convert electrical energy. Energy storage devices, such as capacitors and inductors, complete the circuit by supplying power during the non-conducting state of the switching devices.

[0005] An SMPS transfers power from a DC source or AC source (usually mains power) to a DC load, such as consumer electronics, while converting the voltage and current characteristics. Figure 1 A block diagram of a mains-operated AC / DC SMPS with output voltage regulation can be seen in .

[0006] SMPSs typically incorporate pulse-width modulation (PWM) and / or frequency modulation (FM) control integrated circuits (ICs) for output voltage regulation. The controller manages the period during which the power switch within the SMPS is on. This controller is typically implemented in a feedback loop configuration in which the SMPS's output characteristic (e.g., the power supply output voltage) is measured. This measurement signal is used to determine the time the power switch operates in conducting or blocking mode. The ratio of the conducting mode time to the total period of the switching waveform is defined as the duty cycle. As the DC output load dynamically changes, the controller adjusts the duty cycle to maintain the required output voltage required by the system.

[0007] exist Figure 1In a 1.5-μm CMOS topology, feedback is provided to the controller from the secondary (output). This is called secondary-side control and may involve an optocoupler. In other topologies, primary-side control can be used to eliminate the optocoupler.

[0008] The controller is powered when the decoupling capacitor C is charged and is essential for the SMPS to operate on demand. Figure 2 and Figure 3 is shown in the figure. Due to the rectified input DC rail voltage (V 入 ), the controller operates at a significantly lower DC bias compared to the MOSFET, so a DC / DC conversion is used to power the controller.

[0009] Figure 2 The figure shows a well-known standard flyback converter that uses a depletion-mode device to charge the decoupling capacitor of a PWM control IC. A depletion-mode MOSFET with an adjustable drain current level powers the IC, which acts as a current source with the device in saturation mode. Resistor R can be used to adjust the current level, while the input DC rail (V 入 ) does not affect the current level. As the decoupling capacitor, C, becomes increasingly charged, this increases the voltage bias on the source of the depletion-mode transistor, and the gate-source voltage becomes increasingly negative. When the source voltage approaches the device threshold voltage, the depletion-mode MOSFET switches to the off state (i.e., its resistance increases significantly). Figure 2 A simplified version of the circuit is shown as Figure 3 The operation of a depletion mode transistor is shown.

[0010] Gallium nitride (GaN) is a wide bandgap material with properties that make it a suitable candidate for use in several application areas requiring solid-state devices (eg, radio frequency electronics, optoelectronics, power electronics).

[0011] GaN technology allows the design of transistors with high electron mobility and high saturation velocity. These properties have made GaN a good candidate for high-power and high-temperature microwave applications, such as radar and cellular communication systems. As these systems expand in terms of users and desired capabilities, interest in increasing their operating frequencies and powers has correspondingly grown. Higher-frequency signals can carry more information (bandwidth) and allow the use of smaller antennas with very high gain.

[0012] Furthermore, GaN, with its wide bandgap, offers the possibility of emitting light at higher frequencies, such as in the green, blue, violet and ultraviolet parts of the electromagnetic spectrum.

[0013] Gallium nitride (GaN) is increasingly being recognized as a very promising material for power devices with the potential to increase power density, reduce on-state resistance, and achieve high-frequency response. Applications include portable consumer electronics, solar inverters, electric vehicles, and power supplies. The wide bandgap (E g =3.39eV) resulting in a high critical electric field (E c =3.3MV / cm), which can result in a device design with a shorter drift region and therefore lower on-resistance if compared to a silicon-based device with the same breakdown voltage.

[0014] The use of aluminum gallium nitride (AlGaN) / GaN heterostructures also allows the formation of a two-dimensional electron gas (2DEG) at the heterointerface, where carriers can achieve very high carrier mobility (μ = 2000 cm 2 / (Vs)). In addition, the piezoelectric polarization charge present in the AlGaN / GaN heterostructure leads to a high electron density in the 2DEG layer (e.g., 1x10 13 cm -2 These characteristics allow the development of high electron mobility transistors (HEMTs) and Schottky barrier diodes with very competitive performance parameters. A large amount of research is focused on the development of power devices using AlGaN / GaN heterostructures.

[0015] However, the 2DEG inherent in the AlGaN / GaN heterointerface presents challenges when attempting to design enhancement-mode rather than depletion-mode devices. Despite this, several approaches have been proposed that could lead to enhancement-mode devices, including the use of metal-insulator-semiconductor structures, fluorine treatment, recessed gate structures, and the use of p-type GaN layers. Due to the relative maturity and controllability of epitaxial growth of pGaN layers (compared to other technologies), the pGaN / AlGaN / GaN HEMT is the leading structure currently commercialized.

[0016] Figure 4 The cross section of the active region of a pGaN HEMT according to the prior art is schematically shown. The device includes an AlGaN layer 1, a GaN layer 2 (also known as a GaN buffer layer), a transition layer 3, a silicon substrate 4, a substrate terminal 5, a SiO2 passivation layer 6, a surface passivation dielectric 7, and a source terminal. Figure 8 , drain terminal 9, gate terminal 10 and highly p-doped GaN cap 11. The device shown is a lateral three-terminal device with an AlGaN / GaN heterostructure grown epitaxially on a standard silicon wafer. A transition layer 3 is used to allow the growth of high-quality GaN layers despite the significant lattice mismatch between GaN 2 and Si 4. Carbon p-type doping is typically added to the GaN layers and the transition layer. Finally, a thin cap GaN layer is typically added to form a GaN layer with a capacitance greater than 1x101.9 cm- 3 Typical pGaN gate devices have a threshold voltage of approximately 1.5 to 2V and a gate turn-on bias of approximately 8V.

[0017] While enhancement-mode devices are used as the main power switches in some power electronics applications, there are applications where depletion-mode devices may be more suitable or may be used in conjunction with enhancement-mode devices; for example, in startup circuits in the power applications mentioned above. Generally speaking, depletion-mode AlGaN / GaN transistors are made by placing a Schottky metal contact 12, which serves as the gate terminal, directly on the AlGaN layer 1 (excluding the pGaN capping layer present in enhancement-mode devices), as shown in FIG. Figure 5 What I see.

[0018] In prior art devices, integrating the startup components with the main power transistor is not straightforward. This is due to compatibility issues between the Schottky gate used for the normally-on transistor and the p-GaN gate used for the normally-off transistor. Furthermore, threshold control of the normally-on transistor is limited to the use of Schottky metallization, and furthermore, such control is limited if a normally-off device using a p-GaN gate is monolithically integrated.

[0019] In some prior art systems, resistor components are used instead of depletion mode devices. in ) will affect the charging time of the decoupling capacitor C, making this a less efficient solution. To reduce the charging time, either the resistor used needs to be reduced (which increases the charging losses) or the size of the capacitor C needs to be reduced, which is usually not possible.

[0020] In prior art depletion-mode Schottky-gate devices, the device's threshold voltage (i.e., the gate bias at which the device is considered to move from the on-state to the off-state, and vice versa) depends on process parameters such as, but not limited to, the AlGaN layer thickness, the aluminum mole fraction, and the gate metal stack. Consequently, adjusting the threshold voltage to a level optimal for a particular application requires changes to the epitaxial growth and / or gate metal processing, which is both time-consuming and cost-ineffective. In contrast, the ability to reliably adjust the device threshold voltage through layout modifications would be significantly less time-consuming and more cost-effective. This capability is currently not available in prior art.

[0021] Prior art depletion-mode devices have a limit on the maximum positive gate bias voltage that can be applied to the gate terminal before the dominant on-state conduction path (i.e., the low-resistance path) changes from drain-source to gate-source in the on-state. This maximum bias voltage depends on the Schottky barrier height at the gate contact and does not exceed 2V. Prior art normally-on HEMT devices do not exist that can be biased beyond this voltage level.

[0022] US 2014 / 042452 and US 2014 / 015591 suggest using a depletion-mode HEMT in the gate to limit the overvoltage.

[0023] US 2015 / 076563 relates to a conventional normally-on HEMT in which p-GaN islands on an AlGaN layer are placed between the source and drain terminals in the same direction as the current flow. The p-GaN islands are positioned adjacent to the drift region, in the same direction as the current flow between the source and drain. In this arrangement, the p-GaN islands cannot be used to control the device's threshold voltage. Summary of the Invention

[0024] The present disclosure relates to the use of a monolithically integrated GaN-based device, preferably comprising a normally-off enhancement-mode field-effect transistor as the main power switch and a high-voltage, normally-on, depletion-mode transistor as the startup component.

[0025] An object of the present disclosure is to provide a monolithically integrated GaN-based device comprising a normally-off enhancement-mode transistor as a main power switch and a normally-on, high-voltage depletion-mode transistor as a startup component. The enhancement-mode transistor may comprise a highly doped semiconductor gate structure of a continuous strip or a closed shape placed between the main terminals, source, and drain of the power switch. The depletion-mode transistor may comprise a gate structure based on a discontinuous highly doped semiconductor layer comprising islands within a strip or a closed shape surrounding a cell that, when a gate voltage is applied, is used to modulate a conductive path between a high-voltage terminal and a low-voltage terminal. All such islands may be connected to the same gate electrode. The startup component may also be connected to an internal or external capacitor to provide a supply voltage to other electronic components in the switch-mode power supply, such as a controller or protection circuit.

[0026] The devices of the present disclosure are superior to prior art devices for the following reasons:

[0027] • The startup components can be monolithically integrated with the main enhancement-mode power transistor. This integration can allow for overall system size / cost reduction, lower BOM (Bill of Materials), and improved reliability;

[0028] • This integration improves performance by reducing parasitic components associated with interconnections between discrete devices;

[0029] • Both enhancement-mode and depletion-mode devices can be fabricated in the same manufacturing process. The ability to form both enhancement-mode and depletion-mode devices without any additional process steps reduces the cost of integrated devices;

[0030] • Using depletion-mode HEMTs instead of resistors, enhancement-mode devices are more energy-efficient;

[0031] • In embodiments where the gate of the depletion-mode device includes a discrete highly doped region, the proposed device is able to control the depletion-mode device threshold voltage by adjusting the transistor layout design rather than adjusting the epitaxial growth or gate metal stack. This layout redesign can result in an optimized device at a much lower cost / effort than other approaches used in prior art devices;

[0032] • An increased positive gate bias (>7V) can be applied to the depletion mode device before the dominant on-state channel changes from drain-source to gate-source. At higher positive gate terminal biases, an increase in the carrier density in the channel below the gate terminal can be achieved, thereby reducing the overall on-state resistance and hence the losses in the device.

[0033] In a configuration where the gate is biased at 0V and the source is raised to a higher potential by, for example, charging a capacitor, the maximum potential level at the source terminal can be adjusted by layout design before the depletion transistor turns off, more precisely by controlling the distance between the pGaN islands. This is advantageous because the exact potential level can depend on the application. This adjustment of the potential level can be done at the layout level without requiring process modifications for different applications.

[0034] According to one aspect of the present disclosure, a heterojunction power device based on a group III nitride semiconductor is provided, comprising:

[0035] A first heterojunction transistor is formed on a substrate, and the first heterojunction transistor includes:

[0036] a first III-nitride semiconductor region formed on the substrate, wherein the first III-nitride semiconductor region includes a first heterojunction including at least one two-dimensional carrier gas of the second conductivity type;

[0037] a first terminal operatively connected to the first Group III nitride semiconductor region;

[0038] a second terminal laterally spaced from the first terminal and operatively connected to the first Group III nitride semiconductor region;

[0039] a first gate region formed on the first Group III nitride semiconductor region between the first terminal and the second terminal; and

[0040] A second heterojunction transistor is formed on the substrate, and the second heterojunction transistor includes:

[0041] a second III-nitride semiconductor region formed on the substrate, wherein the second III-nitride semiconductor region includes a second heterojunction including at least one two-dimensional carrier gas of the second conductivity type;

[0042] a third terminal operatively connected to the second Group III nitride semiconductor region;

[0043] a fourth terminal laterally spaced from the third terminal in a first dimension and operatively connected to the second Group III-nitride semiconductor region;

[0044] a first plurality of highly doped semiconductor regions of the first conductivity type formed on the second Group III nitride semiconductor region, the first plurality of highly doped semiconductor regions being formed between the third terminal and the fourth terminal; and

[0045] A second gate region is operatively connected to the first plurality of highly doped semiconductor regions.

[0046] One of the first heterojunction transistor and the second heterojunction transistor is an enhancement-mode field-effect transistor, and the other of the first heterojunction transistor and the second heterojunction transistor is a depletion-mode field-effect transistor.

[0047] The present disclosure provides an integrated device that can use an enhancement-mode HEMT as the main power switch and a high-voltage depletion-mode HEMT that can power auxiliary electronics integrated into a switch-mode power supply. The depletion-mode HEMT in the integrated device can be used as a startup device to provide a low voltage, such as 5V, from a high-voltage rail.

[0048] In prior art systems, for example Figure 3 In the circuit shown, the output voltage is given by the gate threshold voltage. This type of DC / DC conversion has poor efficiency and high losses. Therefore, it can only be used for short periods of time or with low power.

[0049] The use of a depletion-mode HEMT in the present disclosure, rather than using a resistor in its place, is a more energy-efficient and elegant solution.

[0050] Monolithic integration of the above components allows for reduction in overall system size and cost. It also improves performance by reducing parasitic components associated with interconnections between discrete devices.

[0051] Preferably, the starting substrate can be silicon. However, any other substrate compatible with current technology manufacturing processes for GaN devices can be used. The use of a silicon substrate contributes to the low cost, high reproducibility, and wide availability of foundries supporting the process. Alternative substrate materials may include sapphire, silicon carbide (SiC), gallium nitride (GaN), and gallium arsenide (GaAs). Other alternative materials are also possible. In addition, the present disclosure covers the possibility of growing a Group III nitride semiconductor region including a heterojunction (or heterostructure) on a first substrate suitable for this purpose and then transferring the heterostructure on a second substrate. The second substrate can be any of the aforementioned substrates or a different substrate (e.g., polydimethylsiloxane, PDMS, a flexible substrate, diamond). Silicon as a substrate material will be used for illustrative purposes in the following embodiments and figures.

[0052] The first gate region may be formed above the first plurality of highly doped semiconductor regions. The first gate region may include an ohmic contact. Alternatively, the active gate region may include a Schottky contact. In principle, the ohmic contact provides higher hole injection, which may be beneficial for device sag passivation and stability under high voltage stress conditions, while the Schottky contact provides lower gate leakage current in the on-state.

[0053] The first terminal and the second terminal may be laterally spaced apart from one another in a first dimension, or alternatively, the first terminal and the second terminal may be spaced apart from one another in a second dimension.

[0054] The first heterojunction of the first III-nitride semiconductor region may include: a first III-nitride semiconductor layer having a first band gap and formed on the substrate; a second III-nitride semiconductor layer having a second band gap different from the first band gap and disposed on the first III-nitride semiconductor layer; and at least one two-dimensional carrier gas formed at an interface between the first and second III-nitride semiconductor layers to provide a channel. The second heterojunction of the second III-nitride semiconductor region may include: a third III-nitride semiconductor layer having a first band gap and formed on the substrate; a fourth III-nitride semiconductor layer having a second band gap different from the first band gap and disposed on the third III-nitride semiconductor layer; and at least one two-dimensional carrier gas formed at an interface between the third and fourth III-nitride semiconductor layers to provide a channel.

[0055] Each of the first, second, third, and fourth Group III nitride semiconductor layers includes any one of gallium nitride (GaN), aluminum gallium nitride (AlGaN), and indium aluminum gallium nitride (InAlGaN).

[0056] Heterostructures can include: elemental semiconductors (e.g., Si, Ge), binary compounds from Groups III and IV (e.g., GaAs), or Groups II and VI (e.g., ZnS), or Groups III and V (e.g., GaN), binary alloy semiconductors (e.g., SiGe), ternary alloys (e.g., AlGaAs), quaternary alloys (e.g., InGaAsP), or even quinary materials (e.g., GaInPSbAs). Some examples of possible heterostructures are therefore as follows: AlGaAs / GaAs, InGaP / GaAs, InP / InGaAs, InAlAs / InGaAs, SiGe / Si, AlGaAs / InGaAs, InAlAs / InGaAs, and InAlN / GaN, AlGaN / GaN. Preferably, the heterostructure will be an AlGaN / GaN heterostructure containing a two-dimensional electron gas (2DEG); this will be used for illustrative purposes in the examples and figures below. GaN and AlGaN technology allows the design of transistors with high electron mobility and high saturation velocity.

[0057] The at least one two-dimensional carrier gas may be a two-dimensional electron gas (2DEG) or a two-dimensional hole gas (2DHG). 2DEG has an advantage of having much higher carrier mobility than 2DHG.

[0058] The first heterojunction transistor may be configured as an enhancement-mode field-effect transistor, and the second heterojunction transistor may be configured as a depletion-mode field-effect transistor.

[0059] The second gate region may include a Schottky contact. Alternatively, the second gate region may include an ohmic contact.

[0060] The first heterojunction transistor may further include at least one highly doped semiconductor region formed above the first Group III nitride semiconductor region. The at least one highly doped semiconductor region may be formed between the first terminal and the second terminal. The first gate terminal may be formed above the at least one highly doped semiconductor region.

[0061] The first plurality of highly doped semiconductor regions may include at least two highly doped semiconductor regions laterally spaced apart from each other in the second dimension.

[0062] Highly doped semiconductor regions (islands) can be placed on the semiconductor surface of the heterojunction. Under zero gate-source terminal bias, they deplete the conductive channel (2D carrier gas) directly beneath them, but do not deplete the region between them where the 2D carrier gas remains undepleted. Consequently, along a path where no highly doped layer exists (above the 2D carrier gas formed below the region between the islands), an uninterrupted channel exists between the third (source) and fourth (drain) terminals at zero gate-source bias. This uninterrupted channel exists as long as the gate-source bias is above a first threshold voltage.

[0063] Applying a large negative bias to the gate terminal relative to the source terminal (or alternatively, applying a large positive source bias to the source relative to the gate) reduces the carrier concentration in the conductive channel (region) between the drain and source terminals due to the extension of the electric field from the highly doped islands to the region between the islands. This lateral electric field (directed perpendicular to the current flow) depletes the 2D carrier gas formed beneath the region between the highly doped semiconductor islands, thereby obstructing the current path through the 2D carrier gas between the source (third terminal) and drain (fourth terminal). The critical gate bias value at which the device is considered to transition from the on-state (low resistance) to the off-state is defined as the first threshold voltage or device threshold voltage. Note that, as described above, instead of applying a negative potential to the gate relative to the source terminal, the same result can be achieved by keeping the gate grounded and applying a positive potential to the source.

[0064] Each highly doped semiconductor region can be spaced apart from the nearest other highly doped semiconductor regions. The threshold voltage can be controlled by the spacing between adjacent highly doped islands, the layer thickness, and the doping fraction. The specific on-resistance of the depletion mode transistor can be controlled by the number of spacings between highly doped islands and the width / area of the highly doped islands relative to the spacing / separation area between the islands.

[0065] The at least two highly doped semiconductor regions may comprise discrete regions, wherein each of the at least two highly doped semiconductor discrete regions may be separated from the nearest other highly doped semiconductor region by a predetermined distance. The discrete regions (or discontinuous islands) may be formed such that no highly doped semiconductor layer exists between adjacent islands, thereby providing a direct, unobstructed conductive path between the third terminal (source) and the fourth terminal (drain) provided by the undepleted 2D carrier gas layer. Adjacent islands may be closely spaced together in a row across (and orthogonal to) the current path, such that a potential applied to the gate modulates the conductive region (i.e., portion of the 2D carrier gas layer) between the islands, thereby modulating the direct path between the source and drain.

[0066] Compared to the prior art devices shown in Figure 5As a component of the proposed device, the proposed depletion-mode transistor has advantages at the device level compared to the Schottky-gate depletion-mode AlGaN / GaN HEMT (shown in Figure 5).

[0067] The proposed device is able to control the device threshold voltage by adjusting the transistor layout design rather than adjusting the epitaxial growth or gate metal stack. The layout redesign results in an optimized device at much lower cost / effort than other currently available methods.

[0068] The depletion-mode device used as a component can be a normally-on depletion-mode device, in which an increased positive gate bias (>7V) can be applied before the main conduction channel changes from drain-source to gate-source. Currently, in prior art devices, the voltage at which gate conduction occurs is typically between 0.7 and 2V. At a higher positive gate terminal bias, the disclosed device can achieve an increased carrier density in the channel below the gate terminal, thereby reducing the overall on-state resistance and therefore reducing device losses.

[0069] The at least two highly doped semiconductor regions may be aligned in the first dimension. In other words, the at least two highly doped semiconductor regions may form a row of highly doped semiconductor regions extending in a second dimension in a direction different from the current flow between the first terminal and the second terminal.

[0070] Depletion-mode transistors can have two threshold voltages. The first threshold voltage can be negative and can be equivalent to the threshold voltage of a classic normally-on transistor, indicating a transition from the off state to the on state. Preferably, the second threshold voltage can be positive and can be characterized by a sharp increase in current. The second threshold voltage can occur at the same value as the threshold voltage of an integrated normally-off device with a continuous highly doped semiconductor gate.

[0071] When the gate voltage of a depletion-mode transistor is very negative, adjacent highly doped semiconductor gate islands deplete a portion of the 2D carrier gas between them, obstructing the path for electrons or holes to flow from the source to the drain. Once the gate-source voltage is equal to or greater than the first threshold voltage, 2D carrier gas begins to form in the middle of the spacing between adjacent p-type islands. At this stage, a conductive path is established between the source and drain. The first threshold voltage can be adjusted by controlling the spacing between adjacent highly doped semiconductor islands. As the gate-source voltage increases above the first threshold voltage but remains below the second threshold voltage, the formation of a 2D carrier gas channel expands from the middle of the spacing between adjacent highly doped semiconductor islands toward the edges of the highly doped semiconductor gate islands. Current continues to increase as the on-state resistance decreases. When the second threshold voltage (preferably positive) is reached, a sharp increase in current is observed as the 2D carrier gas diffuses directly beneath the highly doped (p-type gate) islands, allowing current to flow through this area, resulting in an increased conductive area. It is characterized by a sharp increase in current and, as a result, a sharp decrease in on-state resistance. The rate of current increase depends on the ratio of the width of the highly doped semiconductor gate islands to the spacing between them.

[0072] At least two highly doped semiconductor regions may be in contact with the second Group III nitride semiconductor region. Preferably, at least two highly doped semiconductor regions may be in contact with the fourth Group III nitride semiconductor layer.

[0073] The first dimension may be perpendicular to the second dimension.Thus, the highly doped semiconductor regions and the spaces between adjacent highly doped semiconductor regions are formed between the source terminal and the drain terminal.

[0074] At least two highly doped semiconductor regions may comprise p-type gallium nitride (p-GaN) material. The p-GaN forms a potential barrier with the underlying AlGaN material. The high doping of the p-GaN contributes to a depletion region extending through the AlGaN layer to the 2DEG, which varies with the potential applied to the gate terminal relative to the source terminal. As the potential on the gate increases, hole tunneling occurs from the gate terminal into the semiconductor. A certain amount of hole current through the gate has a positive impact on device stability during dynamic high-voltage stress, but if the current is too high, it will be seen as control terminal leakage, affecting the driver and the overall losses of the device.

[0075] The device may also include a transition layer formed between the substrate and the first or second III-nitride semiconductor regions. The transition layer may be present between the heterostructure and the bulk substrate to minimize lattice mismatch or accommodate mechanical stress in the heterostructure. The transition layer may include a nucleation layer. The nucleation layer may be made of aluminum nitride (AlN) or any other suitable material and may be placed on the substrate. The nucleation layer may form the first sublayer of a transition layer comprised of different sublayers of the same material as the first and second semiconductor layers of the heterostructure device (e.g., AlGaN or GaN material). This helps relieve mechanical stress and accommodate lattice mismatch between the substrate (e.g., silicon) and the heterostructure formed on top.

[0076] In embodiments of the present disclosure where the substrate is silicon and the heterostructure is based on a Group III nitride compound such as GaN, the transition layer may comprise Al x GaN 1-x N (x is the aluminum mole fraction of the compound) or Al to produce a multilayer stack (also known as a superlattice) x GaN 1-x N / A y GaN 1-y N (y is the aluminum mole fraction of the compound) for any composition.

[0077] By using the same substrate and sharing the AlGaN / GaN layer on the substrate, the first heterojunction transistor and the second heterojunction transistor can be monolithically integrated into a single device.

[0078] Advantageously, depletion-mode transistors can be monolithically integrated with the main, typically enhancement-mode, power transistor. This integration can reduce overall system size and cost, lowering the BOM (bill of materials) and improving reliability. Furthermore, it can improve performance by reducing parasitic components associated with the interconnects between discrete devices.

[0079] The first heterojunction transistor and the second heterojunction transistor may be laterally spaced apart from each other in a first dimension.The first heterojunction transistor and the second heterojunction transistor may be in physical contact with each other or may be separated by a distance.

[0080] The heterojunction power device may further include an isolation layer formed between the first heterojunction transistor and the second heterojunction transistor.

[0081] The isolation layer can be formed by selectively etching the AlGaN layer down to the underlying GaN layer to locally remove the 2D carrier gas. After etching, a passivation layer can be deposited and possibly fill the space created in the groove by etching.

[0082] Isolation can be defined as the portion of the device outside the active area (AA mask layer) based on the layout. This represents the area of the device where no 2D carrier gas layer exists.

[0083] The first heterojunction transistor and the second heterojunction transistor may be formed in the same active area of the device, for example by sharing a drain region and a drain terminal. Alternatively, the first heterojunction transistor and the second heterojunction transistor may be formed as two different blocks of the active area (i.e., with an isolation region between them).

[0084] The first heterojunction transistor can be configured as a power switch. When used as a switch in power electronics applications, it is preferred that the first heterojunction transistor be a normally-off device. The first heterojunction transistor must withstand a rated voltage (e.g., 100V, 200V, or 600V), meaning its breakdown voltage must exceed the rated voltage and deliver a nominal current (e.g., 1A, 20A, or 100A) in the on-state. This current varies with the power rating and the requirements of the system in which the device is used. The gate terminal is connected to a gate driver, which can be monolithically integrated with the switch or externally provided. Gate control determines whether the switch is on or off, or transitions between these states. When referring to a normally-off device, we mean that the switch is normally off when 0V is applied between the gate and source, and turns on only when a positive gate-to-source voltage above the threshold voltage is applied. Broadly speaking, in terms of requirements and system operation, a power switch is similar to other power switches such as power MOSFETs or IGBTs.

[0085] The second heterojunction transistor can be configured to function as a startup component. As a startup component, the second heterojunction transistor can be a normally-on device due to the negative first threshold voltage. In a basic example of a startup scheme, the gate of the second heterojunction transistor can be connected to ground or to the source of the first heterojunction transistor (i.e., the power switch). The source of the second heterojunction transistor (i.e., the normally-on transistor) can be connected to a capacitor, which can be monolithically integrated or external. The drains of the first and second heterojunction transistors are connected to the same terminal. When a high rail voltage is present at the common drain terminal, the normally-on device turns on, charging the capacitor until its source potential rises above the absolute value of the first threshold voltage. At this point, the second heterojunction transistor, acting as a startup device, turns off. This helps create a low-voltage power supply for other circuits in the power system, such as a controller.

[0086] The second heterojunction transistor may be configured to function as a high electron mobility transistor.

[0087] The second heterojunction transistor may be configured to operate as a diode. When used as a diode, preferably, the active gate region may be operatively connected to the third (source) terminal. Alternatively, the active gate region may be operatively connected to the fourth (drain) terminal.

[0088] This diode can be used as an anti-parallel diode, conducting current in the opposite direction of the power switch. The diode can also be used as a freewheeling diode. In this case, the sources of the two transistors are connected together, the drains of the two transistors are connected together, the gate of the main switch is the control terminal, and the gate of the normally-on transistor is connected to the source of the normally-on transistor to allow operation of the diode.

[0089] Several such power switches (normally-off transistors) and normally-on transistors configured as antiparallel diodes can be monolithically integrated. An example is a half-bridge configuration, where one power switch operates on the low side and the other on the high side. Each of these power switches can have an antiparallel normally-on transistor configured as a diode.

[0090] Preferably, the distance between adjacent highly doped semiconductor regions may be less than 1000 nm. More preferably, the distance between adjacent highly doped semiconductor regions may be less than 500 nm.

[0091] In both the startup configuration and the anti-parallel configuration, as described above, the second terminal and the fourth terminal can be operatively connected. In other words, the drain terminal of the first heterojunction transistor can be operatively connected to the drain terminal of the second heterojunction transistor. The drain region can be a single drain region, wherein both the first heterojunction transistor and the second heterojunction transistor are connected to the single drain region.

[0092] In embodiments without a separate isolation structure, the drain region of the first heterojunction transistor and the drain region of the second heterojunction transistor may provide self-isolation between the first heterojunction transistor and the second heterojunction transistor.

[0093] In the startup configuration, the first terminal can be operatively connected to the second gate region. In other words, the source terminal of the first heterojunction transistor can be connected to the gate region of the second heterojunction transistor. The gate of the depletion-mode transistor can be connected to other internal or external low voltage nodes without changing the essence of the present invention; for example, the gate of the depletion-mode transistor can be connected to an internal or external ground potential or a potential close to ground, to an internal or external Kelvin terminal, which is connected to the first terminal or a low voltage power supply node and through the use of a resistive element.

[0094] The first heterojunction transistor and the second heterojunction transistor may share the same active region. There may be no obvious isolation between the first heterojunction transistor and the second heterojunction transistor except for the isolation provided by the drain terminal as self-isolation. The first Group III nitride semiconductor region and the second Group III nitride semiconductor region may form a continuous semiconductor region. The first heterojunction transistor and the second heterojunction transistor may be formed on a single substrate. The first Group III nitride semiconductor region and the second Group III semiconductor region may form a single region for both the first heterojunction transistor and the second heterojunction transistor. In other words, the transistors are monolithically integrated, sharing the same substrate, transition layer and GaN buffer layer. This helps to reduce device manufacturing costs, packaging costs and bill of materials.

[0095] According to other aspects of the present disclosure, a circuit is provided that includes the aforementioned heterojunction power device and further includes a capacitor electrically connected to the third terminal of the normally-on transistor. When used as a startup device, the normally-on transistor may also be connected to an internal or external capacitor to provide a supply voltage to other electronic components (e.g., a controller or protection circuit in a switch-mode power supply).

[0096] The source terminal (third terminal) of the depletion-mode transistor can be connected to an internal or external decoupling capacitor, causing the capacitor to charge when the depletion-mode (first heterojunction) transistor is in the on-state. As the decoupling capacitor becomes increasingly charged, the voltage bias on the source of the depletion-mode transistor increases, and the gate-source voltage becomes increasingly negative. When the source voltage approaches the device threshold voltage, the depletion-mode transistor switches to the off-state (i.e., its resistance increases significantly).

[0097] According to other aspects of the present disclosure, a circuit is provided that includes the heterojunction power device described above and further includes an integrated interface circuit that provides at least one of the following functions: a current control function, a voltage control function, and a disable function. The integrated interface circuit provides improved features for integrated startup power circuits and improved integration into power systems.

[0098] The integrated interface circuit may include one or more current control blocks. The integrated interface circuit may also include one or more regulators and a disabling unit. In addition, additional capacitors may be integrated before and after each of the current control block, the regulator, and the disabling unit, each additional capacitor forming a capacitance to the third terminal.

[0099] The current control block limits current flowing from the first terminal of the first heterojunction transistor to the load.

[0100] The regulator and disable unit have at least one of two purposes. They can regulate the output voltage to a level required by an internal or external load. For example, the voltage at the first terminal of the first heterojunction transistor is 20V, and the output of the regulator and disable unit is 5V. A second purpose can be, for example, disabling the startup power supply via an internal or external signal to reduce its power consumption.

[0101] Note that one or several current control blocks and one or several regulator and disabling units may be connected in series in any order without changing the essence of the present disclosure.

[0102] The circuit can be used to power the system during the startup phase.The circuit can also be used to power additional integrated circuits on the chip.

[0103] In some embodiments, the integrated current control block may be a resistor element, which may be made using a metal layer or a 2DEG layer.

[0104] In other embodiments, the current control block may include a current source. The current source may include a low-voltage depletion-mode HEMT and a resistor. The source of the low-voltage depletion-mode HEMT may be connected to a first terminal of the resistor, while the gate may be connected to a second terminal of the resistor. The second terminal of the resistor and the drain of the low-voltage depletion-mode HEMT may form two terminals of the current control block.

[0105] In similar embodiments, an RLC network may be included in parallel or in series with a resistive element or with a current source to improve the characteristics of the current control block.

[0106] The current control block may also include circuitry that generates an additional voltage drop. This circuitry may include one or more low-voltage diodes, one or more low-voltage HEMTs with gates connected to their sources, or a low-voltage enhancement-mode HEMT with a divider connected between the drain and source terminals of the HEMT (with the divider's midpoint connected to the HEMT's gate terminal).

[0107] The current control block may also include circuitry to adjust the current in the current control block. This current reduction circuitry may include a depletion-mode HEMT or an enhancement-mode HEMT connected in series or parallel with the resistive element in the current source. The gate of the HEMT may be connected to a node within the integrated pull-down circuitry of the regulator and disable unit.

[0108] The regulator and disable unit may be composed of one or more auxiliary low-voltage heterojunction transistors having a drain, a source, and a gate; wherein the auxiliary gate region terminal is operatively connected to the current control circuit (block) and the pull-down circuit (block). The low-voltage heterojunction transistor may be of depletion mode or enhancement mode.

[0109] The current control block can be connected between the drain or source of the auxiliary transistor and the auxiliary gate region. The pull-down circuit block can be connected between the auxiliary gate terminal and the third terminal and source of the heterojunction power device (the same as the low-voltage terminal of the GaN chip).

[0110] In some embodiments, the pull-down circuit block may be composed of a series of source-gate connected enhancement mode HEMTs. In other embodiments, the integrated pull-down circuit block may be a series of Schottky diodes or one or more Zener diodes.

[0111] In other embodiments, the integrated pull-down circuit block can be one or more normally-on or normally-off HEMTs connected in parallel or series. Additional capacitors or resistors may be connected in series with the HEMTs. The gate potential of the pull-down HEMT is controlled to set the voltage drop across the pull-down HEMT, thereby setting the gate voltage of the auxiliary low-voltage heterojunction transistor and the voltage drop across the same auxiliary low-voltage heterojunction transistor.

[0112] In one embodiment, the gate terminal of the pull-down HEMT may be connected to the output of a voltage divider between the gate terminal of the auxiliary HEMT and the third terminal.

[0113] In other embodiments, the gate terminal of the pull-down HEMT may be connected to the output of a voltage divider between the source or drain terminal of the auxiliary transistor and the third terminal.

[0114] In other embodiments, an additional current control block is connected to the drain or source of the auxiliary low-voltage heterojunction transistor. This additional current control block is connected to an additional pull-down circuit (connected to the third terminal). In this embodiment, the gate terminal of the first pull-down HEMT can be connected to the output of a voltage divider on the additional pull-down circuit.

[0115] In all of these embodiments of the pull-down circuit, the voltage divider may be composed of a resistive element, such as a resistor formed of a metal or a 2DEG; a capacitor; a current source formed of a depletion-mode HEMT with its source connected to the first terminal of the resistive element and its gate connected to the second terminal; a Schottky diode, an enhancement-mode HEMT with its gate terminal connected to its source terminal; a HEMT with its gate terminal connected to the output of the voltage divider between its drain and source; or a similar voltage divider circuit.

[0116] The pull-down circuit may also include an element to compensate for or reduce the effects of temperature. This element is a specific embodiment of a voltage divider. The first portion of the voltage divider may include an integrated resistor, while the second portion may include a current source consisting of a normally-on HEMT (with its source connected to the first terminal of the additional resistor and its gate connected to the second terminal of the resistor). The first portion of the voltage divider may also include a similar current source connected in parallel with the resistor. The second portion of the voltage divider may also include a resistor connected in parallel with the current source.

[0117] The two parts of the voltage divider will experience increasing voltage drops as temperature increases at a given current. However, the current source and resistor change their voltage drops at different rates. By sizing the normally-on HEMT and resistor, the output of the voltage divider can be designed so that the voltage drop across the pull-down circuit and / or the voltage drop across the auxiliary HEMT have less temperature dependence.

[0118] In some embodiments, the regulator and disable unit include a disable function. This disable function is achieved by turning on one or more normally-on or normally-off HEMTs in the integrated pull-down circuit block. This lowers the gate potential of the auxiliary HEMT and reduces or interrupts the current through the auxiliary HEMT. The signal that turns on the heterojunction transistor can be referred to as a disable signal. The disable signal can be provided by an external control chip directly or through an integrated circuit such as a logic inverter or voltage clamp. Furthermore, the disable signal can be provided by an additional integrated circuit such as a voltage protection circuit, a logic inverter, or a current protection circuit.

[0119] Because the heterojunction transistors in the current control block, as well as in the regulator and disable cells, are preferably low-voltage devices, their source and drain terminals can be interchanged, as they are typically fabricated in a symmetrical (or similar) manner. Low-voltage devices are those with a rated breakdown voltage typically below 20V and limited current capability (less than 100mA). However, it should be understood that these devices can also be high-power or high-voltage devices, although this increases cost and complexity.

[0120] According to another aspect of the present disclosure, a method for manufacturing a heterojunction power device based on a group III nitride semiconductor is provided, the method comprising:

[0121] forming a substrate;

[0122] forming a first III-nitride semiconductor region formed on the substrate, wherein the first III-nitride semiconductor region includes a first heterojunction including at least one two-dimensional carrier gas of the second conductivity type;

[0123] forming a first terminal operatively connected to the first Group III nitride semiconductor region;

[0124] forming a second terminal laterally spaced from the first terminal and operatively connected to the first Group III nitride semiconductor region; and

[0125] forming a first gate region over the first Group III nitride semiconductor region;

[0126] forming a second III-nitride semiconductor region formed on the substrate, wherein the second III-nitride semiconductor region includes a second heterojunction including at least one two-dimensional carrier gas of a second conductivity type;

[0127] forming a third terminal operatively connected to the second Group III nitride semiconductor region;

[0128] forming a fourth terminal laterally spaced apart from the third terminal in a first dimension and operatively connected to the second Group III-nitride semiconductor region;

[0129] forming a first plurality of highly doped semiconductor regions of the first conductivity type over the second Group III nitride semiconductor region between the third terminal and the fourth terminal; and

[0130] forming a second gate region above the first plurality of highly doped semiconductor regions,

[0131] wherein one of the first heterojunction transistor and the second heterojunction transistor is

[0132] An enhancement-mode field-effect transistor, and the other of the first heterojunction transistor and the second heterojunction transistor is a depletion-mode field-effect transistor.

[0133] The first plurality of highly doped semiconductor regions (in the enhancement-mode transistor) and the second plurality of highly doped regions (in the depletion-mode transistor) can be fabricated in the same process step. The distinction between continuous and discontinuous highly doped semiconductor regions can be achieved through layout changes using the same mask. Furthermore, the threshold voltage of the normally-off enhancement-mode transistor (with a continuous layer) can be the same as the second threshold voltage of the normally-on depletion-mode transistor. The ability to form both enhancement-mode and depletion-mode devices without any additional process steps is advantageous for cost reasons and facilitates the integration of the first and second heterojunction transistors.

[0134] This allows the integration of high-voltage depletion-mode GaN devices with high-voltage enhancement-mode GaN devices using a fabrication process that cannot be used to form high-voltage depletion-mode devices with Schottky contacts directly on the top AlGaN layer. In prior art devices, additional process steps must be used to fabricate the devices, and monolithic integration would be cumbersome. BRIEF DESCRIPTION OF THE DRAWINGS

[0135] Figure 1 shows a block diagram of a mains operated AC / DC switch mode power supply (SMPS) with output voltage regulation according to the prior art;

[0136] Figure 2 A schematic circuit diagram of a flyback converter according to the prior art is shown, wherein the flyback converter has an enhancement-mode power transistor used as a main power switch and a high-voltage depletion-mode transistor used as a startup component, wherein the high-voltage depletion-mode transistor charges an IC controller decoupling capacitor;

[0137] Figure 3 A schematic circuit diagram showing an enhancement mode power transistor and a high voltage depletion mode startup component;

[0138] Figure 4 shows a schematic cross-section of the active region of a state-of-the-art enhancement-mode p-GaN HEMT according to the prior art;

[0139] Figure 5 shows a schematic cross section of the active region of a state-of-the-art depletion-mode HEMT with a Schottky gate terminal;

[0140] Figure 6 A schematic perspective view showing a device according to an embodiment of the present disclosure;

[0141] Figure 7A shows a top view of a device according to other embodiments of the present disclosure, wherein a high voltage transistor and a depletion mode transistor share the same active region;

[0142] Figure 7B Shown Figure 7A a schematic perspective view of a portion of the device shown;

[0143] Figure 8 shows a schematic perspective view of a depletion mode device used as a component in an integrated device according to an embodiment of the present disclosure;

[0144] Figure 9A shows a schematic top view of a depletion mode device used as a component in an integrated device according to an embodiment of the present disclosure;

[0145] Figure 9B Shown Figure 9A A schematic cross-sectional view of a depletion-mode device is shown;

[0146] Figure 10A A top view of a device according to another embodiment of the present disclosure is shown, wherein the depletion mode device is Figure 5 Schottky gate device shown;

[0147] Figure 10B Shown Figure 10A a schematic perspective view of a portion of the device shown;

[0148] Figure 11 shows a schematic perspective view of a depletion mode device configured to operate in a diode mode for use as a component in an integrated device according to an embodiment of the present disclosure;

[0149] Figure 12A shows a schematic top view of a layout of a power HEMT with a continuous p-GaN gate monolithically integrated with an anti-parallel diode with a discontinuous p-GaN gate according to an embodiment of the present disclosure; and

[0150] Figure 12B Shown Figure 12A Schematic top view of the layout of the unit cell of the integrated HEMT / anti-parallel diode device is shown.

[0151] Figure 13 A schematic representation of an embodiment of a startup power supply circuit comprising an integrated interface circuit is shown. The integrated interface circuit consists of one or several current control blocks connected in series with the first terminal of a depletion-mode heterojunction transistor and one or several regulators and disable units.

[0152] Figure 14 A circuit schematic representation of an embodiment of a current control block comprising a depletion-mode heterojunction transistor and a resistive element is shown.

[0153] Figure 15 A circuit schematic representation of an embodiment of a regulator and a disabling unit is shown, wherein the current control block is connected to the source of an auxiliary heterojunction transistor, and wherein the auxiliary heterojunction transistor is a depletion-mode transistor.

[0154] Figure 16 A circuit schematic representation of an embodiment of a regulator and a disabling unit is shown, wherein the current control block is connected to the drain of an auxiliary heterojunction transistor, and wherein the auxiliary heterojunction transistor is an enhancement mode transistor.

[0155] Figure 17 A circuit schematic representation of an embodiment of a pull-down circuit is shown, the pull-down circuit including an enhancement mode heterojunction transistor in a threshold multiplier configuration and the enhancement mode heterojunction transistor controlled by a disable signal.

[0156] Figure 18 A schematic circuit representation of an embodiment of a pull-down circuit is shown, the pull-down circuit including an enhancement-mode heterojunction transistor configured in a threshold multiplier configuration and an enhancement-mode heterojunction transistor controlled by a disable signal. In this embodiment, a voltage divider of the pull-down circuit includes a temperature compensation circuit including a current source in parallel with a resistive element.

[0157] Figure 19 A circuit schematic representation of an embodiment of a regulator and a disabling unit is shown, wherein the pull-down circuit includes an enhancement-mode heterojunction transistor in a threshold multiplier configuration, in which a voltage divider is connected to the source of an auxiliary heterojunction transistor and the voltage divider includes a HEMT in a threshold multiplier configuration.

[0158] Figure 20 A circuit schematic representation of an embodiment of a regulator and a disabling unit is shown, wherein the pull-down circuit includes an enhancement-mode heterojunction transistor in a threshold multiplier configuration, in which a voltage divider is connected to the drain of an auxiliary heterojunction transistor and the voltage divider includes a HEMT in a threshold multiplier configuration.

[0159] Figure 21 A schematic circuit representation of another embodiment of a regulator and disable unit is shown, wherein the pull-down circuit includes an enhancement-mode heterojunction transistor in a threshold multiplier configuration, wherein a voltage divider of the pull-down circuit is connected to the source-assisted heterojunction transistor, and wherein the voltage divider includes a current source formed by a normally-on HEMT and a resistor, and the HEMT in a threshold multiplier configuration. In this embodiment, the output of the voltage divider is an external terminal of the HEMT in the threshold multiplier configuration.

[0160] Figure 22 A schematic circuit diagram of another embodiment of a regulator and disable unit is shown, in which the pull-down circuit includes an enhancement-mode heterojunction transistor configured as a threshold multiplier. In this embodiment, the current control block includes a resistive element connected to the source of the auxiliary heterojunction transistor. Furthermore, it includes an enhancement-mode heterojunction transistor controlled by a disable signal. DETAILED DESCRIPTION

[0161] The present disclosure will be more fully understood from the accompanying drawings, which should not, however, be considered limited to the particular embodiments shown, but are for purposes of illustration and understanding only.

[0162] Figure 6 A schematic perspective view of an active region of a GaN-based semiconductor device according to an embodiment of the present disclosure is shown. The device is presented in three dimensions: a first dimension (z direction), a second dimension (x direction), and a third dimension (y direction).

[0163] In this embodiment, the device comprises a semiconductor (e.g. silicon) substrate 4 defining a major (horizontal) surface at the bottom of the device. It will be appreciated that any other substrate used for GaN devices may be used. Examples of alternative substrate materials are sapphire, silicon carbide and GaN.

[0164] Below the substrate 4 there is a substrate terminal 5. The device comprises a transition layer 3 formed on top of the semiconductor substrate 4. The transition layer 3 comprises a combination of III-V semiconductor materials that serves as an intermediate step to allow subsequent growth of high quality III-V semiconductor material regions. The transition layer (also referred to as the buffer layer 3) may comprise a single layer of Al x GaN 1-x N (x varies between 0 and 1) or any Al to produce a multilayer stack x GaN 1-x N / GaN composition. It will be appreciated that the buffer layer 3 may not be used in the device, particularly when the substrate 4 is not Si.

[0165] A semiconductor region is formed on top of the buffer layer 3. The semiconductor region comprises several layers. The first semiconductor layer 2 is a high-quality III-V semiconductor (e.g., GaN) and may itself comprise several layers. The GaN semiconductor layer 2 is grown on top of the buffer 3 / substrate 4 stack using a suitable growth technique. Examples of these techniques include metal-organic chemical vapor deposition (MOCVD) and molecular beam epitaxy (MBE).

[0166] Another semiconductor layer 1 of a III-V semiconductor containing a molar fraction of aluminum is formed on top of the first semiconductor layer 2. The AlGaN layer 1 is formed so that a heterostructure is formed at the interface between the GaN layer 2 and the AlGaN layer 1, resulting in the formation of a two-dimensional electron gas (2DEG).

[0167] The device consists of a high-voltage enhancement-mode field-effect transistor (EFT) as the main power switch and a high-voltage depletion-mode EFT as the startup component. The EFT and the depletion-mode transistors are separated by an isolation region 20, which prevents undesired conduction between the two transistors.

[0168] The enhancement mode transistor includes a high voltage drain terminal 9 arranged in physical contact with the AlGaN layer 1. The high voltage drain terminal 9 forms an ohmic contact with the 2DEG. A low voltage source terminal 8 is also arranged in physical contact with the AlGaN layer 1 and also forms an ohmic contact with the 2DEG.

[0169] The enhancement-mode transistor includes a region of highly p-doped III-V semiconductor 11 formed in contact with AlGaN semiconductor layer 1. In this embodiment, this region is formed of p-GaN material. A gate control terminal 10 is disposed above highly doped region 11. The gate terminal comprises a metal contact placed on p-GaN region 11. Highly doped region 11 is a continuous layer (a strip or a closed shape surrounding a cell) of p-type GaN semiconductor placed on AlGaN layer 1, and p-type GaN semiconductor 11 is electrically connected to gate electrode 10.

[0170] The depletion-mode transistor also includes a high-voltage drain terminal 16 arranged in physical contact with the AlGaN layer 1. The high-voltage drain 16 terminal forms an ohmic contact to the 2DEG. A low-voltage source terminal 19 is also arranged in physical contact with the AlGaN layer 1 and also forms an ohmic contact to the 2DEG. The drain 16 terminal and the source 19 terminal are composed of ohmic metal contacts on the surface of the AlGaN layer 1, or directly contacted with a good electrical connection to the 2DEG.

[0171] Multiple regions of highly p-doped III-V semiconductor 18 are formed in contact with the AlGaN semiconductor layer 1. These regions, formed from p-GaN material in this embodiment, function to reduce the 2DEG carrier concentration beneath the highly doped regions 18 when the device is unbiased. The p-GaN regions 18 are discrete and spaced apart in the second dimension (the x-direction). The p-GaN regions 18 (also known as p-GaN islands) extend in discontinuous lines along the x-direction. The discontinuous layer of the p-type GaN gate is made of islands placed within a strip or closed shape. The highly p-doped GaN regions 18 can be magnesium (Mg) doped. They extend along an axis perpendicular to the axis connecting the source terminal 19 and the drain terminal 16 and along which current flows.

[0172] The highly doped layer 18 in the discontinuous gate structure of the depletion-mode device can be fabricated in the same process step as the highly doped layer 11 of the enhancement-mode device. All p-GaN layers (continuous or discontinuous) can be fabricated in the same process step. The differences between the continuous and discontinuous layers are achieved through layout changes using the same mask.

[0173] The gate control terminal 17 is positioned above the highly doped region 18 to control the carrier density of the 2DEG at the interface between semiconductor layer 1 and semiconductor layer 2. All p-GaN islands 18 in the depletion-mode device are connected to the same gate electrode 17. The gate terminal 17 consists of a metal contact placed on the intervening regions of the p-GaN islands 18. The electrical connection between the high-voltage terminal (drain) 16 and the low-voltage terminal (source) 19 is determined by a voltage signal applied to the third terminal (gate) 17. The gate control terminal 17 can be either an ohmic contact or a Schottky contact.

[0174] The discontinuous layers of p-type GaN gates 17 and 18 of the depletion mode transistor are connected to the source terminal 8 of the high voltage enhancement mode field effect transistor. Therefore, the source terminal 8 of the enhancement mode transistor is electrically connected to the gate terminal 17 of the depletion mode transistor.

[0175] The drain terminal 9 of the enhancement mode transistor is connected to the drain terminal 16 of the depletion mode transistor.

[0176] The source terminal 19 of the depletion-mode transistor is connected to an internal or external decoupling capacitor (not shown), so that the capacitor is charged when the depletion-mode transistor is in the on-state. As the decoupling capacitor becomes increasingly charged (increasing the voltage bias on the source 19 of the depletion-mode transistor), the gate-source voltage of the depletion-mode transistor becomes increasingly negative. When the source 19 voltage approaches the device threshold voltage, the depletion-mode transistor switches to the off-state (i.e., its resistance increases significantly).

[0177] Figure 7A A top view of a device according to other embodiments of the present disclosure is shown, in which a high-voltage enhancement-mode transistor and a depletion-mode transistor share the same active region. The figure shows the device in two dimensions: a first dimension (z-direction) and a second dimension (x-direction). The top view of the device shows a high-voltage main transistor and a depletion-mode transistor. A continuous p-GaN strip 11 is present in the gate 10 of the main enhancement-mode transistor, while a discontinuous strip 18 is present in the gate 17 of the depletion-mode transistor. The pad layout is shown. The gate 17 of the depletion-mode transistor and the source 8 of the main switch share the same pad. Except for the drain region 9 and the drain region 16, the two devices share the same active region and there is no specific separation between them. At the boundary, one side of the drain belongs to the main switch, while the other side of the drain belongs to the depletion-mode transistor.

[0178] Figure 7B Shown Figure 7A Schematic perspective view of a portion of the device shown in , indicated by area A.

[0179] Figure 8 A schematic perspective view of a depletion-mode device for use as a component in an integrated device according to an embodiment of the present disclosure is shown.

[0180] A 2DEG forms along the interface between the GaN layer 2 and the AlGaN layer 1. When a gate voltage is applied, the gate structure, comprising discontinuous p-GaN layers in islands 18 within the stripe, modulates the conductive path between the high-voltage drain terminal 16 and the low-voltage source terminal 19. By discontinuous islands, it is meant that there is no p-GaN layer between adjacent islands 18, and therefore a direct, unobstructed conductive path 13 exists between the source terminal 19 and the drain terminal 16. However, adjacent islands 18 within the stripe are placed close enough together to intersect (orthogonal to) the current path 13 so that a potential applied to the gate terminal 17 modulates the conductive region 13 between the islands 18 and, therefore, the direct path between the source 19 and the drain 16.

[0181] The conductive channel between drain terminal 16 and source terminal 19 is a two-dimensional electron gas (2DEG) formed at the interface of AlGaN / GaN heterostructure 1 and AlGaN / GaN heterostructure 2. P-doped GaN islands 18 are placed on the AlGaN surface 1 of the heterojunction, and at zero gate terminal bias, depletion of the conductive channel (2DEG) beneath the heterojunction occurs. At zero bias, an uninterrupted channel exists between source terminal 19 and drain terminal 16 along path 13, where p-doped GaN layer 18 is absent (between islands 18). At zero bias, the conductive channel exists in the region where p-GaN layer 18 is absent vertically above.

[0182] When a negative bias is applied to gate terminal 17 relative to source terminal 19, the carrier concentration in the conductive channel (region) between drain terminal 16 and source terminal 19 decreases due to a lateral electric field extending from p-doped GaN islands 18 to the region between the islands. This lateral electric field develops in the x-direction, perpendicular to the axis connecting source 19 and drain 16 terminals. This lateral field depletes the 2DEG, thereby increasing the 2DEG resistance between source 19 and drain 16. The critical gate bias at which the device is considered to transition from the on-state (low resistance) to the off-state (high resistance) is defined as the first threshold voltage. Note that instead of applying a negative potential to gate 17, it is also possible to maintain gate 17 at ground and apply a positive potential to source 19 to achieve the same result. As the bias on gate terminal 17 becomes increasingly negative, channel modulation, which enables the device to function as a transistor, is achieved by lateral JFET depletion of the conductive channel in regions where p-GaN islands 18 are not positioned vertically above.

[0183] Parameters that affect the first threshold voltage include, but are not limited to, the separation between the p-doped GaN islands 18, the thickness of the AlGaN layer 1, and the aluminum mole fraction of the AlGaN layer 1. Other parameters that affect the specific on-resistance of the depletion-mode transistor are the amount of separation between the p-doped GaN islands 18 and the length of the p-doped GaN islands 11 relative to the separation between the islands.

[0184] Since the discontinuous highly doped semiconductor layer of the depletion mode device is made of islands 18, and by changing the layout spacing between the discontinuous p-type islands 18, the depletion mode transistor is normally turned on until its source terminal 19 connected to the capacitor rises to the desired voltage level, and then the device is turned off.

[0185] As the gate-source voltage increases above the first threshold voltage but remains below the second threshold voltage, the formation of the 2DEG channel expands from the middle of the spacing between adjacent p-GaN islands 18 toward the edges of the p-GaN gate islands 18. As the on-state resistance decreases, the current continues to increase.

[0186] Depletion-mode devices have a second threshold voltage that is higher (more positive) than the first threshold voltage. This second threshold voltage is characterized by a sharp increase in current. This second threshold voltage level corresponds to the formation of a 2DEG directly beneath the p-GaN islands 18, rather than between the islands. When the 2DEG expands beneath the p-gate islands 18, allowing current to flow through this area, the current increases sharply, resulting in an increased conductive area. The sharpness (or gentleness) of the current reaching and exceeding the second threshold voltage depends on the ratio between the combined area of the pGaN islands 18 and the combined area of the regions (partitions) between the pGaN islands. A higher ratio results in a sharper (more abrupt) increase in current. A lower ratio results in a smoother increase in current upon reaching the second threshold voltage. This sharp increase in current sharply reduces on-state resistance.

[0187] In addition to epitaxy / process modifications, the threshold voltage of the depletion-mode device can also be adjusted through layout modifications. The depletion-mode device is thus a normally-on device (due to the negative first threshold voltage), but is characterized by a second, sharp increase in current when the second threshold voltage is reached. Furthermore, the proposed normally-on depletion-mode device can tolerate an increased positive gate bias (>7V) before the dominant conduction-state channel changes from drain-source to gate-source.

[0188] Figure 9A A schematic top view of a depletion mode transistor for use as a component in an integrated device according to an embodiment of the present disclosure is shown. Figure 8 The transistor shown in . The figure shows the device in two dimensions: a first dimension (z direction) and a second dimension (x direction).

[0189] Figure 9B Shown Figure 9A The edge of the depletion mode device shown Figure 9A Schematic cross section of the indicated cutting line. The figure shows the device in two dimensions: the second dimension (x-direction) and the third dimension (y-direction).

[0190] Figure 10A A top view of a device according to another embodiment of the present disclosure is shown, wherein the depletion mode device is Figure 5 The figure shows the device in two dimensions: a first dimension (z direction) and a second dimension (x direction). In this embodiment, the depletion mode device has a Schottky contact 12 as the gate contact.

[0191] Figure 10B Shown Figure 10A Schematic perspective view of a portion of the device shown. The device is presented in three dimensions: a first dimension (z-direction), a second dimension (x-direction), and a third dimension (y-direction).

[0192] Figure 11 A schematic perspective view of a depletion-mode device configured to operate in diode mode for use as a component in an integrated device according to an embodiment of the present disclosure is shown. The device is presented in three dimensions: a first dimension (z-direction), a second dimension (x-direction), and a third dimension (y-direction). In this embodiment, a normally-on depletion-mode MOSFET with discontinuous p-GaN islands 18 is configured for diode mode by connecting gate 17 and source 19 together. Alternatively, this can be accomplished by connecting drain 16 and gate 17 together.

[0193] The distance (spacing) between p-GaN islands 18 can be used to adjust the voltage level at which the diode conducts current in the forward mode. This is particularly advantageous compared to prior art devices using a continuous p-GaN layer, which results in a large forward voltage. For example, the spacing between adjacent p-GaN islands 18 (or adjacent multiple p-GaN islands in embodiments of devices with multiple p-GaN island strips) can be used to adjust the turn-on forward voltage to approximately 0.3V to 0.5V, which is typical for Schottky diodes in silicon. Schottky diodes are known to be more efficient than bipolar diodes due to their lower forward turn-on voltage and very low reverse recovery losses. To avoid undesirable negative turn-on voltages for the diode, the spacing between adjacent p-GaN islands 18 in this embodiment is very small (on the order of tens or hundreds of nanometers).

[0194] When a 2DEG forms beneath the p-GaN layer, a second increase in current occurs at a higher voltage level (above the open-circuit voltage level) during forward conduction. To minimize the on-state resistance during forward conduction, the diode can be operated above the second threshold voltage.

[0195] The diode shown in this embodiment can be used as a high voltage diode, having a source 19 and a gate 17 operatively connected to each other and having a drift region present between the drain side of the gate edge 17 and the drain terminal 16. The diode can also be used as a free-wheeling diode or an anti-parallel diode and can also be monolithically integrated with a normally-off GaN-based HEMT.

[0196] Figure 12AA schematic top view shows the layout of a power HEMT with a continuous p-GaN gate layer 18 monolithically integrated with an anti-parallel diode with a discontinuous p-GaN gate 18, according to an embodiment of the present disclosure. The device is presented in three dimensions: the first (z-direction), the second (x-direction), and the third (y-direction). The top view of the device shows a high-voltage main transistor and a depletion-mode transistor. A continuous p-GaN strip 11 is present in the gate 10 of the main enhancement-mode transistor, while a discontinuous strip 18 is present in the gate 17 of the diode. Aside from the drain regions 9 and 16, the two devices share the same active area and have no specific separation between them. At the boundary, one side of the drain belongs to the main switch, while the other side of the drain belongs to the depletion-mode transistor.

[0197] Figure 12B Shown by Figure 12A Schematic top view of the layout of a unit cell of an integrated HEMT / anti-parallel diode device shown as cell A in FIG. The figure shows the device in two dimensions: a first dimension (z-direction) and a second dimension (x-direction).

[0198] This shows a multi-finger structure for integrating anti-parallel diodes with discontinuous p-GaN islands 18. Figure 11 As shown, the diode in this embodiment is a diode according to an embodiment of the present disclosure. The main HEMT device is a normally-off device using a continuous p-GaN layer 11 connected to the device's gate 26. The diode (its source 19 is connected to its internal gate 17) has discontinuous p-GaN islands 18. In this particular layout example (shown here in a top view), in a single-finger structure, one side of the drain is part of the main power device (i.e., the normally-off p-GaN HEMT), while the other side 16 of the drain serves as the cathode 31 of the anti-parallel diode. The anti-parallel diode has an anode 30 terminal formed by connecting its internal source 19 and internal gate 17 together. The drain of the main HEMT is connected to the cathode 31 (drain 16) of the anti-parallel diode, while the source of the main HEMT is connected to the anode (source 19 and gate 17) of the anti-parallel diode.

[0199] When the main HEMT device is in the on-state (with an appropriate gate bias and a drain bias higher than the source bias), the antiparallel diode is turned off. The diode is in forward conduction (on-state) when the voltage at the HEMT's source terminal, connected to the diode's anode 30, is higher than the voltage at the HEMT's drain terminal, connected to the diode's cathode 31. In this embodiment, the diode's turn-on voltage can be controlled by the spacing (distance) between adjacent p-GaN islands 18. When the anode terminal 30 is at 0V (the diode's internal source-gate connection is at 0V), the spacing between adjacent p-GaN islands 11 is very small to allow the lateral depletion region to deplete the 2DEG between the p-GaN islands 18.

[0200] Alternatively, the diode's source terminal 19 can be configured as a Schottky contact to avoid the diode having a zero or negative turn-on voltage. In this case, the p-GaN islands 18 also serve to reduce leakage in the off state, reducing leakage caused by tunneling through the Schottky contact in blocking mode (reverse bias of the diode) and pushing the electric field away from the Schottky contact (the diode's anode) towards the cathode.

[0201] The gate contact 17 in contact with the p-GaN island 18 can be made of ohmic or Schottky metallization. The Schottky contact has the advantage of low gate leakage current, while the ohmic contact is beneficial for improving device stability and passivating the recess in the AlGaN and GaN buffer layers through hole injection.

[0202] In addition, the diode mode devices described herein can be used in pull-down networks during the turn-off period of the auxiliary gate device described in PCT publication WO / 2019 / 012293A1, and this disclosure is incorporated herein by reference in its entirety.

[0203] In other examples of embodiments of the present disclosure, a circuit is provided that includes the heterojunction power device described above and further includes an integrated interface circuit that provides at least one of the following functions: a current control function, a voltage control function, and a disable function. The integrated interface circuit provides improved features for integrated startup power circuits and improved integration into power systems.

[0204] Figure 13A schematic diagram of an exemplary embodiment of an integrated interface circuit is shown. The circuit consists of a number of building blocks. The drain of the integrated depletion-mode transistor is connected to the drain of the enhancement-mode power transistor, and the gate is connected to the source terminal of the enhancement-mode power transistor. Note that the gate of the depletion-mode transistor can be connected to other low voltage nodes, internal or external, without changing the essence of the invention; for example, the gate of the depletion-mode transistor can be connected to an internal or external ground potential or a potential close to ground, to an internal or external Kelvin terminal, which is connected to a first terminal or a low voltage power supply node, or using a resistive element. In Figure 13 In the embodiment shown, the current from the source of the depletion mode transistor 21 passes through the current control block 51 before reaching the regulator and disable unit 50. The output of the regulator and disable unit can be a lower, regulated voltage. Alternatively, the regulator and disable unit 50 can disconnect the current source from the load side. Figure 13 In the embodiment shown, the current will flow through the second current control unit 52 before reaching the load 53. Additional capacitors 54, 55, 56, 57, 58 can be integrated before and after each block to improve performance. Figure 13 The combination of the three integrated blocks is only an example. More or fewer current control blocks, regulators and disable units are possible without changing the essence of the present invention.

[0205] Figure 14 An embodiment of a current control block 60 is shown comprising a depletion-mode heterojunction transistor 60b and a resistive element 60a, wherein the source of the transistor is connected to a first terminal and the gate is connected to a second terminal of the resistive element.

[0206] Figure 15 and Figure 16 Two embodiments of the regulator and disable units 67, 68 are shown. These units include auxiliary heterojunction transistors 63, 64, which can be enhancement mode transistors or depletion mode transistors. They also include pull-down circuits 61, 66, which together with the current control blocks 62, 65 define the voltage at the gate of the auxiliary heterojunction transistors. The current control blocks can be as follows Figure 15 connected to the source of the auxiliary transistor as shown, or as Figure 16 In addition, the pull-down blocks 61, 66 may include an input terminal for a disable signal. Adding a disable signal may reduce the voltage drop across the pull-down circuit, increase the voltage drop across the auxiliary transistor, or even completely turn off the auxiliary transistor.

[0207] Figures 17 to 18 Various exemplary embodiments of pull-down circuits are shown. Figure 17 An embodiment of a pull-down circuit 77 is shown, comprising an enhancement mode heterojunction transistor 74 having its gate connected to the outputs of voltage dividers 75 , 76 . Figure 18 An embodiment is shown in which current sources 82, 83 are connected in parallel to a resistive element 80, which forms part of a voltage divider 79, 80. This can change the temperature characteristics of the voltage drop across this part of the voltage divider at a given current. The resistive elements and depletion mode transistors in the current sources can be sized so that the effects of temperature on the output voltage can be partially compensated.

[0208] Figure 19 and Figure 20 Schematic representation of a circuit of two exemplary embodiments of a regulator and disabling unit 93, 99 is shown, wherein the voltage dividers 87, 88, 89, 90, 97, 98, 101, 102 of the pull-down circuit are connected to the sources of the auxiliary heterojunction transistors 91, 95 (e.g. Figure 19 as shown) or drain (as Figure 20 ). In addition, in these embodiments, the voltage divider includes enhancement mode heterojunction transistors 86, 92, 94, 103 configured in a threshold multiplier configuration. Figure 19 In the embodiment of FIG, an enhancement mode transistor configured as a threshold multiplier causes a voltage drop, similar to a Zener diode. The pull-down circuit is activated only when the source of the auxiliary transistor reaches this voltage. Figure 20 In the embodiment shown, the same threshold multiplier arrangement limits the gate voltage of the enhancement mode transistor forming the pull-down circuit.

[0209] Figure 21 A further embodiment of the regulator and disabling unit 112 is shown, wherein the voltage divider of the pull-down circuit is connected to the drain of the auxiliary transistor 107. In this embodiment, the voltage divider comprises additional current control blocks 104, 105 and an enhancement transistor 106 configured as a threshold multiplier, and wherein the output of the voltage divider is the gate of the latter transistor.

[0210] Figure 22 A schematic circuit diagram of another exemplary embodiment of a regulator and disable unit 119 is shown, wherein the pull-down circuit includes an enhancement-mode heterojunction transistor 116 configured as a threshold multiplier. In this embodiment, the current control block includes a resistive element 113 connected to the source of the auxiliary heterojunction transistor. In addition, it includes an enhancement-mode heterojunction transistor 115 controlled by a disable signal.

[0211] Reference Signs List

[0212] 1 AlGaN layer

[0213] 2 GaN layer

[0214] 3 Transition layer

[0215] 4 Substrate

[0216] 5 Substrate terminals

[0217] 6 SiO2 passivation

[0218] 7 Surface passivation dielectric

[0219] 8 Enhanced source terminal

[0220] 9 Enhanced drain terminal

[0221] 10 Enhancement gate terminal

[0222] 11 Enhanced-mode p-GaN capping

[0223] 12 Schottky gate terminal

[0224] 13 Conductive channel at zero bias

[0225] 14 Connection of Enhancement Mode Source Terminal to Depletion Mode Gate Terminal

[0226] 15 Connection from Enhancement Drain Terminal to Depletion Drain Terminal

[0227] 16 Depletion drain terminal

[0228] 17 Depletion gate terminal

[0229] 18 Depletion-mode p-GaN region

[0230] 19 Depletion source terminal

[0231] 20 Isolation

[0232] 21 Depletion-mode devices

[0233] 22 Enhanced devices

[0234] 26 Gate pad metal

[0235] 27 Source pad metal

[0236] 28 Drain pad metal

[0237] 29 active area

[0238] 30 diode anode

[0239] 31 diode cathode

[0240] 50 disabled units

[0241] 51 Current control block

[0242] 52 Current control block

[0243] 53 Resistor

[0244] 54 capacitors

[0245] 55 capacitor

[0246] 56 capacitors

[0247] 57 Capacitor

[0248] 58 capacitors

[0249] 59 Voltage Source

[0250] 60 Current control block

[0251] 60A resistor element

[0252] 60b heterojunction transistor

[0253] 61 Pull-down circuit

[0254] 62 Current control block

[0255] 63 Auxiliary heterojunction transistor

[0256] 64 Auxiliary heterojunction transistor

[0257] 65 Current control block

[0258] 66 Pull-down circuit

[0259] 67 Regulator and Disable Unit

[0260] 68 Regulator and Disable Unit

[0261] 73 Heterojunction Transistor

[0262] 74 Heterojunction Transistor

[0263] 75 resistor element

[0264] 76 Resistor

[0265] 77 Pull-down circuit

[0266] 78 Heterojunction Transistor

[0267] 79 Resistor

[0268] 80 resistor element

[0269] 81 Heterojunction Transistor

[0270] 82 Heterojunction Transistor

[0271] 83 Resistor

[0272] 84 Pull-down circuit

[0273] 85 Current control block

[0274] 86 Heterojunction Transistor

[0275] 87 Resistor

[0276] 88 resistor element

[0277] 89 Resistor

[0278] 90 Resistor

[0279] 91 Heterojunction Transistor

[0280] 92 Heterojunction Transistor

[0281] 93 Regulator and Disable Unit

[0282] 94 Heterojunction Transistor

[0283] 95 Heterojunction Transistor

[0284] 96 Current Control Block

[0285] 97 Resistor

[0286] 98 resistor element

[0287] 99 Regulator and Disable Unit

[0288] 100 GaN integrated circuits

[0289] 101 Resistor

[0290] 102 resistor elements

[0291] 103 Heterojunction Transistor

[0292] 104 Heterojunction Transistor

[0293] 105 resistor element

[0294] 106 Heterojunction Transistor

[0295] 107 Heterojunction Transistor

[0296] 108 Current Control Block

[0297] 109 Heterojunction Transistor

[0298] 110 resistor element

[0299] 111 Resistor

[0300] 112 Regulator and Disable Unit

[0301] 113 Resistor

[0302] 114 Heterojunction Transistor

[0303] 115 Heterojunction Transistor

[0304] 116 Heterojunction Transistor

[0305] 117 Resistor

[0306] 118 resistor element

[0307] 119 Regulator and Disable Unit

[0308] In this disclosure, unless otherwise specified, a heterojunction transistor may be any known heterojunction-based transistor, such as a p-gate HEMT transistor, or a Schottky-gate transistor or an insulated-gate transistor, such as a MISFET (Metal Insulator Semiconductor Field-Effect Transistor). A diode may be a Schottky diode, a Zener diode, or a pn diode, or a diode formed from a transistor by connecting a gate terminal to any other terminal. The heterojunction chip or heterojunction power device described in this disclosure may be referred to as a heterojunction intelligent power device, a heterojunction intelligent chip, a heterojunction power integrated circuit, or a heterojunction integrated circuit.

[0309] A skilled artisan will appreciate that in the preceding description and the appended claims, positional terms such as "top," "above," "overlapping," "below," "side," and the like are made with reference to conceptual illustrations of the device, such as those showing standard cross-sectional perspective views and those shown in the accompanying drawings. These terms are used for ease of reference and are not intended to be limiting. Therefore, these terms should be understood to refer to the device when in the orientation shown in the accompanying drawings.

[0310] Although the present disclosure has been described in terms of preferred embodiments as set forth above, it should be understood that these embodiments are illustrative only and that the claims are not limited to these embodiments. In light of this disclosure, those skilled in the art will be able to make modifications and substitutions, which are considered to fall within the scope of the appended claims. Each feature disclosed or shown in this specification, whether alone or in any suitable combination with any other features disclosed or shown herein, may be included in the present disclosure.

[0311] Many other effective alternatives will occur to those skilled in the art.It should be understood that the present disclosure is not limited to the described embodiments, but includes all modifications that fall within the spirit and scope of the present disclosure.

Claims

1. A heterojunction power device based on a group III nitride semiconductor, comprising: A first heterojunction transistor is formed on a substrate, wherein the first heterojunction transistor includes: a first III-nitride semiconductor region formed on the substrate, wherein the first III-nitride semiconductor region includes a first heterojunction including at least one two-dimensional carrier gas of the second conductivity type; a first terminal operatively connected to the first Group III nitride semiconductor region; a second terminal laterally spaced from the first terminal and operatively connected to the first Group III nitride semiconductor region; a first gate region formed on the first Group III nitride semiconductor region between the first terminal and the second terminal; and A second heterojunction transistor is formed on the substrate, wherein the second heterojunction transistor comprises: a second III-nitride semiconductor region formed on the substrate, wherein the second III-nitride semiconductor region includes a second heterojunction including at least one two-dimensional carrier gas of the second conductivity type; a third terminal operatively connected to the second Group III nitride semiconductor region; a fourth terminal laterally spaced from the third terminal in a first dimension and operatively connected to the second Group III-nitride semiconductor region; a first plurality of highly doped semiconductor regions of a first conductivity type formed on the second Group III nitride semiconductor region, the first plurality of highly doped semiconductor regions being formed between the third terminal and the fourth terminal; and a second gate region operatively connected to the first plurality of highly doped semiconductor regions, wherein one of the first heterojunction transistor and the second heterojunction transistor is an enhancement-mode field-effect transistor, and the other of the first heterojunction transistor and the second heterojunction transistor is a depletion-mode field-effect transistor; and The heterojunction power device further includes a capacitor electrically connected to the third terminal.

2. The heterojunction power device according to claim 1, wherein: The first heterojunction of the first Group III nitride semiconductor region comprises: a first Group III nitride semiconductor layer having a first band gap and formed on the substrate; a second Group III nitride semiconductor layer having a second band gap different from the first band gap and provided on the first Group III nitride semiconductor layer; and at least one two-dimensional carrier gas of a second conductivity type formed at an interface between the first Group III nitride semiconductor layer and the second Group III nitride semiconductor layer to provide a channel; and The second heterojunction of the second group III nitride semiconductor region includes: a third Group III nitride semiconductor layer having a first band gap and formed on the substrate; a fourth Group III nitride semiconductor layer having a second band gap different from the first band gap and provided on the third Group III nitride semiconductor layer; and At least one two-dimensional carrier gas of the second conductivity type is formed at an interface between the third Group III nitride semiconductor layer and the fourth Group III nitride semiconductor layer to provide a channel.

3. The heterojunction power device according to claim 2, wherein: Each of the first, second, third, and fourth III-nitride semiconductor layers comprises any one of gallium nitride (GaN), aluminum gallium nitride (AlGaN), and indium aluminum gallium nitride (InAlGaN), and wherein the at least one two-dimensional carrier gas is a two-dimensional electron gas (2DEG) or a two-dimensional hole gas (2DHG).

4. The heterojunction power device according to claim 1, wherein: The first heterojunction transistor is configured as an enhancement mode field effect transistor used as a power switch, and wherein the second heterojunction transistor is configured as a depletion mode field effect transistor used as a startup device.

5. The heterojunction power device according to claim 1, wherein: The gate region of any of the transistors is characterized by a Schottky contact or an Ohmic contact to the metal contact layer.

6. The heterojunction power device according to claim 1, wherein: The first heterojunction transistor further includes at least one highly doped semiconductor region of the first conductivity type formed on the first Group III nitride semiconductor region. The at least one highly doped semiconductor region is formed between the first terminal and the second terminal, and wherein a first gate terminal is formed on the at least one highly doped semiconductor region, and The first plurality of highly doped semiconductor regions in the second heterojunction transistor further include: at least two highly doped semiconductor regions of the first conductivity type that are in contact with the second III-nitride semiconductor region and are laterally spaced apart from each other in the second dimension.

7. The heterojunction power device according to claim 6, wherein: The first dimension defined by the current in the on-state is perpendicular to the second dimension.

8. The heterojunction power device according to claim 1, wherein: The first heterojunction transistor and the second heterojunction transistor are monolithically integrated within a single device.

9. The heterojunction power device according to claim 1, further comprising: An isolation structure is formed between the first heterojunction transistor and the second heterojunction transistor.

10. The heterojunction power device according to claim 1, wherein: The second terminal is operatively connected to the fourth terminal.

11. The heterojunction power device according to claim 10, wherein: The second terminal and the fourth terminal are configured as a self-isolating structure.

12. The heterojunction power device according to claim 1, wherein: The first terminal is operatively connected to the second gate region.

13. The heterojunction power device according to claim 1, wherein: The second gate region is connected to an internal ground or an external ground or a potential close to ground.

14. The heterojunction power device according to claim 1, wherein: The second gate region is connected to a Kelvin terminal connected to the first terminal.

15. The heterojunction power device according to claim 1, wherein: The first heterojunction transistor and the second heterojunction transistor share a same active region.

16. The heterojunction power device according to claim 1, wherein: The second heterojunction transistor is configured as a diode, and the third terminal is connected to the second gate region.

17. The heterojunction power device according to claim 16, wherein: The diode is connected to the first heterojunction transistor in an anti-parallel configuration, and wherein the first terminal is connected to the third terminal and the second terminal is connected to a fourth terminal.

18. A circuit comprising the heterojunction power device according to claim 1.

19. A circuit comprising one or more heterojunction power devices according to claim 1.

20. A circuit comprising at least two heterojunction power devices according to claim 1 arranged in a half-bridge configuration.

21. A circuit comprising at least two heterojunction power devices according to claim 17 arranged in a half-bridge configuration.

22. A method for manufacturing a heterojunction power device based on a Group III nitride semiconductor, the method comprising: forming a substrate; forming a first III-nitride semiconductor region formed on the substrate, wherein the first III-nitride semiconductor region includes a first heterojunction including at least one two-dimensional carrier gas of the second conductivity type; forming a first terminal operatively connected to the first Group III nitride semiconductor region; forming a second terminal laterally spaced from the first terminal and operatively connected to the first Group III nitride semiconductor region; and forming a first gate region on the first Group III nitride semiconductor region; forming a second III-nitride semiconductor region formed on the substrate, wherein the second III-nitride semiconductor region includes a second heterojunction including at least one two-dimensional carrier gas of a second conductivity type; forming a third terminal operatively connected to the second Group III nitride semiconductor region; forming a fourth terminal laterally spaced apart from the third terminal in a first dimension and operatively connected to the second Group III-nitride semiconductor region; forming a first plurality of highly doped semiconductor regions of the first conductivity type on the second Group III nitride semiconductor region between the third terminal and the fourth terminal; and forming a second gate region on the first plurality of highly doped semiconductor regions, wherein one of the first heterojunction transistor and the second heterojunction transistor is an enhancement-mode field-effect transistor, and the other of the first heterojunction transistor and the second heterojunction transistor is a depletion-mode field-effect transistor; and Connect a capacitor to the third terminal.

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