Method for correcting layout
By expanding and correcting the DRAM array layout, the problem of inaccurate optical proximity correction is solved, the reliability and product yield of OPC are improved, and the uniformity of key sizes is ensured.
Patent Information
- Application Number
- CN202010846878.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2020-08-21
- Publication Date
- 2025-07-25
- Estimated Expiration
- 2040-08-21
AI Technical Summary
During the DRAM array layout correction process, the prior art failed to effectively consider the impact of optical diameter, resulting in inaccurate optical proximity correction, uneven key dimensions and fluctuations in photoresist profiles, affecting product yield.
By providing methods for initial layout expansion and correction, including expanding the initial layout, reconstructing the hierarchy and correcting, ensuring key dimension uniformity, avoiding photoresist layer profile fluctuations, and using inversion lithography technology for precise correction.
It improves the reliability of OPC, ensures product yield, avoids fluctuations in the outline of the photoresist layer, and achieves uniformity of key dimensions.
Smart Images
Figure CN114077159B_ABST
Abstract
Description
Technical Field
[0001] This application belongs to the field of semiconductor technology, and particularly relates to a method for correcting a layout. Background Art
[0002] Currently, when correcting the layout of a DRAM (Dynamic Random Access Memory) array, to save time, a layout area with a smaller size is usually selected for correction, and then this layout area is expanded into a larger array area. The influence of the optical diameter is not considered in this smaller-size layout area, which will lead to inaccurate optical proximity correction, resulting in uneven critical dimensions (CD) or fluctuations in the photoresist profile on the wafer, and further affecting the product yield. Summary of the Invention
[0003] Based on this, it is necessary to provide a method for correcting a layout that can solve the above problems in view of the problems in the above background art.
[0004] This application provides a method for correcting a layout, including:
[0005] Providing an initial layout;
[0006] Expanding the initial layout to obtain an expanded layout;
[0007] Correcting the expanded layout to obtain a corrected layout;
[0008] Obtaining a target layout based on the corrected layout.
[0009] After correcting the layout using the method for correcting a layout in the above embodiment, the reliability of OPC is higher, the critical dimensions are uniform, and it will not cause fluctuations in the photoresist layer profile on the wafer, thereby ensuring the product yield.
[0010] In one embodiment, the initial layout includes a central layout and a peripheral layout, and the peripheral layout surrounds the outside of the central layout unit.
[0011] In one example, the initial layout is expanded based on the relationship between the size of the peripheral layout and the optical diameter.
[0012] In one embodiment, when the size of the peripheral layout is smaller than the optical diameter, the central layout is two-dimensionally expanded and the peripheral layout is one-dimensionally expanded to obtain an expanded layout;
[0013] The expanded layout includes the central layout and a peripheral expanded layout, and the peripheral expanded layout includes the expanded peripheral layout and the expanded central layout.
[0014] In one embodiment, the expansion of the initial layout stops when the size of the peripheral expansion layout is greater than the optical diameter.
[0015] In one embodiment, it further includes:
[0016] Re-expand the expanded layout.
[0017] In one embodiment, the re-expansion of the expanded layout includes:
[0018] Perform two-dimensional expansion on the central layout and one-dimensional expansion on the peripheral expansion layout.
[0019] In one embodiment, the correction of the expanded layout to obtain a corrected layout includes:
[0020] Reconstruct the hierarchical structure of the expanded layout;
[0021] Perform correction on the reconstructed expanded layout to obtain a corrected layout.
[0022] In one embodiment, the reconstruction of the hierarchical structure of the expanded layout includes:
[0023] Reconstruct the central layout and the expanded central layout into an array of two-dimensional structural units, and the array of two-dimensional structural units has a first direction and a second direction.
[0024] In one embodiment, the reconstruction of the hierarchical structure of the expanded layout further includes:
[0025] Reconstruct part of the peripheral expansion layout into an array of two-dimensional structural units.
[0026] In one embodiment, the reconstruction of the hierarchical structure of the expanded layout further includes:
[0027] Reconstruct the peripheral expansion layout into a first one-dimensional unit array, a second one-dimensional unit array and a connection layout; the connection layout is located between the first one-dimensional unit array and the second one-dimensional unit array.
[0028] In one embodiment, the array of two-dimensional structural units has a first length along the first direction and a second length along the second direction;
[0029] The first one-dimensional unit array has a first extension length along the first direction and the first extension length is the same as the first length;
[0030] The second one-dimensional unit array has a second extension length along the second direction and the second extension length is the same as the second length.
[0031] In one embodiment, obtaining the target layout based on the corrected layout includes:
[0032] Extracting the central layout, the connection layout, and a part of the first one-dimensional cell array and a part of the second one-dimensional cell array corresponding to the central layout of the corrected layout, and combining them to form the target layout.
[0033] In one embodiment, it further includes:
[0034] Expanding the target layout to obtain the complete layout. Description of the Drawings
[0035] To more clearly illustrate the technical solutions of the embodiments of the present application, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.
[0036] Figure 1 It is a flowchart of the layout correction method provided by the present application.
[0037] Figures 2 to 8 It is a schematic diagram of the layout obtained in each step of the layout correction method provided by the present application.
[0038] Description of the reference numerals: 10, initial layout; 101, central layout; 102, peripheral layout; 11, extended layout; 111, peripheral extended layout; 1111, extended peripheral layout; 1112, extended central layout; 12, corrected layout; 121, 122, two-dimensional structure cell array; 123, first one-dimensional cell array; 124, second one-dimensional cell array; 125, connection layout; 13, target layout; 14, complete layout. Detailed Embodiments
[0039] To facilitate the understanding of the present application, the following will describe the present application more comprehensively with reference to the relevant drawings. The preferred embodiments of the present application are shown in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the understanding of the disclosure content of the present application more thorough and comprehensive.
[0040] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the technical field to which the present application belongs. The terms used in the description of the present application in this specification are only for the purpose of describing specific embodiments and are not intended to limit the present application. The term "and / or" used herein includes any and all combinations of one or more of the related listed items.
[0041] In the case of using "including", "having", and "containing" described in this text, unless explicit limiting terms are used, such as "only", "consisting of", etc., another component can also be added. Unless otherwise mentioned, terms in the singular form can include the plural form and should not be understood as having a quantity of one.
[0042] Please refer to Figure 1 , this application provides a method for correcting a layout, including the following steps:
[0043] S11: Provide an initial layout;
[0044] S12: Expand the initial layout to obtain an expanded layout;
[0045] S13: Correct the expanded layout to obtain a corrected layout;
[0046] S14: Obtain a target layout based on the corrected layout.
[0047] After correcting the layout using the layout correction method in the above embodiment, the reliability of the OPC is higher, the critical dimensions are uniform, and it will not cause fluctuations in the profile of the photoresist layer on the wafer, thus ensuring the yield of the product.
[0048] In step S11, please refer to Figure 1 S11 in Figure 2 , and provide the initial layout 10.
[0049] In one example, the initial layout 10 includes a central layout 101 and a peripheral layout 102, and the peripheral layout 102 surrounds the outside of the central layout unit 101. Specifically, in this embodiment, the initial layout 10 can be a 9-cell structure, that is, as Figure 2 shown, the number of the central layout 101 is one, that is, Figure 1 layout C in
[0050] In step S12, please refer to Figure 1 step S12 in Figures 3 to 4 , and expand the initial layout 10 to obtain an expanded layout 11.
[0051] In one example, the initial layout 10 is expanded based on the relationship between the size of the peripheral layout 102 and the optical diameter.
[0052] In one example, asFigure 3 As shown, when the size of the peripheral layout 102 is smaller than the optical diameter, two-dimensional expansion of the central layout 101 and one-dimensional expansion of the peripheral layout 102 are performed to obtain the expanded layout 11; the expanded layout 11 includes the central layout 101 and the peripheral expanded layout 111, and the peripheral expanded layout 111 includes the expanded peripheral layout 1111 and the expanded central layout 1112. The size of the peripheral layout 102 can be understood as the minimum distance from the outer boundary of the peripheral layout 102 to the outer boundary of the central layout 101. The size of the optical diameter (OD: Optical Diameter) is obtained according to the following empirical formula. The empirical formula for the optical diameter is: OD = 20(λ / NA) / (1 + sigmamax). If sigmamax = 1, NA = 1.35, and λ = 193 nm, then OD is 1.43 um. For example, when the boundaries of the layout UL, layout L, layout LL, layout B, layout T, layout UR, layout R, and layout LR are all rectangles, as long as the length or width of the rectangular boundary of any one of the layouts UL, L, LL, B, T, UR, R, and LR is smaller than the optical diameter, the initial layout 10 needs to be expanded to obtain the expanded layout 11. In this example, the central layout 101 is expanded two-dimensionally once, and the peripheral layout 102 is expanded one-dimensionally to obtain the expanded layout 11; that is, the expanded central layout 1112 in the expanded layout 11 includes eight layouts C obtained by expanding the central layout 101, and the expanded peripheral layout 1111 includes one layout UL, one layout UR, one layout LL, one layout LR, three layouts L, three layouts R, three layouts T, and three layouts B. The expanded central layout 1112 and the expanded peripheral layout 1111 form a new peripheral layout, that is, the peripheral expanded layout 111.
[0053] Specifically, if the size of the peripheral expanded layout 111 in the expanded layout 11 obtained after one expansion, such as Figure 3 is greater than the optical diameter, the expansion of the initial layout 10 stops. If the size of the peripheral expanded layout 111 in the expanded layout 11 obtained after one expansion, such as Figure 3 is smaller than the optical diameter, the obtained expanded layout 11 needs to be expanded again until the size of the peripheral expanded layout 111 in the obtained expanded layout 11 is greater than the optical diameter. The size of the peripheral expanded layout 111 can be understood as the minimum distance from the outer boundary of the new peripheral layout formed by the expanded central layout 1112 and the expanded peripheral layout 1111 to the outer boundary of the central layout 101.
[0054] In one example, the extended layout 11 is further extended, including: two-dimensionally extending the central layout 101 and one-dimensionally extending the peripheral extended layout 111. The number of extensions is determined by the size of the peripheral extended layout 111 in the obtained extended layout 11 and the size of the optical diameter. After the extension, the obtained extended layout 11 is as Figure 4 shown.
[0055] In step S13, please refer to Figure 1 step S13 in and Figures 5 to 6 , and the extended layout 11 is corrected to obtain the corrected layout 12.
[0056] In one example, step S13 may include the following steps:
[0057] S131: Reconstruct the hierarchical structure of the extended layout 11;
[0058] S132: Correct the reconstructed extended layout 11 to obtain the corrected layout 12.
[0059] In one example, step S131 may include the following steps:
[0060] Reconstruct the central layout 101 and the extended central layout 1112 into a two-dimensional structural unit array 121, as Figure 5 shown. The two-dimensional structural unit array 121 has a first direction and a second direction.
[0061] In one example, after reconstructing the central layout 101 and the extended central layout 1112 into the two-dimensional structural unit array 121, step S131 further includes the following steps:
[0062] Reconstruct part of the peripheral extended layout 111 into a two-dimensional structural unit array 122, as Figure 5 shown. For example, the two-dimensional structural unit array 122 may be an active area array in a DRAM memory cell array region.
[0063] It should be noted that Figure 5 the squares in each two-dimensional structural unit array are the peripheral layout 1111 or the extended central layout 1112 extended before reconstruction.
[0064] Specifically, the first direction may be the direction from the two-dimensional structural array unit L' to the two-dimensional structural array unit R' in Figure 5 , and the second direction may be the direction from the two-dimensional structural array unit T' to the two-dimensional structural array unit B' in Figure 5 .
[0065] In another example, after reconstructing the central layout 101 and the extended central layout 1112 into an array of two-dimensional structural units 121, step S131 may further include the following steps:
[0066] Reconstruct the peripheral extended layout 111 into a first one-dimensional unit array 123, a second one-dimensional unit array 124 to connect the layout 125; the connection layout 125 is located between the first one-dimensional unit array 123 and the second one-dimensional unit array 124, as Figure 6 shown. Figure 6 The first one-dimensional unit array 123 in is several unit Xs arranged along the first direction between the two-dimensional structural units CR, and the second one-dimensional unit array 124 is several unit Ys arranged along the second direction between the two-dimensional structural units CR. Specifically, the distance between unit Xs can be the pitch of 1 cycle in the first direction of the basic unit; the distance between unit Ys can be the pitch of 1 cycle in the second direction of the basic unit. For example, the basic unit can be a single active region in the DRAM storage array region.
[0067] In one example, the two-dimensional structural unit array 121 has a first length in the first direction and a second length in the second direction; the first one-dimensional unit array 123 has a first extended length in the first direction and the first extended length is the same as the first length; the second one-dimensional unit array 124 has a second extended length in the second direction and the second extended length is the same as the second length.
[0068] It should be noted that the first extended direction of the first one-dimensional unit array 123 is the arrangement direction of several unit Xs, and the second extended direction of the second one-dimensional unit array 124 is the arrangement direction of several unit Ys.
[0069] In step S132, the inverted lithography technology can be used to correct the reconstructed extended layout 11 to obtain the corrected layout 12.
[0070] In step S14, please refer to Figure 1 the S14 step in and Figures 7 to 8 , and based on the corrected layout 12, obtain the target layout 13.
[0071] In one example, step S14 may include the following steps:
[0072] Extract the central layout 101, the connection layout 125 of the corrected layout 12, and the corresponding part of the first one-dimensional unit array 123 and the second one-dimensional unit array 124 of the central layout 101 and merge them to form the target layout 13, as Figure 7 shown.
[0073] Specifically, the obtained target layout 13 includes 9 two-dimensional structural unit arrays, that is, the target layout 13 includes asFigure 7 The two-dimensional structure unit arrays UL'', UR'', LL'', LR'', L'', C'', R'', T'' and B'' shown in
[0074] In another example, after combining to form the target layout 13, the following steps may further be included:
[0075] The target layout 13 is expanded to obtain the full layout 14, and the diagram of the full layout 14 is as Figure 8 shown. Specifically, the two-dimensional structure unit array C'' of the corrected target layout 13 is two-dimensionally expanded; the two-dimensional structure unit arrays L'', R'', T'' and B'' are one-dimensionally expanded. The target layout can be directly expanded according to the actual size of the full layout to obtain the corrected full layout, and the corrected full layout can ensure the correction accuracy of OPC. For example, the full layout may be the entire layout of the DRAM memory cell array area.
[0076] The technical features of the above-described embodiments can be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as the scope recorded in this specification.
[0077] The above-described embodiments only represent several implementation manners of the present application. The description is relatively specific and detailed, but it should not be construed as a limitation on the scope of the patent application. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present application, several modifications and improvements can still be made, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application shall be subject to the appended claims.
Claims
1. A method for correcting a layout, characterized in that including: providing an initial layout; extending the initial layout to obtain an extended layout; correcting the extended layout to obtain a corrected layout; obtaining a target layout based on the corrected layout; wherein, the initial layout includes a central layout and a peripheral layout, and the peripheral layout surrounds the outside of the central layout unit; extending the initial layout based on the relationship between the size of the peripheral layout and the optical diameter; when the size of the peripheral layout is smaller than the optical diameter, performing two-dimensional extension on the central layout and one-dimensional extension on the peripheral layout to obtain an extended layout; the extended layout includes the central layout and a peripheral extended layout, and the peripheral extended layout includes an extended peripheral layout and an extended central layout.
2. The method for correcting a layout according to claim 1, wherein when the size of the peripheral extended layout is greater than the optical diameter, stop extending the initial layout.
3. The method for correcting a layout according to any one of claims 1-2, characterized in that, further including: re-extending the extended layout.
4. The method for correcting a layout according to claim 3, wherein The re-extending the extended layout includes: performing two-dimensional extension on the central layout and one-dimensional extension on the peripheral extended layout.
5. The method for correcting a layout according to claim 1, characterized in that The correcting the extended layout to obtain a corrected layout includes: reconstructing the hierarchical structure of the extended layout; correcting the reconstructed extended layout to obtain a corrected layout.
6. The method for correcting a layout according to claim 5, wherein the reconstructing the hierarchical structure of the extended layout includes: reconstructing the central layout and the extended central layout into a two-dimensional structure unit array, and the two-dimensional structure unit array has a first direction and a second direction.
7. The method for correcting a layout according to claim 6, wherein the reconstructing the hierarchical structure of the extended layout further includes: reconstructing a part of the peripheral extended layout into a two-dimensional structure unit array.
8. The method for correcting a layout according to claim 6, wherein The reconstructing the hierarchical structure of the extended layout further includes: reconstructing the peripheral extended layout into a first one-dimensional unit array, a second one-dimensional unit array and a connecting layout; the connecting layout is located between the first one-dimensional unit array and the second one-dimensional unit array.
9. The method for correcting a layout according to claim 8, wherein the two-dimensional structure unit array has a first length along the first direction and a second length along the second direction; the first one-dimensional unit array has a first extension length along the first direction and the first extension length is the same as the first length; the second one-dimensional unit array has a second extension length along the second direction and the second extension length is the same as the second length.
10. The method for correcting a layout according to claim 9, wherein the obtaining a target layout based on the corrected layout includes: extracting the central layout, the connecting layout and a part of the first one-dimensional unit array and a part of the second one-dimensional unit array corresponding to the central layout of the corrected layout and merging them to form a target layout.
11. The method for correcting a layout according to claim 10, wherein, further including: extending the target layout to obtain a complete layout.
Citation Information
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