Error cache techniques for improved error correction in memory devices

Abstract

This application is directed to error caching techniques for improved error correction in memory devices. A device such as a memory device can use an error cache to store indications of defective memory cells that are identified, and can use the stored indications to augment an error correction procedure. If one or more errors are detected in data read from a memory array, the device can check the error cache, and if a bit of the data is indicated as being associated with a defective cell, the bit can be inverted. After such an inversion, the data can be checked for errors again. If the inversion corrects an error, the resulting data can be error-free, or can include a reduced number of errors that can be corrected using an error correction scheme.

Description

[0001] Cross-reference

[0002] The present patent application claims priority to U.S. Patent Application No. 16 / 993,956, entitled “ERROR CACHING TECHNIQUES FOR IMPROVED ERROR CORRECTION IN A MEMORY DEVICE” to Eilert et al., filed August 14, 2020, assigned to the present assignee and expressly incorporated herein in its entirety by reference thereto. TECHNICAL FIELD

[0003] The technical field relates to error caching techniques for improved error correction in a memory device. BACKGROUND

[0004] Memory devices are widely used in various electronic devices such as computers, wireless communication devices, cameras, digital displays, and the like to store information. Information is stored by programming memory cells within a memory device to different states. For example, a binary memory cell can be programmed to one of two supported states, often denoted by a logic 1 or a logic 0. In some examples, an individual memory cell can support more than two states, any of which can be stored. To access stored information, a component can read or sense at least one stored state in a memory device. To store information, a component can write or program a state in a memory device.

[0005] There are a variety of types of memory devices and memory cells, including magnetic hard disks, random access memory (RAM), read only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase change memory (PCM), self- selective memory, sulfide memory technology, and the like. Memory cells can be volatile or non-volatile. Non-volatile memory, such as FeRAM, can maintain their stored logic state for extended periods of time even in the absence of an external power source. Volatile memory devices, such as DRAM, can lose their stored state when disconnected from an external power source. SUMMARY

[0006] A method is described. In some examples, the method can include receiving a command to read data from a memory array, the command indicating an address associated with a set of memory cells within the memory array; reading the data from the set of memory cells in response to the command; determining, based at least in part on the indicated address, whether a cache includes an indication of a defective memory cell in the set of memory cells; and performing, for the data, a procedure for error correction based at least in part on whether the cache includes the indication.

[0007] A method is described. In some examples, the method can include receiving a command to read data from a memory array, the command indicating an address associated with a set of memory cells within the memory array; reading the data from the set of memory cells in response to the command; determining, based at least in part on reading the data from the set of memory cells, that the data includes an error; identifying, among the set of memory cells, a memory cell associated with the error; and writing, based at least in part on determining that the data includes the error, an indication of the memory cell being defective to a cache.

[0008] An apparatus is described. In some examples, the apparatus can include a memory array, a cache configured to store an indication of defective memory cells within the memory array, and circuitry configured to cause the apparatus to receive a command to read data from the memory array, the command indicating an address associated with a set of memory cells within the memory array; read the data from the set of memory cells in response to the command; check the cache for the indication of a defective memory cell in the set of memory cells based at least in part on the indicated address; and perform, for the data, a procedure for error correction based at least in part on whether the cache includes the indication. BRIEF DESCRIPTION OF DRAWINGS

[0009] Figure 1 Examples of systems that support error cache techniques for improved error correction in memory devices in accordance with examples as disclosed herein are described.

[0010] Figure 2 Examples of memory dies that support error cache techniques for improved error correction in memory devices in accordance with examples as disclosed herein are described.

[0011] Figure 3 Examples of systems that support error cache techniques for improved error correction in memory devices in accordance with examples as disclosed herein are described.

[0012] Figure 4 Examples of process flows that support error cache techniques for improved error correction in memory devices in accordance with examples as disclosed herein are described.

[0013] Figure 5 A block diagram showing a memory device supporting error cache techniques for improved error correction in a memory device according to aspects of the present disclosure is presented.

[0014] Figure 6 and 7 A flow diagram illustrating one or more methods supporting error cache techniques for improved error correction in a memory device according to examples as disclosed herein is presented. DETAILED DESCRIPTION

[0015] Some memory systems can utilize error detection or correction techniques, which can be generally referred to as error checking techniques, to detect or correct errors in data retrieved from a memory array. For example, error checking techniques can determine whether data is corrupted when stored in a memory array, and in some cases can attempt to correct detected errors. However, error checking techniques can be limited to detecting or correcting up to a certain number of errors (e.g., a single error correction (SEC) scheme can be able to detect and correct a single error in a set of data, a SEC double error detection (DED) scheme can be able to detect up to two errors and correct one error in a set of data, and other examples of error checking techniques). In some cases, data can include errors that exceed the number of correctable or detectable errors for an error checking scheme (e.g., a SECDED scheme can not be able to detect or correct three errors in a set of data, and other examples of numbers and schemes).

[0016] The techniques described herein can utilize an error cache for error correction, which can result in a relatively more robust error checking technique, among other advantages. The error cache can include entries indicating locations of one or more defective memory cells in a memory array, and the memory device can use the error cache to perform one or more procedures for error correction. For example, upon reading data from a memory array, the memory device can detect a certain number of errors in the data that the memory device is unable to correct using only parity information for the data (e.g., a memory device using a SECDED error checking scheme can detect two errors in the data, among other examples). In such examples, the memory device can determine whether the error cache includes an entry for the address of the data. If the error cache includes the entry, the memory device can select one or more bits of the data to be inverted based on the entry. For example, the memory device can identify, based on the address associated with the data and a corresponding entry in the error cache, that a bit of the data is associated with a defective memory cell. The memory device can invert the bit corresponding to the defective memory cell to obtain altered data. After such an inversion, the memory device can then apply an error checking scheme to the altered data, which can enable the memory device to correct the data based on the associated parity information (e.g., if the inverted bit corrects one of the two detected errors, thus leaving only a single error, the memory device can be able to correct the remaining error using a SECDED scheme and output the corrected data).

[0017] Some errors associated with a memory array can be fixed (e.g., due to a memory cell being defective, such as being “stuck” at storing a certain logic state), while other errors can be time-varying (e.g., due to transient conditions such as temperature or electromagnetic effects, such that the associated memory cell can not actually be defective). The cache can be managed (e.g., populated and pruned or otherwise maintained with its entries) so as to include indications of memory cells associated with fixed errors and to prune or otherwise not include indications of memory cells associated with time-varying errors. For example, the error cache can include indications of defective memory cells for an address, but the memory device can determine that there are no errors in one or more sets of data read from the address. In some such examples, the memory device can remove the indication from the cache, which can result in relatively efficient cache utilization and pruning of entries associated with time-varying errors, among other advantages.

[0018] Features of the disclosure are first described in the context of a system and die as described with reference to Figure 1 and 2 Features of the disclosure are first described in the context of a system and die as described with reference to Figure 3 and 4Features of the disclosure are described in the context of memory systems and process flows described. These and other features of the disclosure are further illustrated and described with reference to device diagrams and flow diagrams involving, for example, a host device 105, an external memory controller 120, and a memory device 110 as Figures 5-7 Error caching techniques for improved error correction in memory devices are described.

[0019] Figure 1 An example of a system 100 that supports error caching techniques for improved error correction in memory devices in accordance with examples as disclosed herein is illustrated. The system 100 can include a host device 105, a memory device 110, and a plurality of channels 115 coupling the host device 105 with the memory device 110. The system 100 can include one or more memory devices 110, but aspects of the one or more memory devices 110 can be described in the context of a single memory device (e.g., the memory device 110).

[0020] The system 100 can include portions of an electronic device, such as a computing device, a mobile computing device, a wireless device, a graphics processing device, a vehicle, or other system. For example, the system 100 can illustrate aspects of a computer, a laptop computer, a tablet computer, a smartphone, a cellular phone, a wearable device, an internet-connected device, a vehicle controller, etc. The memory device 110 can be a component of the system that is operable to store data for one or more other components of the system 100.

[0021] At least portions of the system 100 can be an example of the host device 105. The host device 105 can be an example of a processor or other circuitry within a device that uses memory to perform processes, such as within a computing device, a mobile computing device, a wireless device, a graphics processing device, a computer, a laptop computer, a tablet computer, a smartphone, a cellular phone, a wearable device, an internet-connected device, a vehicle controller, a system on a chip (SoC), a graphics processing unit (GPU), or some other fixed or portable electronic device, among other examples. In some examples, the host device 105 can refer to hardware, firmware, software, or a combination thereof that implements the functionality of the external memory controller 120. In some examples, the external memory controller 120 can be referred to as a host or host device 105.

[0022] Memory device 110 can be a standalone device or component that is operable to provide physical memory addresses / space that can be used or referenced by system 100. In some examples, memory device 110 can be configurable to work with one or more different types of host devices. Signaling between host device 105 and memory device 110 can be operable to support one or more of: modulation schemes to modulate signals, various pin configurations for communicating signals, various form factors for physical packaging of host device 105 and memory device 110, clock signaling and synchronization between host device 105 and memory device 110, timing conventions, or other factors.

[0023] Memory device 110 can be operable to store data for components of host device 105. In some examples, memory device 110 can act as a slave-type device to host device 105 (e.g., responsive to and executing commands provided by host device 105 through external memory controller 120). Such commands can include one or more of write commands for write operations, read commands for read operations, refresh commands for refresh operations, or other commands.

[0024] Host device 105 can include one or more of external memory controller 120, processor 125, basic input / output system (BIOS) component 130, or other components such as one or more peripheral components or one or more input / output controllers. Components of the host device can be coupled to each other using bus 135.

[0025] Processor 125 can be operable to provide control or other functionality for at least a portion of system 100 or at least a portion of host device 105. Processor 125 can be a general -purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or a combination of these components. In such examples, processor 125 can be an example of a central processing unit (CPU), a graphics processing unit (GPU), a general purpose GPU (GPGPU), or a SoC, among other examples. In some examples, external memory controller 120 can be implemented by processor 125 or be a part of the processor.

[0026] BIOS component 130 can be a software component that includes a BIOS that operates as firmware, which can initialize and run various hardware components of system 100 or host device 105. BIOS component 130 can also manage data flow between processor 125 and various components of system 100 or host device 105. BIOS component 130 can include a program or software stored in one or more of read-only memory (ROM), flash memory, or other nonvolatile storage.

[0027] Memory device 110 can include a device memory controller 155 and one or more memory dies 160 (e.g., memory chips) to support a desired or specified capacity for data storage. Each memory die 160 can include a local memory controller 165 (e.g., local memory controller 165-a, local memory controller 165-b, local memory controller 165-N), and a memory array 170 (e.g., memory array 170-a, memory array 170-b, memory array 170-N). Memory array 170 can be a collection of memory cells (e.g., one or more grids, one or more banks, one or more tiles, one or more sections), where each memory cell can be operable to store data for at least one bit. A memory device 110 including two or more memory dies can be referred to as a multi-die memory or a multi-die package, or a multi-chip memory or a multi-chip package.

[0028] Device memory controller 155 can include circuitry, logic, or components operable to control operations of memory device 110. Device memory controller 155 can include hardware, firmware, or instructions that enable memory device 110 to perform various operations and can be operable to receive, transmit, or execute commands, data, or control information related to components of memory device 110. Device memory controller 155 can be operable to communicate with one or more of external memory controller 120, one or more memory dies 160, or processor 125. In some examples, device memory controller 155 can control operations of memory device 110 described herein in conjunction with local memory controllers 165 of memory dies 160.

[0029] In some examples, memory device 110 can receive data or commands, or both, from host device 105. For example, memory device 110 can receive a write command indicating that memory device 110 is to store data for host device 105 or a read command indicating that memory device 110 is to provide data stored in memory dies 160 to host device 105.

[0030] The local memory controller 165 (e.g., local to the memory die 160) can include circuitry, logic, or components operable to control operations of the memory die 160. In some examples, the local memory controller 165 can be operable to communicate (e.g., receive or transmit data or commands, or both) with the device memory controller 155. In some examples, the memory device 110 can not include the device memory controller 155, and the local memory controller 165 or the external memory controller 120 can perform various functions described herein. Thus, the local memory controller 165 can be operable to communicate with the device memory controller 155, with other local memory controllers 165, or directly with the external memory controller 120, or the processor 125, or a combination thereof. Examples of components that can be included in the device memory controller 155 or the local memory controller 165, or both, can include a receiver for receiving signals (e.g., from the external memory controller 120), a transmitter for transmitting signals (e.g., to the external memory controller 120), a decoder for decoding or demodulating received signals, an encoder for encoding or modulating signals to be transmitted, or various other circuitry or controllers operable to support operations of the described device memory controller 155 or local memory controller 165, or both.

[0031] The external memory controller 120 can be operable to enable communication of one or more of information, data, or commands between components of the system 100 or the host device 105 (e.g., the processor 125) and the memory device 110. The external memory controller 120 can translate or interpret communications exchanged between components of the host device 105 and the memory device 110. In some examples, the external memory controller 120 or other components of the system 100 or the host device 105, or functions thereof described herein, can be implemented by the processor 125. For example, the external memory controller 120 can be hardware, firmware, or software, or some combination thereof implemented by the processor 125 or another component of the system 100 or the host device 105. Although the external memory controller 120 is depicted as being external to the memory device 110, in some examples, the external memory controller 120 or functions thereof described herein can be implemented by one or more components of the memory device 110 (e.g., the device memory controller 155, the local memory controller 165), or vice versa.

[0032] The components of the host device 105 can exchange information with the memory device 110 using one or more channels 115. The channels 115 can be operable to support communications between the external memory controller 120 and the memory device 110. Each channel 115 can be an example of a transmission medium that carries information between the host device 105 and the memory device. Each channel 115 can include one or more signal paths or transmission media (e.g., conductors) between terminals associated with the components of the system 100. A signal path can be an example of an electrically conductive path that is operable to carry a signal. For example, a channel 115 can include a first terminal that includes one or more pins or pads at the host device 105 and one or more pins or pads at the memory device 110. A pin can be an example of an electrically conductive input or output point of a device of the system 100, and a pin can be operable to act as part of a channel.

[0033] The channels 115 (and associated signal paths and terminals) can be dedicated to communicating one or more types of information. For example, the channels 115 can include one or more command and address (CA) channels 186, one or more clock signal (CK) channels 188, one or more data (DQ) channels 190, one or more other channels 192, or a combination thereof. In some examples, signaling can be communicated via the channels 115 using single data rate (SDR) signaling or double data rate (DDR) signaling. In SDR signaling, one modulation symbol (e.g., a signal level) of a signal can be registered for each clock cycle (e.g., on a rising or falling edge of a clock signal). In DDR signaling, two modulation symbols (e.g., signal levels) of a signal can be registered for each clock period (e.g., on both a rising edge and a falling edge of a clock signal).

[0034] In some examples, bit errors can occur due to memory cell defects (e.g., from a manufacturing process, latent defects that occur after manufacturing, etc.). For example, a memory cell can include a defect that produces a fixed error (e.g., the memory cell can be defective), or detected errors in a memory cell can be time-varying errors (e.g., due to operating conditions or other random error occurrences, a relatively functional memory cell can include relatively infrequent errors).

[0035] Error checking techniques can be able to detect or correct up to a certain number of errors in data written to a memory array and subsequently read from the memory array based on parity information generated for the data, which in some cases can also be stored in the memory array (e.g., in association with the corresponding data). For example, a SEC parity scheme can support detection of a single error in data based on parity information for the data, a SECDED parity scheme can support detection of up to two errors and correction of a single error in data based on parity information for the data, and other examples of error detection schemes. In some cases, data can include more than the number of errors that can be corrected based on associated parity information.

[0036] As described herein, system 100 can implement an error cache for error correction, which can result in a relatively more robust error checking technique (e.g., an increase in the number of errors that can be corrected relative to the number that can be corrected based on parity information alone), among other advantages. For example, one or more components of system 100 (e.g., memory device 110, host device 105, device memory controller 155, local memory controller 165, external memory controller 120, or any combination thereof) can maintain an error cache in order to provide information for error correction to an error correction engine, as described with reference to Figure 3

[0037] Memory device 110 can use the error cache to perform one or more procedures for error correction. For example, memory device 110 can detect a number of errors in data read from a memory array, but can not be able to correct the errors using parity information for the data (e.g., memory device 110 can detect two errors in a SECDED scheme, among other examples). In such examples, memory device 110 can determine whether the error cache includes an entry for an address of the data. If the error cache includes an entry, memory device 110 can select one or more bits of the data to be inverted based on the entry. For example, memory device 110 can identify a location of a defective memory cell within the address based on an indication written to the entry. Memory device 110 can invert the bits corresponding to the defective memory cell to obtain altered data. Memory device 110 can then be able to correct the altered data using parity information for the data (e.g., if the inverted bits change the two previously detected errors to a single error in a SECDED scheme, memory device can be able to correct the error and output corrected data). Thus, by using the error cache to track known error locations (e.g., defective memory cells), the error correction capability of an error correction scheme can be enhanced.

[0038] ​In some examples, the memory device 110 can update the error cache. For example, if the memory device 110 identifies data as error free when the error cache includes an indication of a defective memory cell associated with the data, the memory device 110 can remove the indication from the cache in some cases, which can result in relatively efficient cache utilization and concentration of cache entries on fixed errors over time, among other advantages.

[0039] Figure 2 An example of a memory die 200 that supports error cache techniques for improved error correction in a memory device, in accordance with examples as disclosed herein, is described. The memory die 200 can be referred to as a memory chip, a memory device, or an electronic memory apparatus, for example, with reference to Figure 1 The described example of a memory die 160. In some examples, the memory die 200 can be referred to as a memory chip, a memory device, or an electronic memory apparatus. The memory die 200 can include one or more memory cells 205, which can each be programmable to store a different logical state (e.g., programmed to one of a set of two or more possible states). For example, the memory cells 205 can be operable to store one bit of information (e.g., a logical 0 or a logical 1) at a time. In some examples, the memory cells 205 (e.g., multi-level memory cells) can be operable to store more than one bit of information at a time (e.g., logical 00, logical 01, logical 10, logical 11). In some examples, the memory cells 205 can be arranged in an array, for example, with reference to Figure 1 The described memory array 170.

[0040] The memory cells 205 can store electrical charges representing programmable states in capacitors. DRAM architectures can include capacitors that include a dielectric material to store electrical charges representing programmable states. Other storage devices and components are possible in other memory architectures. For example, a non-linear dielectric material can be employed. The memory cells 205 can include logical storage components such as capacitors 230 and switching components 235. The capacitors 230 can be examples of a dielectric capacitor or a ferroelectric capacitor. Nodes of the capacitors 230 can be coupled with a voltage source 240, which can be a cell plate reference voltage such as Vpl, or can be ground such as Vss.

[0041] The memory die 200 can include one or more access lines (e.g., one or more word lines 210 and one or more digit lines 215) arranged in a pattern, such as a grid-like pattern. An access line can be an electrically conductive line coupled with a memory cell 205 and can be used to perform an access operation on the memory cell 205. In some examples, a word line 210 can be referred to as a row line. In some examples, a digit line 215 can be referred to as a column line or a bit line. References to access lines, row lines, column lines, word lines, digit lines, or bit lines, etc., can be interchanged without affecting understanding or operation. The memory cells 205 can be positioned at intersections of the word lines 210 and the digit lines 215.

[0042] Operations such as reads and writes can be performed on the memory cells 205 by activating or selecting an access line, such as one or more of the word lines 210 or the digit lines 215. A single memory cell 205 can be accessed at an intersection of a word line 210 and a digit line 215 by biasing the word line 210 and the digit line 215 (e.g., applying a voltage to the word line 210 or the digit line 215). Intersections of the word lines 210 and the digit lines 215 in a two-dimensional or three-dimensional configuration can be referred to as addresses of the memory cells 205.

[0043] Accessing the memory cells 205 can be controlled by a row decoder 220 or a column decoder 225. For example, the row decoder 220 can receive a row address from a local memory controller 260 and activate a word line 210 based on the received row address. The column decoder 225 can receive a column address from the local memory controller 260 and can activate a digit line 215 based on the received column address.

[0044] Selecting or deselecting a memory cell 205 can be accomplished by activating or deactivating a switch component 235 using a word line 210. A capacitor 230 can be coupled with a digit line 215 using the switch component 235. For example, when the switch component 235 is deactivated, the capacitor 230 can be isolated from the digit line 215, and when the switch component 235 is activated, the capacitor 230 can be coupled with the digit line 215.

[0045] A sense component 245 can be operable to detect a state (e.g., a charge) stored on the capacitor 230 of a memory cell 205 and determine a logic state of the memory cell 205 based on the stored state. The sense component 245 can include one or more sense amplifiers to amplify or otherwise convert a signal generated from accessing the memory cell 205. The sense component 245 can compare the detected signal from the memory cell 205 to a reference 250 (e.g., a reference voltage). The detected logic state of the memory cell 205 can be provided as an output of the sense component 245 (e.g., to an input / output 255) and can be indicated to another component of a memory device including the memory die 200.

[0046] The local memory controller 260 can control access to the memory cells 205 through various components (e.g., row decoder 220, column decoder 225, sense component 245). The local memory controller 260 can be a reference Figure 1 The described example of the local memory controller 165. In some examples, one or more of the row decoder 220, column decoder 225, and sense component 245 can be collocated with the local memory controller 260. The local memory controller 260 can be operable to receive one or more of commands or data from one or more different memory controllers (e.g., the external memory controller 120 associated with the host device 105, another controller associated with the memory die 200), translate the commands or data (or both) into information that can be used by the memory die 200, perform one or more operations on the memory die 200, and communicate data from the memory die 200 to the host device 105 based on performing the one or more operations. The local memory controller 260 can generate row signals and column address signals to activate a target word line 210 and a target digit line 215. The local memory controller 260 can also generate and control various voltages or currents used during operation of the memory die 200. In general, the magnitude, shape, or duration of the applied voltages or currents discussed herein can vary and can be different for the various operations discussed in operating the memory die 200.

[0047] The local memory controller 260 can be operable to perform one or more access operations on one or more memory cells 205 of the memory die 200. Examples of access operations can include write operations, read operations, refresh operations, precharge operations, or activate operations, among others. In some examples, the access operations can be performed or otherwise coordinated by the local memory controller 260 in response to various access commands (e.g., from the host device 105). The local memory controller 260 can be operable to perform other access operations not listed here or other operations related to operation of the memory die 200 that are not directly related to accessing the memory cells 205.

[0048] The local memory controller 260 can be operable to perform a write operation (e.g., a program operation) on one or more memory cells 205 of the memory die 200. During a write operation, a memory cell 205 of the memory die 200 can be programmed to store a desired logical state. The local memory controller 260 can identify a target memory cell 205 on which to perform the write operation. The local memory controller 260 can identify a target word line 210 and a target digit line 215 coupled with the target memory cell 205 (e.g., an address of the target memory cell 205). The local memory controller 260 can activate the target word line 210 and the target digit line 215 (e.g., apply a voltage to the word line 210 or the digit line 215) to access the target memory cell 205. The local memory controller 260 can apply a particular signal (e.g., a write pulse) to the digit line 215 during the write operation to store a particular state (e.g., a charge) in the capacitor 230 of the memory cell 205. The pulse used as part of the write operation can include one or more voltage levels for a duration of time.

[0049] The local memory controller 260 can be operable to perform a read operation (e.g., a sense operation) on one or more memory cells 205 of the memory die 200. During a read operation, a logical state stored on a memory cell 205 of the memory die 200 can be determined. The local memory controller 260 can identify a target memory cell 205 on which to perform the read operation. The local memory controller 260 can identify a target word line 210 and a target digit line 215 coupled with the target memory cell 205 (e.g., an address of the target memory cell 205). The local memory controller 260 can activate the target word line 210 and the target digit line 215 (e.g., apply a voltage to the word line 210 or the digit line 215) to access the target memory cell 205. The target memory cell 205 can transfer a signal to the sense component 245 in response to biasing the access lines. The sense component 245 can amplify the signal. The local memory controller 260 can activate the sense component 245 (e.g., latch the sense component) and thereby compare the signal received from the memory cell 205 to the reference 250. Based on the comparison, the sense component 245 can determine the logical state stored on the memory cell 205.

[0050] The local memory controller 260 and the memory die 200 can implement an error cache 265 to support error correction for data stored in and read from the memory array. The error cache 265 can be implemented as a portion of the memory array, as a separate memory array, or as a combination of a portion of the memory array and a separate memory array. The error cache 265 can be implemented as a portion of the memory array, as a separate memory array, or as a combination of a portion of the memory array and a separate memory array. Figure 2The local memory controller 260 coupled as shown in the middle. Alternatively, in some cases, the error cache 265 can be coupled with the local memory controller 260. And in some cases (e.g., where the memory cells 205 are non-volatile), the error cache 265 can be or include a portion of the memory array.

[0051] For example, the local memory controller 260 (or another controller of the memory device 110 or host device 105) can maintain (e.g., manage) the contents of the error cache 265 in order to provide information for error correction, as described with reference to Figure 3 The error cache 265 can be populated with one or more entries indicative of a location of one or more defective memory cells of the memory die 200. For example, the local memory controller 260 can identify an error in data associated with an address, and the local memory controller 260 can write a location of the error cache 265 identified based at least in part on identifying the error. For example, the local memory controller 260 can store an address (e.g., a physical address) of one or more memory cells from which data was read, possibly along with an offset parameter indicative of a location of a memory cell within a set of memory cells associated with the address, where the memory cell is associated with a detected error.

[0052] The local memory controller 260 can use information stored in the error cache 265 to perform one or more procedures for error correction. For example, error checking logic (e.g., within the memory die 200) can detect a number of errors in data read from the memory array, but can not be able to correct the errors using parity information for the data (e.g., the local memory controller 260 can detect two errors in a SECDED scheme, among other examples). The error checking logic can be or include an error correction engine 315, as described with reference to Figure 3 The local memory controller 260 can determine whether the error cache 265 includes an entry for an address associated with the data. If the error cache 265 includes such an entry, the local memory controller 260 can select one or more bits of the data to be inverted based on the entry. For example, the local memory controller 260 can identify a location of a defective memory cell based on an indication written to the entry. The local memory controller 260 can invert bits corresponding to the defective memory cell to obtain altered data. The local memory controller 260 can input the altered data into the error checking logic, which can then be able to correct the data based on associated parity information (e.g., if the inverted bits change two detected errors to a single error in a SECDED scheme, the memory device can be enabled to correct the error and output corrected data).

[0053] In some examples, the local memory controller 260 can update the error cache 265. For example, the local memory controller 260 can fail to identify an error in data associated with an address, where the error cache 265 includes an indication of a defective memory cell for the address. In at least some such cases, the local memory controller 260 can remove the indication from the error cache 265, which can result in relatively efficient cache utilization, among other advantages.

[0054] Figure 3 An example of a system 300 that supports error cache techniques for improved error correction in a memory device, in accordance with examples as disclosed herein, is illustrated. The system 300 can be an example of aspects of the system 100 or the memory device 110, respectively, as described with reference to Figure 1 and 2

[0055] The system 300 can include a memory array 310, which can be an example of the memory array 170. The system 300 can also include an error cache 305 and an error correction engine 315. The system 300 can be configured to perform one or more error checking procedures using the error correction engine 315 and the error cache 305, which can reduce the probability of errors in communication (e.g., transmission of corrupted data from the memory array 310). Generally speaking, Figure 3 The components illustrated in FIG. 3 can implement the procedures and operations described herein related to error checking, but it should be understood that there can be more or fewer components than those shown that implement the procedures described. Additionally or alternatively, while illustrated as separate for illustrative clarity, various components described herein can be combined or physically located in different manners than illustrated.

[0056] The error cache 305 can maintain a list of memory cells (e.g., defective memory cells) associated with previously detected errors. For example, the system 300 can track a list of known stuck-at bits (e.g., memory cells that store the same logical state, regardless of which logical state is written to the memory cell). In some examples, the list can be generated based on error correction code results or from testing performed during one or more maintenance cycles (e.g., refresh cycles) (e.g., the system 300 can perform a diagnostic procedure for the memory device during a refresh or other suitable time period, and the error cache 305 can be populated based on the results of the procedure). In some examples, the information can be loaded into the error cache 305 at power-up (e.g., in NVM, the list can be loaded into a content addressable memory (CAM) or static RAM at power-up of the memory device).

[0057] ​System 300 can receive a command, e.g., from a host device. The command can indicate an address 320 associated with data (e.g., a logical address associated with data or a physical address associated with a set of memory cells within memory array 310 for writing or reading data).

[0058] When the received command is a write command, system 300 can store data in memory array 310. In some cases, system 300 can also check error cache 305, and if error cache 305 contains one or more entries for address 320 (e.g., entries indicating a state in which a memory cell is “stuck”), system 300 can write data to memory array 310 such that bits stored to a stuck memory cell align with the stuck state of the memory cell (e.g., if a memory cell is stuck in a logical state of “1,” system 300 can write data such that a bit having a value of “1” is stored at the indicated position of the stuck memory cell), among other examples. For example, system 300 can invert data and also store any associated inversion flags in memory array 310 or error cache 305.

[0059] When the received command is a read command, a controller of system 300 can perform a read operation to retrieve corresponding data 340 from indicated address 320 of memory array 310. In some examples, system 300 can also read parity information for data 340 (e.g., parity bits 355 previously generated based on data 340) from memory array 310. Additionally or alternatively, system 300 can read some or all of parity bits 355 from error cache 305.

[0060] System 300 can perform an error check using error correction engine 315 (e.g., based on a parity scheme associated with the error correction engine, such as a SEC parity scheme or a SECDED parity scheme). For example, in response to a read command for data 340, error correction engine 315 can receive data 340 and parity bits 355 associated with data 340. Error correction engine 315 can perform a procedure to detect or correct errors in data 340 in using parity bits 355.

[0061] In some cases, the error correction engine can fail to identify errors in the data 340. For example, the data 340 can contain no errors or the number of errors can exceed the detection capability of the error correction scheme (e.g., three or more errors can result in a valid codeword in a SECDED scheme, and the error correction engine 315 can fail to identify errors in the data 340). In some other cases, the error correction engine 315 can identify a correctable number of one or more errors in the data 340, and can correct the one or more errors to obtain corresponding corrected data 345. For example, the error correction engine 315 can identify a single error in a SEC or SECDED scheme, and can correct the single error (e.g., flip a bit from a first logical state to a correct second logical state, the flipped bit identified using the parity bit 355), and subsequently output the corrected data 345, for example, to a host device requesting the data.

[0062] In some cases, the error correction engine 315 can compare the number of detected errors to a threshold and determine whether the threshold is satisfied. If the threshold is satisfied, the error correction engine 315 can be unable to correct the detected errors (e.g., the error correction engine 315 can detect two errors in a SECDED error correction scheme, but can be unable to correct the two errors). The threshold can be any number (e.g., 1 or greater). Based on the threshold being satisfied, the system 300 can query the error cache 305 to determine whether the error cache 305 contains an entry for the address 320.

[0063] In response to the query, the error cache 305 can send information 350 to the error correction engine 315. The information 350 can include error correction information that can enable the error correction engine 315 to correct a number of errors. As an illustrative example, the information 350 stored in the error cache 305 can include an indication of the address 320, an indication of locations of one or more defective memory cells in a set of memory cells associated with the address 320 in the memory array 310 (e.g., an offset parameter indicating locations of defective memory cells within the address 320), an error count for the defective memory cells, metadata associated with the memory cells, or any combination thereof.

[0064] System 300 can identify one or more defective memory cells based on information 350 (e.g., information 350 can indicate locations of one or more defective memory cells in addresses 320 storing data 340). System 300 can change values of one or more bits associated with one or more defective memory cells. For example, error correction engine 315 can invert values of bits associated with defective memory cells (e.g., from 0 to 1 or from 1 to 0) to obtain altered data (e.g., data 340 with one or more bits read from one or more defective memory cells inverted). Altered data can be input to error correction engine 315 (or alternatively, a second error correction engine, possibly based on a different parity scheme) for a second error checking procedure. By changing (e.g., inverting) bits associated with one or more defective memory cells according to indications stored in error cache 305, error correction engine 315 can be enabled to correct errors in data 340 based on correcting a reduced number of errors in corresponding altered data. As an illustrative example, if error correction engine 315 detects two errors in a SECDED scheme, the errors can be corrected by inverting one or both bits associated with defective memory cell indications stored in error cache 305 (e.g., a single error can be corrected by bit inversion, and error correction engine 315 can use parity bits 355 to identify and correct the remaining error). Error correction engine 315 can output corrected data 345 after correcting one or more errors in altered data or determining that altered data is error free.

[0065] System 300 can maintain error cache 305. For example, system 300 can employ a method for testing for error locations of a cache and continuously updating (e.g., adding or expunging) a list of "bad" locations (e.g., defective memory cells), which can increase efficiency of error cache 305. Error correction engine 315 can determine one or more results of one or more error correction or detection procedures. Error correction engine 315 can send information 335 indicating the one or more results. In one illustrative example, error correction engine 315 can fail to identify an error in data 340. If error cache 305 includes an entry for address 320 (e.g., an indication of a defective memory cell in a set of memory cells associated with address 320), information 335 can indicate expunging the entry based on failing to identify the error. Such expunging can result in more efficient cache utilization and expunge entries of error cache 305 that can not be results of fixed errors (e.g., an indication of a defective memory cell can be stored in advance based on identifying a time-varying error), which can reduce the probability of incorrectly inverting bits in subsequent error procedures.

[0066] In some examples, system 300 can remove the indication from error cache 305 based on one or more thresholds. For example, system 300 can increment a counter or otherwise track a number of times (e.g., consecutive times) that no error is detected for a memory cell indicated as defective by error cache 305. If the number of times that no error is detected satisfies a threshold, system 300 can remove the entry of error cache corresponding to the memory cell. By updating error cache 305 based on satisfying the threshold, system 300 can prune entries of error cache that can be associated with time-varying errors while avoiding pruning entries based on accidental error-free determinations (e.g., if a defective memory cell happens to be stuck at a state corresponding to a logical value written to the memory cell).

[0067] As another illustrative example, error correction engine 315 can identify an error in data 340 associated with a particular memory cell. If error cache 305 lacks an entry for address 320, information 335 can indicate writing an entry for address 320 in error cache 305, or if an entry for address 320 exists but lacks an indication of the particular memory cell, writing an indication that the particular memory cell is defective. In some cases, if error cache 305 already contains an entry for address 320, information 335 can indicate incrementing an error count associated with the memory cell based on identifying the memory cell as being associated with an error. Writing an indication that the particular memory cell is defective to error cache 305 (e.g., so as to determine bit inversion in response to a subsequent read from the memory cell) can be based on the incremented error count satisfying a threshold. By tracking an error count for a memory cell using error cache 305 and generating an indication that the memory cell is defective based on the error count for the memory cell satisfying a threshold, system 300 can reduce the likelihood of adding a memory cell with a time-varying error to error cache 305 (e.g., the threshold can help ensure that error cache 305 contains memory cells with fixed defects, among other examples).

[0068] Figure 4 An example of a process flow 400 that supports error cache techniques for improved error correction in a memory device, in accordance with examples as disclosed herein, is illustrated. The process flow can be an example of operations performed by system 100, memory device 110, or system 300, respectively, as described with reference to Figures 1-3 In general, the operations shown in Figure 4 may illustrate a procedure and operations of a memory device (or memory system) using an error cache to perform an error correction procedure, but it should be understood that there can be more or fewer operations than those shown. Additionally or alternatively, the operations can be added, removed, or performed in a different order than shown in Figure 4 In general, the operations shown in may illustrate a procedure and operations of a memory device (or memory system) using an error cache to perform an error correction procedure, but it should be understood that there can be more or fewer operations than those shown. Additionally or alternatively, the operations can be added, removed, or performed in a different order than shown in

[0069] At 405, the memory device can receive a command. For example, the memory device can receive a read command from a host device. The command can indicate an address (e.g., a logical or physical address) of data to be read from a memory array within the memory device.

[0070] The memory device can map the address (e.g., as received or based on a logical to physical mapping to obtain a physical address) to the memory array as well as an error cache of the memory device (e.g., as referenced Figure 3 The memory array 310 and error cache 305 described). For example, if the command received at 405 is a read command, at 410, the memory device can read data from the memory array based on the address indicated by the command. In some instances, the memory device can also read parity bits associated with the data from the memory array. The memory device can also search the error cache using the address to obtain an entry associated with the address (e.g., the memory device can determine whether the cache contains an entry for the indicated address or an address that maps to the indicated address). For example, the memory device can query the error cache at the same time (e.g., in parallel) that it reads the data and uses the parity bits to perform a first error checking procedure for the data. That is, any time period allocated to search the error cache and provide the cache’s information (e.g., apply the query to the error cache and return the results to the error correction engine) with the address can be such that the cache’s information can be used for the error correction engine before the first error checking procedure for the original data is complete.

[0071] At 415, the memory device can determine whether any errors are detected in the data. For example, the memory device can input the data and associated parity bits into an error correction engine as part of a first procedure. The memory device can use the parity bits to determine whether there is one or more errors in the data.

[0072] In some examples, the memory device can detect no errors in the data. For example, the data can contain no errors or the number of errors can exceed the detection capability of the parity scheme associated with the parity bits (e.g., a SECDED scheme can fail to identify three or more errors in the data). At 425, based on the results of the error checking procedure indicating that the data contains no errors, the memory device can output the data. In some examples, the memory device can perform one or more operations for the error cache based on failing to detect errors in the data. For example, the memory device can determine that the error cache includes an entry for the address (e.g., a previous procedure result indicated that a memory cell in the address stored an error data state and the error cache was updated with the location of the memory cell). At 420, the memory device can remove the indication from the cache based on failing to detect errors in the data (e.g., based on a count of error-free reads of the memory cell or address satisfying a threshold). For example, the indication of the defective memory cell can have been stored based on a previous error checking procedure but due to a time-varying error (e.g., a single occurrence of an error in a non-defective memory cell). Removing the indication from the cache if no errors are detected can free the cache to store information associated with other defective memory cells, can improve cache utilization and search speed, and reduce the probability of incorrectly flipping bits for functional memory cells, among other advantages.

[0073] In some examples, the memory device can identify the number of correctable errors and can correct the original data accordingly. For example, the error correction engine can identify a single error in a SEC or SECDED scheme and can correct the single error (e.g., flip a bit from a first logical state to a correct second logical state) before outputting the corrected data at 425 to, for example, a host device that requested the data.

[0074] In some examples, the memory device can detect one or more errors in the data using the parity bits, but can not be able to correct the errors using the parity bits. For example, the memory device can compare the number of detected errors in the data to a threshold and determine whether the threshold is satisfied. If the threshold is satisfied, the memory device can detect the errors, but can not be able to correct the detected errors using the parity bits (e.g., the memory device can detect two errors in a SECDED error correction scheme, but can not be able to correct the two errors).

[0075] At 430, the memory device can determine whether the error cache includes an entry for the address indicated by the command, which can enable the memory device to use information in the error cache to correct the data, among other advantages. For example, the memory device can use the address to search the error cache to identify whether the error cache includes an indication of one or more defective memory cells within the set of memory cells from which the data was read. The entry can include an indication of the address, an indication of a location of the one or more defective memory cells within the associated set of memory cells (e.g., an offset parameter indicating a location of the defective memory cell within the address or corresponding physical address), an error count for the defective memory cell, metadata associated with the memory cell, or any combination thereof.

[0076] If the cache includes an entry for the address, at 440, the memory device can invert or otherwise alter one or more bits of the data. For example, the memory device can use information in the error cache to identify a location of a defective memory cell in the set of memory cells. The memory device can “flip” a bit associated with the defective memory cell (e.g., alter the data such that the bit read from the indicated memory cell has a different logical value than the logical value read from the memory cell).

[0077] At 445, the memory device can correct the altered data. For example, the memory device can input the altered data to an error correction engine and perform a second error checking procedure using the altered data and the parity bits. By flipping one or more bits (e.g., a single bit that was inverted based on an indication of the associated memory cell), the memory device can reduce the number of errors such that the memory device can correct the altered data based on the parity bits (e.g., can reduce two detectable errors to one correctable error by inverting the bit in a SECDED scheme, among other examples of numbers and schemes). After correcting the data or obtaining a result of the second procedure indicating that the altered data does not include an error, the memory device can output the data at 425.

[0078] In some other examples, although an error is detected at 415, the memory device can determine at 430 that the cache fails to include an entry for the address. In such examples, the memory device can proceed to 435. At 435, the memory device can update the error cache to add or update an entry for the associated address and an indication of the memory cell that includes the error. By dynamically updating the cache based on detecting an error, the memory device can track defective memory cells, which can enhance the robustness of the error correction procedure (e.g., the error cache can enable the memory device to convert a number of detectable errors to a number of correctable errors, among other examples).

[0079] Figure 5 A block diagram 500 of a memory device 505 that exhibits error caching techniques that support improved error correction for use in a memory device in accordance with examples as disclosed herein is shown. The memory device 505 can be an example of aspects of a memory device as described with reference to Figures 1-4 The memory device 505 can include a command receiver 510, a read component 515, a cache component 520, an error check component 525, an output component 530, and a diagnostic component 535. Each of these modules can communicate, directly or indirectly, with one another (e.g., via one or more buses).

[0080] The command receiver 510 can receive a command to read data from a set of memory cells within a memory array, the command indicating an address associated with the set of memory cells. The read component 515 can read the data from the set of memory cells in response to the command. The cache component 520 can determine, based on the indicated address, whether a cache includes an indication of a defective memory cell in the set of memory cells. The error check component 525 can perform, for the data, a procedure for error correction based on whether the cache includes the indication.

[0081] In some examples, the cache component 520 can determine that the cache includes the indication. In such examples, to perform the procedure for error correction, the error check component 525 can determine, based on the data and parity information associated with the data, that the data includes one or more errors, invert bits associated with the defective memory cell to obtain altered data based on the determination that the data includes the one or more errors, and determine, after inverting the bits, whether the altered data includes a second set of one or more errors based on the altered data and the parity information.

[0082] In some cases, the error check component 525 can correct, after inverting the bits, the second set of one or more errors to obtain corrected data based on the altered data and the parity information.

[0083] The output component 530 can output, by the memory device that includes the memory array, the corrected data in response to the command.

[0084] In some examples, the error check component 525 can determine that a number of errors included in the one or more errors satisfies a threshold, where inverting the bits is based on determining that the number of errors satisfies the threshold.

[0085] In some examples, the error checking component 525 can input the data and the parity information to error checking logic, where determining that the data contains one or more errors is based on inputting the data and the parity information to the error checking logic. In some examples, the error checking component 525 can input the altered data and the parity information to the error checking logic after inverting the bits, where determining whether the altered data contains a second set of one or more errors is based on inputting the altered data and the parity information to the error checking logic.

[0086] In some examples, the error checking component 525 can determine that the data contains an error based at least in part on a procedure for error correction. The cache component 520 can identify, among the set of memory cells, a respective memory cell associated with the error. The cache component 520 can write, to the cache, an indication that the respective memory cell is defective based at least in part on determining that the data contains the error.

[0087] In some examples, the diagnostic component 535 can perform a diagnostic procedure for the memory array prior to receiving the command. In some examples, the cache component 520 can write, to the cache, an indication that a memory cell is defective based on the diagnostic procedure.

[0088] In some examples, the cache component 520 can determine that the cache contains an indication that a memory cell is defective, and the error checking component 525 can determine that no error is detected for the data based on a procedure for error correction. In some examples, the cache component 520 can remove the indication from the cache based on determining that no error is detected for the data.

[0089] The command receiver 510 can receive a command to read data from a set of memory cells within a memory array, the command indicating an address associated with the set of memory cells. The read component 515 can read the data from the set of memory cells in response to the command. In some examples, the error checking component 525 can determine that the data contains an error based on reading the data from the set of memory cells. In some examples, the error checking component 525 can identify, among the set of memory cells, a memory cell associated with the error. The cache component 520 can write, to the cache, an indication that the memory cell is defective based on determining that the data contains the error.

[0090] The cache component 520 can increment an error count associated with the memory cell based on identifying the memory cell as being associated with the error, where writing the indication to the cache is based on the incremented error count satisfying a threshold.

[0091] In some examples, the command receiver 510 can receive a second command to read second data from the set of memory cells. In some examples, the cache component 520 can determine, in response to the second command, that the cache includes an indication that a memory cell is defective. In some examples, the error checking component 525 can perform a procedure for error correction based on the cache including the indication for the second data.

[0092] In some examples, to perform the procedure for error correction, the error checking component 525 can determine, based at least in part on the parity information for the second data, that the second data includes one or more errors. The error checking component 525 can invert bits associated with the memory cell to obtain altered data based on determining that the second data includes one or more errors. The error checking component 525 can correct one or more errors in the altered data to obtain corrected data based on the parity information after inverting the bits.

[0093] The output component 530 can output the corrected data from the memory device including the memory array in response to the second command.

[0094] In some examples, the error checking component 525 can input the second data and the parity information to error checking logic, where determining that the second data includes one or more errors is based on inputting the second data and the parity information to the error checking logic. In some examples, the error checking component 525 can input the altered data and the parity information to the error checking logic after inverting, where correcting one or more errors in the altered data is based at least in part on inputting the altered data and the parity information to the error checking logic.

[0095] In some examples, the error checking component 525 can determine, based on the procedure for error correction, that no errors are detected for the second data. In some examples, the cache component 520 can remove the indication from the cache based on determining that no errors are detected for the data.

[0096] In some cases, the cache includes a second memory array, a portion of the memory array, or a combination thereof.

[0097] In some cases, where the cache includes an entry for the indicated address, the entry can include the indication that the memory cell is defective, and the entry can include an address of the memory cell, an offset of the indicated address associated with the memory cell, an error count for the memory cell, metadata associated with the memory cell, or any combination thereof.

[0098] Figure 6 A flow diagram illustrating one or more methods 600 that support error cache techniques for improved error correction in memory devices in accordance with aspects of the present disclosure is shown. The methods 600 can be performed by an apparatus such as the memory device 200 described with reference to FIG. 2, the memory device 400 described with reference to FIG. 4, or any other suitable apparatus.Figures 1-5 The memory devices described or components thereof perform the operations of method 600. For example, the operations of method 600 can be performed by the memory devices described with reference to Figure 5 The memory devices described perform the operations of method 600. In some examples, the memory devices can execute a set of instructions to control the functional elements of the memory devices to perform the described functions. Additionally or alternatively, the memory devices can perform aspects of the described functions using special-purpose hardware.

[0099] At 605, the memory device can receive a command to read data from a memory array, the command indicating an address associated with a set of memory cells within the memory array. The operations of 605 can be performed according to the methods described herein. In some examples, aspects of the operations of 605 can be performed by a command receiver as described with reference to Figure 5 The memory devices described perform the operations of method 600. In some examples, the memory devices can execute a set of instructions to control the functional elements of the memory devices to perform the described functions. Additionally or alternatively, the memory devices can perform aspects of the described functions using special-purpose hardware.

[0100] At 610, the memory device can read data from the set of memory cells in response to the command. The operations of 610 can be performed according to the methods described herein. In some examples, aspects of the operations of 610 can be performed by a read component as described with reference to Figure 5 The memory devices described perform the operations of method 600. In some examples, the memory devices can execute a set of instructions to control the functional elements of the memory devices to perform the described functions. Additionally or alternatively, the memory devices can perform aspects of the described functions using special-purpose hardware.

[0101] At 615, the memory device can determine, based on the indicated address, whether a cache includes an indication of a defective memory cell in the set of memory cells. The operations of 615 can be performed according to the methods described herein. In some examples, aspects of the operations of 615 can be performed by a cache component as described with reference to Figure 5 The memory devices described perform the operations of method 600. In some examples, the memory devices can execute a set of instructions to control the functional elements of the memory devices to perform the described functions. Additionally or alternatively, the memory devices can perform aspects of the described functions using special-purpose hardware.

[0102] At 620, the memory device can perform, for the data, a procedure for error correction based on whether the cache includes the indication. The operations of 620 can be performed according to the methods described herein. In some examples, aspects of the operations of 620 can be performed by an error check component as described with reference to Figure 5 The memory devices described perform the operations of method 600. In some examples, the memory devices can execute a set of instructions to control the functional elements of the memory devices to perform the described functions. Additionally or alternatively, the memory devices can perform aspects of the described functions using special-purpose hardware.

[0103] In some examples, an apparatus as described with reference to Figures 1-5 The memory devices described perform the operations of method 600. In some examples, the memory devices can execute a set of instructions to control the functional elements of the memory devices to perform the described functions. Additionally or alternatively, the memory devices can perform aspects of the described functions using special-purpose hardware.

[0104] Some examples of the method 600 and the apparatus described herein can further include operations, features, means, or instructions for determining that the cache includes an indication, where performing the procedure for error correction includes determining that the data includes one or more errors based on the data and the parity information associated with the data, inverting bits associated with the memory cell to obtain altered data based on the indication that the memory cell is defective and the determination that the data includes one or more errors, and determining whether the altered data includes a second set of one or more errors based at least in part on the altered data and the parity information after inverting the bits.

[0105] Some examples of the method 600 and the apparatus described herein can further include operations, features, means, or instructions for correcting the second set of one or more errors based on the altered data and the parity information to obtain corrected data after inverting the bits.

[0106] Some examples of the method 600 and the apparatus described herein can further include operations, features, means, or instructions for outputting the corrected data by a memory device including the memory array in response to the command.

[0107] Some examples of the method 600 and the apparatus described herein can further include operations, features, means, or instructions for determining that a number of errors included in the one or more errors satisfies a threshold, where inverting the bits can be based on the determination that the number of errors satisfies the threshold.

[0108] Some examples of the method 600 and the apparatus described herein can further include operations, features, means, or instructions for inputting the data and the parity information to error checking logic, where determining that the data includes one or more errors can be based on inputting the data and the parity information to the error checking logic, and inputting the altered data and the parity information to the error checking logic after inverting the bits, where determining whether the altered data includes a second set of one or more errors can be based on inputting the altered data and the parity information to the error checking logic.

[0109] Some examples of the method 600 and the apparatus described herein can further include operations, features, means, or instructions for determining that the data includes an error based on the procedure for error correction, identifying a respective memory cell associated with the error among the set of memory cells, and writing an indication that the respective memory cell can be defective to the cache based on the determination that the data includes the error.

[0110] The method 600 and some examples of the devices described herein can further include operations, features, means, or instructions for performing a diagnostic procedure for the memory array prior to receiving the command; and writing an indication that the memory cell can be defective to the cache based on the diagnostic procedure.

[0111] The method 600 and some examples of the devices described herein can further include operations, features, means, or instructions for determining that the cache includes an indication that the memory cell can be defective; determining that no error was detected for the data based on the procedure for error correction; and removing the indication from the cache based on determining that no error was detected for the data.

[0112] In the method 600 and some examples of the devices described herein, the cache includes a second memory array, a portion of the memory array, or a combination thereof.

[0113] In the method 600 and some examples of the devices described herein, the cache includes an entry for the indicated address, the entry including the indication that the memory cell can be defective, and wherein the entry includes an address of the memory cell, an offset of the indicated address associated with the memory cell, an error count of the memory cell, metadata associated with the memory cell, or any combination thereof.

[0114] Figure 7 A flow diagram illustrating one or more methods 700 that support error cache techniques for improved error correction in memory devices in accordance with aspects of the present disclosure is shown. The operations of method 700 can be implemented by a memory device or its components as described herein. For example, the operations of method 700 can be performed by a memory device as described with reference to Figs. 1-2, 4, and 5 A-5C according to Figure 5 In some examples, a memory device can execute a set of instructions to control the functional elements of the memory device to perform the described functions. Additionally or alternatively, the memory device can perform aspects of the described functions using special-purpose hardware.

[0115] At 705, the memory device can receive a command to read data from a memory array, the command indicating an address associated with a set of memory cells within the memory array. The operations of 705 can be performed according to the methods described herein. In some examples, aspects of the operations of 705 can be performed by a command receiver as described with reference to Figs. 1-2, 4, and 5 A-5C. Figure 5

[0116] At 710, the memory device can read data from the set of memory cells in response to the command. The operations of 710 can be performed according to the methods described herein. In some examples, aspects of the operations of 710 can be performed by a read component as described with reference to Figs. 1-2, 4, and 5 A-5C. Figure 5 At 710, the memory device can read data from the set of memory cells in response to the command. The operations of 710 can be performed according to the methods described herein. In some examples, aspects of the operations of 710 can be performed by a read component as described with reference to Figs. 1-2, 4, and 5 A-5C.​

[0117] At 715, the memory device can determine that the data includes an error based on reading the data from the set of memory cells. The operations of 715 can be performed according to the methods described herein. In some examples, aspects of the operations of 715 can be performed by an error checking component as described with reference to Figure 5 FIG. 7.

[0118] At 720, the memory device can identify, among the set of memory cells, a memory cell associated with the error. The operations of 720 can be performed according to the methods described herein. In some examples, aspects of the operations of 720 can be performed by an error checking component as described with reference to Figure 5 FIG. 7.

[0119] At 725, the memory device can write, to the cache, an indication that the memory cell is defective based on determining that the data includes the error. The operations of 725 can be performed according to the methods described herein. In some examples, aspects of the operations of 725 can be performed by a cache component as described with reference to Figure 5 FIG. 7.

[0120] In some examples, an apparatus as described herein can perform one or more of the methods, such as the method 700. The apparatus can include features, means, or instructions for receiving a command to read data from a memory array, the command indicating an address associated with a set of memory cells within the memory array, reading the data from the set of memory cells in response to the command, determining that the data includes an error based on reading the data from the set of memory cells, identifying, among the set of memory cells, a memory cell associated with the error, and writing, to a cache, an indication that the memory cell is defective based on determining that the data includes the error.

[0121] Some examples of the method 700 and apparatus described herein can further include operations, features, means, or instructions for incrementing an error count associated with the memory cell based on identifying the memory cell as being associated with the error, where writing the indication to the cache can be based on the incremented error count satisfying a threshold.

[0122] Some examples of the method 700 and apparatus described herein can further include operations, features, means, or instructions for receiving a second command to read second data from the set of memory cells, determining, in response to the second command, that the cache includes an indication that the memory cell can be defective, and performing, for the second data, a procedure for error correction that can be based on the cache including the indication.

[0123] In some examples of the method 700 and the devices described herein, executing the program for error correction can include operations, features, means, or instructions for determining that the second data includes one or more errors based on the parity information for the second data; inverting bits associated with the memory cell to obtain altered data based on determining that the second data includes one or more errors; and correcting one or more errors in the altered data based on the parity information after the inverting to obtain corrected data.

[0124] Some examples of the method 700 and the devices described herein can further include operations, features, means, or instructions for outputting the corrected data by a memory device including the memory array in response to the second command.

[0125] Some examples of the method 700 and the devices described herein can further include operations, features, means, or instructions for inputting the second data and the parity information to error checking logic, where determining that the second data includes one or more errors can be based on inputting the second data and the parity information to the error checking logic, and inputting the altered data and the parity information to the error checking logic after inverting the bits, where correcting one or more errors in the altered data can be based on inputting the altered data and the parity information to the error checking logic.

[0126] Some examples of the method 700 and the devices described herein can further include operations, features, means, or instructions for determining that no error is detected for the second data based on the program for error correction; and removing the indication from the cache based on determining that no error is detected for the second data.

[0127] In some examples of the method 700 and the devices described herein, the cache includes the second memory array, a portion of the memory array, or a combination thereof.

[0128] In some examples of the method 700 and the devices described herein, the cache includes an entry for the indicated address, the entry including an indication that the memory cell can be defective, and where the entry includes an address of the memory cell, an offset of the indicated address associated with the memory cell, an error count of the memory cell, metadata associated with the memory cell, or any combination thereof.

[0129] It should be noted that the methods described above describe possible implementations, and that the operations and the steps can be rearranged or otherwise modified and that other implementations are possible. Furthermore, portions from two or more of the methods can be combined.

[0130] An apparatus is described. The apparatus can include a memory array, a cache configured to store an indication of a defective memory cell within the memory array, and a circuit configured to cause the apparatus to receive a command to read data from the memory array, the command indicating an address associated with a set of memory cells within the memory array, read the data from the set of memory cells in response to the command, check the cache based on the indicated address for an indication that a memory cell in the set of memory cells is defective, and perform a procedure for error correction on the data based on whether the cache contains the indication.

[0131] Some examples of the apparatus can include error checking logic, where to perform the procedure for error correction, the circuit can be further configured to cause the apparatus to input the data and parity information for the data into the error checking logic to determine whether the data contains one or more errors, invert bits associated with the memory cell to obtain altered data based at least in part on the cache containing the indication and the determination that the data contains one or more errors, and input the altered data and the parity information into the error checking logic to determine whether the altered data contains a second set of one or more errors.

[0132] In some examples, the error checking logic is further configured to contain at least one of the second set of one or more errors.

[0133] In some examples, the circuit is further configured to cause the apparatus to determine that a number of errors contained in the one or more errors satisfies a threshold, and invert the bits based at least in part on the determination that the number of errors satisfies the threshold.

[0134] In some examples, the circuit is further configured to cause the apparatus to receive a previous command to read second data from the set of memory cells prior to the command, determine that the second data contains an error associated with the memory cell, and update the cache to contain the indication that the memory cell is defective based at least in part on the determination that the second data contains the error.

[0135] Information and signals described herein can be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that can be referenced throughout the above description can be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof. Some drawings can illustrate signals as single signals; however, it will be understood by a person of ordinary skill in the art that the signals can represent a bus of signals, where buses can have a variety of bit widths.

[0136] The terms "in electronic communication," "in conductive contact," "connected," and "coupled" can refer to a relationship between components that supports the flow of signals between the components. Components are in electronic communication with each other (or in conductive contact with each other, or connected to each other, or coupled to each other) if there exists any conductive path between the components that can support the flow of signals between the components at any time. The conductive path between components that are in electronic communication with each other (or in conductive contact with each other, or connected to each other, or coupled to each other) can be an open circuit or a closed circuit at any given time, based on the operation of the device that includes the connected components. The conductive path between connected components can be a direct conductive path between the components, or the conductive path between connected components can be an indirect conductive path that can include intervening components such as switches, transistors, or other components. In some examples, the flow of signals between connected components can be interrupted for a period of time, for example, using one or more intervening components such as switches or transistors.

[0137] The term "coupled" refers to the condition of components moving from an open circuit relationship between the components, in which signals cannot currently be conveyed between the components via a conductive path, to a closed circuit relationship between the components, in which signals can be conveyed between the components via a conductive path. When a component such as a controller couples other components together, the component initiates a change that allows signals to flow between the other components through a conductive path in which signals were not previously permitted to flow.

[0138] The term "isolated" refers to a relationship between components in which signals cannot currently flow between the components. Components are isolated from each other if there is an open circuit between the components. For example, components that are isolated from each other by a switch positioned between the two components are isolated from each other when the switch is open. When a controller isolates two components, the controller implements a change that prevents signals from flowing between the components using a conductive path in which signals were previously permitted to flow.

[0139] Devices discussed herein that include a memory array can be formed on a semiconductor substrate such as silicon, germanium, silicon-germanium alloys, gallium arsenide, gallium nitride, etc. In some examples, the substrate is a semiconductor wafer. In other examples, the substrate can be a silicon-on-insulator (SOI) substrate such as a silicon-on-glass (SOG) or a silicon-on-sapphire (SOP), or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate or sub-regions of the substrate can be controlled by doping with various chemical species including, but not limited to, phosphorus, boron, or arsenic. Doping can be performed during initial formation or growth of the substrate, by ion implantation, or by any other doping method.

[0140] The switching components or transistors discussed herein can represent field effect transistors (FETs) and include a three-terminal device including a source, a drain, and a gate. The terminals can be connected to other electronic elements by conductive materials such as metals. The source and drain can be conductive and can include heavily doped (e.g., degenerate) semiconductor regions. The source and drain can be separated by a lightly doped semiconductor region or channel. If the channel is n-type (i.e., majority carriers are electrons), the FET can be referred to as an n-type FET. If the channel is p-type (i.e., majority carriers are holes), the FET can be referred to as a p-type FET. The channel can be capped by an insulating gate oxide. The channel conductivity can be controlled by applying a voltage to the gate. For example, applying a positive or negative voltage to an n-type or p-type FET, respectively, can cause the channel to become conductive. A transistor can be "turned on" or "activated" when a voltage greater than or equal to the threshold voltage of the transistor is applied to the gate of the transistor. A transistor can be "turned off" or "deactivated" when a voltage less than the threshold voltage of the transistor is applied to the gate of the transistor.

[0141] The description set forth herein describes example configurations and does not represent all of the possible configurations that can be implemented. The terminology used herein that the term "exemplary" means "serving as an example, instance, or illustration," and not "preferred" or "superior" over other examples. The detailed description includes specific details for the purpose of providing an understanding of the described technologies. These technologies, however, can be practiced without these specific details. In some instances, well-known structures and devices are shown in block diagram form in order to avoid obscuring the concepts of the described examples.

[0142] In the drawings, like reference numerals can be used to denote like components throughout the several views. Additionally, components of the same type can be distinguished by following the reference numeral with a dashed line and a second label wherein the second label differs from the previous second label of the like component. If only the first reference numeral is used in the specification, the description is applicable to any one of the like components having the same first reference numeral irrespective of the second reference numeral.

[0143] Information and signals described herein can be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that can be referenced throughout the above description can be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof.

[0144] The various illustrative blocks and modules described in connection with the present disclosure herein can be implemented or performed with a general-purpose processor, a DSP, an ASIC, an FPGA or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. The general-purpose processor can be a microprocessor, but in the alternative, the processor can be any processor, controller, microcontroller, or state machine. The processor can also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration).

[0145] The functions described herein can be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the functions can be stored on or transmitted over as one or more instructions or code on a computer-readable medium. Other examples and implementations are within the scope of the disclosure and appended claims. For example, due to the nature of software, functions described above can be implemented using software executed by a processor, hardware, firmware, hardwiring, or combinations of any of these. Features implementing functions can also be physically located at various positions, including being distributed such that portions of functions are implemented at different physical locations. Also, as used herein, including in the claims, "or" as used in a list of items (for example, a list of items prefaced by a phrase such as "at least one of" or "one or more of") indicates an inclusive list such that, for example, a list of at least one of A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Also, as used herein, the phrase "based on" shall not be construed as a reference to a closed set of conditions. For example, an exemplary step that is described as "based on condition A" can be based on both a condition A and a condition B without departing from the scope of the present disclosure. In other words, as used herein, the phrase "based on" shall be construed in the same manner as the phrase "based at least in part on."

[0146] Computer-readable media includes both non-transitory computer storage media and communication media including any medium that facilitates transfer of a computer program from one place to another. A non-transitory storage medium can be any available medium that can be accessed by a general purpose or special purpose computer. By way of example, and not limitation, non-transitory computer-readable media can comprise RAM, ROM, electrically erasable programmable read only memory (EEPROM), compact disk (CD) ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other non-transitory medium that can be used to carry or store desired program elements in the form of instructions or data structures and that can be accessed by a general-purpose or special-purpose computer, or a general-purpose or special-purpose processor. Also, any connection is properly termed a computer-readable medium. For example, if the software is transmitted from a website, server, or other remote source using a coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave, then the coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave are included in the definition of medium. Disk and disc, as used herein, include CD, laser disc, optical disc, digital versatile disc (DVD), floppy disk and Blu-ray disc where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above are also included within the scope of computer-readable media.

[0147] The description herein is presented to enable a person skilled in the art to make or use the disclosure. Various modifications to the disclosure will be readily apparent to those skilled in the art, and the generic principles defined herein can be applied to other variations without departing from the scope of the disclosure. Thus, the disclosure is not to be limited to the examples and designs described herein but is to be accorded the broadest scope consistent with the principles and novel features disclosed herein.

Claims

1. A method of error correction, comprising: receiving a command to read data from a memory array, the command indicating an address associated with a set of memory cells within the memory array; reading the data from the set of memory cells in response to the command; determining, based at least in part on the indicated address, whether a cache contains an indication that a memory cell in the set of memory cells is defective; and performing, for the data, a procedure for the error correction based at least in part on whether the cache contains the indication.

2. The method of claim 1, further comprising: determining that the cache contains the indication, wherein performing the procedure for the error correction comprises: determining, based at least in part on the data and parity information associated with the data, that the data contains one or more errors; inverting a bit associated with the memory cell to obtain altered data based at least in part on the indication that the memory cell is defective and determining that the data contains the one or more errors; and determining, after inverting the bit, whether the altered data contains a second set of one or more errors based at least in part on the altered data and the parity information.

3. The method of claim 2, further comprising: correcting the second set of one or more errors to obtain corrected data based at least in part on the altered data and the parity information after inverting the bit.

4. The method of claim 3, further comprising: outputting, by a memory device containing the memory array, the corrected data in response to the command.

5. The method of claim 2, further comprising: determining that a number of errors contained in the one or more errors satisfies a threshold, wherein inverting the bit is based at least in part on determining that the number of errors satisfies the threshold.

6. The method of claim 2, further comprising: inputting the data and the parity information to error checking logic circuitry, wherein determining that the data contains the one or more errors is based at least in part on inputting the data and the parity information to the error checking logic circuitry; and inputting the altered data and the parity information to the error checking logic circuitry after inverting the bit, wherein determining whether the altered data contains the second set of one or more errors is based at least in part on inputting the altered data and the parity information to the error checking logic circuitry.

7. The method of claim 1, further comprising: determining, based at least in part on the procedure for the error correction, that the data contains an error; identifying, among the set of memory cells, a respective memory cell associated with the error; and writing, based at least in part on determining that the data contains the error, the indication that the respective memory cell is defective to the cache.

8. The method of claim 1, further comprising: performing a diagnostic procedure for the memory array prior to receiving the command; and writing the indication that the memory cell is defective to the cache based at least in part on the diagnostic procedure.

9. The method of claim 1, further comprising: determining that the cache includes the indication that the memory cell is defective; determining that no error is detected for the data based at least in part on the procedure for the error correction; and removing the indication from the cache based at least in part on determining that no error is detected for the data.

10. The method of claim 1, wherein the cache comprises a second memory array, a portion of the memory array, or a combination thereof.

11. The method of claim 1, wherein the cache includes an entry for the indicated address, the entry including the indication that the memory cell is defective, and wherein the entry includes an address of the memory cell, an offset of the indicated address associated with the memory cell, an error count for the memory cell, metadata associated with the memory cell, or any combination thereof.

12. A method of error correction, comprising: receiving a command to read data from a memory array, the command indicating an address associated with a set of memory cells within the memory array; reading the data from the set of memory cells in response to the command; determining that the data includes an error based at least in part on reading the data from the set of memory cells; identifying a memory cell associated with the error among the set of memory cells; writing an indication that the memory cell is defective to a cache based at least in part on determining that the data includes the error; and performing a procedure for the error correction based at least in part on the cache including the indication for the data.

13. A method of error correction, comprising: receiving a command to read data from a memory array, the command indicating an address associated with a set of memory cells within the memory array; reading the data from the set of memory cells in response to the command; determining that the data includes an error based at least in part on reading the data from the set of memory cells; identifying a memory cell associated with the error among the set of memory cells; incrementing an error count associated with the memory cell based at least in part on identifying the memory cell as associated with the error; writing an indication that the memory cell is defective to a cache based at least in part on determining that the data includes the error, wherein writing the indication to the cache is based at least in part on the incremented error count satisfying a threshold; and performing a procedure for the error correction based at least in part on the cache including the indication for the data.

14. A method of error correction, comprising: receiving a command to read data from a memory array, the command indicating an address associated with a set of memory cells within the memory array; reading the data from the set of memory cells in response to the command; determining that the data contains an error based at least in part on reading the data from the set of memory cells; identifying a memory cell associated with the error among the set of memory cells; writing an indication that the memory cell is defective to a cache based at least in part on determining that the data contains the error; performing a procedure for error correction of the data based at least in part on the cache containing the indication; receiving a second command to read second data from the set of memory cells; determining that the cache contains the indication that the memory cell is defective in response to the second command; and performing the procedure for error correction of the second data based at least in part on the cache containing the indication.

15. The method of claim 14, wherein performing the procedure for error correction of the second data comprises: determining that the second data contains one or more errors based at least in part on parity information for the second data; inverting bits associated with the memory cell to obtain altered data based at least in part on determining that the second data contains the one or more errors; and correcting one or more errors in the altered data to obtain corrected data based at least in part on the parity information after the inverting.

16. The method of claim 15, further comprising: outputting the corrected data by a memory device containing the memory array in response to the second command.

17. The method of claim 15, further comprising: inputting the second data and the parity information to error checking logic circuitry, wherein determining that the second data contains the one or more errors is based at least in part on inputting the second data and the parity information to the error checking logic circuitry; and inputting the altered data and the parity information to the error checking logic circuitry after the inverting, wherein correcting the one or more errors in the altered data is based at least in part on inputting the altered data and the parity information to the error checking logic circuitry.

18. The method of claim 14, further comprising: determining that no error is detected for the second data based at least in part on performing the procedure for error correction of the second data; and removing the indication from the cache based at least in part on determining that no error is detected for the second data.

19. The method of claim 12, wherein the cache comprises a second memory array, a portion of the memory array, or a combination thereof.

20. The method of claim 12, wherein the cache includes an entry for the indicated address, the entry including the indication that the memory cell is defective, and wherein the entry includes an address of the memory cell, an offset of the indicated address associated with the memory cell, an error count of the memory cell, metadata associated with the memory cell, or any combination thereof.

21. A memory device, the memory device comprising: a memory array; a cache configured to store an indication of a defective memory cell within the memory array; and circuitry configured to cause the memory device to: receive a command to read data from the memory array, the command indicating an address associated with a set of memory cells within the memory array; read the data from the set of memory cells in response to the command; check the cache based at least in part on the indicated address for an indication that a memory cell of the set of memory cells is defective; and perform a procedure for error correction based at least in part on whether the cache contains the indication for the data.

22. The memory device of claim 21, further comprising: error checking logic circuitry, wherein to perform the procedure for the error correction, the circuitry is further configured to cause the memory device to: input the data and parity information for the data into the error checking logic circuitry to determine whether the data contains one or more errors; inversion a bit associated with the memory cell to obtain altered data based at least in part on the cache containing the indication and determining that the data contains one or more errors; and input the altered data and the parity information into the error checking logic circuitry to determine whether the altered data contains a second set of one or more errors.

23. The memory device of claim 22, wherein the error checking logic circuitry is further configured to: correct at least one of the second set of one or more errors.

24. The memory device of claim 23, wherein the circuitry is further configured to cause the memory device to: determine that a number of errors contained in the one or more errors satisfies a threshold; and inversion the bit based at least in part on determining that the number of errors satisfies the threshold.

25. The memory device of claim 23, wherein the circuitry is further configured to cause the memory device to: receive a previous command to read second data from the set of memory cells prior to the command; determine that the second data contains an error associated with the memory cell; and update the cache to contain the indication that the memory cell is defective based at least in part on determining that the second data contains the error.

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