Addressing region namespaces and non-partitioned memory based on data characteristics

Abstract

The present application relates to addressing a zone namespace and non-partitioned memory based on data characteristics. The present invention provides a memory device comprising a first zone configured as a non-partitioned addressable memory and a second zone configured as a zone namespace. A write command including a payload and a functional specification of the payload is received, wherein the functional specification indicates whether the payload includes sequentially writable data. Based on the functional specification of the payload, a corresponding one of the first zone or the second zone of the memory device is determined, wherein the second zone is to store sequentially writable data. The payload is stored in the corresponding one of the first zone or the second zone of the memory device.

Description

Technical Field

[0001] Embodiments of the present disclosure relate generally to memory subsystems, and more particularly to addressing region namespaces and non-partitioned memory based on data characteristics. Background Art

[0002] The memory subsystem may include one or more memory devices that store data. The memory devices may be, for example, non-volatile memory devices and volatile memory devices. In general, the host system may utilize the memory subsystem to store data at the memory devices and retrieve data from the memory devices. Summary of the invention

[0003] Aspects of the present application relate to a system comprising: a memory device comprising a first region configured as a non-partitioned addressable memory and a second region configured as a zone namespace; and a processing device operatively coupled to the memory device to perform operations comprising: receiving a write command comprising a payload and a functional specification of the payload, wherein the functional description indicates whether the payload comprises sequentially writable data; identifying a corresponding one of the first region or the second region of the memory device based on the functional specification of the payload, wherein the second region will store sequentially writable data; and storing the payload in the corresponding one of the first region or the second region of the memory device.

[0004] Another aspect of the present application relates to a method comprising: receiving a write command including a logical block address, a payload, and a tag indicating whether the payload is designated as metadata; in response to determining that the tag indicates that the payload is designated as metadata, identifying a first namespace identifier corresponding to a first region of a memory device, wherein the first region is configured as a non-partitioned namespace; converting the logical block address and the first namespace identifier to a physical block address in the first region of the memory device; and writing the payload to the physical block address in the first region of the memory device.

[0005] Yet another aspect of the present application relates to a non-transitory computer-readable storage medium, comprising instructions which, when executed by a processing device, cause the processing device to perform operations comprising: receiving a write command comprising a payload and a functional description of the payload, wherein the functional description indicates whether the payload comprises sequentially writable data; identifying a corresponding one of a first area or a second area of ​​the memory device based on the functional specification of the payload, wherein the first area is configured as a non-partitioned addressable memory and the second area is configured as a regional namespace, wherein the second area will store sequentially writable data; and storing the payload in the corresponding one of the first area or the second area of ​​the memory device. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The present disclosure will be more fully understood from the detailed description given below and the accompanying drawings of various embodiments of the present disclosure. However, the drawings should not be considered to limit the present disclosure to specific embodiments, but are only for explanation and understanding.

[0007] Figure 1 An example computing system including a memory subsystem according to some embodiments of the present disclosure is described.

[0008] Figure 2 A block diagram illustrating an example host system according to some embodiments of the present disclosure.

[0009] Figure 3 A block diagram illustrating an example memory subsystem according to some embodiments of the present disclosure.

[0010] Figure 4 is a flow chart of an example method for marking a write request to indicate a functional designation of a payload of the write request, according to some embodiments of the present disclosure.

[0011] Figure 5 and 6 is a flow chart of an example method for executing a tagged write command to write a payload to an appropriate memory region according to some embodiments of the present disclosure.

[0012] Figure 7 is a block diagram of an example computer system in which embodiments of the present disclosure may operate. DETAILED DESCRIPTION

[0013] Aspects of the present disclosure relate to storing data in a regional namespace memory or a non-partitioned memory according to the characteristics of the data. The memory subsystem may be a storage device, a memory module, or a combination of a storage device and a memory module. Figure 1Examples of storage devices and memory modules are described. In general, a host system may utilize a memory subsystem that includes one or more components, such as memory devices that store data. The host system may provide data to be stored at the memory subsystem and may request data to be retrieved from the memory subsystem.

[0014] The memory subsystem may include multiple memory devices to store data from the host system. An example of a non-volatile memory device is a NAND memory device. Figure 1 Other examples of non-volatile memory devices are described. The memory subsystem includes a memory subsystem controller that can communicate with the memory device to perform operations such as reading data, writing data, or erasing data at the memory device and other such operations. Figure 1 The memory subsystem controller is described in more detail.

[0015] The host system may send an access request (e.g., a write command, a read command) to the memory subsystem, such as storing data on a memory device of the memory subsystem and reading data from a memory device of the memory subsystem. As specified by the host request, the data to be read or written is referred to as "host data". The host request may include logical address information (e.g., logical block address (LBA), namespace) of the host data, which is the location associated with the host data by the host system. The logical address information (e.g., LBA, namespace) may be part of the metadata of the host data. Metadata, host data, or both together may be referred to as "payload" hereinafter. Metadata, host data, and parity data for error correction may collectively form an error correction code (ECC) codeword. Metadata may also include data versions (e.g., for distinguishing the degree of aging of the data written), valid bitmaps (specifying which LBAs or logical transfer units contain valid data), etc.

[0016] Each of the memory devices may include one or more memory cell arrays. A memory cell ("cell") is an electronic circuit that stores information. Depending on the cell type, a cell may store one or more bits of binary information and have various logical states related to the number of bits stored. The logical states may be represented by binary values ​​such as "0" and "1" or a combination of such values. For example, a single-level cell (SLC) may store one bit of information and have two logical states, a multi-level cell (MLC) may store two bits of information and have four logical states, and a triple-level cell (TLC) may store three bits of information and have eight logical states.

[0017] In some embodiments, a file system can be used as a way to organize user data on one or more memory devices of a memory subsystem by providing programs for storing, retrieving and updating data and managing available space on one or more memory devices. The file system organizes data in an efficient manner and can be tuned to the specific characteristics of the memory device. File systems are used on various types of data storage devices to maintain the physical location of computer files. File systems usually allocate space in a granular manner, usually using multiple physical units on the memory device. The file system is responsible for organizing files and directories, and tracking which areas of the device belong to certain files and which areas are not used. The file system contains data blocks that store actual data from an application or operating system running on the host system, as well as metadata blocks. This file system metadata contains information about the design, structure, and layout of data structures used to store actual data. In other embodiments, object storage can be used instead of a file system. For example, in some large-scale computing embodiments, objects can be used instead of files when the characteristics of those objects are more appropriate (for example, the presence of comprehensive metadata stored with files eliminates the hierarchical file structure associated with the file system).

[0018] Shingled magnetic recording (SMR) hard drives store data in partially overlapping tracks to increase storage density and, therefore, the capacity of the hard drive. Overlapping track formats are used because the write head cannot be made as narrow as the read head using existing hard drive technology (e.g., because reducing the write head to a smaller size will result in a magnetic field generated by the write head that is insufficient to change the magnetization of the storage medium). When each track is written, the track overlaps a portion of the previously written track, leaving a remaining portion that can be subsequently read by the read head but is too narrow to be updated by the write head. Therefore, writing to a track overwrites an area of ​​an adjacent track. To avoid overwriting existing data, tracks are grouped into regions, and data written to a region is appended after the last track of valid data in the region. Data is written sequentially to tracks within each region. If data in a valid track is to be modified, all valid tracks in the region are read into memory and rewritten with the modified data. Therefore, SMR hard drives have a requirement that write commands write data sequentially (e.g., to sequential physical blocks on a storage medium). However, to support existing file systems that store metadata non-sequentially, an SMR hard drive may provide a feature that converts a limited number of non-sequential writes to sequential writes, for example, by mapping non-sequential logical block addresses to sequential physical block addresses. This conversion may be performed by the hard drive controller during idle time between I / O operations. For example, a hard drive may perform hundreds (e.g., 200 to 300) of I / O operations per second, and the hard drive controller has ample time to convert random writes to sequential writes (e.g., at least 100 microseconds may be available for each I / O operation).

[0019] Some memory devices are also configured with zone namespaces. In a zone namespace, the address space of a memory device is divided into zones that allow for more efficient management of data as the capacity of the memory device increases. However, a host system designed to work with a conventional file system may face certain challenges when interacting with a memory device with a zone namespace. For example, a conventional file system may write data in blocks as small as 4 kilobytes (KB), while a zone namespace memory device may have an optimal write size in the range of approximately 100 KB (e.g., 64 KB, 128 KB, 196 KB).

[0020] In addition, the zone namespace does not directly support out-of-order writes, so random writes to the zone namespace are rejected and not performed. Many file systems utilize an in-place write method (i.e., random writes, also referred to herein as "non-sequential" writes), typically with a smaller granularity than is optimal for the zone namespace. For example, file system metadata is typically written using random writes. However, in the zone namespace, writes are performed sequentially starting from the beginning of each zone. The conversion techniques performed by SMR hard drives are not feasible in solid-state memory devices that perform more I / O operations per second and do not have enough processing power to perform remapping within the available time (e.g., within 1 microsecond). Therefore, the zone namespace, although very suitable for storing sequential data of a file system such as SMR, does not provide effective support data written using random writes, such as file system metadata written by an SMR file system.

[0021] Aspects of the present disclosure address the above and other deficiencies by providing a memory subsystem that effectively combines a non-partitioned namespace for randomly written data (e.g., metadata) and a zone namespace for sequentially written data (e.g., "host data") in the same memory subsystem (e.g., SSD). By using a non-partitioned namespace to store metadata and using a zone namespace to store host data, the memory subsystem can support existing file systems, such as an SMR file system. The expected size of metadata is typically a fraction (e.g., less than one percent) of the size of the host data of the file system, so the size of the non-partitioned namespace can be determined based on the size of the zone namespace allocated for the host data. The memory subsystem can direct write commands from the host to the non-partitioned namespace or the zone namespace based on whether the payload of each write command is metadata or data. A relatively small non-partitioned namespace may correspond to a memory area using cells (e.g., TLC or SLC) with a relatively long program / erase life suitable for storing metadata, which is written more frequently than host data. A zone namespace may correspond to a memory region that uses cells (eg, QLC) that are more economically suitable for storing larger amounts of infrequently written data (eg, host data).

[0022] Advantages of the present disclosure include, but are not limited to, more efficient use of a memory subsystem to provide solid-state storage for a file system such as a shingled magnetic recording (SMR) file system. Existing file systems designed for use with disk storage devices do not need to be modified to accommodate differences between the memory subsystem and the disk storage device, such as those associated with storing randomly written metadata, while also using a zone namespace that efficiently supports sequentially written metadata. In addition, randomly written metadata can be stored in a memory device with a longer lifespan, and less frequently written sequential host data can be stored in a memory device that is more economical but has a shorter lifespan. Thus, aspects of the present disclosure result in a memory device that performs better and lasts longer.

[0023] Figure 1 An example computing system 100 is illustrated that includes a memory subsystem 110 according to some embodiments of the present disclosure. Memory subsystem 110 may include media such as one or more volatile memory devices (e.g., memory device 140), one or more non-volatile memory devices (e.g., memory device 130), or a combination of the like.

[0024] The memory subsystem 110 may be a storage device, a memory module, or a combination of a storage device and a memory module. Examples of storage devices include solid-state drives (SSDs), flash drives, universal serial bus (USB) flash drives, embedded multimedia controller (eMMC) drives, universal flash storage (UFS) drives, secure digital (SD) cards, and hard disk drives (HDDs). Examples of memory modules include dual in-line memory modules (DIMMs), small outline DIMMs (SO-DIMMs), and various types of non-volatile dual in-line memory modules (NVDIMMs).

[0025] The computing system 100 can be a computing device such as a desktop computer, a laptop computer, a network server, a mobile device, a vehicle (e.g., an airplane, drone, train, car, or other transportation vehicle), an Internet of Things (IoT) enabled device, an embedded computer (e.g., an embedded computer included in a vehicle, industrial equipment, or a networked commercial device), or such a computing device that includes a memory and a processing device.

[0026] The computing system 100 may include a host system 120 coupled to one or more memory subsystems 110. In some embodiments, the host system 120 is coupled to multiple memory subsystems 110 of different types. Figure 1An example of a host system 120 coupled to a memory subsystem 110 is illustrated. As used herein, "coupled to" or "coupled with" generally refers to a connection between components, which can be an indirect communication connection or a direct communication connection (e.g., without intervening components), whether wired or wireless, including connections such as electrical connections, optical connections, magnetic connections, etc.

[0027] The host system 120 may include a processor chipset and a software stack executed by the processor chipset. The processor chipset may include one or more cores, one or more caches, a memory controller (e.g., an NVDIMM controller), and a storage protocol controller (e.g., a PCIe controller, a SATA controller). The host system 120 uses the memory subsystem 110, for example, to write data to the memory subsystem 110 and read data from the memory subsystem 110.

[0028] The host system 120 may be coupled to the memory subsystem 110 via a physical host interface. Examples of the physical host interface include, but are not limited to, a Serial Advanced Technology Attachment (SATA) interface, a Peripheral Component Interconnect Express (PCIe) interface, a Universal Serial Bus (USB) interface, a Fibre Channel, a Serial Attached SCSI (SAS), a Double Data Rate (DDR) memory bus, a Small Computer System Interface (SCSI), a Dual In-line Memory Module (DIMM) interface (e.g., a DIMM socket interface supporting Double Data Rate (DDR)), etc. The physical host interface may be used to transfer data between the host system 120 and the memory subsystem 110. When the memory subsystem 110 is coupled to the host system 120 through a physical host interface (e.g., a PCIe bus), the host system 120 may further utilize an NVM Express (NVMe) interface to access components (e.g., the memory device 130). The physical host interface may provide an interface for transferring control, address, data, and other signals between the memory subsystem 110 and the host system 120. Figure 1 Memory subsystem 110 is illustrated as an example. In general, host system 120 can access multiple memory subsystems via the same communication connection, multiple separate communication connections, and / or a combination of communication connections.

[0029] The memory devices 130, 140 may include any combination of different types of non-volatile memory devices and / or volatile memory devices. Volatile memory devices (e.g., memory device 140) may be, but are not limited to, random access memory (RAM), such as dynamic random access memory (DRAM) and synchronous dynamic random access memory (SDRAM).

[0030] Some examples of non-volatile memory devices (e.g., memory device 130) include NAND-type flash memory and write-in-place memory, such as a three-dimensional cross-point ("3D cross-point") memory device, which is a cross-point array of non-volatile memory cells. The cross-point array of non-volatile memory cells can be combined with a stackable cross-grid data access array to perform bit storage based on changes in body resistance. In addition, compared to many flash-based memories, cross-point non-volatile memories can perform write-in-place operations, where non-volatile memory cells can be programmed without pre-erasing the non-volatile memory cells. NAND-type flash memory includes, for example, two-dimensional NAND (2D NAND) and three-dimensional NAND (3D NAND).

[0031] Each of the memory devices 130 may include one or more memory cell arrays. One type of memory cell, such as a single-level cell (SLC), may store one bit per cell. Other types of memory cells, such as multi-level cells (MLC), three-level cells (TLC), four-level cells (QLC), and five-level cells (PLC) may store multiple bits per cell. In some embodiments, each of the memory devices 130 may include one or more memory cell arrays, such as SLC, MLC, TLC, QLC, PLC, or any combination of these. In some embodiments, a particular memory device may include an SLC portion and an MLC portion, a TLC portion, a QLC portion, or a PLC portion of a memory cell. The memory cells of the memory device 130 may be grouped into pages that may refer to logical units of a memory device for storing data. For some types of memory (e.g., NAND), pages may be grouped to form blocks.

[0032] Although nonvolatile memory components such as a 3D cross-point array of nonvolatile memory cells and NAND-type flash memory (e.g., 2D NAND, 3D NAND) are described, the memory device 130 may be based on any other type of nonvolatile memory, such as read-only memory (ROM), phase-change memory (PCM), self-selected memory, other chalcogenide-based memories, ferroelectric transistor random access memory (FeTRAM), ferroelectric random access memory (FeRAM), magnetic random access memory (MRAM), spin transfer torque (STT)-MRAM, conductive bridging RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), or non-(NOR) flash memory, or electrically erasable programmable read-only memory (EEPROM).

[0033] The memory subsystem controller 115 (or, for simplicity, controller 115) may communicate with the memory device 130 to perform operations such as reading data, writing data, or erasing data at the memory device 130 and other such operations. The memory subsystem controller 115 may include hardware, such as one or more integrated circuits and / or discrete components, buffer memory, or a combination thereof. The hardware may include digital circuits with dedicated (i.e., hard-coded) logic to perform the operations described herein. The memory subsystem controller 115 may be a microcontroller, dedicated logic circuit (e.g., a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), etc.), or other suitable processor.

[0034] The memory subsystem controller 115 may include a processing device including one or more processors (e.g., processor 117) configured to execute instructions stored in a local memory 119. In the illustrated example, the local memory 119 of the memory subsystem controller 115 includes an embedded memory configured to store instructions for executing various processes, operations, logic flows, and routines that control the operation of the memory subsystem 110, including handling communications between the memory subsystem 110 and the host system 120.

[0035] In some embodiments, local memory 119 may include memory registers that store memory pointers, fetched data, etc. Local memory 119 may also include read-only memory (ROM) for storing microcode. Figure 1 The example memory subsystem 110 in FIG. 1 has been illustrated as including a memory subsystem controller 115, but in another embodiment of the present disclosure, the memory subsystem 110 does not include a memory subsystem controller 115, but may instead rely on external control (e.g., provided by an external host or by a processor or controller separate from the memory subsystem).

[0036] In general, the memory subsystem controller 115 may receive commands or operations from the host system 120, and may convert the commands or operations into instructions or appropriate commands to achieve the desired access to the memory device 130. The memory subsystem controller 115 may be responsible for other operations such as wear leveling operations, garbage collection operations, error detection and error correction code (ECC) operations, encryption operations, cache operations, and address conversion between logical addresses (e.g., logical block addresses (LBA), namespaces) and physical addresses (e.g., physical block addresses) associated with the memory device 130. The memory subsystem controller 115 may further include a host interface circuit to communicate with the host system 120 via a physical host interface. The host interface circuit may convert commands received from the host system into command instructions to access the memory device 130, and convert responses associated with the memory device 130 into information for the host system 120.

[0037] The memory subsystem 110 may also include additional circuits or components not illustrated. In some embodiments, the memory subsystem 110 may include a cache or buffer (e.g., DRAM) and address circuits (e.g., row decoders and column decoders) that may receive addresses from the memory subsystem controller 115 and decode the addresses to access the memory device 130.

[0038] In some embodiments, the memory device 130 includes a local media controller 135 that operates in conjunction with the memory subsystem controller 115 to perform operations on one or more memory cells of the memory device 130. An external controller (e.g., the memory subsystem controller 115) can externally manage the memory device 130 (e.g., perform media management operations on the memory device 130). In some embodiments, the memory subsystem 110 is a managed memory device that includes an original memory device 130 having control logic (e.g., the local controller 132) on the die and a controller (e.g., the memory subsystem controller 115) for media management within the same memory device package. An example of a managed memory device is a managed NAND (MNAND) device.

[0039] The memory subsystem 110 includes a memory zone manager 113. In one embodiment, the memory zone manager 113 may manage the writing and storage of data across different zones / portions of the memory device 130 and the memory device 140. As described above, the memory device 130 may include a non-volatile memory device (e.g., NAND). In one embodiment, a first zone of the memory device 130 is configured with a non-partition namespace, and a second zone of the memory device 130 is configured with a regional namespace. The non-partition namespace may correspond to a non-partition addressable memory zone, which may be a portion of the memory device 130 that is not included in the regional namespace. The size of the first zone (which corresponds to the non-partition namespace) storing metadata is relatively small compared to the size of the second zone (which corresponds to the regional namespace) and the total capacity of the memory device 130. The first zone may include, for example, TLC or SLC memory cells, and the second zone may include, for example, QLC memory cells.

[0040] The memory zone manager 113 may determine in which namespace to store the payload contained in the write request. Storing the payload in a namespace results in the payload being stored in memory cells of a zone configured as the namespace. Thus, for example, storing the payload in a non-partitioned namespace results in the payload being stored in memory cells of a first zone, and storing the payload in a regional namespace results in the payload being stored in memory cells of a second zone. Although specific namespaces, zones, and memory cells are described in the examples herein, any suitable namespace, zone, or memory cell may be used. For example, in another embodiment, there may be two non-partitioned namespaces, one of which corresponds to a zone containing TLC memory cells, and the other of which corresponds to a zone containing SLC memory cells, and the memory zone manager 113 may determine which of the three namespaces (a first conventional, a second conventional, or a regional namespace) stores the payload contained in the write request based on characteristics of the payload, such as the size of the payload and the functional designation of the payload. Thus, for example, metadata having a size less than a threshold number of bytes may be stored in a first non-partitioned zone, and metadata having a size greater than a threshold number of bytes may be stored in a second non-partitioned zone.

[0041] In certain embodiments, the memory subsystem controller 115 includes at least a portion of the memory region manager 113. In certain embodiments, the memory region manager 113 is part of the host system 110, an application, or an operating system. In other embodiments, the local media controller 135 includes at least a portion of the memory region manager 113 and is configured to perform the functionality described herein.

[0042] The memory zone manager 113 may receive a write command from the host system 120, from the memory subsystem controller 115, or from some other component of the memory subsystem 110. The write command may include a logical address, a payload, and a tag reflecting characteristics of the payload. The characteristics may represent a functional designation of the data in the payload or an expected update frequency of the data in the payload. In one embodiment, the source of the write request may be a file system, in which case the tag in the write command may indicate whether the data in the payload is data or metadata. In another embodiment, the source of the write request may be a key-value store, in which case the tag in the write command may indicate whether the data in the payload is a key or a value.

[0043] When the storage devices are configured via the NVMe protocol, each namespace may be a certain number of one or more storage devices 130-140, which may be formatted into logical blocks (e.g., ranges of LBA space). The NVMe protocol provides access to a single namespace, which appears as a standard block device on which file systems and applications may be deployed without any modification. The storage zone manager 113 identifies one of the zones (or corresponding namespaces) for each host request (e.g., each read or write request) based on one or more characteristics of the request (e.g., tags included in the request), and stores the payload in the identified zone (or corresponding namespace).

[0044] In a particular embodiment, write requests from the host file system may be intercepted on the host system by a software architecture designed to intercept write requests and determine certain characteristics of the write requests. The software architecture may be implemented, for example, as a device mapper operating at the Linux kernel level (e.g., as part of a driver stack) for mapping physical block devices to higher-level virtual block devices.

[0045] The device mapper may determine whether the payload associated with each write command corresponds to metadata or host data by querying the file system. The device mapper may then associate a tag with the write command to provide the functional designation of the payload as metadata or host data, and send the write command to the storage subsystem (e.g., via a host interface). The storage subsystem may use the tag to identify the functional designation of the payload when receiving the write command. If the tag indicates that the payload is metadata, the storage subsystem may write the payload to a non-partitioned namespace, or if the tag indicates that the payload is host data, the storage subsystem may write the payload to a regional namespace. In addition, since the non-partitioned namespace stores metadata and is a fraction of the size of the regional namespace, the non-partitioned namespace may economically contain memory zones where the physical memory blocks are TLC or SLC NAND memories, which have relatively long program / erase lifespans. Because the zone namespace stores host data and is expected to be written sequentially (e.g., as in the case where host data is stored by an SMR file system), the zone namespace may include memory zones where the physical memory blocks are QLC NAND memory, which can store large amounts of data more economically than TLC or SLC NAND memory.

[0046] The read command may be processed by the memory subsystem using a data allocation table constructed when executing a write command. The data allocation table may include an association between a logical block address of a write payload and a corresponding functional designation of the payload. Upon receiving a read command, the memory subsystem may determine whether the payload is in a non-partition namespace or a regional namespace by retrieving the functional designation associated with the logical block address from the data allocation table. For example, if the functional designation of the logical block address is metadata, then the payload is in a non-partition namespace, and if the functional designation is host data, then the payload is in a regional namespace. The logical block address may be used to retrieve the payload from the identified namespace and provided to the host file system.

[0047] Therefore, the memory subsystem can effectively use the non-partitioned namespace for randomly written data and the zone namespace for sequentially written data to efficiently perform read and write operations for the SMR file system or other file systems that write data sequentially and non-sequentially. The zone file system can use QLC NAND storage devices for host data to more economically meet the growing required capacity of storage devices, while the conventional file system can use NAND storage devices with longer program / erase life (such as TLC or SLC NAND) for host data and a relatively small amount of metadata stored by the host file system.

[0048] Based on the tags introduced above, the memory zone manager 113 may identify a zone of the memory device 130 for storing the payload. For example, if the tag indicates that the data in the payload is metadata from a file system, the memory zone manager 113 may identify a first zone of the memory device 130 as a zone for storing the payload. If the tag indicates that the data in the payload is data from a file system, the memory zone manager 113 may identify a second zone of the memory device 130 as a zone for storing the payload. Similarly, if the tag indicates that the data in the payload is a key from a key value store (KVS), the memory zone manager 113 may identify the first zone. If the tag indicates that the data in the payload is a value from a KVS, the memory zone manager 113 may identify the second zone.

[0049] In one embodiment, the tag may indicate that the data in the payload is expected to be updated frequently (e.g., at least once within a specified time period), in which case the memory zone manager 113 may identify the first area as a zone for storing the payload. Alternatively, if the tag indicates that the data in the payload is expected to be updated infrequently, the memory zone manager 113 may identify the second zone as a zone for storing the payload. The second zone may include memory that may be block-oriented and may have a higher latency than the memory in the first zone. The memory in the first zone may be byte-oriented and may have a smaller capacity than the memory in the second zone, which may be a high-capacity memory. That is, the low-latency memory in the first zone for storing frequently updated data may be a single-level or three-level cell memory, while the high-capacity memory in the second zone for storing less frequently updated data may be a memory with a higher number of bits per cell (e.g., a four-level cell memory).

[0050] Once the memory zone manager 113 has identified the zone (or corresponding namespace) on which to store the payload, the memory zone manager 113 may store the payload in the identified zone (or corresponding namespace). The memory zone manager 113 may then update the data allocation table to associate the logical address with an indication of the identified zone reflecting the location of the payload on the memory device.

[0051] Figure 2Block diagram 200 illustrating an example host system according to some embodiments of the present disclosure. In one embodiment, host system 120 includes an operating system 210, which includes a file system 211, a data allocation device mapper 220, and a system table 250. Operating system 210 may also include a key-value store or another type of application (not shown). System table 250 may store descriptors of data stored by file system 211, such as information about each file, including metadata and data. File system 211 may send a write request 212 including a payload. A write request (also referred to herein as a write command) may be a host request that includes a logical address and a payload of data or metadata to be written to the storage subsystem at the logical address.

[0052] In a particular embodiment, a write request 212 from a host file system may be intercepted on the host system 120 by a software architecture designed to intercept write requests and determine certain characteristics of the write requests. The software architecture may be implemented, for example, as a device mapper 220 operating at the Linux kernel level (e.g., as part of a driver stack) for mapping physical block devices to higher-level virtual block devices. The device mapper 220 may pass information from the virtual block device to the memory subsystem. In some implementations, the software architecture may be implemented at the kernel space level or at the user space level.

[0053] In certain embodiments, the device mapper 220 may intercept write commands 212 issued by the file system 211 or from a key value store (KVS). In the file system 211, for example, a write request from the host system 120 may be used for data or metadata. A write request for data from the host system 120 may contain actual data from an application or operating system 210 running on the host system, while a write request for metadata may contain information about the design, structure, and layout of a data structure for storing actual data. The size of a data write request tends to be larger than metadata and is expected to be stored for a longer period of time with minimal updates. Metadata write requests tend to be smaller than data writes and are expected to be updated frequently. Metadata should also be consistent, and therefore other I / O operations may be suspended when metadata is written. Thus, metadata write requests are expected to be executed quickly with low latency. The device mapper may determine, for example, whether a write command 212 is for data or metadata based on the system table 250 of the file system 211. The system table 250 may store descriptors of data stored by the file system. The device mapper 220 may search the system table 250 to identify a descriptor associated with the data specified in the write request, such as whether the data specified in the write request is for metadata or data. The device mapper 220 may then indicate characteristics of the write command, such as the functional designation of the payload or the expected update frequency of the payload. For example, the device mapper 220 may determine whether the payload represents metadata or data. The device mapper may then associate a tag reflecting this characteristic with the write command.

[0054] In a particular embodiment, the data distribution device mapper 220 may intercept the write request 212. The data distribution device mapper 220 may use the system table 250 to identify characteristics about the payload. For example, the data distribution device mapper 220 may send a query 214 to the file system 211 to determine the characteristics of the payload, such as whether the payload is data or metadata. The file system 211 may provide the payload characteristics 216 (such as a functional designation indicating whether the payload is data or metadata) to the data distribution device mapper 220 in response to the query 214. As another example, the file system 211 may send a read request 224 including a logical address of a previously stored payload to retrieve the previously stored payload. The data distribution device mapper 220 may intercept the read request 224, but in this example, the data distribution device mapper 220 does not identify the payload characteristics of the read request because the payload does not have the read request 224. In another example, the data distribution device mapper 220 may determine whether the payload is a key or a value in a key-value store.

[0055] Once the characteristics of the payload are determined, the data allocation device mapper 220 can attach the attributes describing the characteristics of the payload to the write request. In one embodiment, a tag reflecting the characteristics of the payload is associated with the write request. The data allocation device mapper 220 can set the value of the field in the driver stack. For example, the Linux driver stack has a StreamID field, and the data allocation device mapper 220 can use the StreamID field as a tag to indicate the characteristics of the payload. The Linux driver is programmed to retain and save the StreamID field. That is, once set, for example, when the command passes through the block level and the NVMe driver, the StreamID tag will not be disturbed. Therefore, in some embodiments, the device mapper can set the StreamID tag to specify the type of data in the write command, and the write command can then be forwarded to the memory subsystem together with the StreamID. In the file system instance, setting the streamID to zero can indicate that the payload is for data, and setting the streamID to one can indicate that the payload is for metadata. In the key-value storage instance, setting the streamID to zero can indicate that the payload is for value, and setting the streamID to one can indicate that the payload is for key. There may be other ways to associate a tag with a write request to reflect the characteristics of the payload. The data distribution device mapper 220 or other components of the operating system 210 may send a write request 222 containing attributes describing the characteristics of the payload based on the write request 212 to the memory subsystem 110 via the host interface 230. The data distribution device mapper 220 may send a read request 226 based on the read request 224 to the memory subsystem 110 via the host interface 230.

[0056] Figure 3 A block diagram 300 illustrates an example memory subsystem 110 including a memory zone manager 113 according to some embodiments of the present disclosure. The memory zone manager 113 may store a data allocation table 304, which may associate logical addresses with functional designations or other identifiers that reflect the location of data on a memory device. In one embodiment, the allocation table 304 may be stored in Figure 1 The memory subsystem 110 also includes the local memory 119 of the above reference. Figure 1 The memory device 130 described herein may include a first memory area 320 that may include a set of physical memory blocks corresponding to logical memory blocks of a non-regional namespace 322 (e.g., a non-partitioned namespace as described above). The memory device 130 may also include a second memory area 330 that may include a set of physical memory blocks corresponding to logical memory blocks of a regional namespace 332.

[0057] In one embodiment, the memory zone manager 113 may receive a write command 302 from the host system 120 that specifies a logical address, a tag, and a payload. The memory zone manager 113 may identify a zone of the memory device 130 that stores the payload based on the tag. The tag may indicate characteristics of the payload, such as the functional designation of the data in the payload or the expected update frequency of the data. For example, the tag may indicate whether the payload represents metadata or data, or a key or value. In another example, the tag may indicate whether the data in the payload is expected to be updated frequently, such as at least once within a specified time period (as may be metadata), or whether the data is expected to be stored for a long time with fewer expected updates. As an example, frequently updated data may be updated once per second, while less frequently updated data may be updated every 30 seconds.

[0058] In a particular embodiment, the memory zone manager 113 may determine in which of the memory zones 320, 330 of the memory device 130 to store the payload based on the tag. If the tag indicates that the payload is for metadata (or a key of a key-value pair, or its expected frequent update), the memory zone manager 113 may determine that the identified memory zone in which the payload will be stored is the first memory zone 320. As an example, the first memory zone 320 may include a relatively small capacity memory with low latency (such as TLC or SLC NAND). Alternatively, if the tag indicates that the payload is for data (or a value of a key-value pair, or its expected long-term storage), the memory zone manager 113 may determine that the identified memory zone in which the payload will be stored is the second memory zone 330. As an example, the second memory zone 330 may include a larger capacity, less performance-dependent memory (such as QLC NAND). The larger capacity memory device may be block-oriented and may have a higher latency than the low latency memory device. In addition, the low latency memory device may be byte-oriented and may have a smaller capacity than the high capacity memory device. That is, a low-latency memory device for storing frequently updated data may be a single-level or three-level cell memory, while a high-capacity memory device for storing less frequently updated data may be a memory with a higher number of bits per cell (e.g., a four-level cell memory). The identified memory areas may be configured as corresponding namespaces. For example, a first memory area 320 may be configured as a non-regional (e.g., conventional) namespace 322, and a second memory area 330 may be configured as a regional namespace 332. Due to the correspondence between the memory areas 320, 330 and the namespaces 322, 332, the memory areas 320, 330 or the namespaces 322, 332 may be used to address the memory in the areas 320, 330.

[0059] If the identified zone is the first memory zone 320, the memory zone manager 113 may write the payload to the first memory zone 320 (arrow 306). In this case, the payload is stored as host metadata 324 at a location in the first memory zone 320 based on a specified logical block address (which can be converted to a physical block address by the memory subsystem 110). Alternatively, if the identified zone is the second memory zone 330, the memory zone manager 113 may write the payload to the second memory zone 330 (arrow 312). In this case, the payload is stored as host data 334 at a location in the second memory zone 330 based on a specified logical block address (which can be converted to a physical block address by the memory subsystem 110). In another example, there may be multiple zone namespaces, and if the identified zone is the second memory zone 330, the payload may be stored in the zone namespace specified by the namespace identifier in the logical address of the write command 302. That is, the destination region namespace may be a namespace different from the region namespace 332 , which may be understood as a default region namespace 332 that may be overwritten by the region namespace specified in the logical address of the write command 302 .

[0060] In another example, because the first memory area may store host data 326 in addition to host metadata 324, the write command 302 may include host data stored in the first memory area 320 by the memory area manager 113 (e.g., based on characteristics other than the functional designation) because the functionally designated payload having the host data is stored in the second memory area 330.

[0061] The memory zone manager 113 may update the data allocation table 304 by associating the logical address in the write command 302 with a tag (e.g., a functional designation) from the write command 302 or other indication of the identified zone to which the payload is written. The indication of the zone may be, for example, an identifier associated with the identified zone (e.g., "1" or "2"), an identifier associated with the identified namespace (e.g., "non-partition" or "region"), or a characteristic of the payload (e.g., a designation of "metadata" or "data").

[0062] In one embodiment, the memory zone manager 113 may receive a read command 310 specifying a logical address from the host system 120. The memory zone manager 113 may identify a zone of the memory device 130 from which to retrieve the data requested by the read command based on the logical address. The memory zone manager 113 may retrieve an indication of the zone where the requested data is located from the data allocation table 304, for example, by searching the data allocation table 304 for the logical address specified in the read command 310. If the memory zone manager 113 stores data at the logical address, then the indication of the data for the zone is associated with the logical address in the allocation table. The memory zone manager 113 may retrieve the data by identifying which of the memory zones 320, 330 corresponds to the indication of the zone. For example, if the indication of the zone is a zone identifier, such as "1" or "2", then the corresponding zone may be identified based on the zone identifier. As another example, if the indication of the zone is a namespace identifier (e.g., "non-partition" or "region"), then the corresponding one of the namespaces 322, 332 may be identified based on the namespace identifier. As another example, if the indication of the zone is a characteristic of the payload (e.g., a designation of "metadata" or "data"), then a corresponding one of the zones 320, 330 (or namespaces 322, 332) can be identified based on the characteristics of the payload (e.g., the first memory zone 320 corresponds to the designation "metadata" and the second memory zone 330 corresponds to the designation "host data").

[0063] The memory zone manager 113 may retrieve data from the logical block address portion of the logical address of the identified one of the memory zones 320, 330 (or the identified one of the namespaces 322, 332 corresponding to the respective zones 320, 330). If the identified zone is the first memory zone 320, the memory zone manager 113 may retrieve host metadata 324 at the specified logical block address from the first memory zone 320 (arrow 308) and send the retrieved host metadata 324 to the host system 120 (arrow 316). Alternatively, if the identified zone is the second memory zone 330, the memory zone manager 113 may retrieve host data 334 at the specified logical block address from the second memory zone 330 (arrow 314) and send the retrieved host data 334 to the host system 120 (arrow 316). In another example, because the first memory area may store host data 326 in addition to host metadata 324, the first memory area may contain the host data 326 at the specified logical block address, in which case the host data 326 may be retrieved from the first memory area 320 (arrow 308) and returned to the host system 120 (arrow 316).

[0064] Figure 44 is a flow chart of an example method 400 implemented by a host system for marking a write request to indicate a functional designation of a payload according to some embodiments of the present disclosure. The method 400 may be performed by processing logic, which may include hardware (e.g., a processing device, a circuit, dedicated logic, programmable logic, microcode, hardware of a device, an integrated circuit, etc.), software (e.g., instructions running or executed on a processing device), or a combination thereof. In some embodiments, the method 400 is performed by Figure 2 The data distribution device mapper 220 of the embodiment of the present invention is executed. Although it is shown in a specific sequence or order, unless otherwise specified, the order of the process can be modified. Therefore, the illustrated embodiment should be understood as an example only, and the illustrated process can be performed in different orders, and some processes can be performed in parallel. In addition, one or more processes can be omitted in various embodiments. Therefore, not all processes are required in each embodiment. Other process flows are possible.

[0065] At operation 410, processing logic receives a write request from a file system that includes a payload. The write request may also include a logical address to which the payload is to be written. The write request may alternatively be received from a key-value store or other application. At operation 420, the processing device uses a data structure associated with the file system (or key-value store) to determine the functional designation (or other characteristics) of the payload. The data structure associated with the application may be a system table that describes the payload. For example, a file system system table may describe whether the payload is for data or metadata. As another example, in a key-value store instance, a key-value store system table may describe whether the payload is for a key or for a value. The data structure associated with the application is not limited to these examples.

[0066] At operation 430, processing logic associates a tag reflecting the functional designation (or other characteristic) of the payload with the write request. The functional designation of the data in the payload, such as whether the data in the payload represents metadata or data, or a key or a value. Alternatively or in addition, another characteristic of the payload may represent an expected update frequency of the data in the payload. In one embodiment, the tag associated with the write request may be part of a driver stack. For example, as described above, the tag may be a StreamID in the Linux driver stack.

[0067] At operation 440, processing logic issues a write command to the memory subsystem. The write command includes a payload and a tag, and may also include a logical address received in the write command. The memory subsystem may be an SSD, as described above. The memory subsystem may include, for example, one or more single-level or three-level cell storage device types and one or more four-level cell storage device types.

[0068] Figure 51 is a flow chart of an example method 500 implemented by a memory subsystem controller for executing a tagged write command to write a payload to an appropriate memory region according to some embodiments of the present disclosure. The method 500 may be performed by processing logic, which may include hardware (e.g., a processing device, a circuit, dedicated logic, programmable logic, microcode, hardware of a device, an integrated circuit, etc.), software (e.g., instructions running or executed on a processing device), or a combination thereof. In some embodiments, the method 500 is performed by Figure 1 The memory area manager 113 of the embodiment of the present invention is executed. Although shown in a specific sequence or order, unless otherwise specified, the order of the process can be modified. Therefore, the illustrated embodiments should be understood as examples only, and the illustrated processes can be performed in a different order, and some processes can be performed in parallel. In addition, one or more processes can be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are possible.

[0069] At operation 510, processing logic receives a write command that includes a payload and a functional designation (or other characteristic) of the payload. The functional designation of the data in the payload may indicate whether the data in the payload represents metadata or data in a file system, or a key or value of a key-value pair. The functional designation may also be understood to indicate whether the payload contains data that can be written sequentially. Alternatively or in addition, another characteristic of the payload may indicate an expected update frequency of the data in the payload. The write command may also include a logical address to be written to the payload.

[0070] At operation 520, processing logic identifies a corresponding one of the first region or the second region of the memory device based on the functional designation of the payload. The second region may be configured as a regional namespace for storing sequentially writable data. Figure 3 As described, if the processing device determines that the functional designation of the data in the payload is metadata (or a key of a key-value pair), the processing device may identify a first region of a memory device for storing the payload. If the processing device determines that the functional designation of the payload is data (or a value of a key-value pair), the processing device may identify a second region of a memory device for storing the payload. At operation 530, the processing logic stores the payload in the identified corresponding first or second memory region of the memory device. At operation 540, the processing logic updates the data allocation table to associate the logical address with the functional designation of the payload (or other indication of the identified first or second memory region).

[0071] Figure 66 is a flow chart of an example method 600 implemented by a memory subsystem controller for executing a tagged write command to write a payload to an appropriate memory region according to some embodiments of the present disclosure. The method 600 may be performed by processing logic, which may include hardware (e.g., a processing device, a circuit, dedicated logic, programmable logic, microcode, hardware of a device, an integrated circuit, etc.), software (e.g., instructions running or executed on a processing device), or a combination thereof. In some embodiments, the method 600 is performed by Figure 1 The memory area manager 113 of the embodiment of the present invention is executed. Although shown in a specific sequence or order, unless otherwise specified, the order of the process can be modified. Therefore, the illustrated embodiments should be understood as examples only, and the illustrated processes can be performed in a different order, and some processes can be performed in parallel. In addition, one or more processes can be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are possible.

[0072] At operation 602, processing logic receives a write command including a logical block address, a payload, and a tag indicating whether the payload is designated as metadata. At operation 604, the processing device determines whether the tag indicates that the payload is designated as metadata. If so, then at operation 608, the processing device identifies a first namespace ID corresponding to a first memory area configured as a non-partitioned namespace. For example, the first memory area may include a TLC or SLC NAND memory. At operation 610, the processing device converts the logical block address and the first namespace ID to a physical block address in the first memory area. At operation 612, the processing device writes the payload to the physical block address in the first memory area.

[0073] If operation 604 determines that the flag indicates that the payload is not designated as metadata, then at operation 614, processing logic identifies a second namespace ID corresponding to a second memory area configured as a partitioned namespace. For example, the second memory area may include a QLC NAND memory. At operation 616, the processing device converts the logical block address and the second namespace ID to a physical block address in the second memory area. At operation 618, the processing device writes the payload to the physical block address in the second memory area.

[0074] Figure 7 An example machine of a computer system 700 is illustrated within which a set of instructions for causing the machine to perform any one or more of the methodologies discussed herein may be executed. In some embodiments, the computer system 700 may correspond to a host system (e.g., Figure 1 1) a host system 120 that includes, is coupled to, or utilizes a memory subsystem (e.g., Figure 1The memory subsystem 110 of the controller may be used to execute the operation of the controller (for example, execute the operating system to execute the corresponding Figure 1 In some embodiments, the machine may be connected (e.g., using a network) to other machines. The machine may operate in the capacity of a server or a client machine in a client-server network environment, or in the capacity of a peer machine in a peer-to-peer (or distributed) network environment, or as a server or a client machine in a cloud-based computing infrastructure or environment.

[0075] The machine may be a personal computer (PC), a tablet PC, a set-top box (STB), a personal digital assistant (PDA), a cellular phone, a network appliance, a server, a network router, a switch or a bridge, or any machine capable of executing (sequentially or otherwise) a set of instructions that specify actions to be taken by the machine. In addition, while a single machine is described, the term "machine" should also be construed to include any collection of machines that individually or jointly execute a set (or multiple sets) of instructions to perform any one or more of the methodologies discussed herein.

[0076] The example computer system 700 includes a processing device 702 that communicates with each other via a bus 730, a main memory 704 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM), such as synchronous DRAM (SDRAM) or RDRAM, etc.), a static memory 706 (e.g., flash memory, static random access memory (SRAM), etc.), and a data storage system 718.

[0077] The processing device 702 represents one or more general-purpose processing devices, such as a microprocessor, a central processing unit, etc. More specifically, the processing device can be a complex instruction set computing (CISC) microprocessor, a reduced instruction set computing (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, or a processor that implements other instruction sets, or a processor that implements a combination of instruction sets. The processing device 702 can also be one or more special-purpose processing devices, such as an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA), a digital signal processor (DSP), a network processor, etc. The processing device 702 is configured to execute instructions 726 for performing the operations and steps discussed herein. The computer system 700 may further include a network interface device 708 to communicate via a network 720.

[0078] The data storage system 718 may include a machine-readable storage medium 724 (also referred to as a computer-readable medium) having stored thereon one or more sets of instructions 726 or software embodying any one or more of the methodologies or functions described herein. The instructions 726 may also reside, completely or at least partially, within the main memory 704 and / or within the processing device 702 during execution thereof by the computer system 700, the main memory 704 and the processing device 702 also constituting machine-readable storage media. The machine-readable storage medium 724, the data storage system 718, and / or the main memory 704 may correspond to Figure 1 Memory subsystem 110.

[0079] In one embodiment, instructions 726 include instructions for implementing a method corresponding to a memory device selection component (e.g., Figure 1 113) of the memory area manager 113. Although the machine-readable storage medium 724 is shown as a single medium in the example embodiment, the term "machine-readable storage medium" should be considered to include a single medium or multiple media storing one or more sets of instructions. The term "machine-readable storage medium" should also be considered to include any medium capable of storing or encoding a set of instructions for execution by a machine and causing the machine to perform any one or more of the methods of the present disclosure. Therefore, the term "machine-readable storage medium" should be considered to include, but not limited to, solid-state memory, optical media, and magnetic media.

[0080] Some portions of the previous detailed description have been presented in terms of algorithms and symbolic representations of operations on data bits within a computer memory. These algorithmic descriptions and representations are the means by which those skilled in the art of data processing use the substance of their work to most effectively communicate to other skilled in the art. An algorithm is here and generally considered to be a self-consistent sequence of operations that result in a desired result. An operation is an operation that requires physical manipulation of physical quantities. These quantities are typically, but not necessarily, in the form of electrical or magnetic signals that can be stored, combined, compared, and otherwise manipulated. Sometimes, primarily for general reasons, it has proven convenient to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, etc.

[0081] It should be borne in mind, however, that all of these and similar terms are to be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. The present disclosure may refer to the actions and processes of a computer system or similar electronic computing device that manipulates and transforms data represented as physical (electronic) quantities within a computer system's registers and memories into other data similarly represented as physical quantities within the computer system's memories or registers or other such information storage systems.

[0082] The present disclosure also relates to an apparatus for performing the operations described herein. This apparatus may be specially constructed for the intended purpose, or it may comprise a general purpose computer selectively activated or reconfigured by a computer program stored in the computer. Such a computer program may be stored in a computer-readable storage medium, such as, but not limited to, any type of disk, including floppy disks, optical disks, CD-ROMs and magnetic optical disks, read-only memories (ROMs), random access memories (RAMs), EPROMs, EEPROMs, magnetic or optical cards, or any type of medium suitable for storing electronic instructions, each coupled to a computer system bus.

[0083] The algorithms and displays presented herein are not inherently related to any particular computer or other device. Various general purpose systems may be used with programs according to the teachings herein, or it may prove convenient to construct a more specialized device to perform the method. The structures of a variety of these systems will be presented as set forth in the description below. In addition, the present disclosure is described without reference to any particular programming language. It will be appreciated that the teachings of the present disclosure as described herein may be implemented using a variety of programming languages.

[0084] The present disclosure may be provided as a computer program product or software, which may include a machine-readable medium having stored thereon instructions that can be used to program a computer system (or other electronic device) to perform a process according to the present disclosure. A machine-readable medium includes any mechanism for storing information in a form readable by a machine (e.g., a computer). In some embodiments, a machine-readable (e.g., computer-readable) medium includes a machine (e.g., computer) readable storage medium, such as a read-only memory ("ROM"), a random access memory ("RAM"), a magnetic disk storage medium, an optical storage medium, a flash memory component, etc.

[0085] In the foregoing specification, embodiments of the present disclosure have been described with reference to specific example embodiments thereof. It will be apparent that various modifications may be made to the present invention without departing from the broader spirit and scope of the embodiments of the present disclosure as set forth in the appended claims. Therefore, the description and drawings should be viewed in an illustrative sense rather than a restrictive sense.

Claims

1. A system comprising: File system; as well as A processing device that performs operations including the following: receiving a write command including a payload from the file system; In response to receiving the write command, determining, using the file system, a characteristic of the payload, wherein the characteristic of the payload indicates whether the write command is for data or for metadata; in response to determining the characteristic of the payload, associating a flag reflecting the characteristic of the payload with the write command, wherein the flag indicates whether the payload is data or metadata; as well as The write command including the tag is sent to a memory subsystem, wherein the memory subsystem stores the payload in a corresponding one of a first area or a second area of ​​a memory device, wherein the corresponding one of the first area or the second area is identified based on the tag, and wherein the second area is to store data that can be written sequentially.

2. The system of claim 1 , wherein when the tag corresponds to metadata, the corresponding one of the first zone or the second zone is the first zone, and when the tag corresponds to data, the corresponding one of the first zone or the second zone is the second zone.

3. The system of claim 2, wherein when the tag corresponds to metadata, the memory subsystem stores the payload in the first region of the memory device, and when the tag corresponds to data, the memory subsystem stores the payload in the second region of the memory device. 4 . The system of claim 2 , wherein when the tag corresponds to metadata, the payload comprises random access write data.

5. The system of claim 2, wherein when the tag corresponds to data, the payload comprises sequentially written data.

6. The system of claim 1, wherein the first region comprises at least one of a triple level cell (TLC) memory or a single level cell (SLC) memory, and wherein the second region comprises a quad level cell (QLC) memory.

7. The system of claim 1, wherein the file system comprises a shingled magnetic recording (SMR) file system.

8. The system of claim 1, wherein the write command further comprises a logical address, the operation further comprising: A data allocation table is updated to associate the logical address with a functional designation of the payload, wherein the functional designation of the payload is based on the tag.

9. The system of claim 8, wherein the memory subsystem performs operations comprising: receiving a read command including a logical address; identifying, using the data allocation table, a functional designation associated with the received logical address; identifying the corresponding one of the first region or the second region of the memory device based on the functional designation associated with the received logical address; and One or more blocks are retrieved from the corresponding one of the first region or the second region of the memory device.

10. A method comprising: receiving a write command including a payload from a file system; In response to receiving the write command, determining, using the file system, a characteristic of the payload, wherein the characteristic of the payload indicates whether the write command is for data or for metadata; In response to determining the characteristic of the payload, associating a tag reflecting the characteristic of the payload with the write command, wherein the tag indicates whether the payload is data or metadata; and sending the write command including the tag to a memory subsystem, wherein the memory subsystem stores the payload in a corresponding one of a first area or a second area of ​​a memory device, wherein the corresponding one of the first area or the second area is identified based on the tag, and wherein the second area is to store data that can be written sequentially.

11. The method of claim 10, wherein the write command further comprises a logical block address, and the memory subsystem performs operations comprising: responsive to determining that the tag indicates that the payload is designated as metadata, identifying a first namespace identifier corresponding to the first region of the memory device, wherein the first region is configured as a non-partitioned namespace; converting the logical block address and the first namespace identifier to a physical block address in the first region of the memory device; and The payload is written to the physical block address in the first region of the memory device.

12. The method of claim 11, wherein the memory subsystem performs operations further comprising: responsive to determining that the tag indicates that the payload is designated as data, identifying a second namespace identifier corresponding to the second region of the memory device, wherein the second region is configured as a partitioned namespace; converting the logical block address and the second namespace identifier to a physical block address in the second region of the memory device; and The payload is written to the physical block address in the second region of the memory device.

13. The method of claim 10, wherein when the tag indicates that the payload is designated as data, the payload comprises sequential write data, and wherein when the tag indicates that the payload is designated as metadata, the payload comprises random access write data.

14. The method of claim 10, wherein the first region comprises at least one of a triple level cell (TLC) memory or a single level cell (SLC) memory, and wherein the second region comprises a quad level cell (QLC) memory.

15. A non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device, cause the processing device to perform operations comprising: receiving a write command including a payload from a file system; In response to receiving the write command, determining, using the file system, a characteristic of the payload, wherein the characteristic of the payload indicates whether the write command is for data or for metadata; in response to determining the characteristic of the payload, associating a flag reflecting the characteristic of the payload with the write command, wherein the flag indicates whether the payload is data or metadata; as well as The write command including the tag is sent to a memory subsystem, wherein the memory subsystem stores the payload in a corresponding one of a first area or a second area of ​​a memory device, wherein the corresponding one of the first area or the second area of ​​the memory device is identified based on the tag, and wherein the second area is to store data that can be written sequentially.

16. The non-transitory computer-readable storage medium of claim 15, wherein when the tag corresponds to metadata, the corresponding one of the first zone or the second zone is the first zone, and when the tag corresponds to data, the corresponding one of the first zone or the second zone is the second zone.

17. The non-transitory computer-readable storage medium of claim 16, wherein when the tag corresponds to metadata, the memory subsystem stores the payload in the first region of the memory device, and when the tag corresponds to data, the memory subsystem stores the payload in the second region of the memory device.

18. The non-transitory computer-readable storage medium of claim 15, wherein the first region comprises at least one of triple level cell (TLC) memory or single level cell (SLC) memory, and wherein the second region comprises quad level cell (QLC) memory.

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