Apparatus, system, and method for refresh mode

Abstract

This application relates to devices, systems, and methods for refresh modes. A memory can need to perform a target refresh operation to refresh 'victim' word lines that are close to 'aggressor' word lines that are frequently accessed. To refresh the victims at a high enough rate, multiple victims can need to be refreshed as part of the same refresh operation. However, certain word lines (e.g., word lines in the same section or adjacent sections of the memory) cannot be refreshed together. The memory can have a section comparator that can check stored aggressor addresses and can provide a signal in the absence of two stored addresses that can be refreshed together. Based in part on the signal, the memory can activate one of several different refresh modes that can control the type of refresh operation performed in response to a refresh signal.

Description

Technical Field

[0001] This disclosure generally relates to semiconductor devices, such as semiconductor memory devices. Background Technology

[0002] The semiconductor memory device may include several memory cells for storing information. The stored information may be encoded as binary data, and each memory cell may store a single bit of the information. The information in the memory cells may decay over time. To prevent information loss, the memory may periodically refresh the information in the memory cells. Summary of the Invention

[0003] According to embodiments of this disclosure, an apparatus is provided. The apparatus includes: a memory array comprising a plurality of segments; an intruder detector configured to store one or more addresses; a segment comparator configured to provide an active command signal when at least two of the one or more addresses stored in the intruder detector are located in different non-adjacent segments of the plurality of segments; and a theft rate control circuit configured to activate a first refresh mode when the control signal is at an inactive level and to activate a second refresh mode when the control signal is at the active level. Each of the one or more addresses is associated with one of the plurality of segments.

[0004] According to another embodiment of this disclosure, an apparatus is provided. The apparatus includes: a memory array including a plurality of word lines, each associated with a row address; and refresh control circuitry configured to store a plurality of row addresses and determine whether at least two of the stored plurality of row addresses can be refreshed simultaneously, configured to simultaneously provide a first target refresh address and a second target refresh address if a first target refresh address and a second target refresh address, each based on a different one of the stored plurality of row addresses, can be refreshed simultaneously, and configured to provide the first target refresh address and then provide the second target refresh address if the first target refresh address and the second target refresh address cannot be refreshed simultaneously.

[0005] According to another embodiment of this disclosure, a method is provided. The method includes: storing a plurality of row addresses; activating a control signal when at least two of the stored row addresses do not represent word lines that can be refreshed simultaneously; generating a first refresh address based on a first of the stored row addresses; generating a second refresh address based on a second of the stored row addresses; and simultaneously refreshing a first word line associated with the first refresh address and a second word line associated with the second refresh address as part of a target refresh operation when the control signal is not active, and sequentially refreshing the first word line and the second word line as part of corresponding first and second target refresh operations when the control signal is active. Each of the stored row addresses is associated with a word line of a memory array. Attached Figure Description

[0006] Figure 1 This is a block diagram of a semiconductor device according to an embodiment of the present disclosure.

[0007] Figure 2 This is a block diagram of a memory array according to some embodiments of the present disclosure.

[0008] Figure 3 This is a block diagram of a refresh control circuit according to some embodiments of the present disclosure.

[0009] Figure 4 This is a block diagram of the memory portion of a refresh control circuit according to some embodiments of the present disclosure.

[0010] Figure 5 This is a state diagram of the refresh mode of a memory according to some embodiments of the present disclosure.

[0011] Figure 6 This is a timing diagram of different refresh modes according to some embodiments of this disclosure.

[0012] Figure 7 This is a state diagram of a memory having a refresh management mode according to some embodiments of the present disclosure.

[0013] Figure 8 This is a timing diagram of different refresh modes according to some embodiments of this disclosure.

[0014] Figure 9 This is a flowchart of a method according to some embodiments of the present disclosure. Detailed Implementation

[0015] The following description of certain embodiments is exemplary in nature and is in no way intended to limit the scope of this disclosure or its application or use. In the following detailed description of embodiments of the systems and methods of the invention, reference is made to the accompanying drawings, which form a part of this document, and the drawings are illustrated by describing specific embodiments in which the described systems and methods can be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the currently disclosed systems and methods, and it should be understood that other embodiments may be utilized, and structural and logical changes may be made without departing from the spirit and scope of this disclosure. Furthermore, for clarity, detailed descriptions of certain features will not be elaborated where they would be obvious to those skilled in the art, so as not to obscure the description of embodiments of this disclosure. Therefore, the following detailed description should not be construed in a limiting sense, and the scope of this disclosure is limited only by the appended claims.

[0016] A memory device may include a memory array having a plurality of memory cells, each memory cell located at the intersection of word lines (rows) and digital lines (columns). Information may be stored in the memory cells (e.g., as charge on a capacitive element). The information may decay over time. The memory may refresh the memory cells to restore the value of the information stored therein. For example, the memory may enter a self-refresh mode, in which the memory is refreshed row by row. For example, a first group of rows may be refreshed, then the next group of rows, and so on. Refreshing one or more rows in such a sequence may be called an automatic refresh operation. The refresh rate of the rows may be based on the information decay rate, and the memory may operate through an automatic refresh operation sequence so that information is not lost.

[0017] Certain conditions can increase the rate at which information decays in memory. For example, if a particular row is repeatedly accessed, memory cells in nearby rows may decay at an increased rate. Therefore, it is important to identify the repeatedly accessed 'aggressor' row so that nearby 'victim' rows can be refreshed as part of the target refresh. During self-refresh mode, memory can perform automatic refresh and target refresh operations in combination to ensure that victim rows are refreshed in a timely manner, since the information within them may decay in other ways before they are refreshed as part of the automatic refresh operation. However, this can introduce trade-offs, as the target refresh operation may consume time slots originally allocated to the automatic refresh operation.

[0018] To save time, memory can refresh multiple rows simultaneously. However, some addresses cannot be refreshed as part of the same refresh operation. While the addresses used as parts of an automatic refresh operation are predictable and can be selected to allow multiple addresses to be refreshed concurrently, the addresses involved in the target refresh are often unpredictable and may contain addresses that cannot be refreshed together. For example, memory can identify victim rows that cannot be refreshed simultaneously (e.g., because they are located in the same memory segment). Importantly, dynamically reallocating the types of refreshes performed by memory can accommodate different memory conditions.

[0019] This disclosure relates to apparatus, systems, and methods for refresh modes. The memory may have different refresh modes. In response to a refresh signal, the memory may perform different numbers and types of refresh operations based on the active refresh mode. For example, a first mode may include a target refresh operation that refreshes more than one victim address at a time, while a second mode may include a target refresh operation that refreshes only one victim address at a time. The memory may monitor various indicators of the memory to determine which refresh mode to activate. For example, refresh control circuitry may track whether identified attacker lines are in the same segment of the memory. If they are not in the same segment, the first refresh mode can be used. If they are in the same segment and cannot be refreshed simultaneously, the second refresh mode can be used.

[0020] In some embodiments, the memory may include additional refresh modes that help ensure both automatic refresh operations and targeted refresh operations are performed at a sufficiently high rate to prevent information decay. For example, the memory may include a counter that changes based on the refresh mode in operation. Based in part on the counter, additional refresh modes, such as those in which only automatic refresh operations are performed, can be activated.

[0021] Figure 1 This is a block diagram of a semiconductor device according to an embodiment of the present disclosure. Semiconductor device 100 may be a semiconductor memory device, such as a DRAM device integrated on a single semiconductor chip.

[0022] Semiconductor device 100 includes memory array 118. Memory array 118 is shown as containing multiple memory banks. Figure 1 In one embodiment, the memory array 118 is shown to include eight memory banks BANK0 to BANK7. In other embodiments, the memory array 118 may include more or fewer memory banks. Each memory bank includes multiple word lines WL, multiple bit lines BL, and multiple memory cells MC arranged at the intersections of the multiple word lines WL and the multiple bit lines BL. The selection of word lines WL is performed by row decoder 108, and the selection of bit lines BL is performed by column decoder 110. Figure 1In this embodiment, row decoder 108 includes a corresponding row decoder for each memory bank, and column decoder 110 includes a corresponding column decoder for each memory bank. Bit line BL is coupled to a corresponding sense amplifier (SAMP). Read data from bit line BL is amplified by the sense amplifier SAMP and transmitted to read / write amplifier 120 via complementary local data line (LIOT / B), transmission gate (TG), and complementary main data line (MIOT / B). Conversely, write data is transmitted to the sense amplifier SAMP via complementary main data line MIOT / B, transmission gate TG, and complementary local data line LIOT / B, and written to the memory cell MC coupled to bit line BL.

[0023] The semiconductor device 100 may use multiple external terminals, including: a command and address (C / A) terminal coupled to the command and address bus to receive command and address and CS signals; a clock terminal for receiving clock CK and / CK; a data terminal DQ for providing data; and a power supply terminal for receiving power supply potentials VDD, VSS, VDDQ and VSSQ.

[0024] The clock terminal supplies external clocks CK and / CK to input circuit 112. These external clocks are complementary. Input circuit 112 generates an internal clock ICLK based on CK and / CK. The ICLK clock is provided to command decoder 106 and to internal clock generator 114. Internal clock generator 114 provides various internal clocks LCLK based on the ICLK clock. The LCLK clock can be used for timing operations of various internal circuits. The internal data clock LCLK is provided to input / output circuit 122 to time the operation of circuits contained within input / output circuit 122, for example, to a data receiver to time the reception of written data.

[0025] The power supply terminals are supplied with power potentials VDD and VSS. These power potentials VDD and VSS are supplied to the internal voltage generator circuit 124. The internal voltage generator circuit 124 generates various internal potentials VPP, VOD, VARY, VPERI, etc., based on the power potentials VDD and VSS supplied to the power supply terminals.

[0026] The power supply terminals are also supplied with power potentials VDDQ and VSSQ. Power potentials VDDQ and VSSQ are supplied to the input / output circuit 122. In embodiments of this disclosure, the power potentials VDDQ and VSSQ supplied to the power supply terminals may be the same potentials as the power potentials VDD and VSS supplied to the power supply terminals. In another embodiment of this disclosure, the power potentials VDDQ and VSSQ supplied to the power supply terminals may be different potentials from the power potentials VDD and VSS supplied to the power supply terminals. The power potentials VDDQ and VSSQ supplied to the power supply terminals are used in the input / output circuit 122 so that power supply noise generated by the input / output circuit 122 does not propagate to other circuit blocks.

[0027] The C / A terminal may supply a memory address. The memory address supplied to the C / A terminal is transmitted to the address decoder 104 via the command / address input circuit 102. The address decoder 104 receives the address and supplies the decoded row address XADD to the row decoder 108 and the decoded column address YADD to the column decoder 110. The address decoder 104 may also supply a decoded bank address BADD, which indicates a bank in the memory array 118 containing the decoded row address XADD and column address YADD. Commands may be supplied to the C / A terminal. Examples of commands include timing commands for controlling the timing of various operations, access commands for accessing memory (e.g., read commands for performing read operations and write commands for performing write operations), and other commands and operations. Access commands may be associated with one or more row addresses XADD, column addresses YADD, and bank addresses BADD used to indicate the memory cell to be accessed.

[0028] Commands can be provided as internal command signals to command decoder 106 via command / address input circuitry 102. Command decoder 106 includes circuitry to decode the internal command signals to generate various internal signals and commands for performing operations. For example, command decoder 106 can provide row command signals for selecting word lines and column command signals for selecting bit lines.

[0029] Device 100 can receive access commands as read commands. When a read command is received and is promptly supplied to the bank address, row address, and column address, read data is read from the memory cells in memory array 118 corresponding to the row and column addresses. The read command is received by command decoder 106, which provides an internal command to provide the read data from memory array 118 to RW amplifier 120, which then provides the data to I / O circuitry 122 along the global data bus. The read data is output to the outside of device 100 from data terminal DQ via input / output circuitry 122.

[0030] Device 100 can receive access commands as write commands. When a write command is received and is supplied to the bank address, row address, and column address in a timely manner, write data is supplied to RW amplifier 120 via the DQ terminal. The write data is written to memory cells in memory array 118 corresponding to the bank address, row address, and column address. The write command is received by command decoder 106, which provides an internal command to cause the write data to be received by the data receiver in input / output circuit 122. A write clock may also be provided to an external clock terminal to time the reception of write data by the data receiver in input / output circuit 122.

[0031] The device 100 may also receive commands that cause it to perform one or more refresh operations as part of a self-refresh mode. In some embodiments, the self-refresh mode command may be externally issued to the memory device 100. In some embodiments, the self-refresh mode command may be periodically generated by components of the device. In some embodiments, a refresh signal AREF may also be activated when an external signal indicates a self-refresh enters a command. The refresh signal AREF may be a pulse signal activated when the command decoder 106 receives a signal indicating entry into the self-refresh mode. The refresh signal AREF may be activated immediately after the command input and may thereafter be activated cyclically according to a desired internal timing. The refresh signal AREF can be used to control the timing of refresh operations during the self-refresh mode. Therefore, refresh operations may continue automatically. A self-refresh exit command may stop the automatic activation of the refresh signal AREF and return it to an idle state. The refresh signal AREF is supplied to the refresh control circuitry 116.

[0032] In response to each pulse of the refresh signal AREF, several word lines of the memory array 118 can be refreshed. The refresh control circuitry 116 can generate several internal 'pumps' associated with each pulse of the refresh signal AREF. Each pump can be accompanied by one or more refresh addresses RXADD, which indicate which word line(s) should be refreshed as part of that pump. For example, the refresh control circuitry 116 can receive the refresh signal AREF and can issue two pumps. The first pump can be associated with a first refresh address RXADD1, and the second pump can be associated with refresh addresses RXADD2 and RXADD3. In some embodiments, each refresh address can be used to indicate more than one word line. Continuing with the previous example, the first refresh address RXADD1 can cause four word lines to be refreshed, while the second refresh address RXADD2 and the third refresh address RXADD3 can each cause one word line to be refreshed. Different pumps (and refresh addresses) can be associated with automatic refresh or targeted refresh operations.

[0033] An automatic refresh operation may involve refreshing a sequence of word lines (e.g., WL0, WL1, WL2, ... WLn, WL0). The refresh address published as part of the automatic refresh operation may be referred to as the automatic refresh address. A targeted refresh operation may involve selecting specific word lines for refresh. For example, refresh control circuitry 116 may track accesses to memory array 118 to identify offender rows (and / or potential offender rows) and may calculate the addresses of victims of those offenders to be refreshed as part of the targeted refresh operation. For simplicity, the term "offender address" will be used to refer to addresses identified by the memory as offenders, regardless of whether they are actual or potential offenders.

[0034] The refresh control circuit 116 can perform a mix of automatic refresh operations and targeted refresh operations. The type of refresh operation performed can be based on how the refresh address RXADD is generated. Therefore, the first surge can be an automatic refresh operation, the second surge can be a targeted refresh operation, and so on. The refresh control circuit 116 can determine how many surges to generate and how to distribute the surges among different refresh operations. The refresh control circuit 116 can activate one or more different refresh modes, which controllably manage the number and type of refresh operations performed in response to the activation of the refresh signal AREF. The different types of refresh modes that can be activated will be discussed in more detail herein. The refresh control circuit 116 may include logic (e.g., a state machine) to determine which refresh mode is in operation. After performing a refresh operation in response to the activation of the refresh signal AREF, the refresh control circuit 116 can use one or more criteria to determine whether the same or different refresh modes should be activated.

[0035] When certain refresh modes are in operation, the refresh control circuit 116 may issue two refresh addresses as part of each surge during a target refresh operation. However, there may be situations where this is not possible because the two refresh addresses are associated with word lines that cannot be refreshed simultaneously. For example, the two addresses may represent word lines in the same (or adjacent) segments. The refresh control circuit 116 may store the intruder word lines in the intruder detector circuit. The refresh control circuit 116 may check whether there are at least two stored intruders that can be refreshed simultaneously (e.g., because they are in different non-adjacent segments). If so, a first refresh mode may be activated, in which victims based on those addresses are refreshed as part of the same refresh surge. If not, a second refresh mode may be activated, in which victims based on those addresses are refreshed sequentially.

[0036] Figure 2 This is a block diagram of a memory array according to some embodiments of the present disclosure. In some embodiments, the memory array 200 may be included in... Figure 1In memory array 118. Memory array 200 is a simplified view of the memory array, which helps to illustrate the problem of multiple word lines in the same (or adjacent) segments being refreshed as part of the same refresh operation.

[0037] Memory array 200 comprises three segments: segment 0 (210), segment 1 (220), and segment 2 (230). Each segment contains several memory cells at the intersection of digital line 203 and word lines such as word lines 212, 222, 224, and 232. For clarity, only a limited number of segments, digital lines, and word lines are shown. Other exemplary embodiments may have more (or fewer) segments, digital lines, and word lines.

[0038] Digital lines can be coupled to a set of sense amplifiers that can be shared between different neighboring segments. For example, sense amplifier 204 is shared by both segment 0 210 and segment 1 220, while sense amplifier 206 is shared by both segment 1 220 and segment 2230. During refresh operation, a word line indicated by the refresh address RXADD can be activated. Digital line 203 can read information from the activated word line to the sense amplifier. The sense amplifier can use an inactive digital line 203 in a neighboring segment as a reference voltage. The sense amplifier can determine the value read along the active digital line based on a comparison of the read voltage with the reference voltage, and can then restore the initial value of the memory cell along the digital line back to the memory cell at the intersection with the active word line.

[0039] It may not be possible to refresh two word lines in the same segment simultaneously, such as word lines 222 and 224. A digital line intersecting word line 222 may also intersect word line 224. Therefore, sense amplifiers 204 and 206 cannot simultaneously read and write data to both word lines 222 and 224.

[0040] It may also be impossible to refresh two word lines in different but adjacent segments simultaneously because a shared sense amplifier cannot be used to read data from digital lines in two coupled segments at the same time. For example, if the refresh address indicates word line 222, information can be read out along digital line 203 to sense amplifiers 204 and 206. Sense amplifier 204 can use digital line 203 in segment 210 as a reference, while sense amplifier 206 can use digital line 203 in segment 230 as a reference. Therefore, although only word line 222 is active in segment 220, the digital lines in adjacent segments 210 and 230 are used to provide reference voltages to sense amplifiers 204 and 206. Therefore, when word line 222 is refreshed, word lines 212 or 232 may not be refreshed simultaneously. It should be noted that since word lines 212 and 232 are in non-adjacent segments 210 and 230 respectively and do not share a sense amplifier, it is possible to refresh the word lines simultaneously.

[0041] Return to reference Figure 1 The refresh control circuit 116 may include a segment comparator that checks whether the stored addresses identified as aggressors are in the same segment (because the victims to be refreshed will also be in the same segment as the aggressors). The segment comparator may also check whether the addresses are in neighboring segments. The value of the row address can be used to check segment similarity / proximity. For example, a portion of the row address (e.g., a subset of the bits of the row address) may indicate which segment the word line associated with that row address is in. If multiple aggressor addresses associated with word lines in different (non-neighboring) segments are stored in the aggressor detector, the refresh control circuit 116 may provide multiple refresh addresses as part of a target refresh operation. If all aggressors are in the same (or neighboring) segments, the refresh control circuit 116 may provide a single refresh address as part of each target refresh operation. For example, addresses in the aggressor detector may all be associated with word lines in segments adjacent to at least one other address in the aggressor detector, but as long as at least one pair is not adjacent to each other, the victims of that pair may be refreshed together. For example, if the memory stores addresses for word lines 212, 222, 224, and 232, then word lines 212 and 232 can be refreshed simultaneously, even if all those addresses are associated with word lines in at least one other neighboring segment.

[0042] Figure 3 This is a block diagram of a refresh control circuit according to some embodiments of the present disclosure. In some embodiments, the refresh control circuit 300 may be included in... Figure 1 In the refresh control circuit 116.

[0043] The refresh control circuit 300 may have a first portion 310 shared among the memory banks and individual memory bank logic 320, each memory bank logic being compatible with one of the memory banks in the memory array (e.g., Figure 1 (118) is associated with it. In Figure 3 In this example, there may be 32 memory banks (e.g., Bank0 to Bank31), but in other example embodiments, more or fewer memory banks may be used. Figure 4 The memory logic 320 is described in more detail below.

[0044] The refresh control circuit 300 can receive activation (e.g., a pulse) of the refresh signal AREF. Based on the currently operating refresh mode, the central portion 310 of the refresh control circuit 300 provides several surge signals to the memory logic portion 320, which in turn provides refresh addresses to the row decoders of its respective memory. For example, the central portion 310 can provide a signal Rfsh indicating that an automatic refresh operation should be performed and a signal RHR indicating that a target refresh operation should be performed. In some embodiments, the memory portion 320 can jointly receive both signals Rfsh and RHR. Thus, each memory can jointly perform the same number of surges and the same type of refresh operation based on which refresh mode is activated by the central portion 310.

[0045] The central portion 310 includes a dynamic steal rate control circuit 312, which determines which refresh mode is currently in operation. For example, the dynamic steal rate control circuit 312 can act as a state machine and can enable one of several different refresh modes. Figure 3 In this example, the refresh control circuit 300 has four different modes (e.g., modes 0 to 3). [The text abruptly ends here.] Figures 5 to 6 The details of the different refresh modes are discussed in more detail. The refresh mode in operation can partially determine the number and type of surge signals Rfsh and RHR provided to the memory bank section 320.

[0046] The dynamic steal rate control circuit 312 provides enable signals to indicate which refresh mode the device is currently in. For example, the dynamic steal rate control circuit 312 may have enable signals Mode0En, Mode1En, Mode2En, and Mode3En for each of the modes. These signals may be binary signals that are high when the mode is enabled (while the other enable signals may be low). Other schemes may be used for the enable signals in other example embodiments. For example, a single multi-bit enable signal may be used, which has different states for different modes (e.g., a two-bit signal with four states, one state for each mode).

[0047] The dynamic steal rate control circuit 312 can use various methods to determine which refresh mode to enable. For example, the dynamic steal rate control circuit 312 may include a steal rate control counter 314. The steal rate control counter 314 manages a steal rate control count (SRCC) value used to track insufficient auto-refresh operations. For example, if the memory enters a refresh mode that primarily performs auto-refresh operations, the steal rate control counter 314 may increase the SRCC value. When the memory enters a refresh mode that primarily performs target refresh operations, the steal rate control counter 314 may decrease the SRCC value. An SRCC value at its minimum (and / or below a threshold) may trigger the activation of a refresh mode that performs more auto-refresh operations. Figure 5 Further details regarding the management of the rate-of-flight (SRCC) control counter 314 are discussed below. The SRCC control counter 314 stores the SRCC value as a binary number. The number of bits used to store the SRCC may be based in part on calculations used to determine which refresh modes should be used at what frequency. In some embodiments, the SRCC may be a 4-bit number. Other SRCC lengths may be used in other embodiments. The length of the SRCC value may be based in part on the desired rate of automatic refresh and target refresh operations.

[0048] The dynamic steal rate control circuit 312 may also receive a SameSecRequestBnk signal from the memory portion 320 of the refresh control circuit 300. The SameSecRequestBnk signal indicates whether any (and which) memory portion 320 holds the address of an intruder that is entirely in the same segment (or entirely in adjacent segments). For example, the SameSecRequestBnk signal may be a multi-bit signal, where a single bit represents each memory portion. The bit for a given memory portion may be active if the memory portion 320 holds an intruder in the same (or adjacent) segment. In some embodiments, the dynamic steal rate control 312 may determine which refresh mode to use based on the SRCC value and whether any bit of the SameSecRequestBnk signal is at a high logic level.

[0049] The central portion 310 of the refresh control circuit 300 may also include a refresh timing control circuit 316. The refresh timing control circuit 316 can manage and provide various internal signals based on refresh modes indicated by refresh mode signals Mode0En to Mode3En. For example, the refresh timing control circuit 316 can receive a refresh signal AREF and generate several timing signals, which can then control the activation of one or more surge signals. For example, the refresh timing control circuit 316 can provide an auto-refresh signal Rfsh and a target refresh signal RHR. The auto-refresh signal Rfsh and the target refresh signal RHR can be jointly provided to the memory logic portion 320. When the signal Rfsh is active (e.g., at a high logic level), it can indicate that an auto-refresh operation should be performed. When the signal RHR is active (e.g., at a high logic level), it can indicate that a target refresh operation should be performed. By managing the timing of when the signals Rfsh and RHR are active, the refresh timing circuit 316 can control how many refresh operations are performed and what type of operation is performed in response to each AREF signal. Then, the storage section 320 can publish a refresh address to its corresponding row decoder to perform the actual refresh operation.

[0050] The behavior of the refresh timing control circuit 316 can be based on which of the mode enable signals Mode0En to Mode3En is active (e.g., based on which refresh mode is active). For example, if the first refresh mode signal Mode0En is active, the refresh timing control circuit 316 can provide a signal Rfsh (e.g., to indicate an auto-refresh operation) and then provide two signals RHR (e.g., to indicate two target refresh operations) in response to the activation of the refresh signal AREF. In some embodiments, the refresh timing control circuit 316 can also generate and provide an auto-refresh address and the signal Rfsh, and can determine which and how many word lines are associated with the auto-refresh address based on the active refresh mode enable signal. In some embodiments, the auto-refresh address can be generated by the memory logic 320, and various additional signals (not shown) can be passed to the memory logic 320 to control which and how many word lines are associated with the auto-refresh address.

[0051] Figure 4 This is a block diagram of the memory bank portion of a refresh control circuit according to some embodiments of the present disclosure. In some embodiments, the memory bank portion 400 may include... Figure 3 In the storage bank portion 320. The storage bank portion 400 may be associated with a single storage bank of the memory array and can be communicated via the row decoder 430 (e.g., Figure 1 The line decoder 108 provides a refresh address to manage refresh operations, and the line decoder can then refresh the line indicated by the refresh address RXADD.

[0052] The memory bank portion 400 may include auto-refresh address control circuitry 420, which can be used to manage auto-refresh addresses. In response to the auto-refresh signal Rfsh being at an active level, the auto-refresh control circuitry 420 can provide an auto-refresh address RXADD. For example, each auto-refresh address may indicate a certain number of word lines (e.g., 4 word lines) that can be refreshed simultaneously. The auto-refresh address RXADD can indicate multiple word lines by truncating a portion of the row address (e.g., a certain number of bits), such that the refresh address indicates multiple word lines. After providing the refresh address RXADD, the auto-refresh address control 420 can update the refresh address to move to the next group of word lines in the word line sequence. For example, the auto-refresh address control circuitry 420 can increment certain bits of the refresh address RXADD to generate the next refresh address. In some embodiments, the auto-refresh address control 420 may be located in the central portion of the refresh control circuitry (e.g., Figure 3 (310)

[0053] The memory section 400 may include various circuitry and structures for detecting intruder addresses and calculating refresh addresses based on the victims of those intruders. For example, the memory section 400 may include intruder detector circuitry. The intruder detector circuitry may store received row addresses XADD and may identify intruders based on the stored row addresses. For example, the intruder detector may include memory structures such as content-addressable memory (CAM) 402. CAM 402 may have several registers, each of which may hold received memory addresses, such as row addresses XADD. Row addresses may be provided along the address bus as part of an access operation to the row associated with that row address XADD. The received row address may be compared with other addresses already stored in CAM 402. If no match is found, the received row address may be stored in CAM 402 (replacing the old address if necessary). If a match is found, the address may be identified as an intruder. In some embodiments, each register in CAM 402 may be associated with a counter that increments when a match is found. The value of the counter can be used to identify the intruder.

[0054] In some embodiments, CAM 402 may receive each address XADD along the row address bus. In some embodiments, CAM 402 may receive a sampling signal, and may receive only the address XADD while the sampling signal is active. In some embodiments, the sampling signal may be activated by random, semi-random, and / or pseudo-random timing.

[0055] CAM 402 can be managed by a steal output control circuit 410. The steal output control circuit 410 determines which addresses stored in CAM 410 should be used to calculate the victim address. The selected victim address may be commonly referred to as the 'seed' address. The steal output control circuit 410 may include output priority control circuitry 412, which can select which addresses stored in CAM 402 should be used as seeds. For example, the steal output control circuit 410 can select the two oldest addresses in CAM 402, or the two addresses most recently matched along the address bus.

[0056] The stealing output control circuit 410 may also include a segment comparator circuit 414. The segment comparator 414 examines addresses in CAM 402 to determine if the addresses in CAM 402 are in the same (or adjacent) segment of the memory. If at least two addresses exist in different non-adjacent segments (and multiple addresses exist in CAM 402), the segment comparator 414 may provide a high logic level signal, SameSecRequest, to the memory. This can be used in part as a signal to put the memory into a refresh mode, in which only a single address is refreshed as part of a target refresh operation. The output priority control 412 may also take into account the results from the segment comparator 414. For example, the output priority control 412 may prioritize finding two addresses in different non-adjacent segments (if such address pairs are available).

[0057] The stealing output control circuit 410 can provide a first seed address and a second seed address from CAM 402 to a first victim calculator 406 and a second victim calculator 407, respectively. Victim address calculators 406 and 407 can determine the addresses of victims (or potential victims) for those seed addresses and then refresh those addresses. In some embodiments, the victim can be based on a word line physically close to the word line represented by the seed address. For example, the victim can be a word line adjacent to the seed address (e.g., R+ / -1). The calculated victim addresses can be stored in a first latch 408 and a second latch 409, respectively. The first latch 408 can hold a first refresh address RXADD1 provided by the first seed address victim calculator 406, and the second latch 409 can hold a second refresh address RXADD2 provided by the second seed address victim calculator 407.

[0058] The stored refresh addresses are provided to the line decoder 430, which can simultaneously refresh the word lines associated with the first refresh address RXADD1 and the second refresh address RXADD2. Two address buses couple refresh control circuitry to the line decoder 430. The line decoder 430 may have different portions for each segment of a given memory bank. Each segment of the line decoder 430 may receive addresses RXADD1 and RXADD2, which together serve as inputs to a multiplexer. Control signals generated within the line decoder 430 determine which of the two addresses RXADD1 and RXADD2 within that segment is used for refreshing. In some embodiments, each segment of the line decoder 430 may have two multiplexers, one for each received address, each multiplexer selecting between providing the received address for refreshing or not providing an address. The decoder for refreshing addresses RXADD1 and RXADD2 can provide command signals to each segment of the line decoder 430. The two multiplexers in each segment can respond to the opposite level of the command signal for that segment, so that only one multiplexer is in operation at a time (e.g., providing an address).

[0059] The steal output control circuit 410 can provide a second seed skip signal, Seed2Skip. When the Seed2Skip signal is at the active level, the line decoder can refresh the first refresh address RXADD1 without refreshing the second refresh address RXADD2. The steal output control circuit 410 can provide the Seed2Skip signal at the active level when there is only one detected intruder that needs to refresh its victim (e.g., if only one address is stored in CAM 402).

[0060] In the target refresh operation, the memory may be in refresh mode, where two addresses are refreshed simultaneously as part of the target refresh operation (e.g., because the SameSecRequestBank signal is inactive for each memory bank). The steal output control circuit 410 may retrieve a first seed address Seed1 and a second seed address Seed2 from CAM 402. Victim calculators 406 and 407 may calculate first and second victim addresses based on the corresponding first and second seeds. For example, the first refresh address RXADD1 may be the R+1 victim of Seed1, and the second refresh address RXADD2 may be the R+1 victim of Seed2. These two refresh addresses may be refreshed by the line decoder 430. Victim calculators 406 and 407 may then provide corresponding third and fourth victim addresses based on the corresponding first and second seed addresses. For example, the first refresh address RXADD1 may now be the R-1 victim of Seed1, and the second refresh address RXADD2 may now be the R-1 victim of Seed2. The line decoder 430 may refresh these two refresh addresses simultaneously. The stealing output control circuit 410 can then retrieve a new seed address from CAM 402 for further refresh operations.

[0061] In an instance target refresh operation, the memory may be in a refresh mode in which only one refresh address is refreshed per pump (e.g., because at least one of the signals SameSecRequestBank is active). The steal control circuitry 410 may retrieve a first seed address Seed1 from CAM 402. The first seed address Seed1 may be provided to a first victim address calculator 406, which may calculate a first refresh address RXADD1 (e.g., it may be R+1 of Seed1) and provide the first refresh address to a first latch 408. A line decoder 430 may then refresh the first refresh address RXADD1. The first victim address calculator 406 may then calculate a second refresh address based on the first seed address Seed1. For example, the refresh address RXADD1 may be updated to the R-1 address of Seed1. The line decoder 430 may then refresh this address. The steal output control 410 may then retrieve one or more new addresses from CAM 402 to be used as seed addresses for subsequent target refresh operations.

[0062] In some embodiments, word lines farther from the seed word line may also be refreshed. For example, the memory may refresh word lines adjacent to the R+ / -1 word line (e.g., the R+ / -2 word line). The R+ / -2 word line may experience a slower decay rate than the R+ / -1 word line and therefore may need to be refreshed less frequently. To mitigate this, the memory may periodically refresh the R+ / -2 word line instead of the R+ / -1 word line. For example, the memory bank portion 400 may include R+ / -2 steal rate control circuitry 404, which provides a signal RHR2en. When the signal RHR2en is active, instead of calculating the R+1 or R-1 victim address, the first victim address calculator 406 and the second victim address calculator 407 may instead calculate the R+2 and R-2 victim addresses.

[0063] The R+ / -2 stealing rate control circuit 404 can count the number of times a target refresh operation is executed (e.g., the number of times the signal RHR is activated), and can provide the signal RHR2en at an operating level based on this count. For example, the signal RHR2en can be active for one of every eight target refresh operations.

[0064] Figure 5 This is a state diagram of a memory refresh mode according to some embodiments of the present disclosure. In some embodiments, state diagram 500 may represent a refresh mode that can be generated by... Figures 1 to 4 Different refresh modes are used by one or more memories (or memory components). For example, state diagram 500 can represent the states of a state machine, such as... Figure 3 The dynamic theft rate control circuit 312.

[0065] Mode 510 indicates checking the rate-of-steal control counter (SRCC) (e.g.) Figure 3 The value of SRCC 314) and the same segment address signal (e.g. Figures 3 to 4 The value of SameSecRequestBnk. Based on these values, the state machine can determine which refresh mode to execute (520 to 550) upon receiving a refresh signal (e.g., AREF). After executing the refresh associated with the determined refresh mode, the state machine can return to the initial mode (510) to determine which refresh mode to use for the next activation of the refresh signal.

[0066] Initial mode 510 can also represent the initial state of the memory system. For example, after a power-on or reset operation of the memory (e.g., indicated by the PwrUpRst signal), the memory may enter initial mode 510 and begin monitoring the SRCC value and the SameSecRequestBnk signal. In some embodiments, the SRCC value may be reset to its initial value (e.g., 0) in response to the PwrUpRst signal.

[0067] If the SameSecRequestBnk signal is low for all banks (e.g., all bank refresh portions contain at least one pair of refresh addresses in different non-adjacent segments) and the SRCC is at its maximum value (or above a threshold), the memory may enter a first refresh mode 520. The first refresh mode 520 may involve performing an automatic refresh operation followed by at least one target refresh operation, wherein multiple target refresh addresses are refreshed together. After performing the refresh operation, the SRCC value may remain at its current (e.g., maximum) value, and the memory may return to its initial state 510.

[0068] If the SameSecRequestBnk signal is low for all banks (e.g., all bank refresh portions contain at least one pair of refresh addresses in different non-adjacent segments) and the SRCC is below its maximum value (or below a threshold), the memory can enter a second refresh mode 530. The second refresh mode 530 can be similar to the first refresh mode 520, except that in the second refresh mode 530, more word lines are refreshed as part of the automatic refresh operation. After performing a refresh operation in response to the refresh signal in the second mode, the SRCC value can be incremented.

[0069] If the SameSecRequestBnk signal has at least one bit at a high logic level (e.g., at least one memory bank does not contain a pair of identified intruders in different non-proximity segments) and the SRCC is at a minimum value (e.g., 0), the memory can enter a third refresh mode 540. In the third refresh mode 540, in response to the refresh signal AREF, the memory can perform an automatic refresh operation, but not a targeted refresh operation. After performing the refresh operation, the SRCC value can be incremented by a certain value. For example, in Figure 5 In this embodiment, the SRCC value can be increased by 7. Different values ​​(and different maximum values ​​of SRCC) can be used to adjust the average number of seed addresses that are refreshed each time the refresh signal AREF is activated.

[0070] If the SameSecRequestBnk signal has at least one bit at a high logic level (e.g., at least one memory bank does not contain a pair of identified intruders in different non-adjacent segments) and the SRCC is above a minimum value (e.g., SRCC > 0), the memory may enter a fourth refresh mode 550. In fourth refresh mode 550, in response to the refresh signal AREF, the memory may perform a target refresh operation but not an automatic refresh operation. In fourth refresh mode 550 (unlike first mode 520 and second mode 530), each target refresh operation may involve refreshing a single refresh address.

[0071] Figure 6These are timing diagrams of different refresh modes according to some embodiments of the present disclosure. Timing diagrams 620 to 650 illustrate different groups of refresh operations that can be performed in response to activation of a refresh signal (e.g., AREF) when the memory is in different refresh modes. In some embodiments, timing diagrams 620 to 650 may represent Figure 5 The corresponding refresh modes are 520 to 550. It should be noted that timing diagrams 620 to 650 may not share the same access time, and may not be scaled proportionally to each other. For example, a refresh operation represented by timing diagram 640 may take longer to complete than a refresh operation represented by timing diagram 650.

[0072] The timing diagram 620 shows the first refresh mode (e.g., Figure 5 The refresh operation (mode 520) is as follows. In response to the activation of the refresh signal, three refresh surges may exist. The first surge is used for automatic refresh operation, and four word lines can be refreshed. The second surge is used for targeted refresh operation. During the first surge, R+1 victims at the first seed address Seed1 and the second seed address Seed2 can be refreshed. The third surge can be used to refresh R-1 victims at addresses Seed1 and Seed2. In some embodiments, when an R+ / -2 refresh is required, the second surge can be used to refresh R+2 victims at addresses Seed1 and Seed2, and the third surge can be used to refresh R-2 victims at addresses Seed1 and Seed2.

[0073] The timing diagram 630 shows the second refresh mode (e.g., Figure 5 The refresh operation of mode 530. Timing diagram 630 is generally similar to timing diagram 620, except that in timing diagram 630, more word lines are refreshed during the first automatic refresh surge. Specifically, during the first surge of timing diagram 630, eight word lines are refreshed as part of the automatic refresh operation.

[0074] The timing diagram 640 shows the third refresh mode (e.g., Figure 5 The refresh operation (mode 540) is as follows. Timing diagram 640 contains two refresh surges. During each refresh surge, 16 word lines are refreshed as part of the automatic refresh operation.

[0075] The timing diagram 650 is shown as the fourth refresh mode (e.g., Figure 5The refresh operation in mode 550 is a portion thereof. Timing diagram 650 includes four refresh surges. Each surge is used to refresh a target refresh operation of a single refresh word line. For example, the first surge can be used to refresh the R+1 victim of the first seed address Seed1. The second surge can be used to refresh the R-1 victim of the first seed address Seed1. The third surge can be used to refresh the R+1 victim of the second seed address Seed2. The fourth surge can be used to refresh the R-1 victim of the second seed address Seed2. In some embodiments, if an R+ / -2 refresh is required, the R+2 or R-2 victim can be refreshed instead.

[0076] Figure 7 This is a state diagram of a memory having a refresh management mode according to some embodiments of the present disclosure. State diagram 700 may be generally similar to... Figure 5 The difference between state diagram 500 and state diagram 700 is that state diagram 700 includes two additional refresh modes to accommodate the refresh management (RFM) mode of the memory. For simplicity, similar to the previous ones... Figure 5 The patterns and operations described will no longer be relative to Figure 7 Repeating this again.

[0077] Some memories may include an RFM mode, wherein when RFM mode is enabled, the controller can monitor memory access operations and control the ratio of automatic refresh operations to target refresh operations. When RFM mode is enabled, the memory can move from an initial state 710 to an RFM-enabled mode 760. While RFM mode remains enabled, the memory can perform a refresh as part of a fifth mode 770 when the RFM signal is active and the refresh signal AREF is received from the controller, and can perform a refresh as part of a sixth mode 780 when the refresh signal AREF received via the RFM signal is not active. In some embodiments, the controller can count memory access operations and can activate the RFM signal when the count exceeds a threshold.

[0078] Mode 770 may involve performing target refresh operations, each target refresh operation refreshing a single victim word line. Mode 780 may include automatic refresh and target refresh operations.

[0079] Figure 8 These are timing diagrams for different refresh modes according to some embodiments of this disclosure. Timing diagrams 870 and 880 may represent... Figure 7 The fifth refresh mode 770 and the sixth refresh mode 780. The timing diagrams 870 and 880 are generally similar to... Figure 6 The timing diagram.

[0080] Timing diagram 870 illustrates a fifth refresh mode comprising three refresh surges. The first surge refreshes four word lines as part of the automatic refresh operation. The second surge refreshes victims R+1 (or R+2) at the first seed address Seed1. The third surge refreshes victims R-1 (or R-2) at the first seed address Seed1.

[0081] Timing diagram 880 illustrates the sixth refresh pattern, which includes four refresh surges. The first two surges are used to refresh victims R+1 and R-1 (or R+2 and R-2) at the first seed address Seed1. The third and fourth surges are used to refresh victims R+1 and R-1 (or R+2 and R-2) at the second seed address Seed2.

[0082] Of course, it should be understood that any of the examples, embodiments, or processes described herein may be combined with or separated from one or more other examples, embodiments, and / or processes and / or performed in a separate apparatus or apparatus portion of a system, apparatus, or method according to the invention.

[0083] Figure 9 This is a flowchart of a method according to some embodiments of the present disclosure. In some embodiments, method 900 may be performed by... Figures 1 to 4 One or more of the devices or systems can perform this action, and can Figures 5 to 8 It can be operated in one or more ways as described in the document.

[0084] Method 900, typically beginning at block 910, describes storing multiple row addresses, each associated with a word line of the memory array. Row addresses can be received along the row address bus as part of an access operation to the memory. The row addresses can be stored in an intruder detector (e.g., Figure 4 In CAM 402). In some embodiments, only a portion of the addresses along the bus may be sampled and stored. In some embodiments, all addresses along the bus may be stored.

[0085] Box 910 may typically be followed by box 920, which describes activating a control signal when no at least two of the stored row addresses represent word lines that can be refreshed simultaneously. For example, a segment comparator may examine the stored addresses to determine whether at least two of the stored addresses are in different non-adjacent segments. In some embodiments, the segment comparator may examine addresses in an intruder detector in response to a refresh signal (e.g., AREF).

[0086] Box 920 may generally be followed by box 930, which describes generating a first refresh address based on a first of a plurality of stored row addresses. The first refresh address may be an address associated with a word line adjacent to a word line represented by the first of the plurality of stored row addresses. In some embodiments, the first refresh address may be generated in response to a refresh signal AREF. In some embodiments, the first refresh address may be generated in response to a target refresh signal (e.g., RHR).

[0087] Box 930 may typically be followed by box 940, which describes generating a second refresh address based on a second of a plurality of stored row addresses. The process of generating the second refresh address may generally be similar to that described in box 930 for generating the first refresh address. In some embodiments, the operations described in boxes 930 and 940 may be performed simultaneously.

[0088] Box 940 may typically be followed by box 950, which describes a portion of the simultaneous refreshing of the first word line associated with the first refresh address and the second word line associated with the second refresh address as a target refresh operation when the control signal is not active, and a portion of the sequential refreshing of the first word line and the second word line as corresponding first and second target refresh operations when the control signal is active.

[0089] Whether two refresh addresses are refreshed together can be based on which refresh mode of the memory is in operation. For example, method 900 may include activating the refresh mode of the memory based on a control signal.

[0090] Finally, the foregoing discussion is intended to illustrate the system of the invention only and should not be construed as limiting the appended claims to any particular embodiment or group of embodiments. Therefore, while the system of the invention has been described in detail with reference to exemplary embodiments, it should be understood that many modifications and alternative embodiments can be devised by those skilled in the art without departing from the broader and established spirit and scope of the system of the invention as set forth in the appended claims. Therefore, the specification and drawings should be viewed in an illustrative manner and are not intended to limit the scope of the appended claims.

Claims

1. A memory device comprising: A memory array comprising multiple segments; An attacker detector configured to store one or more addresses, each of which is associated with one of the plurality of segments; A segment comparator configured to provide a control signal at an active level if none of the one or more addresses stored in the aggressor detector are located in different non-adjacent segments of the plurality of segments. A rate-of-attack control circuit is configured to activate a first refresh mode when the control signal is at an inactive level and to activate a second refresh mode when the control signal is at the active level. Specifically, as part of the refresh operation when the first refresh mode is in operation, a first refresh address based on one of the stored one or more addresses and a second refresh address based on a different one of the stored one or more addresses are refreshed simultaneously. Specifically, as part of the refresh operation when the second refresh mode is in operation, the first refresh address and the second refresh address are refreshed sequentially.

2. The device of claim 1, wherein in response to the device’s refresh management mode being enabled, the theft rate control circuit is configured to activate a fifth refresh mode in response to the refresh management signal not being active and to activate a sixth refresh mode in response to the refresh management signal being active.

3. The memory device of claim 1, wherein adjacent segments of the plurality of segments share a set of sensing amplifiers.

4. A memory device comprising: A memory array comprising multiple segments; An attacker detector configured to store one or more addresses, each of which is associated with one of the plurality of segments; A segment comparator configured to provide a control signal at an active level if none of the one or more addresses stored in the aggressor detector are located in different non-adjacent segments of the plurality of segments. as well as A rate-of-attempt control circuit is configured to activate a first refresh mode when the control signal is at an inactive level and to activate a second refresh mode when the control signal is at the active level, wherein the refresh operation when the first refresh mode is active includes at least one target refresh operation and at least one automatic refresh operation, and wherein the refresh operation when the second refresh mode is active does not include an automatic refresh operation.

5. A memory device, A memory array comprising multiple segments; An attacker detector configured to store one or more addresses, each of which is associated with one of the plurality of segments; A segment comparator configured to provide a control signal at an active level if none of the one or more addresses stored in the aggressor detector are located in different non-adjacent segments of the plurality of segments. as well as A rate-of-attack control circuit is configured to activate a first refresh mode when a control signal is at an inactive level and to activate a second refresh mode when the control signal is at the active level, wherein the rate-of-attack control circuit includes a rate-of-attack control counter configured to decrease the value of the rate-of-attack control count when a refresh operation is performed while the second refresh mode is active and configured to maintain the value of the rate-of-attack control count when a refresh operation is performed while the first refresh mode is active.

6. The memory device of claim 5, wherein the steal rate control circuit is configured to activate a third refresh mode when the control signal is at the active level and the value of the steal control count is at its minimum, and wherein the refresh operation when the third refresh mode is active includes an automatic refresh operation but not a target refresh operation.

7. The memory device of claim 5, wherein the steal rate control circuit is configured to activate a fourth refresh mode when the control signal is at the inactive level and the value of the steal control count is below a maximum value, wherein the refresh operation when the first refresh mode is active includes partially refreshing a first number of word lines as an automatic refresh operation, and wherein the refresh operation when the fourth refresh mode is active includes partially refreshing a second number of word lines different from the first number as an automatic refresh operation.

8. A memory device comprising: A memory array comprising multiple word lines, each associated with a row address; as well as A refresh control circuit is configured to store a plurality of row addresses and determine whether at least two of the stored row addresses can be refreshed simultaneously; configured to simultaneously provide a first target refresh address and a second target refresh address if they can be refreshed simultaneously based on different first target refresh addresses and second target refresh addresses from the stored row addresses; and configured to provide the first target refresh address and then the second target refresh address if the first target refresh address and the second target refresh address cannot be refreshed simultaneously. The refresh control circuitry includes a steal output control circuitry configured to determine which segment of the memory array each of the stored plurality of row addresses is associated with, and wherein determining whether at least two of the stored plurality of row addresses can be refreshed simultaneously is based on which segments of the array the row addresses are associated with.

9. The memory device of claim 8, further comprising a row decoder configured to refresh a selected one of the plurality of word lines associated with the first target refresh address and the second target refresh address.

10. A memory device comprising: A memory array comprising multiple word lines, each associated with a row address; as well as The refresh control circuit is configured to: Store multiple row addresses and determine whether at least two of the stored row addresses can be refreshed simultaneously. When the first target refresh address and the second target refresh address, which are different among the stored multiple row addresses, can be refreshed simultaneously, the first target refresh address and the second target refresh address are provided simultaneously, and Configured to provide the first target refresh address and then the second target refresh address if the first target refresh address and the second target refresh address cannot be refreshed simultaneously. The refresh control circuitry is configured to provide only the first target refresh address in the event that only a single stored row address exists.

11. A memory device comprising: A memory array comprising multiple word lines, each associated with a row address; as well as The refresh control circuit is configured to: Store multiple row addresses and determine whether at least two of the stored row addresses can be refreshed simultaneously. When the first target refresh address and the second target refresh address, which are different among the stored multiple row addresses, can be refreshed simultaneously, the first target refresh address and the second target refresh address are provided simultaneously, and Configured to provide the first target refresh address and then the second target refresh address if the first target refresh address and the second target refresh address cannot be refreshed simultaneously. The first target refresh address is associated with a word line of a word line associated with the first of the plurality of stored row addresses, and the second target refresh address is associated with a word line of a word line associated with the second of the plurality of stored row addresses.

12. The memory device of claim 11, wherein the refresh control circuitry includes a + / -2 rate control circuitry configured to provide a control signal, and wherein, in response to the control signal being at an active level, the first target refresh address is associated with a word line separated by a word line from the word line associated with the first of the plurality of stored row addresses, and wherein the second target refresh address is associated with a word line adjacent to a word line adjacent to the word line associated with the second of the plurality of stored row addresses.

13. A method for operating a memory device, comprising: A plurality of row addresses are stored, wherein each of the plurality of stored row addresses is associated with a word line of the memory array; The control signal is activated if there are no at least two row addresses among the stored row addresses that represent word lines that can be refreshed simultaneously. A first refresh address is generated based on the first of the stored multiple row addresses; A second refresh address is generated based on the second of the stored plurality of row addresses; When the control signal is not active, the first word line associated with the first refresh address and the second word line associated with the second refresh address are refreshed simultaneously as part of the target refresh operation. When the control signal is active, the first word line and the second word line are refreshed sequentially as part of the corresponding first target refresh operation and second target refresh operation. In response to performing the refresh operation, the value of the steal rate counter is updated; as well as The refresh mode of the memory is activated based on the control signal and the value of the theft rate counter.

14. The method of claim 13, wherein the stored plurality of row addresses are associated with a memory bank of the memory array.

15. The method of claim 13, wherein activating the refresh mode comprises: The first refresh mode is activated when the control signal is not active and the theft rate counter is at its maximum value. The second refresh mode is activated when the control signal is inactive and the theft rate counter is below the maximum value. The third refresh mode is activated when the control signal is in effect and the theft rate counter is at its minimum value. as well as The fourth refresh mode is activated when the control signal is in effect and the theft rate counter is higher than the minimum value.

16. A method for operating a memory device, comprising: A plurality of row addresses are stored, wherein each of the plurality of stored row addresses is associated with a word line of the memory array; The control signal is activated if there are no at least two row addresses among the stored row addresses that represent word lines that can be refreshed simultaneously. A first refresh address is generated based on the first of the stored multiple row addresses; A second refresh address is generated based on the second of the stored plurality of row addresses; When the control signal is not active, the first word line associated with the first refresh address and the second word line associated with the second refresh address are refreshed simultaneously as part of the target refresh operation. When the control signal is active, the first word line and the second word line are refreshed sequentially as part of the corresponding first target refresh operation and second target refresh operation. Determine which segment of the memory array each of the stored row addresses is associated with; as well as The control signal is activated when all of the stored row addresses are in the same segment or adjacent segments of the memory array.

17. A method for operating a memory device, comprising: A plurality of row addresses are stored, wherein each of the plurality of stored row addresses is associated with a word line of the memory array; The control signal is activated if there are no at least two row addresses among the stored row addresses that represent word lines that can be refreshed simultaneously. A first refresh address is generated based on the first of the stored multiple row addresses; A second refresh address is generated based on the second of the stored plurality of row addresses; When the control signal is not active, the first word line associated with the first refresh address and the second word line associated with the second refresh address are refreshed simultaneously as part of the target refresh operation. When the control signal is active, the first word line and the second word line are refreshed sequentially as part of the corresponding first target refresh operation and second target refresh operation. as well as If the stored multiple row addresses contain only one stored row address, skip the second target refresh operation.

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