Row Tracking of Reference Generation for Memory Devices

Abstract

The present disclosure relates to row-by-row tracking of reference generation for a memory device. The disclosure relates to a structure comprising a plurality of magnetic random access memory (MRAM) bit cells, the bit cells comprising a first circuit and a second circuit, the second circuit being connected to the same word line as the first circuit such that the second circuit is configured to be connected in parallel series to generate a reference resistance value for sensing.

Description

Technical Field

[0001] The present disclosure relates to reference generation, and more particularly to circuits and methods for row-wise tracking of reference generation for memory devices and methods of operation. Background Art

[0002] Memory devices are used as internal storage areas in computers and other electronic devices. One specific type of memory used to store data in computers is random access memory (RAM). RAM is often used as the primary on-chip and off-chip storage unit in computing systems and is typically volatile, meaning that any data stored in RAM is lost once the power is turned off.

[0003] Circuit designers are considering using resistive non-volatile memory (NVM) structures for on-chip memory arrays due to their advantages of high speed, low power consumption, non-volatility, and low area consumption. These NVM structures can include spin transfer torque-magnetic tunnel junction magnetic random access memory (STT-MTJ MRAM), spin orbit torque MRAM (SOT-MRAM), and voltage controlled magnetic anisotropy tunnel junction magnetic random access memory (VCMA-MTJ MRAM).

[0004] The MRAM structure includes an array of MRAM cells (e.g., STT-MTJ MRAM cells) arranged in columns and rows. The MRAM cell includes a single field effect transistor (FET) (e.g., n-type field effect transistor (NFET)), a single variable resistor, and a single magnetic tunnel junction (MTJ). The FET and MTJ are connected in series between a source line and a bit line, and the gate of the FET is controlled by the state of the word line. The MTJ is a back-end-of-line (BEOL) multilayer structure that includes a fixed ferromagnetic layer (i.e., a pinned layer) and a switchable ferromagnetic layer (i.e., a free layer) separated by a thin dielectric layer (e.g., a thin oxide layer).

[0005] In conventional MRAM circuits, sensing is difficult due to the limited tunnel magnetoresistance (TMR). Furthermore, in conventional MRAM circuits, the sensing margin is highly dependent on the spread and variability of the reference resistance. Summary of the Invention

[0006] In one aspect of the present disclosure, a structure includes a plurality of magnetic random access memory (MRAM) bit cells, the bit cells including a first circuit and a second circuit connected to the same word line as the first circuit such that the second circuit is configured in a parallel series connection to generate a reference resistance value for sensing.

[0007] In another aspect of the present disclosure, a circuit includes a reference bit circuit comprising a plurality of first columns for generating reference resistance values and a read / write array circuit comprising a plurality of second columns for performing at least one of a read operation and a write operation.

[0008] In another aspect of the disclosure, a method includes programming a plurality of reference bits in a reference bit circuit connected to a read / write array circuit; and sensing the plurality of reference bits using at least one sense amplifier connected to an output of the reference bit circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] In the following detailed description, the present disclosure is described by way of non-limiting examples of exemplary embodiments of the present disclosure with reference to the several accompanying drawings mentioned.

[0010] Figure 1 A magnetic random access memory (MRAM) structure including a reference bit circuit according to some aspects of the present disclosure is shown.

[0011] Figure 2A A reference bit circuit of an MRAM structure according to some aspects of the present disclosure is shown.

[0012] Figure 2B A representation of a reference bit circuit of an MRAM structure according to some aspects of the present disclosure is shown.

[0013] Figure 3 Programming of a reference bit circuit in a first cycle of an MRAM structure according to aspects of the present disclosure is shown.

[0014] Figure 4 Programming of a reference bit circuit in a second cycle of an MRAM structure is shown, in accordance with aspects of the present disclosure.

[0015] Figure 5A A read operation of a reference bit circuit of an MRAM structure according to aspects of the present disclosure is shown.

[0016] Figure 5B A representation of a read operation of a reference bit circuit of an MRAM structure according to aspects of the present disclosure is shown.

[0017] Figure 6A Additional multiple reference bit circuits are shown in accordance with aspects of the present disclosure.

[0018] Figure 6B Representations of additional multiple reference bit circuits according to aspects of the present disclosure are shown. DETAILED DESCRIPTION

[0019] The present disclosure relates to reference generation, and more particularly to circuits and methods for row-by-row tracking of reference generation for a memory device, and methods of operation. More particularly, the memory device is a magnetic random access memory (MRAM). In an embodiment, the memory device can generate a reference signal from the same word line as a read access word line. Advantageously, in addition to the other advantages described herein, the memory device described herein provides accurate midpoint reference generation and row-by-row reference tracking.

[0020] In known MRAM circuits, sensing is difficult due to the limited tunnel magnetoresistance (TMR). In addition, in known MRAM circuits, the sensing margin is highly dependent on the spread and variability of the reference resistance. Therefore, it is necessary to reduce the reference bit variability. To reduce the reference bit variability, known systems use a combination of magnetic tunnel junctions (MTJs) (e.g., four (4) MTJs or 16 MTJs) or use a dedicated sub-array outside the active array as a reference signal.

[0021] Compared to known systems, the present disclosure generates a reference bit on the same active word line as the read access word line. The present disclosure also uses a parallel series connection of MTJs within the active array. Thus, advantageously, by implementing the circuits and methods described herein, the present disclosure provides accurate midpoint reference generation (i.e., (Rp+Rap) / 2), is compatible with midpoint sensing, uses minimal control circuitry, has per-row reference tracking capabilities, reduces the standard deviation (sigma) of midpoint sensing by approximately 50%, and provides redundancy.

[0022] As a more specific example, the memory device (e.g., structure) includes a plurality of MRAM bit cells that are connected in parallel series to form an effective reference resistance for sensing. In an embodiment, the structure uses an additional column in the MRAM array, where the true bit cell used for reference generation is the same as the active bit cell. In addition, the memory device can be written to the MTJ structure using peripheral circuits such as transistor switches or logic gate circuits. In addition, the structure includes a circuit that generates a reference resistance for sensing, where the reference bit can be programmed while the array is being written. In addition, in the circuit that generates the reference resistance for sensing, a read control circuit can be used to generate the reference resistance during a read operation.

[0023] Figure 1 A magnetic random access memory (MRAM) structure including a reference bit circuit according to some aspects of the present disclosure is shown. Figure 1In the embodiment, the MRAM structure 10 includes a reference bit circuit 20 and a read / write array 30. In this embodiment, the reference bit circuit 20 and the read / write array 30 use the same word line WL. The reference bit circuit 20 includes MTJs 35, 50, 55, and 70 connected to corresponding bit lines PBL0, PBL1, APBL0, and APBL1 in the first row, respectively. The first row of the reference bit circuit 20 also includes NFETs 40, 45, 60, and 65 connected to the word line WL. The second row of the reference bit circuit 20 includes MTJs 120, 135, 140, and 155 and NFETs 125, 130, 145, and 150. The third row of the reference bit circuit 20 includes MTJs 200, 215, 220, and 235 and NFETs 205, 210, 225, and 230. The fourth row of reference bit circuit 20 includes MTJs 280, 295, 300, and 315 and NFETs 285, 290, 305, and 310. Furthermore, node T1 is connected to bit lines PBL0 and PBL1, node T2 is connected to source lines PSL0 and APSL0, and node T3 is connected to bit lines APBL0 and APBL1. The connections of bit lines PBL0, PBL1, APBL0, and APBL1 to form nodes T1, T2, and T3 can be implemented directly through metal lines of transmission gate switches.

[0024] exist Figure 1 , read / write array 30 includes MTJs 75, 90, 95, and 115 connected to corresponding bit lines BL0, BL1, BL2, and BL3 in a first row. The first row of read / write array 30 also includes NFETs 80, 85, 100, and 105 connected to word line WL. The second row of read / write array 30 includes MTJs 160, 175, 180, and 195 and NFETs 165, 170, 185, and 190. The third row of read / write array 30 includes MTJs 240, 255, 260, and 275 and NFETs 245, 250, 265, and 270. The fourth row of read / write array 30 includes MTJs 320, 335, 340, and 355 and NFETs 325, 330, 345, and 350.

[0025] exist Figure 1 In the operation of the reference bit circuit 20, the four columns of the reference bit circuit 20 are used for reference bit generation (i.e., reference resistance value). Specifically, the four columns of the reference bit circuit 20 use the word line WL from the same bit cell as the read / write array 30 to generate the reference bit generation (i.e., the value of (RP+RAP) / 2). The read / write array 30 is a read / write array that can be fully understood by a person of ordinary skill in the art without any additional disclosure. The operational details of the programming and reading operations are described in detail in the following. Figure 3 、 4 , 5A and 5B are described in detail.

[0026] Figure 2A The reference bit circuit 20 of the MRAM structure 10 is shown (similar to Figure 1 ). Figure 2B A representation 15 of a reference bit circuit 20 of the MRAM structure 10 is shown. Figure 2B In FIG. 1 , the representation 15 of the reference bit circuit 20 of the MRAM structure 10 causes the node T2 to float. Figure 2B In , RP (parallel resistance) is the low resistance value, and RAP (anti-parallel resistance) is the high resistance value. Figure 2B In the representation 15, a midpoint resistance value (RP / 2+RAP / 2) is generated for the MRAM sense / read operation. Figure 5A and 5B Details of the MRAM sensing / reading operations are described in .

[0027] Figure 3 FIG. 1 shows programming of a reference bit circuit in a first cycle of an MRAM structure according to some aspects of the present disclosure. In the MRAM structure 10, the read / write array 30 is disabled in the first cycle ( Figure 3 ), so that programming of the reference bit can be performed in the reference bit circuit 20. Figure 3 In the MRAM structure 10, the T1 node is set to VDD (i.e., the power supply value), the T2 node is set to GND, and the T3 node is set to GND. Since the T2 and T3 nodes are set to GND, no current will flow through the bit lines APBL0 and APBL1 and the source line APSL0. In addition, when the word line WL is set to VDD, current flows from the bit lines PBL0 and PBL1 to the source line PSL0, causing the free layer to switch to or maintain the parallel resistance (RP) state (i.e., a low resistance value). When the parallel resistance (RP) state is programmed, a logic value of "0" is stored in the MRAM structure 10.

[0028] Figure 4 FIG. 1 shows programming of a reference bit circuit in a second cycle of an MRAM structure according to some aspects of the present disclosure. In the MRAM structure 10, the read / write array 30 is disabled in the second cycle ( Figure 4 ), so that programming of the reference bit can be performed in the reference bit circuit 20. Figure 4In the MRAM structure 10, the T1 node is set to VDD (i.e., the power supply value), the T2 node is set to VDD, and the T3 node is set to GND. Since the T1 and T2 nodes are set to VDD, no current will flow through the bit lines PBL0 and PBL1 and the source line PSL0. In addition, when the word line WL is set to VDD, current flows from the source line APSL0 to the bit lines APBL0 and APBL1, causing the free layer to switch to or maintain the antiparallel resistance (RAP) state (i.e., a high resistance value). When the antiparallel resistance (RAP) state is programmed, a logic value "1" is stored in the MRAM structure 10.

[0029] Figure 5A FIG. 1 shows a read operation of a reference bit circuit of an MRAM structure 10 according to some aspects of the present disclosure. In the MRAM structure 10, the read / write array 30 is disabled (in Figure 5A (shown in gray in the figure), so that a read operation can be performed in the reference bit circuit 20. Figure 5A , the T2 node is floating and the T3 node is set to GND. Since the T2 node is floating and the T3 node is set to GND, no current flows through the bit lines PBL0 and PBL1 and the source line PSL0. In addition, when the word line WL is set to VDD, current flows from the source line APSL0 to the bit lines APBL0 and APBL1, causing the free layer to switch to or maintain an antiparallel resistance (RAP) state (i.e., a high resistance value). In addition, since the T2 node is floating and the T3 node is set to GND, the T1 node generates a reference bit (i.e., (resistance value (RP / 2)+(RAP / 2)) and outputs it to the sense amplifier 370 (see Figure 5B ).

[0030] Figure 5B A representation of a read operation of a reference bit circuit of an MRAM structure according to some aspects of the present disclosure is shown. In the representation of a read operation of the reference bit circuit 20 of the MRAM structure 10, the read / write array 30 is connected to the inputs of a plurality of column multiplexers 360. The column multiplexers 360 select the inputs from the read / write array 30 and output the selected inputs to a plurality of sense amplifiers 370. The sense amplifiers 370 also receive the reference bit generation (i.e., the resistance value ((RP / 2)+(RAP / 2))) from node T1 as input 380, and the T3 node is set to GND. Thus, the MRAM structure 10 uses the input 380, the column multiplexers 360, and the sense amplifiers 370 to sense (i.e., read) the programmed (i.e., stored) value.

[0031] Figure 6A Additional multiple reference bit circuits according to aspects of the present invention are shown. Figure 6A In the embodiment, each of the plurality of reference bit circuits 20' includes Figure 1The same element is used for each of the multiple reference bit circuits 20. Figure 6A , each of the plurality of reference bit circuits 20' is connected together at the T1, T2, and T3 nodes. For example, the T1 nodes of the plurality of reference bit circuits 20' are connected together at points "C" and "F." The T2 nodes of the plurality of reference bit circuits 20' are connected together at points "A" and "D." The T3 nodes of the plurality of reference bit circuits 20' are connected together at points "B" and "E." Finally, one of the plurality of reference bit circuits 20' has a T3 node that is connected to the T1 node of another of the plurality of reference bit circuits 20' (i.e., see the rectangular box with ┴ at both ends, which is between points "B" and "F").

[0032] Figure 6B 1 shows a representation of another plurality of reference bit circuits according to aspects of the present invention. Figure 6B , each representation 15' of the plurality of reference bit circuits 20' is connected to another representation 15' of the plurality of reference bit circuits 20'. For example, points "A" and "C" are connected to four (4) RP (parallel resistor) elements (i.e., corresponding to Figure 1 MTJs 35 and 50 in FIG. 3). In addition, points "A" and "B" are connected to four (4) RAP (resistance-antiparallel) elements (i.e., corresponding to Figure 1 MTJs 55 and 70 in FIG. 1 ). Points “D” and “F” are also connected to four (4) RP (parallel resistor) elements (i.e., these correspond to Figure 1 MTJs 35 and 50 in FIG. 3). Points “D” and “E” are also connected to four (4) RAP (resistance-antiparallel) elements (i.e., these correspond to Figure 1 MTJ 55 and 70 in ). By using Figure 6B According to representation 15, 16 MTJs per row can be used to generate a midpoint resistance value of (RP+RAP) / 2) (i.e., RP / 4+RAP / 4+RP / 4+RAP / 4=(RP+RAP) / 2).

[0033] The disclosed circuits and methods for row-by-row tracking of reference generation for magnetic random access memory (MRAM) can be manufactured in a variety of ways using a variety of different tools. However, in general, these methods and tools are used to form structures with dimensions on the micrometer and nanometer scale. The methods (i.e., techniques) for manufacturing the disclosed circuits and methods for row-by-row tracking of reference generation for magnetic random access memory (MRAM) have been adopted from integrated circuit (IC) technology. For example, these structures are built on a wafer and implemented by patterning a film of material by performing a photolithography process on top of the wafer. In particular, the manufacture of the methods and circuits for row-by-row tracking of reference generation for magnetic random access memory (MRAM) uses three basic building blocks: (i) depositing a thin film of material on a substrate, (ii) applying a patterned mask on top of the film by photolithographic imaging, and (iii) etching the film selectively to the mask.

[0034] The above method is used for the manufacture of integrated circuit chips. The resulting integrated circuit chips can be distributed by the manufacturer in raw wafer form (i.e., as a single wafer with multiple unpackaged chips), as a bare die, or in a packaged form. In the latter case, the chip is mounted in the form of a single-chip package (e.g., a plastic carrier whose leads are fixed to a motherboard or other higher-level carrier) or a multi-chip package (e.g., a ceramic carrier with surface interconnects and / or buried interconnects). In any case, the chip is then integrated with other chips, discrete circuit elements, and / or other signal processing devices as part of (a) an intermediate product (e.g., a motherboard) or (b) a final product. The final product can be any product that includes an integrated circuit chip, ranging from toys and other low-end applications to advanced computer products with displays, keyboards or other input devices, and central processing units. In addition, the circuits and methods for in-memory logic computing disclosed herein can have a wide range of applications in high-throughput processors for machine learning and artificial intelligence.

[0035] The description of various embodiments of the present disclosure has been given for illustrative purposes, but is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is selected to best explain the principles of the various embodiments, practical applications, or technical improvements to technologies found in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.

Claims

1. A memory device structure comprising a plurality of magnetic random access memory (MRAM) bit cells, the bit cells comprising a first circuit and a second circuit, the second circuit being connected to the same word line as the first circuit, such that the second circuit is configured to be connected in parallel series to generate a reference resistance value for sensing, in, The second circuit includes: First line; a first magnetic tunnel junction MTJ directly connected to the first bit line; a first transistor directly connected to the first MTJ; a second transistor having a source directly connected to the drain of the first transistor; a second MTJ directly connected to the second transistor; a second bit line different from the first bit line and directly connected to the second MTJ; and a first source line directly connected to the drain of the first transistor and the source of the second transistor, The gate of the first transistor and the gate of the second transistor are directly connected to the same word line.

2. The structure according to claim 1, wherein The second circuit includes a reference bit circuit including a plurality of columns for generating the reference resistance value.

3. The structure according to claim 2, wherein: The reference bit circuit includes a true bit primitive configured to generate a reference resistance value (RP+RAP) / 2 to implement midpoint sensing.

4. The structure according to claim 1, wherein Each of the first transistor and the second transistor comprises an NFET transistor.

5. The structure according to claim 2, wherein The reference bit circuit includes a series combination of a plurality of magnetic tunnel junction (MTJ) bit cells connected in parallel.

6. The structure according to claim 2, wherein The reference bit circuit includes a plurality of reference bits that are programmed simultaneously when the array of MRAM bit cells is written.

7. The structure according to claim 2, wherein: The reference bit circuit is used to generate a reference resistance value of (RP+RAP) / 2 during a read operation to implement midpoint sensing.

8. The structure according to claim 2, wherein: The reference bit circuit generates the reference resistance value from a same word line as the first circuit, and the first circuit includes a read / write array circuit.

9. A circuit comprising: a reference bit circuit comprising a plurality of first columns for generating reference resistance values; as well as a read / write array circuit comprising a plurality of second columns for performing at least one of a read operation and a write operation, Wherein, the reference bit circuit includes: First line; a first magnetic tunnel junction MTJ directly connected to the first bit line; a first transistor directly connected to the first MTJ; a second transistor having a source directly connected to the drain of the first transistor; a second MTJ directly connected to the second transistor; a second bit line different from the first bit line and directly connected to the second MTJ; and a first source line directly connected to the drain of the first transistor and the source of the second transistor, The gate of the first transistor and the gate of the second transistor are directly connected to the same word line.

10. The circuit according to claim 9, wherein Each of the first transistor and the second transistor comprises an NFET transistor.

11. The circuit according to claim 9, wherein The reference bit circuit includes a series combination of a plurality of magnetic tunnel junction (MTJ) bit cells connected in parallel.

12. The circuit according to claim 9, wherein The reference bit circuit includes a plurality of reference bits that are programmed simultaneously when the array is written.

13. The circuit according to claim 9, wherein The reference bit circuit is used to generate a reference resistance value of (RP+RAP) / 2 during a read operation to implement midpoint sensing.

14. The circuit according to claim 9, wherein The reference bit circuit generates the reference resistance value from a word line that is the same as a word line of the read / write array circuit.

15. A method of operating a memory device, comprising: programming a plurality of reference bits in a reference bit circuit coupled to a read / write array circuit; as well as sensing the plurality of reference bits using at least one sense amplifier connected to an output of the reference bit circuit, Wherein, the reference bit circuit includes: First line; a first magnetic tunnel junction MTJ directly connected to the first bit line; a first transistor directly connected to the first MTJ; a second transistor having a source directly connected to the drain of the first transistor; a second MTJ directly connected to the second transistor; a second bit line different from the first bit line and directly connected to the second MTJ; and a first source line directly connected to the drain of the first transistor and the source of the second transistor, The gate of the first transistor and the gate of the second transistor are directly connected to the same word line.

16. The method according to claim 15, wherein The plurality of reference bits are programmed in the reference bit circuit using the same word line as a word line of the read / write array circuit.

17. The method according to claim 15, wherein: The reference bit circuit includes a plurality of rows, and each of the rows includes a plurality of magnetic tunnel junctions (MTJs).

18. The method according to claim 17, wherein The plurality of MTJs includes sixteen MTJs connected in parallel in each of the rows of the reference bit circuits.

Images