Test circuit, memory device and storage device

Abstract

Test circuitry, memory devices, and storage devices can be provided herein. A word line test circuitry can include an operation signal generator configured to generate a plurality of operation signals in response to a test command, a comparison result generator configured to generate a target voltage based on a test in response to the plurality of operation signals, and generate a comparison signal based on a comparison result between the target voltage and a reference voltage, a current of a target word line varying with a test voltage being reflected in a test current, and a word line defect detector configured to detect a defect in the target word line based on at least one reference count and a count of a reference clock, a period of the reference clock being counted until a level of the comparison signal changes from a first level to a second level.

Description

TECHNICAL FIELD

[0001] Various embodiments of the present disclosure generally relate to an electronic device, and more particularly, to a test circuit, a memory device, a storage device, and an operating method thereof. BACKGROUND

[0002] A storage device stores data under the control of a host. The storage device can include a memory device that stores data and a memory controller that controls the memory device. In general, there are two types of memory devices: a volatile memory device and a non-volatile memory device.

[0003] A volatile memory device can store data only when power is supplied from a power source. When the power is interrupted, the data stored in the volatile memory device can be lost. Examples of the volatile memory device include a static random access memory (SRAM) and a dynamic random access memory (DRAM).

[0004] In a non-volatile memory device, the stored data is retained even if the power from the power source is interrupted. Examples of the non-volatile memory device include a read only memory (ROM), a programmable ROM (PROM), an electrically programmable ROM (EPROM), an electrically erasable programmable ROM (EEPROM), and a flash memory. SUMMARY

[0005] Various embodiments of the present disclosure relate to a storage device that detects a defect in a word line and thus prevents degradation of performance.

[0006] Embodiments of the present disclosure can provide a word line test circuit. The word line test circuit can include an operation signal generator configured to generate a plurality of operation signals in response to a test command, a comparison result generator configured to generate a target voltage based on a test current in response to the plurality of operation signals and generate a comparison signal based on a comparison result between the target voltage and a reference voltage, a current of a target word line varying with a test voltage being reflected in the test current, and a word line defect detector configured to detect a defect in the target word line based on at least one reference count and a count of a reference clock, a period of the reference clock being counted until a level of the comparison signal changes from a first level to a second level.

[0007] Embodiments of the disclosure can provide a memory device. The memory device can include an array of memory cells including a plurality of memory cells, and a word line test circuit configured to generate a test voltage in response to a test command, charge a target voltage based on a test current in which a current of a target word line varying with the test voltage is reflected, generate a comparison signal based on a comparison result between the target voltage and a reference voltage, and detect a defect in the target word line based on at least one reference count and a count of a reference clock, a period of the reference clock being counted until a level of the comparison signal changes from a first level to a second level.

[0008] Embodiments of the disclosure can provide a storage device. The storage device can include a memory controller configured to output a test command instructing to check whether a defect exists in a target word line, and a memory device configured to generate a test voltage in response to the test command, charge a target voltage based on a test current in which a current of a target word line varying with the test voltage is reflected, generate a comparison signal based on a comparison result between the target voltage and a reference voltage, detect a defect in the target word line based on at least one reference count and a count of a reference clock, a period of the reference clock being counted until a level of the comparison signal changes from a first level to a second level, and provide a test response to the memory controller as a response to the test command.

[0009] Embodiments of the disclosure can provide an operating method of a memory device. The operating method of the memory device can include applying a test voltage to a word line to generate a current in the word line, charging a capacitor charger to a stable voltage level based on the current, and determining whether the word line has a defect based on an amount of time taken to discharge the capacitor charger from the stable voltage level to a reference voltage level. BRIEF DESCRIPTION OF DRAWINGS

[0010] Figure 1 FIG. 1 is a diagram illustrating a storage system according to an embodiment of the disclosure.

[0011] Figure 2 FIG. 2 is a diagram illustrating a memory device according to an embodiment of the disclosure.

[0012] Figure 3 FIG. 3 is a diagram illustrating an exemplary structure of any one of a plurality of memory blocks of Figure 2

[0013] Figure 4 FIG. 4 is a diagram illustrating a word line test circuit according to an embodiment of the disclosure.

[0014] Figure 5 FIG. 5 is a diagram illustrating a comparison result generator such as a comparison result generator of Figure 4 FIG. 6 is a diagram illustrating a comparison result generator such as a comparison result generator of​

[0015] Figure 6 is a diagram illustrating a word line defect detector such as Figure 4

[0016] Figure 7 is a circuit diagram illustrating an embodiment of a comparison result generator such as Figure 5

[0017] Figure 8 is a diagram illustrating a variation of a comparison result generator such as Figure 7

[0018] Figure 9 is a diagram illustrating an example of how the current of a target word line changes over time.

[0019] Figure 10 is a diagram illustrating a target voltage over time.

[0020] Figure 11 is a diagram illustrating an embodiment in which a reference clock is counted.

[0021] Figure 12 is a diagram illustrating an embodiment of a method of detecting defects in a plurality of word lines in one memory block.

[0022] Figure 13 is a diagram illustrating an embodiment of a method of detecting defects in a plurality of word lines in one memory block.

[0023] Figure 14 is a diagram illustrating an embodiment of a method of detecting defects in a particular word line in each of a plurality of memory blocks.

[0024] Figure 15 is a flowchart illustrating a method of detecting defects in a word line according to an embodiment of the disclosure.

[0025] Figure 16 is a diagram illustrating a memory controller according to an embodiment of the disclosure.

[0026] Figure 17 is a block diagram illustrating a memory card system to which a storage device is applied according to an embodiment of the disclosure.

[0027] Figure 18 is a block diagram illustrating a solid state drive (SSD) system to which a storage device is applied according to an embodiment of the disclosure.

[0028] Figure 19 is a block diagram illustrating a user system to which a storage device is applied according to an embodiment of the disclosure. ​​​DETAILED DESCRIPTION

[0029] Particular structural and functional descriptions are provided to describe embodiments of the present disclosure. The present disclosure may, however, be practiced in various forms and embodied in various ways, and hence this specification is not to be construed as limiting in any way. Also, throughout the specification, any reference to "one embodiment" or "another embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment. The appearance of the phrases "in one embodiment" or "in another embodiment" in various places in the specification are not necessarily all referring to the same embodiment.

[0030] Figure 1 is a diagram illustrating a storage system according to an embodiment of the present disclosure.

[0031] Referring to Figure 1 , the storage system can be implemented as a personal computer (PC), a data center, an enterprise data storage system, a data processing system including direct attached storage (DAS), a data processing system including a storage area network (SAN), or a data processing system including network attached storage (NAS).

[0032] The storage system can include a storage device 1000 and a host 400.

[0033] The storage device 1000 can be a device that stores data in response to a request received from the host 400 such as a mobile phone, a smart phone, an MP3 player, a laptop computer, a desktop computer, a game console, a TV, a tablet PC, or an in-vehicle infotainment system.

[0034] The storage device 1000 can be manufactured or configured as any one of various types of storage devices according to a host interface that is a scheme of communication with the host 400. For example, the storage device 1000 can be implemented as a solid state disk (SSD), a multimedia card such as an MMC, an embedded MMC (eMMC), a reduced size MMC (RS-MMC), or a micro MMC, a secure digital card such as an SD, a mini SD, or a micro SD, a universal serial bus (USB) storage device, a universal flash storage (UFS) device, a personal computer memory card international association (PCMCIA) card type storage device, a peripheral component interconnect (PCI) card type storage device, a fast PCI (PCI-E) card type storage device, a compact flash (CF) card, a smart media card, and / or a memory stick.

[0035] The memory device 1000 can be manufactured in any one of various types of package forms. For example, the memory device 1000 can be manufactured as a package on package (POP), a system in package (SIP), a system on chip (SOC), a multi-chip package (MCP), a chip on board (COB), a wafer level package (WFP), and / or a wafer level package (WSP).

[0036] The memory device 1000 can include a memory device 100 and a memory controller 200.

[0037] The memory device 100 can operate in response to a control of the memory controller 200. In detail, the memory device 100 can receive a command and an address from the memory controller 200, and can access a memory cell selected through the address from among memory cells (not shown). The memory device 100 can perform an operation indicated by the command on the memory cell selected through the address.

[0038] The command can be, for example, a program command, a read command, or an erase command, and the operation indicated by the command can be, for example, a program operation (or a write operation), a read operation, or an erase operation.

[0039] For example, the memory device 100 can receive a program command, an address, and data, and can program the data to a memory cell selected through the address. Here, the data to be programmed to the selected memory cell can be defined as write data.

[0040] For example, the memory device 100 can receive a read command and an address, and can read data from a region selected through the address in a memory cell array (not shown). Among data stored in the memory device 100, the data read from the selected region can be defined as read data.

[0041] For example, the memory device 100 can receive an erase command and an address, and can erase data stored in a region selected through the address.

[0042] In an embodiment, the memory device 100 can be implemented as a double data rate synchronous dynamic random access memory (DDR SDRAM), a low power double data rate fourth generation (LPDDR4) SDRAM, a graphics double data rate (GDDR) SDRAM, a low power DDR (LPDDR) SDRAM, a Rambus dynamic random access memory (RDRAM), a NAND flash memory, a vertical NAND flash memory, a NOR flash device, a resistive RAM (RRAM), a phase change memory (PRAM), a magnetoresistive RAM (MRAM), a ferroelectric RAM (FRAM), or a spin transfer torque RAM (STT-RAM).

[0043] In the present specification, features and aspects of the present application are described by way of example in the context of a memory device 100 being a NAND flash memory.

[0044] The memory device 100 can store the written data under the control of the memory controller 200, or can read the stored read data and provide the read data to the memory controller 200.

[0045] The memory device 100 can include at least one plane. A single plane can include a memory cell array including memory cells storing written data.

[0046] The memory cell array can include a plurality of memory blocks (not shown). A memory block can be a unit on which an operation of erasing data is performed.

[0047] Each memory block can include a plurality of word lines. For example, a first memory block can include a plurality of word lines, and a second memory block can include a plurality of word lines.

[0048] Each memory block can include a plurality of pages (not shown). A page can be a unit on which a program operation of storing written data or a read operation of reading stored read data is performed.

[0049] The memory device 100 can perform a test operation of detecting defects in one or more word lines in response to a test command TCMD provided from the memory controller 200. To this end, the memory device 100 can include a word line test circuit 300.

[0050] After performing the test operation, the memory device 100 can provide a test result TRST as a response to the test command TCMD to the memory controller 200.

[0051] The test result TRST can include data indicating that the test operation has been completed, data on respective states of the plurality of word lines, or data on a defective word line detected as a defective word line. Here, the state of each of the plurality of word lines can represent, for example, a normal state or a defective state.

[0052] In an embodiment, when a target word line is detected as defective, the memory device 100 can store data on the defective target word line, and can provide the data to the memory controller 200 under the control of the memory controller 200.

[0053] The memory controller 200 can control the overall operation of the memory device 1000.

[0054] When power is applied to the memory device 1000, the memory controller 200 can execute firmware (FW). When the memory device 100 is a flash memory device, the firmware can include a host interface layer, a flash translation layer, and a flash interface layer.

[0055] The host interface layer can control operations between the host 400 and the memory controller 200.

[0056] The flash translation layer can convert a logical address provided from the host 400 into a physical address. For this operation, the memory controller 200 can store mapping data indicating a correspondence between the logical address and the physical address.

[0057] The flash interface layer can control communication between the memory controller 200 and the memory device 100.

[0058] The memory controller 200 can control the memory device 100 such that, in response to a write request, a read request, and an erase request received from the host 400, a program operation, a read operation, and an erase operation are performed, respectively.

[0059] During the program operation, the memory controller 200 can provide a program command, a physical address, and write data to the memory device 100.

[0060] During the read operation, the memory controller 200 can provide a read command and a physical address to the memory device 100.

[0061] During the erase operation, the memory controller 200 can provide an erase command and a physical address to the memory device 100.

[0062] In the absence of a request provided from the host 400, the memory controller 200 can autonomously generate a command, an address, and data. The memory controller 200 can transmit the autonomously generated command, address, and data to the memory device 100.

[0063] For example, the memory controller 200 can generate a command, an address, and data to perform a background operation. Also, the memory controller 200 can transmit the command, address, and data to the memory device 100.

[0064] The background operation can be at least one of a wear leveling operation, a read recycling operation, and a garbage collection operation.

[0065] The wear leveling operation can include storing a count of the number of times an erase operation has been performed on a memory block and programming data to a memory block having a minimum erase count.

[0066] The read recovery operation can include moving data stored in the storage block to another storage block before an uncorrectable error occurs in the data stored in the storage block.

[0067] The garbage collection operation can include copying valid data included in a bad block among the storage blocks to a free block and erasing invalid data in the bad block.

[0068] The memory controller 200 can control two or more memory devices 100. In this case, the memory controller 200 can control the memory devices 100 according to an interleaving scheme to improve operation performance.

[0069] The interleaving scheme can involve controlling the memory devices 100 such that operations of the two or more memory devices 100 overlap each other.

[0070] The memory controller 200 can provide a command to the memory device 100, the command instructing to provide data indicating respective states of a plurality of word lines or data about a defective word line.

[0071] The memory controller 200 can provide a command (not shown) to the memory device 100 based on the test result TRST, the command instructing to treat a storage block corresponding to a defective word line detected as a bad block. In this case, in response to the command, the memory device 100 can treat the storage block corresponding to the defective word line detected as a bad block.

[0072] In an embodiment, when the memory device 100 provides data about a defective target word line to the memory controller 200, the memory controller 200 can control the memory device 100 such that, based on the data, a storage block corresponding to the target word line among a plurality of storage blocks in the memory device 100 is treated as a bad block.

[0073] The word line test circuit 300 included in the memory device 100 can receive a test command TCMD. The word line test circuit 300 can generate a test voltage in response to the test command TCMD.

[0074] The test voltage can be applied to a target word line selected from among a plurality of word lines (not shown). Generally, a word line can be made of a metal material such as copper. Thus, when the test voltage is applied to the target word line, a current is generated and flows through the target word line. The current of the target word line can vary according to the test voltage.

[0075] The word line test circuit 300 can generate a test current in which the current of the target word line is reflected, and can charge a target voltage based on the test current.

[0076] The test current can be used to detect a defect in the target word line. The target voltage can correspond to a magnitude of the test current. When a set time elapses from generation of the test current, the target voltage can become saturated at a certain level. For example, when a certain amount of charge depending on the test current is stored in the capacitor, the target voltage can be generated in response to the certain amount of charge stored in the capacitor.

[0077] The word line test circuit 300 can measure the target voltage. Different methods can be used to measure the analog target voltage. The measured analog target voltage can be converted into a digital value. In another example, when the analog value of the target voltage cannot be directly sensed, the time taken for the target voltage to decrease from its current level to a certain level is measured, and thus the target voltage can be indirectly measured.

[0078] In an embodiment, when the time taken for the target voltage to decrease to a certain level is measured, the word line test circuit 300 can discharge the charged target voltage. In addition, the word line test circuit 300 can count the cycles of a reference clock (not shown) from the time when the charged target voltage is discharged to the time when a predetermined period elapses.

[0079] The word line test circuit 300 can detect a defect in the target word line based on the count of the reference clock and at least one set reference count. The word line test circuit 300 can output data about the detection result.

[0080] Although not shown in the drawings, the storage device 1000 can further include a buffer memory. In an embodiment, the buffer memory can be implemented as a double data rate synchronous dynamic random access memory (DDR SDRAM), a low power double data rate fourth generation (LPDDR4) SDRAM, a graphics double data rate (GDDR) SDRAM, a low power DDR (LPDDR) SDRAM, a Rambus dynamic random access memory (RDRAM), a resistive RAM (RRAM), a phase change memory (PRAM), a magnetoresistive RAM (MRAM), a ferroelectric RAM (FRAM), or a spin transfer torque RAM (STT-RAM).

[0081] The host 400 can communicate with the storage device 1000 through an interface (not shown).

[0082] The interface can be implemented as a serial advanced technology attachment (SATA) interface, a fast SATA (SATAe) interface, a serial attached small computer system interface (SAS), a peripheral component interconnect express (PCIe) interface, a non-volatile memory express (NVMe) interface, an advanced host controller interface (AHCI) interface, or a multimedia card interface. However, the present application is not limited to any particular interface.

[0083] The host 400 can communicate with the storage device 1000 to store write data in the storage device 1000 or acquire read data stored in the storage device 1000.

[0084] In an embodiment, the host 400 can provide the storage device 1000 with a write request requesting the storage device 1000 to store write data. Also, the host 400 can provide the storage device 1000 with the write request, the write data, and a logical address for identifying the write data.

[0085] The storage device 1000 can store the write data provided from the host 400 in the memory device 100 in response to the write request provided from the host 400, and can provide the host 400 with a response indicating that the storage has been completed.

[0086] In an embodiment, the host 400 can provide the storage device 1000 with a read request requesting the storage device 1000 to provide data stored in the storage device 1000 to the host 400. Also, the host 400 can provide the storage device 1000 with the read request and a read address.

[0087] The storage device 1000 can read read data corresponding to the read address provided from the host 400 from the memory device 100 in response to the read request provided from the host 400, and can provide the host 400 with the read data as a response to the read request.

[0088] Figure 2 FIG. 1 is a diagram illustrating a memory device according to an embodiment of the disclosure.

[0089] Referring to Figure 1 and Figure 2 , the memory device 100 can include a memory cell array 110, a peripheral circuit 120, and control logic 130.

[0090] The memory cell array 110 can include a plurality of memory blocks MB1 to MBk (where k is a positive integer of 2 or more).

[0091] Each of the memory blocks MB1 to MBk can be coupled to a local line LL and bit lines BL1 to BLn (where n is a positive integer of 2 or more).

[0092] The local line LL can be coupled to the row decoder 122.

[0093] The local line LL can be coupled to each of the memory blocks MB1 to MBk.

[0094] Although not shown in the drawing, the local line LL can include a first selection line, a second selection line, and a plurality of word lines arranged between the first selection line and the second selection line.

[0095] Although not shown in the drawing, the local line LL can further include a dummy line disposed between the first selection line and the word line, a dummy line disposed between the second selection line and the word line, and a pipeline.

[0096] The bit lines BL1 to BLn can be commonly coupled to the memory blocks MB1 to MBk.

[0097] The memory blocks MB1 to MBk can be implemented as a two-dimensional (2D) or three-dimensional (3D) structure.

[0098] For example, the memory cells in the memory blocks MB1 to MBk having the 2D structure can be horizontally arranged on a substrate.

[0099] For example, the memory cells in the memory blocks MB1 to MBk having the 3D structure can be vertically stacked on a substrate.

[0100] The peripheral circuit 120 can include a voltage generator 121, a row decoder 122, a page buffer group 123, a column decoder 124, an input / output (I / O) circuit 125, and a sensing circuit 126.

[0101] The voltage generator 121 can generate various operation voltages Vop for a program operation, a read operation, and an erase operation in response to the operation command OP_CMD. In addition, the voltage generator 121 can selectively discharge the local line LL in response to the operation command OP_CMD. For example, the voltage generator 121 can generate a program voltage, a verify voltage, a pass voltage, a turn-on voltage, a read voltage, an erase voltage, a source line voltage, etc. under the control of the control logic 130.

[0102] In an embodiment, the voltage generator 121 can generate an internal power supply voltage by regulating an external power supply voltage. The internal power supply voltage generated by the voltage generator 121 can be used as an operation voltage of the memory device 100.

[0103] In an embodiment, the voltage generator 121 can generate a plurality of voltages using the external power supply voltage or the internal power supply voltage. For example, the voltage generator 121 can include a plurality of pumping capacitors for receiving the internal power supply voltage, and can generate a plurality of voltages by selectively enabling the plurality of pumping capacitors under the control of the control logic 130. The generated voltages can be provided to the memory cell array 110 by the row decoder 122.

[0104] In an embodiment, the voltage generator 121 can generate a test voltage using the external power supply voltage or the internal power supply voltage. For example, the voltage generator 121 can generate a test voltage based on the internal power supply voltage under the control of the control logic 130.

[0105] The test voltage generated by the voltage generator 121 can be provided to the row decoder 122.

[0106] Although not shown in the drawings, the test voltage can be a voltage generated using power supplied from an external power source (e.g., a battery) included in the storage device 1000.

[0107] The row decoder 122 can deliver the operation voltage Vop to the local line LL in response to the row address RADD. The operation voltage Vop can be delivered to the selected memory block (any one of MB1 to MBk) through the local line LL.

[0108] For example, during a program operation, the row decoder 122 can apply a program voltage to the selected word line and a program pass voltage having a level lower than that of the program voltage to the unselected word line. During a program verify operation, the row decoder 122 can apply a verify voltage to the selected word line and a verify pass voltage higher than the verify voltage to the unselected word line.

[0109] During a read operation, the row decoder 122 can apply a read voltage to the selected word line and a read pass voltage higher than the read voltage to the unselected word line.

[0110] During an erase operation, the row decoder 122 can select one memory block according to the decoded address. During the erase operation, the row decoder 122 can apply a ground voltage to the word line coupled to the selected memory block.

[0111] The row decoder 122 can deliver the test voltage to the local line LL in response to the row address RADD. The test voltage can be delivered to the memory blocks MB1 to MBk through the local line LL. The test voltage can be delivered to a target word line among a plurality of word lines included in each memory block.

[0112] The page buffer group 123 can include first to nth page buffers PB1 to PBn, which can be coupled to the memory cell array 110 through first to nth bit lines BL1 to BLn. The first to nth page buffers PB1 to PBn can be operated under the control of the control logic 130.

[0113] In detail, the first to nth page buffers PB1 to PBn can be operated in response to page buffer control signals PBSIGNALS. For example, the first to nth page buffers PB1 to PBn can temporarily store data received through the first to nth bit lines BL1 to BLn, or can sense a voltage or a current of the bit lines BL1 to BLn during a read operation or a verify operation.

[0114] During a program operation, when a program voltage is applied to a selected word line, the first page buffer PB1 through the nth page buffer PBn can transfer data DATA received through the column decoder 124 and the input / output circuit 125 to the selected memory cell through the first bit line BL1 through the nth bit line BLn. Based on the received data DATA, the memory cell in the selected page is programmed. The memory cell coupled to the bit line to which a program enable voltage (e.g., a ground voltage) is applied can have an increased threshold voltage. The threshold voltage of the memory cell coupled to the bit line to which a program inhibit voltage (e.g., a power supply voltage) is applied can be maintained.

[0115] During a verify operation, the first page buffer PB1 through the nth page buffer PBn can sense data stored in the selected memory cell from the selected memory cell through the first bit line BL1 through the nth bit line BLn.

[0116] During a read operation, the first page buffer PB1 through the nth page buffer PBn can sense data DATA from the memory cell in the selected page through the first bit line BL1 through the nth bit line BLn and can output the sensed data DATA to the input / output circuit 125 under the control of the column decoder 124.

[0117] During an erase operation, the first page buffer PB1 through the nth page buffer PBn can allow the first bit line BL1 through the nth bit line BLn to float.

[0118] The column decoder 124 can transfer data between the input / output circuit 125 and the page buffer group 123 in response to a column address CADD. For example, the column decoder 124 can exchange data with the page buffer PB1 through PBn through a data line DL, or can exchange data with the input / output circuit 125 through a column line CL.

[0119] The input / output circuit 125 can transfer a command CMD and an address ADD received from the memory controller 200 to the control logic 130, or can exchange data DATA with the column decoder 124.

[0120] Referring to Figure 1 and Figure 2 In an embodiment, the input / output circuit 125 can transfer a test command TCMD output from the memory controller 200 to the control logic 130.

[0121] During a read operation or a verify operation, the sensing circuit 126 can generate a reference current in response to an enable bit VRY_BIT<#> and can compare a sensing voltage VPB received from the page buffer group 123 with a reference voltage generated by the reference current and then output a pass signal PASS or a fail signal FAIL.

[0122] The control logic 130 can control the peripheral circuit 120 by outputting the operation command OP_CMD, the row address RADD, the page buffer control signals PBSIGNALS, and the enable bit VRY_BIT<#> in response to the command CMD and the address ADD.

[0123] Referring to Figure 1 and Figure 2 , the control logic 130 can provide the row address RADD corresponding to a target word line among a plurality of word lines to the row decoder 122 in response to a test command TCMD, and can provide the operation command OP_CMD indicating generation of a test voltage to the voltage generator 121.

[0124] Figure 3 is a diagram of an exemplary structure of a representative memory block (MBi) among a plurality of memory blocks Figure 2 .

[0125] Referring to Figure 3 , Figure 3 , the memory block MBi can be any one of the memory blocks MB1 to MBk. Figure 2

[0126] The memory block MBi can include a first selection line, a second selection line, a plurality of word lines WL1 to WL16, a source line SL, a plurality of bit lines BL1 to BLn, and a plurality of strings ST.

[0127] As assumed in the following description, the first selection line can be, for example, a source selection line SSL.

[0128] As assumed in the following description, the second selection line can be, for example, a drain selection line DSL.

[0129] The plurality of word lines WL1 to WL16 can be arranged in parallel between the source selection line SSL and the drain selection line DSL.

[0130] Figure 3 The number of the word lines WL1 to WL16 shown is exemplary; the present application is not limited to any particular number of word lines.

[0131] ​In general, the plurality of word lines WL1 to WL16 can be made of a metal material. The word lines WL1 to WL16 can have respective resistance values. Parasitic capacitors can exist between the plurality of word lines WL1 to WL16. Accordingly, when each of the operation voltage Vop or the test voltage is applied to the plurality of word lines WL1 to WL16, a current of a certain level flows through each of the word lines WL1 to WL16, and the current gradually decreases over time. In this case, the current can exponentially decrease from the certain level according to an RC time constant given by the resistance of the corresponding word line and the capacitance of the parasitic capacitor between the word lines.

[0132] Here, the resistance of the corresponding word line and the capacitance of the parasitic capacitor differ according to the size (e.g., width, thickness, height, etc.) of the word line, and thus the RC time constant determined thereby can differ according to the size of the word line. When the RC time constant varies for each word line, the level of the current flowing through the plurality of word lines WL1 to WL16 can vary. Also, when the RC time constant varies for each word line, the time taken for the current to decrease below a set level can also vary. In this case, when an operation voltage (e.g., a programming voltage) of the same level is applied to the word lines, the time taken to complete the operation (e.g., the time taken to complete a programming operation) can vary for each of the word lines WL1 to WL16.

[0133] Accordingly, it is necessary to manufacture all of the plurality of word lines WL1 to WL16 to have uniform sizes, but in actual manufacturing steps, one or more word lines among the plurality of word lines WL1 to WL16 can have sizes different from the target sizes. Each word line having a size different from the target size can be defined as a defective word line. The defective word line in the storage device 1000 can cause a decrease in its performance. Accordingly, it is necessary to detect the defective word line to prevent or reduce such degradation.

[0134] The source lines SL can be commonly coupled to the plurality of strings ST.

[0135] The plurality of bit lines BL1 to BLn can be coupled to the strings ST, respectively.

[0136] The plurality of strings ST can be coupled to the bit lines BL1 to BLn and the source lines SL.

[0137] Since each string ST can be configured to be the same, the string ST coupled to the first bit line BL1 is described in detail by way of example.

[0138] The string ST can include a plurality of memory cells MC1 to MC16, at least one first selection transistor, and at least one second selection transistor.

[0139] The memory cells MC1 to MC16 can be serially coupled to each other between the source select transistor SST and the drain select transistor DST.

[0140] The gates of the memory cells MC1 to MC16 can be coupled to the word lines WL1 to WL16, respectively. Accordingly, the number of the memory cells MC1 to MC16 included in one string ST can be equal to the number of the word lines WL1 to WL16.

[0141] Each of the plurality of memory cells MC1 to MC16 can be implemented as, for example, SLC, MLC, TLC, or QLC.

[0142] A group of memory cells among the memory cells included in different strings ST, which are coupled to the same word line, can be referred to as a "physical page (PG)". Accordingly, the memory block MBi can include the same number of physical pages (PG) as the word lines WL1 to WL16. Hereinafter, it is assumed that a memory cell (for example, MC3) included in a physical page (PG) is a selected memory cell.

[0143] As assumed in the following description, the first select transistor can be, for example, a source select transistor SST.

[0144] A first electrode of the source select transistor SST can be coupled to a source line SL. A second electrode of the source select transistor SST can be coupled to a first memory cell MC1 among the plurality of memory cells MC1 to MC16. A gate electrode of the source select transistor SST can be coupled to a source select line SSL.

[0145] As assumed in the following description, the second select transistor can be, for example, a drain select transistor DST.

[0146] A first electrode of the drain select transistor DST can be coupled to a sixteenth memory cell MC16 among the plurality of memory cells MC1 to MC16. A second electrode of the drain select transistor DST can be coupled to a first bit line BL1. A gate electrode of the drain select transistor DST can be coupled to a drain select line DSL.

[0147] Figure 4 FIG. 1 is a diagram illustrating a word line test circuit according to an embodiment of the disclosure.

[0148] Reference Signs Figure 4The word line test circuit 300 can receive a test command TCMD. The word line test circuit 300 can generate a test voltage in response to the test command TCMD. The word line test circuit 300 can generate a target voltage by storing a charge using the test voltage. The word line test circuit 300 can discharge the target voltage, and can generate a comparison signal COMPSIG based on a comparison result between the target voltage and a reference voltage. The word line test circuit 300 can detect a defect in a target word line based on a count of a reference clock and at least one set reference count, a period of the reference clock being counted until a level of the comparison signal COMPSIG changes from a first level to a second level.

[0149] The word line test circuit 300 can include an operation signal generator 310, a comparison result generator 320, and a word line defect detector 330.

[0150] The operation signal generator 310 can generate a plurality of operation signals OPSIG in response to the test command TCMD.

[0151] Each of the operation signals OPSIG can be a turn-on level signal.

[0152] In an embodiment, the operation signal generator 310 can generate first to third operation signals. Also, the operation signal generator 310 can sequentially output the first to third operation signals to the comparison result generator 320 based on a set timing.

[0153] In response to each of the plurality of operation signals OPSIG, the comparison result generator 320 can charge the target voltage based on a test current, a current of the target word line varying with the test voltage being reflected in the test current, and can generate the comparison signal COMPSIG based on a comparison result between the target voltage and a reference voltage.

[0154] In an embodiment, the test current can be less than the current of the target word line.

[0155] The comparison signal COMPSIG can be generated to be at a first level when the target voltage is equal to or greater than the reference voltage. The comparison signal COMPSIG can be generated to be at a second level when the target voltage is less than the reference voltage.

[0156] The reference voltage can be used to determine a time at which the count of the reference clock is to be stopped or terminated. The reference voltage can be set through design, experiment, etc. before a corresponding product is shipped, but the present application is not limited thereto. The reference voltage can also be updated after the product has been shipped.

[0157] According to an embodiment, the operation signal generator 310 can generate first to third operation signals. In this case, the comparison result generator 320 can charge the target voltage in response to the first operation signal. The comparison result generator 320 can discharge the charged target voltage in response to the second operation signal. The comparison result generator 320 can generate the comparison signal COMPSIG based on a comparison result between the discharged target voltage and the reference voltage in response to the third operation signal.

[0158] The word line defect detector 330 can count the period of the reference clock until the level of the comparison signal COMPSIG changes from the first level to the second level. Also, the word line defect detector 330 can detect a defect in the target word line based on the count of the reference clock and at least one reference count, which can be pre-set.

[0159] In an embodiment, the word line defect detector 330 can count the period of the reference clock until the level of the comparison signal COMPSIG changes from the first level to the second level, and can output a detection signal indicating a defect in the target word line according to whether the count of the reference clock is less than at least one reference count.

[0160] In an embodiment, a first reference count and a second reference count less than the first reference count can be pre-set. In this case, the word line defect detector 330 can count the reference clock until the level of the comparison signal COMPSIG changes from the first level to the second level, and can output a detection signal indicating that the target word line is normal according to whether the count of the reference clock falls within a range from the first reference count to the second reference count.

[0161] The word line defect detector 330 can output the data DATA as a test result TRST under the control of the memory controller 200.

[0162] The data DATA can be information indicating respective states of a plurality of word lines. Alternatively, the data DATA can be information about a defective word line.

[0163] The word line test circuit 300 according to an embodiment of the disclosure can be implemented using circuits included in each of the voltage generator 121, the row decoder 122, and the control logic 130 shown in FIG. 1. Figure 2 The word line test circuit 300 according to an embodiment of the disclosure can be implemented using circuits included in each of the voltage generator 121, the row decoder 122, and the control logic 130 shown in FIG. 1.

[0164] According to the above description, the word line test circuit according to an embodiment of the disclosure can prevent performance degradation of a storage device by detecting whether each word line has a defect.

[0165] Figure 5 is a diagram illustrating a comparison result generator according to an embodiment of the disclosure. Figure 4 is a diagram illustrating a comparison result generator according to an embodiment of the disclosure.

[0166] Referring to Figure 5 , the comparison result generator 320 can include a current detector 321, a voltage charger 322, a reference voltage generator 323, and a voltage comparator 324.

[0167] The current detector 321 can detect a test current Ic in response to an operation signal OPSIG generated by the operation signal generator 310. In detail, the current detector 321 can detect a test current Ic that is less than a current of a target word line using a test voltage Vtest in response to a first operation signal. The current detector 321 can deliver the detected test current Ic to the voltage charger 322.

[0168] The voltage charger 322 can charge a target voltage Vc to a voltage obtained by integrating the test current Ic with respect to time. That is, a magnitude of the target voltage Vc charged in the voltage charger 322 can be a result of integrating a magnitude of the test current Ic with respect to time. The voltage charger 322 can deliver the charged target voltage Vc to the voltage comparator 324.

[0169] The reference voltage generator 323 can generate a reference voltage Vref based on the test voltage Vtest. The reference voltage generator 323 can deliver the reference voltage Vref to the voltage comparator 324.

[0170] The voltage comparator 324 can output a comparison signal COMPSIG of a first level or a second level based on a comparison result between the target voltage Vc and the reference voltage Vref in response to the operation signal OPSIG generated by the operation signal generator 310. In detail, the voltage comparator 324 can discharge the target voltage Vc charged in the voltage charger 322 in response to a second operation signal, and can output the comparison signal COMPSIG of the first level or the second level based on a comparison result between the discharged target voltage Vc and the reference voltage Vref in response to a third operation signal.

[0171] The comparison signal COMPSIG can be generated to be at the first level when the target voltage Vc is equal to or greater than the reference voltage Vref. For example, the first level of the comparison signal COMPSIG can be a logic high.

[0172] The comparison signal COMPSIG can be generated to be at the second level when the target voltage Vc is less than the reference voltage Vref. For example, the second level of the comparison signal COMPSIG can be a logic low.

[0173] Figure 6 is an example Figure 4 of a word line defect detector.

[0174] Referring to Figure 6 The word line defect detector 330 can include a clock generator 331, a counter 332, a defect detector 333, a register 334, and a data buffer memory 335.

[0175] The clock generator 331 can generate a reference clock CLK. In detail, the clock generator 331 can generate the reference clock CLK in response to a test command TCMD. Alternatively, the clock generator 331 can generate the reference clock CLK when the storage device 1000 is powered on or booted.

[0176] The reference clock CLK can have a uniform pulse width and a uniform period between corresponding pulses.

[0177] The counter 332 can start counting pulses of the reference clock CLK in response to the comparison signal COMPSIG of the first level. The counter 332 can count the pulses of the reference clock CLK until the level of the comparison signal COMPSIG changes from the first level to the second level. The counter 332 can stop counting the reference clock CLK in response to the comparison signal COMPSIG of the second level.

[0178] In an example, rising edges of the reference clock CLK can be counted. Alternatively, pulses of the reference clock CLK can be counted. In general, the periods of the reference clock CLK can be counted in any suitable manner to generate the count CLK_CNT.

[0179] The counter 332 can provide a signal indicating CLK_CNT to the defect detector 333.

[0180] The defect detector 333 can receive the CLK_CNT signal. In addition, the defect detector 333 can receive a signal indicating at least one reference count CLK_REF.

[0181] The defect detector 333 can output a detection signal DET to the data buffer memory 335 based on CLK_CNT and the at least one reference count CNT_REF.

[0182] The detection signal DET can be data DATA regarding a detection result of a target word line.

[0183] In an embodiment, the defect detector 333 can output the detection signal DET indicating a defect in the target word line according to whether the count CLK_CNT of the reference clock CLK is less than one reference count.

[0184] In an implementation, the defect detector 333 can output a detection signal DET indicating that the target word line is normal, based on whether CLK_CNT falls within the range from the first reference count to the second reference count.

[0185] Register 334 can provide a signal indicating the reference count CNT_REF to defect detector 333.

[0186] The data buffer memory 335 can store data DATA, which is the detection result of the target word line from the detection signal DET. The data buffer memory 335 can output data DATA under the control of the memory controller 200.

[0187] Figure 7 This is an example Figure 5 The circuit diagram of the implementation of the comparison result generator.

[0188] Reference Figure 7 In an implementation, the current detector 321 included in the comparison result generator 320 may include a control current source CS1, a current mirror CM, and a switching assembly SW.

[0189] A control current source CS1 can provide a control current Ia. The first electrode of the control current source CS1 can be connected to the first node N1, and the second electrode of the control current source CS1 can be connected to the second node N2. The control current Ia can flow from the first node N1 to the second node N2.

[0190] The current mirror CM can output the current Is of the target word line, and can also output the current Ic obtained by reducing the current Is of the target word line to the value of the control current Ia.

[0191] In an implementation, the current mirror CM may include a first transistor Tr1 and a second transistor Tr2, whose gate electrodes are connected together.

[0192] The first electrode of the first transistor Tr1 is connected to the first node N1 to which the test voltage Vtest is applied, the second electrode of the first transistor Tr1 is connected to the second node N2, and the gate electrode of the first transistor Tr1 is connected to the second node N2.

[0193] The first electrode of the second transistor Tr2 is connected to the first node N1, the second electrode of the second transistor Tr2 is connected to the third node N3, and the gate electrode of the second transistor Tr2 is connected to the second node N2.

[0194] like Figure 7 As shown, the first transistor Tr1 and the second transistor Tr2 according to the embodiment can be, but are not limited to, P-type transistors, and an N-type transistor can be used to implement the current mirror CM.

[0195] The current Is of the target word line can flow from the second node N2 to the switch component SW.

[0196] The test current Ic can flow from the first node N1 to the third node N3.

[0197] Figure 7 The current mirror CM shown is merely an example, and the present application is not limited to Figure 7 the current mirror shown.

[0198] The switch component SW can electrically couple the current mirror CM to the target word line in response to the first operation signal OPSIG1.

[0199] Here, the target word line can be selected from among a plurality of word lines. The plurality of word lines can be coupled to the local line LL. The local line LL can be coupled to the row decoder 122, for example, a global word line (not shown) or a local word line (not shown) included in the row decoder 122. Accordingly, when the current mirror CM is electrically coupled to the target word line, the current mirror CM is electrically coupled to the row decoder 122.

[0200] In an embodiment, the switch component SW can include a third transistor Tr3 that is turned on in response to the first operation signal OPSIG1. However, the present application is not limited thereto. Although the following description is made in the context in which the switch component SW includes a transistor, SW can be implemented in a suitable manner consistent with the teachings herein.

[0201] A first electrode of the third transistor Tr3 can be coupled to the second node N2, a second electrode of the third transistor Tr3 can be coupled to the row decoder 122, and the first operation signal OPSIG1 can be supplied to a gate electrode of the third transistor Tr3. In an embodiment, the second electrode of the third transistor Tr3 can be coupled to a global word line or a local word line included in the row decoder 122.

[0202] Figure 7 The current detector 321 shown is merely an example of a configuration that detects the test current Ic, and the present application is not limited to Figure 7 the circuit shown. More generally, any type of circuit consistent with the teachings herein can be used to implement the current detector 321.

[0203] In an embodiment, the voltage charger 322 included in the comparison result generator 320 can include a capacitor Cint.

[0204] The capacitor Cint can be charged to a target voltage Vc using the test current Ic output from the current detector 321. A first electrode of the capacitor Cint can be coupled to the third node N3, and a second electrode of the capacitor Cint can be coupled to an electrode having a lower potential than the potential of the test voltage Vtest, for example, ground. The following description is made based on the assumption that the electrode having a lower potential than the potential of the test voltage Vtest is ground. However, the present application is not limited to this configuration.

[0205] In an embodiment, the target voltage Vc charged in the capacitor Cint can be a voltage obtained by integrating the test current Ic with respect to time.

[0206] The target voltage Vc can be applied to the third node N3.

[0207] Figure 7 The voltage charger 322 shown is merely an example of a configuration in which the target voltage Vc is generated by integrating the test current Ic, and the present application is not limited to Figure 7 the circuit shown. The voltage charger 322 can be implemented using any suitable circuit to perform the functions described therefor, for example, a circuit in which an amplifier (not shown) is additionally included in the voltage charger 322.

[0208] In an embodiment, the reference voltage generator 323 included in the comparison result generator 320 can include a reference current source CS2 and a reference resistor Rref.

[0209] The reference current source CS2 can supply a reference current Iref. A first electrode of the reference current source CS2 can be coupled to the first node N1, and a second electrode of the reference current source CS2 can be coupled to the fourth node N4. The reference current Iref can flow from the first node N1 to the reference resistor Rref.

[0210] The reference resistor Rref can have a reference resistance value. The reference resistor Rref can be coupled in series to the reference current source CS2. A first electrode of the reference resistor Rref can be coupled to the reference current source CS2, and a second electrode of the reference resistor Rref can be coupled to ground.

[0211] A reference voltage Vref can be generated at the reference resistor Rref as the reference current Iref flows through the reference resistor Rref. The reference voltage Vref can be applied to the fourth node N4.

[0212] Figure 7 The reference voltage generator 323 shown is merely an example of a configuration in which the reference voltage Vref is generated, and the present application is not limited to Figure 7The reference voltage generator 323 can be implemented using any suitable circuit capable of generating Vref, such as a reference voltage source.

[0213] The voltage comparator 324 included in the comparison result generator 320 can include a flush current source CS3, a discharge control switch assembly Tr4, and a comparator COMP.

[0214] The flush current source CS3 can output a flush current Id. The flush current source CS3 can be coupled in parallel to the capacitor Cint. A first electrode of the flush current source CS3 can be coupled to the third node N3, and a second electrode of the flush current source CS3 can be coupled to the discharge control switch assembly Tr4.

[0215] The flush current Id can be used to discharge a target voltage Vc charged in the voltage charger 322. The flush current Id can flow from the third node N3 to ground through the switch assembly Tr4.

[0216] The discharge control switch assembly Tr4 can electrically couple the flush current source CS3 to ground in response to a second operation signal OPSIG2. The discharge control switch assembly Tr4 can be coupled in series to the flush current source CS3.

[0217] In an embodiment, the discharge control switch assembly Tr4 can be a fourth transistor. However, the present application is not limited to this configuration. The following description is based on the assumption that the discharge control switch assembly Tr4 is a P-type transistor.

[0218] A first electrode of the discharge control switch assembly Tr4 can be coupled to the flush current source CS3, a second electrode of the discharge control switch assembly Tr4 can be coupled to ground, and a second operation signal OPSIG2 can be provided to a gate electrode of the discharge control switch assembly Tr4.

[0219] The discharge control switch assembly Tr4 can be turned on in response to the second operation signal OPSIG2.

[0220] The comparator COMP can be turned on in response to a third operation signal OPSIG3. The comparator COMP can receive the target voltage and the reference voltage, and can output a comparison signal COMPSIG of a first level or a second level based on a comparison result between the target voltage and the reference voltage. A first input terminal of the comparator COMP can be coupled to the third node N3, a second input terminal of the comparator COMP can be coupled to the fourth node N4, the third operation signal OPSIG3 can be provided to a power input terminal of the comparator COMP, and an output terminal of the comparator COMP can be electrically coupled to the word line defect detector 330.

[0221] In an embodiment, the first input terminal can be a non-inverting terminal, and the second input terminal can be an inverting terminal.

[0222] In an embodiment, the first input terminal of the comparator COMP can be a positive electrode, and the second input terminal of the comparator COMP can be a negative electrode.

[0223] In an embodiment, the comparator COMP can output the comparison signal COMPSIG of the first level when the target voltage of the discharging is equal to or greater than the reference voltage, and can output the comparison signal COMPSIG of the second level when the target voltage of the discharging is less than the reference voltage.

[0224] In an embodiment, the comparator COMP can output the comparison signal COMPSIG of the first level when the third operation signal OPSIG3 is received. Further, the comparator COMP can output the comparison signal COMPSIG of the second level after the comparison signal COMPSIG of the first level has been output.

[0225] In an embodiment, the second operation signal OPSIG2 and the third operation signal OPSIG3 can be output after the first operation signal OPSIG1 has been output.

[0226] Figure 7 The voltage comparator 324 illustrated is merely an example of a configuration that compares the target voltage Vc with the reference voltage Vref and outputs a comparison result, and the present application is not limited to Figure 7 the circuit illustrated. The voltage comparator 324 can be implemented using any suitable circuit.

[0227] Figure 8 is a diagram illustrating a variation of the comparison result generator. Figure 7

[0228] In describing the comparison result generator illustrated in Figure 8 , components identical to those in Figure 7 will not be described.

[0229] Referring to Figure 8 , the switching component SW included in the current detector 321 can include a third transistor Tr3 and a fifth transistor Tr5, gate electrodes of which are commonly coupled to each other.

[0230] The third transistor Tr3 is identical to the third transistor Tr3 illustrated in Figure 7 .

[0231] ​The first electrode of the fifth transistor Tr5 is coupled to the fifth node N5, and the second electrode of the second transistor Tr2 is coupled to the fifth node N5. The second electrode of the fifth transistor Tr5 is coupled to the third node N3. The gate electrode of the fifth transistor Tr5 can be coupled to the sixth node N6. The first operation signal OPSIG1 is applied to the sixth node N6.

[0232] The circuit shown is merely an example, and the present application is not limited to Figure 7 the circuit shown. Figure 8 Figure 8

[0233] Figure 9 is a graph illustrating an example of the current of the target word line.

[0234] Referring to Figure 7 and Figure 9 At the first time t1, the first operation signal OPSIG1 can be supplied to the current detector 321. The test voltage Vtest can be applied to the target word line. The current Is of the target word line can increase to a certain level at the first time t1.

[0235] At the first time t1, the level of the current Is(defect) of the defective target word line can be lower than the level of the current Is(normal) of the normal target word line.

[0236] After the first time t1, the current Is of the target word line can decrease non-linearly. Here, the degree of non-linear decrease of the current Is of the target word line can differ depending on the RC time constant.

[0237] After the first time t1, the RC time constant corresponding to the defective target word line can be greater than the RC time constant corresponding to the normal target word line. Accordingly, based on the same period of time, the decrease of the current Is(defect) of the defective target word line can be less than the decrease of the current Is(normal) of the normal target word line.

[0238] The defect in the word line can also be detected by comparing the amount of decrease of the current Is(defect) of the defective target word line with the amount of decrease of the current Is(normal) of the normal target word line and determining the difference therebetween. However, the difference between the amount of decrease corresponding to the defective state and the amount of decrease corresponding to the normal state can not be large. Accordingly, the word line test circuit 300 according to the embodiment of the disclosure can detect the defect in the word line using the target voltage Vc corresponding to the voltage obtained by integrating the current Is of the target word line with respect to time, i.e., the target voltage Vc charged in the capacitor Cint.

[0239] ​​At the second time t2, the level of the current Is of the target word line can reach the level of the control current Ia. The control current Ia is applied in order to clearly detect the difference between the target voltage Vc charged by the current Is (defective) of the defective target word line and the target voltage Vc charged by the current Is (normal) of the normal target word line.

[0240] The control current Ia can be set through experiments, designs, algorithms, etc., and indicated before the corresponding product is shipped. However, the control current can also be updated after the corresponding product is shipped.

[0241] The interval from the first time t1 to the second time t2 can be determined according to the control current Ia.

[0242] Figure 10 is a graph illustrating an exemplary target voltage.

[0243] Referring to Figure 7 and Figure 10 The target voltage Vc can be charged when the current Is of the target word line is generated at the first time t1 and the test current Ic is supplied to the capacitor Cint during the interval from the first time t1 to the second time t2. The target voltage Vc can be increased non-linearly.

[0244] At the second time t2, the target voltage Vc can saturate to a certain level.

[0245] As shown in Figure 9 , since the integral (integral) value of the current Is (defective) of the defective target word line during the interval from the first time t1 to the second time t2 is less than the integral value of the current Is (normal) of the normal target word line, the target voltage Vc (defective) corresponding to the defective target word line can be lower than the target voltage Vc (normal) corresponding to the normal target word line.

[0246] Figure 11 is a graph illustrating an embodiment in which the period of a reference clock is counted.

[0247] Referring to Figure 7 and Figure 11 At a third time t3 after the second time t2, a second operation signal OPSIG2 and a third operation signal OPSIG3 can be supplied to the voltage comparator 324. The voltage comparator 324 can discharge the charged target voltage Vc in response to the second operation signal OPSIG2. In addition, the voltage comparator 324 can compare the discharged target voltage Vc with the reference voltage Vref in response to the third operation signal OPSIG3 and can output a comparison signal COMPSIG based on the comparison result.

[0248] At the third time t3, the target voltage Vc can start discharging, and the level of the target voltage Vc can be higher than the level of the reference voltage Vref. The voltage comparator 324 can output the comparison signal COMPSIG at the first level to the word line defect detector 330 at the time (e.g., the third time t3) when the target voltage Vc starts discharging. The word line defect detector 330 can count the cycles of the reference clock CLK in response to the comparison signal COMPSIG at the first level.

[0249] At the third time t3, the voltage comparator 324 can receive the third operation signal OPSIG3, where the level of the target voltage Vc can be higher than the level of the reference voltage Vref. The voltage comparator 324 can output the comparison signal COMPSIG at the first level to the word line defect detector 330 at the time (e.g., the third time t3) when the third operation signal OPSIG3 is received. The word line defect detector 330 can count the cycles of the reference clock CLK in response to the comparison signal COMPSIG at the first level.

[0250] At the fourth time t4, the level of the target voltage Vc (defective) corresponding to the defective target word line is lower than the level of the reference voltage Vref, and thus the voltage comparator 324 can output the comparison signal COMPSIG at the second level to the word line defect detector 330. The word line defect detector 330 can stop counting the cycles of the reference clock CLK in response to the comparison signal COMPSIG at the second level, and can store the count CLK_CNT corresponding to the defective target word line.

[0251] At the fourth time t4, the level of the target voltage Vc (normal) corresponding to the normal target word line is higher than the level of the reference voltage Vref, and thus the word line defect detector 330 can continue counting the reference clock CLK in response to the comparison signal COMPSIG at the first level.

[0252] At the fifth time t5, the level of the target voltage Vc (normal) corresponding to the normal target word line is lower than the level of the reference voltage Vref, and thus the word line defect detector 330 can stop counting the cycles of the reference clock CLK in response to the comparison signal COMPSIG at the second level, and can store the count CLK_CNT corresponding to the normal target word line.

[0253] The word line defect detector 330 can store the counts CLK_CNT corresponding to the plurality of word lines (e.g., the word lines WL1 to WL16) respectively. Figure 3 The word line defect detector 330 can store the counts CLK_CNT corresponding to the plurality of word lines (e.g., the word lines WL1 to WL16) respectively.

[0254] In an embodiment, the defect detector 333 can store the counts CLK_CNT corresponding to one memory block (e.g., the memory block 320) respectively. Figure 3The plurality of word lines (e.g., word lines WL1 to WL16) in the storage block MBi) shown in FIG. 6 correspond to the counts CLK_CNT. Figure 3 The count CLK_CNT corresponding to the first word line (e.g., WL1) in the storage block (e.g., storage blocks MB1 to MBk) shown in FIG. 6 is stored in the defect detector 333.

[0255] In an embodiment, the defect detector 333 can store the counts CLK_CNT corresponding to the plurality of word lines (e.g., the plurality of word lines WL1 to WL16) in each of the storage blocks (e.g., the storage blocks MB1 to MBk) shown in FIG. 6. Figure 2 The count CLK_CNT corresponding to the first word line (e.g., WL1) in the storage block (e.g., storage blocks MB1 to MBk) shown in FIG. 6 is stored in the defect detector 333. Figure 3 The count CLK_CNT corresponding to the first word line (e.g., WL1) in the storage block (e.g., storage blocks MB1 to MBk) shown in FIG. 6 is stored in the defect detector 333. Here, the first word line is WL1, but this is merely an example, and the present application is not limited thereto.

[0256] In an embodiment, the defect detector 333 can store the counts CLK_CNT corresponding to the plurality of word lines (e.g., the plurality of word lines WL1 to WL16) in each of the storage blocks (e.g., the storage blocks MB1 to MBk) shown in FIG. 6. Figure 2 The count CLK_CNT corresponding to the first word line (e.g., WL1) in the storage block (e.g., storage blocks MB1 to MBk) shown in FIG. 6 is stored in the defect detector 333. Figure 3 The count CLK_CNT corresponding to the first word line (e.g., WL1) in the storage block (e.g., storage blocks MB1 to MBk) shown in FIG. 6 is stored in the defect detector 333. Here, the first word line is WL1, but this is merely an example, and the present application is not limited thereto.

[0257] Figure 12 is a diagram illustrating an embodiment of a method of detecting defects in a plurality of word lines included in one storage block.

[0258] Referring to Figure 12 The counts CLK_CNT corresponding to the plurality of word lines WL1 to WLi (where i is a positive integer greater than k) in one storage block can be stored in the defect detector 333. Figure 12 An embodiment of the method of FIG. 6 uses one reference count CNT_REF.

[0259] The defect detector 333 can determine whether any one of the counts CLK_CNT is less than the reference count.

[0260] For example, as shown in FIG. 6, the count CLK_CNT corresponding to the k-th word line WLk among the plurality of word lines WL1 to WLi is less than the reference count CNT_REF. Figure 12 The defect detector 333 detects each word line corresponding to the count CLK_CNT less than the reference count CNT_REF as a defective word line.

[0261] In an embodiment of the method of FIG. 6, the k-th word line WLk is detected as defective.

[0262] Figure 12 is a diagram illustrating an embodiment of a method of detecting defects in a plurality of word lines included in one storage block.

[0263] Figure 13 Referring to

[0264] In an embodiment of the method of FIG. 6, the k-th word line WLk is detected as defective. Figure 13 ​The counts CLK_CNT corresponding to the plurality of word lines WL1 to WLi in one memory block can be stored in the defect detector 333.

[0265] Any of the plurality of word lines can be manufactured to have a size that is greater or less than a target size. Each word line having a size different from the desired size can be determined to be a defective word line. Therefore, in order to detect a word line having a size different from the target size, two reference values are used to define a target size range.

[0266] Therefore, the defect detector 333 can determine whether there is any count CLK_CNT falling within a range from a first reference count CNT_REF1 to a second reference count CNT_REF2. Here, the range from the first reference count CNT_REF1 to the second reference count CNT_REF2 can be defined as a reference range.

[0267] In Figure 13 an embodiment, the CLK_CNT corresponding to the k-th word line WLk and the CLK_CNT corresponding to the i-th word line WLi do not fall within the reference range. Except for these two counts, the counts of each of the other word lines fall within the reference range.

[0268] The defect detector 333 determines a word line corresponding to a count CLK_CNT falling within the reference range to be normal. The defect detector 333 determines a word line corresponding to a count CLK_CNT falling outside the reference range to be defective.

[0269] In Figure 13 an embodiment, the k-th word line WLk and the i-th word line WLi are detected to be defective.

[0270] Figure 14 is a diagram illustrating an embodiment of a method of detecting a defect in a specific word line in each of a plurality of memory blocks.

[0271] Referring to Figure 14 , counts CLK_CNT corresponding to first word lines WL1 included in a plurality of memory blocks MB1 to MBi, respectively, can be stored in the defect detector 333.

[0272] As described above with reference to Figure 12 , the defect detector 333 can determine whether there is any first word line count less than a reference count CNT_REF. Further, the defect detector 333 detects each word line corresponding to a count CLK_CNT less than the reference count CNT_REF to be a defective word line.

[0273] For example, in Figure 14In this case, the defect detector 333 detects that the first word line WL1 in the k-th memory block MBk is a defective word line.

[0274] Although the first word line WL1 is used as an example in the description, Figure 14 the method can be applied to any set of similar-positioned word lines in a memory block, such as the sixth word line WL6.

[0275] Although not shown in the drawings, as Figure 13 indicated, the defect detector 333 can detect a defect in a target word line based on the count CLK_CNT and the reference range.

[0276] Figure 15 is a flowchart illustrating a method of detecting a defect in a word line according to an embodiment of the disclosure.

[0277] Referring to Figure 15 , in operation S110, the memory device 100 can apply a test voltage Vtest to a selected target word line. In detail, the memory device 100 generates the test voltage Vtest in response to a test command TCMD output from the memory controller 200 and applies the test voltage Vtest to the target word line.

[0278] In operation S120, the memory device 100 charges the target voltage Vc using the test voltage Vtest. In detail, the memory device 100 can generate a current Is of the target word line, which varies with the test voltage Vtest, and can charge the capacitor Cint to the target voltage Vc based on a test current Ic in which the current Is of the target word line is reflected.

[0279] The memory device 100 can discharge the charged target voltage Vc in operation S130 and can start counting periods of a reference clock CLK. In detail, the memory device 100 discharges the charged target voltage Vc using a flush current Id, and starts counting periods of the reference clock CLK from a time at which the target voltage Vc is discharged.

[0280] In operation S140, the memory device 100 determines whether the discharged target voltage Vc is less than a reference voltage Vref.

[0281] When the discharged target voltage Vc is equal to or greater than the reference voltage Vref (No in operation S140), the memory device 100 continues counting periods of the reference clock CLK in operation S150.

[0282] When the target voltage Vc of the discharge is less than the reference voltage Vref (Yes in operation S140), the memory device 100 detects a defect in the target word line based on the count CLK_CNT and the reference count CNT_REF in operation S160, and stores data DATA about the detection result in operation S170.

[0283] Figure 16 FIG. is a diagram illustrating a memory controller according to an embodiment of the disclosure.

[0284] Referring to Figure 1 and Figure 16 , the memory controller 200 can include a processor 210, a RAM 220, an error correction circuit 230, a ROM 260, a host interface 270, and a flash memory interface 280.

[0285] The processor 210 can control overall operations of the memory controller 200.

[0286] The RAM 220 can serve as a working memory, a buffer memory, or a cache memory of the memory controller 200. In an example, the buffer memory can be the RAM 220, and can be, for example, an SRAM.

[0287] The ROM 260 can store various types of information for operations of the memory controller 200 in the form of firmware.

[0288] The memory controller 200 can communicate with an external device (for example, the host 400, an application processor, etc.) through the host interface 270.

[0289] The memory controller 200 can communicate with the memory device 100 through the flash memory interface 280. The memory controller 200 can transmit a command CMD, an address ADDR, a control signal CTRL, etc. to the memory device 100 and receive data DATA from the memory device 100 through the flash memory interface 280.

[0290] The flash memory interface 280 can include, for example, a NAND interface.

[0291] Figure 17 FIG. is a block diagram illustrating a memory card system to which a storage device is applied according to an embodiment of the disclosure.

[0292] Referring to Figure 1 and Figure 17 , the memory card system 2000 can include a memory device 2100, a memory controller 2200, and a connector 2300.

[0293] In an embodiment, the memory device 2100 can be implemented as any one of various nonvolatile memory devices such as an electrically erasable programmable ROM (EEPROM), a NAND flash memory, a NOR flash memory, a phase change RAM (PRAM), a resistive RAM (ReRAM), a ferroelectric RAM (FRAM), and / or a spin transfer torque magnetic RAM (STT-MRAM).

[0294] The memory controller 2200 is coupled to the memory device 2100. The memory controller 2200 can access the memory device 2100. For example, the memory controller 2200 can control read operations, write operations, erase operations, and background operations of the memory device 2100. The memory controller 2200 can provide an interface between the memory device 2100 and the host 400. The memory controller 2200 can execute firmware for controlling the memory device 2100. The memory controller 2200 can be implemented in the same manner as the memory controller 200 of FIG. 1. Figure 1

[0295] In an embodiment, the memory controller 2200 can include components such as a RAM, a processor, a host interface, a memory interface, and an error correction circuit.

[0296] The memory controller 2200 can communicate with an external device through the connector 2300. The memory controller 2200 can communicate with an external device (e.g., the host 400) based on a specific communication protocol. In an embodiment, the memory controller 2200 can communicate with an external device through at least one of various interface protocols such as a universal serial bus (USB), a multimedia card (MMC), an embedded MMC (eMMC), a peripheral component interconnect (PCI), a fast PCI (PCI-E), an advanced technology attachment (ATA) protocol, a serial ATA (SATA), a parallel ATA (PATA), a small computer system interface (SCSI), an enhanced small disk interface (ESDI), an integrated drive electronics (IDE), FireWire, universal flash storage (UFS), WiFi, Bluetooth, and / or a non-volatile memory express (NVMe) protocol. In an embodiment, the connector 2300 can be defined by at least one of the above-described various communication protocols.

[0297] The memory device 2100 and the memory controller 2200 can be integrated into a single semiconductor device to form a memory card such as a personal computer memory card international association (PCMCIA), a compact flash card (CF), a smart media card (SM or SMC), a memory stick, a multimedia card (MMC, RS-MMC, micro- MMC, or eMMC), an SD card (SD, mini-SD, micro-SD, or SDHC), a universal flash storage (UFS), etc. ​

[0298] Figure 18 is a block diagram illustrating a solid state drive (SSD) system to which a storage device is applied, according to an embodiment of the disclosure.

[0299] Referring to Figure 1 and Figure 18 , the SSD system can include a host 400 and an SSD 3000.

[0300] The SSD 3000 can exchange a signal SIG with the host 400 through a signal connector 3001, and can receive power PWR through a power connector 3002. The SSD 3000 can include an SSD controller 3200, a plurality of flash memories 3100_1, 3100_2, and 3100_n, an auxiliary power supply 3300, and a buffer memory 3400.

[0301] According to an embodiment of the disclosure, the SSD controller 3200 can perform the functions of the memory controller 200 of Figure 1 .

[0302] The SSD controller 3200 can control the plurality of flash memories 3100_1, 3100_2, and 3100_n in response to the signal SIG received from the host 400. In an embodiment, the signal SIG can be defined based on an interface of the host 400 and the SSD 3000. For example, the signal SIG can be defined by at least one of various interfaces such as a universal serial bus (USB), a multimedia card (MMC), an embedded MMC (eMMC), a peripheral component interconnect (PCI), a fast PCI (PCI-E), an advanced technology attachment (ATA), a serial ATA (SATA), a parallel ATA (PATA), a small computer system interface (SCSI), an enhanced small disk interface (ESDI), an integrated drive electronics (IDE), FireWire, universal flash storage (UFS), WiFi, Bluetooth, and / or a non-volatile memory express (NVMe) interface.

[0303] The auxiliary power supply 3300 can be coupled to the host 400 through the power connector 3002. The auxiliary power supply 3300 can be provided with the power PWR from the host 400 and charged by the power PWR from the host 400. When the power supply from the host 400 is not smoothly delivered, the auxiliary power supply 3300 can provide power of the SSD 3000. In an embodiment, the auxiliary power supply 3300 can be located inside the SSD 3000 or located outside the SSD 3000. For example, the auxiliary power supply 3300 can be located in a main board and can also provide an auxiliary power supply to the SSD 3000.

[0304] The buffer storage 3400 can temporarily store data. For example, the buffer storage 3400 can temporarily store data received from the host 400 or data received from the plurality of flash memories 3100_1, 3100_2, and 3100_n, or can temporarily store metadata (e.g., a mapping table) of the flash memories 3100_1, 3100_2, and 3100_n. The buffer storage 3400 can include any one of various volatile memories such as DRAM, SDRAM, DDR SDRAM, LPDDR SDRAM, and GRAM or any one of various non-volatile memories such as FRAM, ReRAM, STT-MRAM, and PRAM.

[0305] Figure 19 is a block diagram illustrating a user system to which a storage device is applied according to an embodiment of the disclosure.

[0306] Referring to Figure 19 , the user system 4000 can include an application processor 4100, a memory module 4200, a network module 4300, a storage module 4400, and a user interface 4500.

[0307] The application processor 4100 can execute components included in the user system 4000, an operating system (OS), or a user program. In an embodiment, the application processor 4100 can include a controller, an interface, a graphic engine, etc. for controlling components included in the user system 4000. The application processor 4100 can be provided in the form of a system on chip (SoC).

[0308] The memory module 4200 can serve as a main memory, a working memory, a buffer storage, or a cache memory of the user system 4000. The memory module 4200 can include any one of various volatile RAMs such as DRAM, SDRAM, DDR SDRAM, DDR2 SDRAM, DDR3 SDRAM, LPDDR SDARM, LPDDR2 SDRAM, and LPDDR3 SDRAM or any one of various non-volatile RAMs such as PRAM, ReRAM, MRAM, and FRAM. In an embodiment, the application processor 4100 and the memory module 4200 can be packaged based on a package on package (POP), and then can be provided as a single semiconductor package.

[0309] The network module 4300 can communicate with an external device. In an embodiment, the network module 4300 can support wireless communication such as code division multiple access (CDMA), global system for mobile communication (GSM), wideband CDMA (WCDMA), CDMA-2000, time division multiple access (TDMA), long term evolution (LTE), Wimax, WLAN, UWB, Bluetooth, or WiFi. In an embodiment, the network module 4300 can be included in the application processor 4100.

[0310] The storage module 4400 can store data. For example, the storage module 4400 can store data received from the application processor 4100. Alternatively, the storage module 4400 can transmit data stored in the storage module 4400 to the application processor 4100. In an embodiment, the storage module 4400 can be implemented as a non-volatile semiconductor memory device such as phase-change RAM (PRAM), magnetic RAM (MRAM), resistive RAM (RRAM), NAND flash, NOR flash, or NAND flash having a 3D structure. In an embodiment, the storage module 4400 can be provided as a detachable storage medium (detachable drive) such as an external drive or a memory card of the user system 4000.

[0311] In an example, the storage module 4400 can be operated in the same manner as the storage device 1000 of Figure 1 The storage module 4400 can include a plurality of non-volatile memory devices, each of which can be operated in the same manner as the memory device 100 of Figure 1

[0312] The user interface 4500 can include an interface that inputs data or instructions to the application processor 4100 or outputs data to an external device. In an embodiment, the user interface 4500 can include a user input interface such as a keypad, a key pad, a button, a touch panel, a touch screen, a touch pad, a touch ball, a camera, a microphone, a gyro sensor, a vibration sensor, and a piezo element. The user interface 4500 can further include a user output interface such as a liquid crystal display (LCD), an organic light emitting diode (OLED) display device, an active matrix OLED (AMOLED) display device, an LED, a speaker, and / or a monitor.

[0313] As described above, according to an embodiment of the disclosure, there is an advantage in that a defect in a word line can be detected, and thus performance deterioration of a storage device can be prevented.

[0314] According to an embodiment of the disclosure, a storage device that detects a defect in a word line, and thus prevents performance deterioration of the storage device is provided. ​

[0315] While the application has been illustrated and described in the context of particular embodiments, it will be understood by those skilled in the art that various changes in form and detail can be made therein without departing from the teachings of the present disclosure. The application encompasses all such variations as fall within the scope of the claims.

[0316] Cross Reference to Related Applications

[0317] This application claims priority to Korean Patent Application No. 10-2020-0101386, filed on August 12, 2020, the entire disclosure of which is incorporated herein by reference.

Claims

1. A word line test circuit, the word line test circuit comprising: an operation signal generator that generates a plurality of operation signals in response to a test command; a comparison result generator that generates a target voltage based on a test current in response to the plurality of operation signals, and generates a comparison signal based on a comparison result between the target voltage and a reference voltage, a current of a target word line varying with a test voltage being reflected in the test current; and a word line defect detector that detects a defect in the target word line based on at least one reference count and a count of a reference clock, a period of the reference clock being counted until a level of the comparison signal changes from a first level to a second level. The comparison result generator includes:

2. The word line test circuit of claim 1, wherein, a current detector that detects the test current in response to a first operation signal among the plurality of operation signals; a voltage charger that charges the target voltage; a reference voltage generator that generates the reference voltage based on the test voltage; and a voltage comparator that discharges the target voltage in response to a second operation signal among the plurality of operation signals, and outputs the comparison signal based on the comparison result between the target voltage and the reference voltage in response to a third operation signal among the plurality of operation signals, wherein the test current is a current smaller than the current of the target word line, and wherein the target voltage is a result of integrating the test current with respect to time. The current detector includes:

3. The word line test circuit of claim 2, wherein, a control current source that provides a control current; a current mirror that outputs the test current, the test current being smaller than the current of the target word line by a magnitude of the control current; and a switch assembly that electrically couples the target word line to the current mirror in response to the first operation signal. The voltage charger includes:

4. The word line test circuit of claim 2, wherein, a capacitor that charges the target voltage using the test current. The reference voltage generator includes:

5. The word line test circuit of claim 2, wherein, a reference current source that provides a reference current; and a reference resistor that is coupled in series with the reference current source. The voltage comparator:

6. The word line test circuit of claim 2, wherein, generates the comparison signal of the first level at a time at which the target voltage starts to be discharged, and outputs the comparison signal of the second level at a time at which the target voltage becomes smaller than the reference voltage. The voltage comparator:

7. The word line test circuit of claim 2, wherein, receives the target voltage through a first input terminal, receives the reference voltage through a second input terminal, outputs the comparison signal of the first level when the target voltage is equal to or greater than the reference voltage, and outputs the comparison signal of the second level when the target voltage is smaller than the reference voltage. The operation signal generator outputs the second operation signal and the third operation signal after outputting the first operation signal, 8. The word line test circuit of claim 2, wherein, ​ The voltage comparator outputs the comparison signal of the first level at a time when the third operation signal is received.

9. The word line test circuit of claim 1, wherein, The word line defect detector includes: a clock generator that generates the reference clock; a counter that starts counting the reference clock in response to the comparison signal of the first level and stops the counting in response to the comparison signal of the second level; and a defect detector that outputs a detection signal indicating a defect in the target word line according to whether the count of the reference clock is less than the at least one reference count.

10. The word line test circuit of claim 1, wherein the at least one reference count includes a first reference count and a second reference count that is less than the first reference count, and the word line defect detector includes: a clock generator that generates the reference clock; a counter that starts counting the reference clock in response to the comparison signal of the first level and stops the counting in response to the comparison signal of the second level; and a defect detector that outputs a detection signal indicating normality of the target word line according to whether the count of the reference clock falls within a range from the first reference count to the second reference count.

11. A memory device, the memory device including: an array of memory cells including a plurality of memory cells; and a word line test circuit that: generates a test voltage in response to a test command, charges a target voltage based on a test current, a current of a target word line varying with the test voltage being reflected in the test current, generates a comparison signal based on a comparison result between the target voltage and a reference voltage, and detects a defect in the target word line based on at least one reference count and a count of a reference clock, a period of the reference clock being counted until a level of the comparison signal changes from a first level to a second level.

12. The memory device of claim 11, wherein, The word line test circuit includes: an operation signal generator that generates a plurality of operation signals in response to the test command; a comparison result generator that charges the target voltage in response to a first operation signal among the plurality of operation signals, discharges the target voltage in response to a second operation signal among the plurality of operation signals, and generates the comparison signal based on a comparison result between the target voltage and the reference voltage in response to a third operation signal among the plurality of operation signals; and a word line defect detector that starts counting the reference clock in response to the comparison signal of the first level, stops the counting in response to the comparison signal of the second level, and detects a defect in the target word line based on the count of the reference clock and the at least one reference count, wherein the word line defect detector stores data corresponding to a detection result indicating whether the defect in the target word line is detected.

13. The memory device of claim 12, wherein, the operation signal generator outputs the second operation signal and the third operation signal after outputting the first operation signal, wherein the comparison result generator outputs the comparison signal of the first level at a time when the third operation signal is received.

14. The memory device of claim 12, wherein, the comparison result generator: outputs the comparison signal of the first level when the target voltage is equal to or greater than the reference voltage, and outputs the comparison signal of the second level when the target voltage is less than the reference voltage.

15. The memory device of claim 12, wherein, the comparison result generator: generates the comparison signal of the first level at a time when the target voltage starts discharging, and outputs the comparison signal of the second level at a time when the target voltage becomes less than the reference voltage.

16. The memory device of claim 11, wherein, the test current is smaller than the current of the target word line, wherein the target voltage charged is a result of integrating the test current with respect to time.

17. A storage device, the storage device comprising: a memory controller that outputs a test command instructing to check whether a defect exists in a target word line; and a memory device that: generates a test voltage in response to the test command, charges a target voltage based on a test current, a current of the target word line that varies with the test voltage being reflected in the test current, generates a comparison signal based on a comparison result between the target voltage and a reference voltage, detects a defect in the target word line based on at least one reference count and a count of a reference clock, a period of the reference clock being counted until a level of the comparison signal changes from a first level to a second level, and provides a test response to the memory controller as a response to the test command.

18. The storage device of claim 17, wherein, the memory device: stores data about the target word line when the defect in the target word line is detected, and provides the data to the memory controller under control of the memory controller.

19. The storage device of claim 18, wherein, the memory controller provides a command to the memory device based on the data, the command instructing a memory block corresponding to the target word line among a plurality of memory blocks included in the memory device to be treated as a bad block.

20. The storage device of claim 17, wherein, the test current is smaller than the current of the target word line, wherein the target voltage charged is a result of integrating the test current with respect to time.

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