Split gate trench power mosfet with self-aligned poly to poly isolation

Abstract

Embodiments of this disclosure relate to a split-gate trench power MOSFET with self-aligned polycrystalline-to-polycrystalline isolation. A semiconductor substrate has a trench extending from a front surface, the trench including a lower portion and an upper portion. A first insulating layer is arranged along the lower portion of the trench, and a first conductive material in the lower portion is insulated from the semiconductor substrate through the first insulating layer to form a field plate electrode of a transistor. A second insulating layer is arranged along the sidewalls of the upper portion of the trench. A third insulating layer liner is applied to the top surface of the first conductive material at the bottom of the upper portion of the trench. A second conductive material fills the upper portion of the trench. The second conductive material forms the gate electrode of the transistor, which is insulated from the semiconductor substrate through a second insulating layer and further insulated from the first conductive material through a third insulating layer.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to U.S. Provisional Patent Application No. 63 / 065,198, filed August 13, 2020, the disclosure of which is incorporated herein by reference. Technical Field

[0003] This invention generally relates to metal-oxide-semiconductor field-effect transistor (MOSFET) devices, and in particular, to a split-gate trench power MOSFET device. Background Technology

[0004] refer to Figure 1 This illustration shows an embodiment of a split-gate trench power metal-oxide-semiconductor field-effect transistor (MOSFET) device 10. In this example, the MOSFET device 10 is an n-channel (nMOS) type device formed in and on a semiconductor substrate 12 (e.g., silicon) doped with an n-type dopant, which provides the drain region of the transistor 10. The substrate 12 has a front side 14 and a rear side 16. A plurality of trenches 18 extend deep from the front side 14 into the substrate 12. The trenches 18 extend longitudinally parallel to each other in a direction perpendicular to the cross-section (i.e., into and out of the illustrated page), and adjacent trenches define the side edges of the mesa region 13 of the strip transistor (this type of transistor device is commonly referred to in the art as a strip FET type transistor).

[0005] A p-type doped region 24 is buried in the mesa region 13 of the substrate 12 at a depth offset from the front side 14 (i.e., below it) and is positioned to extend parallel to the front side 14 on opposite sides of each trench 18. The doped region 24 forms the body (channel) region of the transistor, wherein the trench 18 completely penetrates the doped body region 24 and extends into the substrate 12 below the doped body region 24. A surface region 26 heavily doped with n-type dopant is provided in the mesa region 13 of the front side 14 of the substrate 12 and is positioned to extend parallel to the front side 14 on opposite sides of each trench 18, and the surface region 26 contacts the top of the doped body region 24. The doped region 26 forms the source region of the transistor, and the trench 18 completely penetrates the doped source region 26 and further (as described above) completely extends through the doped body region 24 into the substrate 12 below the doped body region 24.

[0006] Each trench 18 has its sidewalls and bottom lined with a first insulating layer 20. For example, the first insulating layer 20 may include an oxide layer (in one embodiment, it consists of oxide thermally grown from the exposed surface of the substrate 12 in each trench 18 and deposited oxide). Each trench 18 is filled with a first polysilicon material 22, wherein the first insulating layer 20 insulates the first polysilicon material 22 from the substrate 12. During the fabrication of the transistor 10, an upper portion of the first insulating layer 20 (e.g., an upper portion adjacent to both the doped body region 24 and the doped region 26) is removed from the upper part of the trench 18 to expose a corresponding upper portion 22a of the first polysilicon material 22, and an annular trench surrounding the upper portion 22a is formed. The sidewalls (inner and outer) of the annular trench are lined with a second insulating layer 30a and a third insulating layer 30b. For example, the second insulating layer 30a and the third insulating layer 30b may each include an oxide layer (in one embodiment, the oxide layer is thermally grown from the exposed surface of the substrate 12 in each annular trench and the exposed surface of the upper portion 22a of the first polysilicon material 22). The remaining opening portion of each annular trench is then filled with the second polysilicon material 32, the second insulating layer 30a insulating the polysilicon material 32 from the substrate 12, and the third insulating layer 30b insulating the polysilicon material 32 from the upper portion 22a. The first polysilicon material 22 at the lower part of the trench 18 forms the field plate electrode of the transistor 10. The second polysilicon material 32 at the upper part of the trench 18 forms the gate of the transistor 10 and extends on the opposite side of the upper portion 22a; the second insulating layer 30a forms the gate oxide layer.

[0007] A stack 40 of layers is formed over each trench 18 and extends on at least a portion of the doped region 26 for the source on opposite sides of each trench 18. Each stack 40 includes a dielectric region formed by an undoped oxide (e.g., tetraethyl orthosilicate (TEOS)) layer 44 and a glass (e.g., borosilicate glass (BPSG)) layer 46.

[0008] Source metal contacts 50 extend between adjacent stacks 40 to form electrical contacts with each doped source region 26. Each source metal contact 50 extends deep into the substrate from the front side 14 to penetrate the doped source region 26 and enter the doped body region 24 (thus providing a body contact for the transistor 10 attached to the source region). A source metal layer 52 extends over both the stacks 40 and the source metal contacts 50 to provide metal connections to all source metal contacts 50. The stacks 40 insulate the source metal layer 52 and the source metal contacts 50 from the gate (polysilicon region 32). Electrical connections (though not explicitly shown, but schematically shown by dashed line 55) are provided to electrically connect the source metal layer 52 to the field plate (polysilicon region 22a). A drain metal layer 54 extends over the rear side 16 of the substrate 12 to provide metal connections to the drain. In each trench 18, a gate metal layer (not explicitly shown because it is offset in a direction perpendicular to the cross-section) is formed to an electrical connection to the gate (polysilicon region 32), which is schematically shown by dashed line 56.

[0009] Transistor 10 can be replaced by a pMOS transistor, wherein both substrate 12 and doped source region 16 are p-type doped, and body region 14 is n-type doped.

[0010] Scanning electron microscopy (SEM) cross-sectional image of a single cell of transistor 10 in Figure 2 As shown in the diagram. There is a desire to reduce the threshold voltage of the power MOSFET 10. For this purpose, the thickness of the gate oxide formed by the second insulating layer 30a between the gate (polysilicon region 32) and the substrate 12 in the upper part of the trench 18 (particularly in the annular trench region) must be very thin. For example, if the thickness of the gate oxide layer is from approximately Thinned to approximately This results in a corresponding reduction in the threshold voltage from approximately 3.5V to approximately 1.75V. The thermal oxidation process used to form the second insulating layer 30a affects not only the thickness of the gate oxide layer but also the insulation between the gate (polysilicon region 32) and the field plate electrode (polysilicon region 22) provided by the third insulating layer 30b. In particular, when providing a thinner second insulating layer 30a to reduce the threshold voltage, the following considerations exist: the third insulating layer 30b in region 70 will be correspondingly thinner, resulting in weak polysilicon-to-polysilicon isolation. Then, in response to the applied gate voltage, the transistor 10 will experience an unacceptable level of gate-source leakage current (IGSS).

[0011] Therefore, there is a need in the art for an improved split-gate trench MOSFET structure that supports a lower threshold voltage while meeting gate-source leakage current requirements. Summary of the Invention

[0012] In one embodiment, a method includes: forming a trench in a semiconductor substrate; lining the trench with a first insulating layer; filling the trench with a first conductive material, the first conductive material being insulated from the semiconductor substrate through the first insulating layer; recessing the first insulating layer to expose an upper portion of the first conductive material within an annular trench portion of the trench; filling the annular trench portion with a photoresist material; developing the photoresist material in the annular trench portion to expose an uppermost portion of the uppermost portion of the first conductive material, leaving residual photoresist material spaced apart from the uppermost portion on the sidewalls of the trench, and defining... A photomask; etching using the photomask to remove the upper portion of the first conductive material down to the level of the recessed first insulating layer; removing residual resist material to open the upper portion of the trench; lining the sidewalls of the upper portion of the trench with a second insulating layer; lining the top surface of the first conductive material at the bottom of the upper portion of the trench with a third insulating layer; and depositing a second conductive material in the upper portion of the trench, the second conductive material being insulated from the semiconductor substrate by the second insulating layer and from the first conductive material by the third insulating layer.

[0013] In one embodiment, a method includes: forming a trench in a semiconductor substrate; lining a lower portion of the trench with a first insulating layer; filling the lower portion of the trench with a first conductive material, the first conductive material being insulated from the semiconductor substrate through the first insulating layer; lining the sidewalls of an upper portion of the trench with a second insulating layer; lining a top surface of the first conductive material at the bottom of the upper portion of the trench with a third insulating layer; and depositing a second conductive material on the upper portion of the trench, the second conductive material being insulated from the semiconductor substrate through the second insulating layer, and the second conductive material being insulated from the first conductive material through the third insulating layer.

[0014] In one embodiment, an integrated circuit includes: a semiconductor substrate having a front surface and a rear surface; a trench extending from the front surface into the semiconductor substrate, the trench including a lower portion and an upper portion; a first insulating layer lining the lower portion of the trench; a first conductive material in the lower portion of the trench, and the first conductive material being insulated from the semiconductor substrate through the first insulating layer; a second insulating layer lining the sidewalls of the upper portion of the trench; a third insulating layer lining the top surface of the first conductive material at the bottom of the upper portion of the trench; and a second conductive material in the upper portion of the trench, the second conductive material being insulated from the semiconductor substrate through the second insulating layer, and the second conductive material being insulated from the first conductive material through the third insulating layer. Attached Figure Description

[0015] To better understand the embodiments, reference will now be made to the accompanying drawings by way of example only, wherein:

[0016] Figure 1This is a cross-sectional view of a power metal-oxide-semiconductor field-effect transistor (MOSFET) device;

[0017] Figure 2 yes Figure 1 Scanning electron micrograph of the cross-section of a power MOSFET device;

[0018] Figure 3 This is a cross-sectional view of a power MOSFET device;

[0019] Figure 4 yes Figure 3 Scanning electron micrograph of the cross-section of a power MOSFET device;

[0020] Figures 5A to 5I It shows Figures 3 to 4 MOSFET device manufacturing process steps;

[0021] Figure 6 yes Figure 5E Scanning electron micrograph of the cross-section of the groove at an intermediate step in the manufacturing process shown. Detailed Implementation

[0022] For reference Figure 3 This figure illustrates a cross-section of one embodiment of a split-gate trench power metal-oxide-semiconductor field-effect transistor (MOSFET) device 100. In this embodiment, the MOSFET device 100 is an n-type trench (nMOS) device formed in and on a semiconductor substrate 12 (e.g., silicon), which provides a drain region for providing transistor 10. The substrate 12 has a front side 14 and a rear side 16. A plurality of trenches 18 extend deep into the substrate 12 from the front side 14. The trenches 18 extend longitudinally parallel to each other in a direction perpendicular to the cross-section (i.e., into and out of the illustrated page), with adjacent trenches defining the side edges of the mesa region 13 of a strip transistor (this type of transistor device is commonly referred to in the art as a strip FET-type transistor). Each trench 18 includes a lower trench portion and a higher trench portion.

[0023] A p-type doped region 24 is buried in the mesa region 13 of the substrate 12 at a depth offset from the front side 14 (i.e., below it) and is positioned to extend parallel to the front side 14 on opposite sides of each trench 18. The doped region 24 forms the body (channel) region of the transistor, wherein the trench 18 completely penetrates the doped body region 24 and extends into the substrate 12 below the doped body region 24. A surface region 26 heavily doped with n-type dopant is provided in the mesa region 13 of the front side 14 of the substrate 12 and is positioned to extend parallel to the front side 14 on opposite sides of each trench 18, and the surface region 26 contacts the top of the doped body region 24. The doped region 26 forms the source region of the transistor, and the trench 18 completely penetrates the doped source region 26 and further (as described above) completely extends through the doped body region 24 into the substrate 12 below the doped body region 24.

[0024] The lower sidewalls and bottom of each trench 18 are lined with a first insulating layer 20. For example, the first insulating layer 20 may include an oxide layer (in one embodiment, it consists of oxide thermally grown from the exposed surface of the substrate 12 in each trench 18 and deposited oxide). The lower portion of each trench 18 is filled with a first polysilicon material 22, wherein the first insulating layer 20 insulates the first polysilicon material 22 from the substrate 12. During the process for manufacturing the transistor 10, the upper portion of the first insulating layer 20 and the upper portion of the first polysilicon material 22 (e.g., adjacent to both the doped body region 24 and the doped region 26) are removed from the upper portion of the trench 18 (i.e., recessed). This exposes the top surface of the recessed polysilicon material 22 at the bottom of the upper portion of the trench 18. The upper sidewalls of the trench 18 are lined with a second insulating layer 130, and the top surface of the recessed polysilicon material 22 is lined with a third insulating layer 132. For example, the second insulating layer 130 and the third insulating layer 132 may each include an oxide layer (in one embodiment, this oxide layer is thermally grown from the exposed surface of the substrate 12 in the upper portion of the trench and the exposed upper end of the first polysilicon material 22). The remaining opening portion of each annular trench 18 is then filled with the second polysilicon material 32, wherein the second insulating layer 130 insulates the polysilicon material 32 from the substrate 12, and the third insulating layer 132 insulates the polysilicon material 32 from the first polysilicon material 22. The first polysilicon material 22 forms the field plate electrode of the transistor 100. The second polysilicon material 32 forms the gate of the transistor 100. The second insulating layer 130 forms the gate oxide layer.

[0025] A stack of layers 40 is formed over each trench 18 and extends on at least a portion of the doped region 26 for the source on opposite sides of each trench 18. Each stack 40 includes a dielectric region formed by an undoped oxide (e.g., tetraethyl orthosilicate (TEOS)) layer 44 and a glass (e.g., borosilicate glass (BPSG)) layer 46.

[0026] Source metal contacts 50 extend between adjacent stacks 40 to form electrical contacts with each doped source region 26. Each source metal contact 50 extends deep into the substrate from the front side 14 to penetrate the doped source region 26 and enter the doped body region 24 (thus providing a body contact for the transistor 10 attached to the source region). A source metal layer 52 extends over both the stacks 40 and the source metal contacts 50 to provide metal connections to all source metal contacts 50. The stacks 40 insulate both the source metal layer 52 and the source metal contacts 50 from the gate (polysilicon region 32). Electrical connections (not explicitly shown) are provided to electrically connect the source metal layer 52 to the recessed polysilicon material 22 forming the field plate. A drain metal layer 54 extends over the back side 16 of the substrate 12 to provide metal connections to the drain. In each trench 18, a gate metal layer (not explicitly shown because it is offset in a direction perpendicular to the cross-section) is electrically connected to the gate (polysilicon region 32), and the gate metal layer and the electrical connection are schematically shown by dashed lines 56.

[0027] Transistor 100 can be replaced by a pMOS transistor, wherein both substrate 12 and doped source region 16 are p-type doped, and body region 14 is n-type doped.

[0028] Scanning electron microscopy (SEM) cross-sectional image of a single cell of transistor 100 in Figure 4 As shown in the diagram. The power MOSFET 100 supports a low threshold voltage because the thickness of the gate oxide layer formed by the second insulating layer 130 between the gate (polysilicon region 32) in trench 18 and the substrate 12 can be controlled to be very thin. For example, the thickness of the gate oxide can be approximately... Within the range. The position and thickness of the third insulating layer 132 can also be controlled to provide sufficient insulation between the gate (polysilicon region 32) and the field plate electrode (polysilicon region 22), thereby generating strong polysilicon-to-polysilicon isolation in region 70′, which is necessary to achieve the desired gate-source leakage current (IGSS) level.

[0029] See now Figures 5A to 5I It shows Figure 3 The process steps for manufacturing MOSFET devices.

[0030] A trench is formed in substrate 12. An insulating layer 20 is lined the upper and lower sidewalls and bottom of the trench 18, extending further on the front side 14 of substrate 12. The upper and lower portions of the trench 18 are then filled with a polysilicon (conductive) material 22. A polishing operation (e.g., chemical mechanical polishing (CMP)) is performed to remove the first polysilicon material 22 not present in the trench 18. The result is as follows: Figure 5A As shown.

[0031] Next, etching operation E1 is performed to recess the first polysilicon material 22 below the level of the top surface 15 of the insulating layer 20. The result is as follows... Figure 5B As shown. More specifically, the etching performed in this step is reactive ion etching (RIE).

[0032] Subsequently, etching operation E2 is performed to recess the insulating layer 20 into the upper portion of the trench 18 and expose the upper portion 22a of the first polysilicon material 22 within the annular trench portion of the upper portion of the trench 18. The result is as follows... Figure 5C As shown. More specifically, the etching performed in this step is buffered oxide etching (BOE).

[0033] Subsequently, resist layer 17 is deposited to fill the recessed area of ​​insulating layer 20 in trench 18 (i.e., the annular trench portion at the top of trench 18) and cover the front side 14 of substrate 12. The result is as follows: Figure 5D As shown.

[0034] Subsequently, photolithography operation E3 is performed to recess the resist layer 17 within the upper portion of the trench 18 and expose the uppermost portion 22b of the upper portion 22a of the first polysilicon material 22. The result is as follows: Figure 5E As shown. Figure 6 It is by Figure 5E The image shows a scanning electron microscope (SEM) image of a trench cross-section during an intermediate step of the manufacturing process. More specifically, the photolithography operation performed at this step includes a resist underexposure technique followed by subsequent resist development. The mask 19 used for performing photolithography operation E3 includes an opening 21 substantially aligned with the center of the first polysilicon material 22 (allowing for a degree of misalignment due to the implemented underexposure photolithography technique), and its width d1 is greater than the width d2 of the first polysilicon material 22 and less than the width d3 of the trench 18. Therefore, after development in photolithography operation E3, the remaining portion 17a of the resist 17 on the upper sidewall of the trench 18 is separated from the uppermost portion 22b of the upper portion 22a of the first polysilicon material 22.

[0035] During the photolithography process of developing the resist 17 using the mask 19 and its openings 21, the underexposure (i.e., reduced light intensity) process creates a self-aligned protective structure to ensure protection of the annular trench portion and the top of the substrate 12 during subsequent manufacturing process operations (e.g., etching process E4 in the next step of manufacturing the recessed polysilicon 22). If this underexposure (reduced light intensity) photolithography were not performed, and standard exposure were instead performed, then the mask 21 would have to be designed to be perfectly aligned with the polysilicon 22 and have the same dimensions. This is extremely difficult (if not impossible) to achieve industrial-scale operation with zero deviation operating margin.

[0036] Using a mask formed by the developed resist 17, an etching operation E4 is then performed to further recess the first polysilicon material 22 (in particular, to remove the upper portion 22a of the first polysilicon material 22 in the upper part of the trench 18) to a level substantially equal to the level of the upper surface 21 of the previously recessed insulating layer 20 in the lower part of the trench 18. The result is as follows: Figure 5F As shown. More specifically, the etching performed in this step is reactive ion etching (RIE).

[0037] Then, resist removal operation E5 is performed to remove the mask formed by the developing resist 17 and open the upper part 18a of the trench 18. The result is as follows... Figure 5G As shown. More specifically, the resist removal performed in this step is carried out using a mixture of sulfuric acid and hydrogen peroxide solution.

[0038] Then, thermal oxidation is performed to form a second insulating layer 130 on the sidewall of the upper portion 18a of the trench 18, and a third insulating layer 132 on the top surface 22c of the remaining portion of the first polysilicon material 22 in the lower portion of the trench 18. The result is as follows: Figure 5H As shown.

[0039] Next, the remaining open space in the upper portion 18a of trench 18 is filled with a second polysilicon (conductive) material 32. A plasma etching operation is then performed to remove the second polysilicon material 32 not present in the upper portion 18a of trench 18. The results are as follows: Figure 5I As shown.

[0040] Then, standard fabrication techniques are continued to complete the fabrication of transistor 100 (including the steps of implanting source region 26 and body region 24). Stack 40 is deposited on the planarized surface of the substrate. Openings for source-body contacts are then formed to extend through stack 40 and into substrate 12. These openings are then filled with material for source contacts 50. Source layer 52 is then deposited on stack 40 and source contacts 50. At any appropriate time during operation, drain contact 54 may be deposited on back side 16 of substrate 12. The results of these standard fabrication techniques are as follows: Figure 3 As shown.

[0041] Although the invention has been described in detail in the accompanying drawings and the foregoing description, such description should be considered illustrative or exemplary rather than restrictive; those skilled in the art can understand and implement the disclosed embodiments and their variations by studying the drawings, the disclosure and the appended claims.

Claims

1. A method for manufacturing a semiconductor device, comprising: Trenches are formed in a semiconductor substrate; The trench is lined with a first insulating layer; The trench is filled with a first conductive material, which is insulated from the semiconductor substrate by the first insulating layer. The first insulating layer is recessed to expose the upper portion of the first conductive material within the annular groove portion of the trench; The annular groove portion is filled with a corrosion-resistant material; The resist material is developed in the annular trench portion to expose the uppermost part of the upper portion of the first conductive material, and residual resist material is left on the sidewall of the trench, spaced apart from the uppermost part and defining the mask; The mask is used to etch away the upper portion of the first conductive material down to the level of the recessed first insulating layer; Remove the residual resist material to open the upper part of the trench; The upper sidewall of the trench is lined with a second insulating layer; The top surface of the first conductive material at the bottom of the upper part of the trench is lined with a third insulating layer; as well as A second conductive material is deposited in the upper part of the trench, the second conductive material being insulated from the semiconductor substrate by the second insulating layer, and the second conductive material being insulated from the first conductive material by the third insulating layer.

2. The method of claim 1, wherein the first conductive material is made of polycrystalline silicon.

3. The method of claim 1, wherein the second conductive material is made of polycrystalline silicon.

4. The method according to claim 1, wherein the first insulating layer is a thermal oxide.

5. The method according to claim 1, wherein the second insulating layer is a thermal oxide.

6. The method according to claim 1, wherein the third insulating layer is a thermal oxide.

7. The method of claim 1, wherein the semiconductor substrate provides the drain region of the transistor, the method further comprising: A doped buried region is formed in the semiconductor substrate, the doped buried region providing the body region of the transistor; as well as A doped surface region is formed in the semiconductor substrate above the doped buried region, the doped surface region providing the source region of the transistor.

8. The method of claim 7, wherein the first conductive material provides the field plate electrode of the transistor, and the second conductive material provides the gate electrode of the transistor.

9. The method according to claim 7, further comprising: An opening is formed that extends through the doped surface region and into the doped buried region; as well as The opening is filled with a third conductive material.

10. The method of claim 9, wherein the third conductive material provides a source contact for the transistor.

11. The method of claim 1, wherein the resist material developed in the annular trench portion comprises: The resist material is exposed through a photomask having an opening larger than the uppermost part of the upper portion of the first conductive material and smaller than the size of the trench.

12. The method of claim 11, wherein the exposure comprises: The light intensity used results in underexposure of a portion of the resist material defined by the opening in the photomask.

13. A method for manufacturing a semiconductor device, comprising: Trenches are formed in a semiconductor substrate; The lower part of the trench is lined with a first insulating layer; The lower portion of the trench is filled with a first conductive material, which is insulated from the semiconductor substrate by the first insulating layer. The upper sidewalls of the trench are lined with a second insulating layer; The top surface of the first conductive material at the bottom of the upper part of the trench is lined with a third insulating layer; as well as A second conductive material is deposited in the upper part of the trench, the second conductive material being insulated from the semiconductor substrate through the second insulating layer, and the second conductive material being insulated from the first conductive material through the third insulating layer; The third insulating layer grows only from the top surface of the first conductive material; The use of a photoresist as a mask includes depositing the photoresist material in the upper part of the trench to surround the upper portion of the first conductive material; as well as The resist material is developed to expose the uppermost part of the upper portion of the first conductive material, and residual resist material is left on the sidewall of the upper portion of the trench, spaced apart from the uppermost part and defining the mask; The development of the resist material includes: exposing the resist material through a mask having an opening larger than the uppermost part of the upper portion of the first conductive material and smaller than the size of the trench.

14. The method of claim 13, wherein the first conductive material and the second conductive material are each made of polycrystalline silicon.

15. The method of claim 13, wherein the first insulating layer, the second insulating layer and the third insulating layer are each made of thermal oxide.

16. The method of claim 13, wherein the semiconductor substrate provides the drain region of the transistor, the method further comprising: A doped buried region is formed in the semiconductor substrate, the doped buried region providing the body region of the transistor; as well as A doped surface region is formed in the semiconductor substrate above the doped buried region, the doped surface region providing the source region of the transistor.

17. The method of claim 16, wherein the first conductive material provides the field plate electrode of the transistor, and the second conductive material provides the gate electrode of the transistor.

18. The method of claim 16, further comprising: An opening is formed that extends through the doped surface region and into the doped buried region; as well as The opening is filled with a third conductive material.

19. The method of claim 18, wherein the third conductive material provides a source contact for the transistor.

20. The method of claim 19, further comprising: After the etching operation, the resist material in the upper part of the trench is removed, and the etching operation removes the first conductive material from the upper part of the trench.

21. The method of claim 13, wherein the exposure comprises: The light intensity used results in underexposure of a portion of the resist material defined by the opening in the photomask.

22. An integrated circuit, comprising: A semiconductor substrate having a front surface and a back surface; A trench extending from the front surface into the semiconductor substrate, the trench comprising a lower portion and an upper portion; A first insulating layer is provided to line the lower part of the trench; A first conductive material is located in the lower portion of the trench, and the first conductive material is insulated from the semiconductor substrate by the first insulating layer; A second insulating layer is provided to line the upper sidewall of the trench; A third insulating layer is provided to line the top surface of the first conductive material at the bottom of the upper part of the trench; as well as In the upper part of the trench, the second conductive material is insulated from the semiconductor substrate by the second insulating layer, and the second conductive material is insulated from the first conductive material by the third insulating layer; The third insulating layer is applied only to the top surface of the first conductive material; as well as A first opening is located between the second insulating layer and the third insulating layer, and the second conductive material contacts the first insulating layer through the first opening.

23. The integrated circuit of claim 22, wherein the first conductive material and the second conductive material are each made of polycrystalline silicon.

24. The integrated circuit of claim 22, wherein the first insulating layer, the second insulating layer and the third insulating layer are each made of thermal oxide.

25. The integrated circuit of claim 22, wherein the semiconductor substrate provides the drain region of the transistor, the integrated circuit further comprising: A doped buried region in the semiconductor substrate, the doped buried region providing the body region of the transistor; as well as A doped surface region above the doped buried region in the semiconductor substrate provides the source region of the transistor.

26. The integrated circuit of claim 25, wherein the first conductive material provides the field plate electrode of the transistor, and the second conductive material provides the gate electrode of the transistor.

27. The integrated circuit according to claim 25, further comprising: An opening that extends through the doped surface region and into the doped buried region; as well as A third conductive material is used to fill the opening.

28. The integrated circuit of claim 27, wherein the third conductive material provides a source contact for the transistor.

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