Chip packaging structure

Abstract

The present invention provides a chip packaging structure, which includes a substrate, a first chip, a second chip, a bridge, a plurality of first bumps, a plurality of second bumps, a plurality of third bumps, and a plurality of solder balls. The first active surface of the first chip and the second active surface of the second chip face the first surface of the substrate. The bridge includes a polymer layer and a pad layer located on the polymer layer. The first chip is electrically connected to the substrate through the first bumps. The second chip is electrically connected to the substrate through the second bumps. The first chip and the second chip are respectively electrically connected to the pad layer through the third bumps. The first bumps and the second bumps have the same size. The solder balls are disposed on the second surface of the substrate and are electrically connected to the substrate. For the chip packaging structure provided by the present invention, the sizes of the bumps are all the same, which can effectively solve the problem of too low yield rate of existing chip assembly and can have better structural reliability.

Description

Technical Field

[0001] The present invention relates to a packaging structure, and more particularly to a chip packaging structure. Background Art

[0002] Currently, in a packaging structure with multiple chip interconnections, the embedded multi-die interconnect bridge (EMIB) technology is adopted to dispose chips on a circuit carrier board, and silicon bridge connectors buried in the circuit carrier board are used to connect multiple chips. However, due to the manufacturing process, the size of the pads of the silicon bridge connectors is significantly smaller than the pad size on a general circuit board, resulting in different sizes of the microbumps (such as 55 microns) connecting the silicon bridge connectors and the chips from the sizes of the microbumps (such as 130 microns) connecting the chips and the circuit board, thereby leading to poor yield performance in chip assembly. Summary of the Invention

[0003] The present invention is directed to a chip packaging structure in which the sizes of the bumps are all the same, which can effectively solve the problem of too low yield in existing chip assembly and can have better structural reliability.

[0004] According to an embodiment of the present invention, a chip packaging structure includes a substrate, a first chip, a second chip, a bridge connector, a plurality of first bumps, a plurality of second bumps, a plurality of third bumps, and a plurality of solder balls. The substrate has a first surface and a second surface opposite to each other. The first chip is disposed on the first surface of the substrate and has a first active surface facing the first surface, and includes a plurality of first pads disposed on the first active surface. The second chip is disposed on the first surface of the substrate and has a second active surface facing the first surface, and includes a plurality of second pads disposed on the second active surface. The bridge connector includes a polymer layer and a pad layer located on the polymer layer. The first bumps are disposed between the first chip and the substrate, and the first chip is electrically connected to the substrate through the first bumps. The second bumps are disposed between the second chip and the substrate, and the second chip is electrically connected to the substrate through the second bumps. The third bumps are disposed between the first chip and the bridge connector and between the second chip and the bridge connector. The first chip and the second chip are respectively electrically connected to the pad layer of the bridge connector through the third bumps. The first bumps and the second bumps have the same size. The solder balls are disposed on the second surface of the substrate and are electrically connected to the substrate.

[0005] In the chip packaging structure according to an embodiment of the present invention, the size of the above-mentioned third bumps is the same as the size of the first bumps.

[0006] In the chip packaging structure according to an embodiment of the present invention, the size of the above-mentioned third bumps is different from the size of the first bumps.

[0007] In the chip packaging structure according to an embodiment of the present invention, the above-mentioned first chip includes at least one first through-silicon via, and the second chip includes at least one second through-silicon via. The first chip and the second chip are located between the bridge and the substrate, and the bridge is electrically connected to the first through-silicon via and the second through-silicon via through third bumps.

[0008] In the chip packaging structure according to an embodiment of the present invention, the orthographic projection of the above-mentioned bridge on the substrate partially overlaps the orthographic projections of the first chip and the second chip on the substrate.

[0009] In the chip packaging structure according to an embodiment of the present invention, the above-mentioned chip packaging structure further includes a first reconfiguration circuit layer. The first reconfiguration circuit layer is disposed on the first surface of the substrate, and is located between the first chip and the substrate and between the second chip and the substrate. The first chip is electrically connected to the substrate through the first bumps and the first reconfiguration circuit layer.

[0010] In the chip packaging structure according to an embodiment of the present invention, the above-mentioned chip packaging structure further includes a second reconfiguration circuit layer. The second reconfiguration circuit layer is disposed on the second surface of the substrate, and is located between the substrate and the solder balls. The solder balls are electrically connected to the substrate through the second reconfiguration circuit layer. The substrate includes at least one conductive via for electrically connecting the first reconfiguration circuit layer and the second reconfiguration circuit layer. The second chip is electrically connected to the substrate through the second bumps and the second reconfiguration circuit layer.

[0011] In the chip packaging structure according to an embodiment of the present invention, the above-mentioned chip packaging structure further includes a chip group. The chip group is disposed on the bridge and is electrically connected to the first through-silicon via of the first chip through the bridge and the third bumps.

[0012] In the chip packaging structure according to an embodiment of the present invention, the above-mentioned chip packaging structure further includes an integrated passive component. The integrated passive component is disposed on the bridge and is electrically connected to the second through-silicon via of the second chip through the bridge and the third bumps.

[0013] In the chip packaging structure according to an embodiment of the present invention, the above-mentioned chip packaging structure further includes a first reconfiguration circuit layer. The first reconfiguration circuit layer is disposed on the first surface of the substrate, and the bridge and the first reconfiguration circuit layer are located between the first chip and the substrate and between the second chip and the substrate. The first chip is electrically connected to the substrate through the first bumps and the first reconfiguration circuit layer.

[0014] In the chip package structure according to an embodiment of the present invention, the above chip package structure further includes a second reconfiguration circuit layer. The second reconfiguration circuit layer is disposed on the second surface of the substrate and is located between the substrate and the solder balls. The solder balls are electrically connected to the substrate through the second reconfiguration circuit layer. The substrate includes at least one first conductive via for electrically connecting the first reconfiguration circuit layer and the second reconfiguration circuit layer. The second chip is electrically connected to the substrate through the second bumps and the second reconfiguration circuit layer.

[0015] In the chip package structure according to an embodiment of the present invention, the above bridge is embedded in the first reconfiguration circuit layer or disposed on the first reconfiguration circuit layer.

[0016] In the chip package structure according to an embodiment of the present invention, the above first reconfiguration circuit layer includes at least one second conductive via for electrically connecting the bridge to the substrate.

[0017] Based on the above, in the chip package structure of the present invention, the sizes of the bumps between each chip and the substrate are the same, that is, the first bumps and the second bumps have the same dimensions. Therefore, the yield of chip assembly can be improved, and thus the chip package structure of the present invention can have better structural reliability. Description of the Drawings

[0018] Figure 1 is a cross-sectional schematic view of a chip package structure according to an embodiment of the present invention;

[0019] Figure 2 is a cross-sectional schematic view of a chip package structure according to another embodiment of the present invention;

[0020] Figure 3 is a cross-sectional schematic view of a chip package structure according to another embodiment of the present invention;

[0021] Figure 4 is a cross-sectional schematic view of a chip package structure according to another embodiment of the present invention;

[0022] Figure 5 is a cross-sectional schematic view of a chip package structure according to another embodiment of the present invention;

[0023] Figure 6 is a cross-sectional schematic view of a chip package structure according to another embodiment of the present invention.

[0024] Description of the Reference Numerals

[0025] 100a, 100b, 100c, 100d, 100e, 100f: Chip package structure;

[0026] 110a, 110b: Substrate;

[0027] 111: First surface;

[0028] 112, 114: Bonding pads;

[0029] 113: Second surface;

[0030] 116: Conductive via;

[0031] 120a, 120c: First chip;

[0032] 121: First active surface;

[0033] 122: First bonding pad;

[0034] 124: First through-silicon via;

[0035] 130a, 130c: Second chip;

[0036] 131: Second active surface;

[0037] 132: Second bonding pad;

[0038] 134: Second through-silicon via;

[0039] 140a, 140b, 140c, 140d: Bridge;

[0040] 142a: Polymer layer;

[0041] 144a: Bonding pad layer;

[0042] 146a: Patterned wiring layer;

[0043] 148a: Conductive via;

[0044] 150: First bump;

[0045] 160: Second bump;

[0046] 170: Third bump;

[0047] 175: Solder ball;

[0048] 180: Chipset;

[0049] 190: Integrated passive device;

[0050] RDL1, RDL1’: First reconfigured wiring layer;

[0051] RDL2: Second reconfigured wiring layer;

[0052] T: Second conductive via. Detailed implementation

[0053] Reference will now be made in detail to exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numerals are used in the drawings and the description to refer to the same or like parts.

[0054] Figure 1 is a cross-sectional schematic view of a chip packaging structure according to an embodiment of the present invention. Please refer to Figure 1 , in this embodiment, the chip packaging structure 100a includes a substrate 110a, a first chip 120a, a second chip 130a, a bridge 140a, a plurality of first bumps 150, a plurality of second bumps 160, a plurality of third bumps 170, and a plurality of solder balls 175. Since the chip packaging structure 100a of this embodiment includes a first chip 120a and a second chip 130a, it can be regarded as a multi-chip packaging structure.

[0055] Specifically, the substrate 110a of this embodiment has a first surface 111 and a second surface 113 opposite to each other, and includes pads 112 disposed on the first surface 111 and pads 114 disposed on the second surface 113. That is to say, the substrate 110a of this embodiment is embodied as a circuit board, where the material of the substrate 110a is, for example, glass or an organic material, and the materials of the pads 112 and 114 are, for example, copper, but not limited thereto. In this embodiment, the pads 112 and 114 are respectively disposed on the first surface 111 and the second surface 113, but in other embodiments, the pads 112 and 114 may also be buried inside the substrate 110a, which still falls within the scope of the present invention.

[0056] Furthermore, the first chip 120a of this embodiment is disposed on the first surface 111 of the substrate 110a, and has a first active surface 121 facing the first surface 111, and includes a plurality of first pads 122 disposed on the first active surface 121. The second chip 130a is disposed on the first surface 111 of the substrate 110a, and has a second active surface 131 facing the first surface 111, and includes a plurality of second pads 132 disposed on the second active surface 131. Here, the nature of the first chip 120a is the same as that of the second chip 130a. For example, both the first chip 120a and the second chip 130a can be logic chips, but not limited thereto. In another embodiment, the nature of the first chip 120a may be different from that of the second chip 130a, that is, the first chip 120a can be a logic chip, and the second chip 130a can be a memory chip, but not limited thereto. This is to integrate heterogeneous chips into a single module.

[0057] Please refer to Figure 1, in this embodiment, the bridge 140a includes a polymer layer 142a and a landing pad layer 144a located on the polymer layer 142a. That is to say, the bridge 140a of this embodiment is not based on silicon, but on a polymer (such as polyimide (PI), but not limited thereto). Further, the bridge 140a of this embodiment further includes at least one patterned wiring layer 146a (schematically showing one patterned wiring layer 146a) and at least one conductive via 148a (schematically showing a plurality of conductive vias 148a). The patterned wiring layer 146a is embedded in the polymer layer 142a and is electrically connected to the landing pad layer 144a through the conductive via 148a. In the manufacturing process, a glass substrate is first provided and a release film is formed on the glass substrate. Then, the polymer layer 142a, the patterned wiring layer 146a, the conductive via 148a, and the landing pad layer 144a are formed on the release film to form the bridge 140a. Here, the bridge 140a can be regarded as a reconfigurable wiring layer bridge (RDL bridge), where the line width and line pitch of the patterned wiring layer 146a and the landing pad layer 144a are, for example, 2 microns to 5 microns respectively. Since the glass substrate has high flatness and strength, a bridge 140a with ultra-fine circuits can be fabricated on the glass substrate, achieving the effect of high-density connection.

[0058] In addition, the first bump 150 of this embodiment is disposed between the first chip 120a and the substrate 110a, where the first chip 120a is electrically connected to the substrate 110a through the first bump 150. That is to say, the first pad 122 of the first chip 120a is electrically connected to the pad 112 of the substrate 110 through the first bump 150. The second bump 160 is disposed between the second chip 130a and the substrate 110a, where the second chip 130a is electrically connected to the substrate 110a through the second bump 160. That is to say, the second pad 132 of the second chip 130a is electrically connected to the pad 112 of the substrate 110a through the second bump 160. The third bump 170 is disposed between the first chip 120a and the bridge 140a and between the second chip 130a and the bridge 140a. The first chip 120a and the second chip 130a are respectively electrically connected to the landing pad layer 144a of the bridge 140a through the third bump 170.

[0059] Further, please refer to again Figure 1, the first chip 120a of this embodiment includes at least one first through-silicon via 124 (one first through-silicon via 124 is schematically shown), and the second chip 130a includes at least one second through-silicon via 134 (one second through-silicon via 134 is schematically shown). The first chip 120a and the second chip 130a are located between the bridge 140a and the substrate 110a, and the bridge 140a is electrically connected to the first through-silicon via 124 and the second through-silicon via 134 through the third bumps 170. That is to say, the contact pad layer 144a of the bridge 140a is electrically connected to the first through-silicon via 124 of the first chip 120a and the second through-silicon via 134 of the second chip 130a through the third bumps 170. Here, the orthographic projection of the bridge 140a on the substrate 110a partially overlaps the orthographic projections of the first chip 120a and the second chip 130a on the substrate 110a.

[0060] In particular, the first bumps 150 and the second bumps 160 of this embodiment have the same size. That is to say, the first bumps 150 and the second bumps 160 are the same in size and shape, and the first bumps 150 and the second bumps 160 can be, for example, micro-bumps (such as 20 microns to 60 microns). The size of the third bumps 170 can be the same as or different from the size of the first bumps 150, and the size of the third bumps 170 can be, for example, 20 microns to 200 microns. In the manufacturing process, the first bumps 150 and the second bumps 160 are first formed on the first chip 120a and the second chip 130a, and then, the first chip 120a and the second chip 130a are bonded to the substrate 110a. After that, the third bumps 170 are formed on the first through-silicon via 124 of the first chip 120a and the second through-silicon via 134 of the second chip 130a, and finally, the bridge 140a is bonded to the first chip 120a and the second chip 130a.

[0061] Since the first bumps 150 and the second bumps 160 of this embodiment have the same size, when the first chip 120a and the second chip 130a are assembled with the substrate 110a, there is no need to consider the size of the connecting bumps, and a higher assembly yield can be achieved, thereby improving the structural reliability of the chip packaging structure 100a. In addition, solder balls 175 are disposed on the second surface 113 of the substrate 110a and are electrically connected to the substrate 110a, and the chip packaging structure 100a can be electrically connected to an external circuit through the solder balls 175.

[0062] Briefly speaking, in the chip packaging structure 100a of this embodiment, the first bump 150 and the second bump 160 have the same size. Therefore, the yield of assembling the first chip 120a and the second chip 130a can be improved, and further, the chip packaging structure 100a of this embodiment can have better structural reliability. In addition, if the properties of the first chip 120a are different from those of the second chip 130a, it means that the chip packaging structure 100a of this embodiment can integrate heterogeneous elements into a single module.

[0063] It must be noted here that the following embodiments follow the component numbers and some contents of the foregoing embodiments, where the same numbers are used to represent the same or similar components, and the description of the same technical content is omitted. For the description of the omitted parts, reference can be made to the foregoing embodiments, and the following embodiments will not repeat them.

[0064] Figure 2 is a cross-sectional schematic view of a chip packaging structure according to another embodiment of the present invention. Please also refer to Figure 1 and Figure 2 , the chip packaging structure 100b of this embodiment is similar to the chip packaging structure 100a of Figure 1 . The difference between the two is that the chip packaging structure 100b of this embodiment further includes a first redistribution layer RDL1. The first redistribution layer RDL1 is disposed on the first surface 111 of the substrate 110b, and is located between the first chip 120a and the substrate 110b and between the second chip 130a and the substrate 110b. The first redistribution layer RDL1 covers the first surface 111 of the substrate 110b and the pads 112, and the first chip 120a is electrically connected to the substrate 110b through the first bump 150 and the first redistribution layer RDL1. The second chip 130a is electrically connected to the substrate 110b through the second bump 160 and the second redistribution layer RDL2. Furthermore, as Figure 2 shown, the chip packaging structure 100b of this embodiment may further include a second redistribution layer RDL2. The second redistribution layer RLD2 is disposed on the second surface 113 of the substrate 110b, and is located between the substrate 110b and the solder balls 175. The solder balls 175 are electrically connected to the substrate 110b through the second redistribution layer RLD2.

[0065] In addition, the substrate 110b of this embodiment further includes at least one conductive via 116 (a plurality of conductive vias 116 are schematically shown), wherein the conductive via 116 electrically connects the first redistribution layer RDL1 and the second redistribution layer RDL2. In addition, as Figure 2As shown, the chip packaging structure 100b of this embodiment further includes a chipset 180. The chipset 180 is disposed on the bridge 140b and is electrically connected to the first silicon through hole 124 of the first chip 120a through the bridge 140b and the third bump 170. In addition, the chip packaging structure 100b of this embodiment may further include an integrated passive component 190, wherein the integrated passive component 190 is disposed on the bridge 140b and is electrically connected to the second silicon through hole 134 of the second chip 130a through the bridge 140b and the third bump 170. Here, the nature of the first chip 120a is the same as that of the second chip 130a. For example, both the first chip 120a and the second chip 130a may be logic chips, radio frequency chips, memories, or system-on-chip (SoC) of a network-on-chip (NoC), but not limited thereto.

[0066] In short, the chip packaging structure 100b of this embodiment achieves heterogeneous integration of the chipset 180 and the integrated passive component 190 into a single module through the first silicon through hole 124 of the first chip 120a and the second silicon through hole 134 of the second chip 130a.

[0067] Figure 3 is a cross-sectional schematic diagram of a chip packaging structure according to another embodiment of the present invention. Please refer to Figure 1 and Figure 3 , the chip packaging structure 100c of this embodiment is similar to the chip packaging structure 100a of Figure 1 . The difference between the two is that in this embodiment, the sizes of the first bump 150, the second bump 160, and the third bump 170 are the same. Furthermore, the chip packaging structure 100c of this embodiment further includes a first reconfiguration wiring layer RDL1. The first reconfiguration wiring layer RDL1 is disposed on the first surface 111 of the substrate 110b, and the bridge 140c and the first reconfiguration wiring layer RDL1 are located between the first chip 120c and the substrate 110b and between the second chip 130c and the substrate 110b. Further, the bridge 140c of this embodiment is buried in the first reconfiguration wiring layer RDL1, which can reduce the overall thickness of the chip packaging structure 100c. The first chip 120c is electrically connected to the substrate 110b through the first bump 150 and the first reconfiguration wiring layer RDL1. Furthermore, the chip packaging structure 100c of this embodiment further includes a second reconfiguration wiring layer RDL2, wherein the second chip 130c is electrically connected to the substrate 110b through the second bump 160 and the second reconfiguration wiring layer RDL2. Here, as Figure 3As shown, neither the first chip 120c nor the second chip 130c is provided with a through-silicon via structure. The second redistribution layer RDL2 is disposed on the second surface 113 of the substrate 110b and is located between the substrate 110b and the solder ball 175. The solder ball 175 is electrically connected to the substrate 110b through the second redistribution layer RDL2. In addition, the substrate 110b of this embodiment further includes at least one first conductive via 116 (a plurality of conductive vias 116 are schematically shown), which electrically connects the first redistribution layer RDL1 and the second redistribution layer RDL2.

[0068] In the manufacturing process, the first bump 150, the second bump 160, and the third bump 170 are first formed on the first chip 120c and the second chip 130c. Then, the first chip 120c and the second chip 130c are bonded to the substrate 110b and the bridge 140c. Since the first bump 150, the second bump 160, and the third bump 170 have the same size, when the first chip 120c and the second chip 130c are assembled with the substrate 110b and the bridge 140c, there is no need to consider the size of the connecting bumps, and a high assembly yield can be achieved, thereby improving the structural reliability of the chip package structure 100c.

[0069] Figure 4 is a cross-sectional schematic view of a chip package structure according to another embodiment of the present invention. Please refer to Figure 3 and Figure 4 simultaneously. The chip package structure 100d of this embodiment is similar to the chip package structure 100c of Figure 3 . The difference between the two is that in this embodiment, the bridge 140d is disposed on the first redistribution layer RDL1.

[0070] Figure 5 is a cross-sectional schematic view of a chip package structure according to another embodiment of the present invention. Please refer to Figure 3 and Figure 5 simultaneously. The chip package structure 100e of this embodiment is similar to the chip package structure 100c of Figure 3 . The difference between the two is that in this embodiment, the first redistribution layer RDL1' includes at least one second conductive via T (two conductive vias T are schematically shown), and the second conductive via T electrically connects the bridge 140c and the pad 112 of the substrate 110b. That is to say, the substrate 110b of this embodiment can be electrically connected to the bridge 140c through the second conductive via T, which can improve the design flexibility.

[0071] Figure 6 is a cross-sectional schematic view of a chip package structure according to another embodiment of the present invention. Please refer to Figure 4 and Figure 6 simultaneously. The chip package structure 100f of this embodiment is similar toFigure 4 is similar to the chip packaging structure 100d, and the difference between the two is that: the first reconfigured wiring layer RDL1’ includes at least one second conductive via T (two conductive vias T are schematically shown), wherein the second conductive via T electrically connects the bridge 140d and the pad 112 of the substrate 110b. That is to say, the substrate 110b of this embodiment can be electrically connected to the bridge 140d through the second conductive via T, which can improve the design flexibility.

[0072] In summary, in the chip packaging structure of the present invention, the sizes of the bumps between each chip and the substrate are the same, that is, the first bump and the second bump have the same size. Therefore, the yield of chip assembly can be improved, and further, the chip packaging structure of the present invention can have better structural reliability. Moreover, the size of the third bump can be the same as or different from the size of the first bump according to the configuration position of the bridge. If the size of the third bump is the same as the size of the first bump, when the first chip, the second chip, the substrate and the bridge are assembled, there is no need to consider the size of the connecting bumps, and a higher assembly yield can be obtained, thereby improving the structural reliability of the chip packaging structure. In addition, the properties of the first chip and the second chip can be different, so that the chip packaging structure of the present invention achieves the effect of heterogeneous integration. In addition, in addition to the first chip and the second chip (for example, two logic chips), a chipset and integrated passive components can also be arranged on the bridge and electrically connected through the through-silicon vias on the bridge and the chip, so that the chip packaging structure of the present invention achieves the effect of heterogeneous integration.

[0073] Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements on some or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A chip packaging structure, characterized in that, Comprising: A substrate having a first surface and a second surface opposite to each other; A first chip disposed on the first surface of the substrate, having a first active surface facing the first surface, and including a plurality of first pads disposed on the first active surface; A second chip disposed on the first surface of the substrate, having a second active surface facing the first surface, and including a plurality of second pads disposed on the second active surface; A bridge including a polymer layer and a pad layer located on the polymer layer; A plurality of first bumps disposed between the first chip and the substrate, wherein the first chip is electrically connected to the substrate through the plurality of first bumps; A plurality of second bumps disposed between the second chip and the substrate, wherein the second chip is electrically connected to the substrate through the plurality of second bumps, and wherein the plurality of first bumps and the plurality of second bumps have the same size; A plurality of third bumps disposed between the first chip and the bridge and between the second chip and the bridge, wherein the first chip and the second chip are respectively electrically connected to the pad layer of the bridge through the plurality of third bumps; A plurality of solder balls disposed on the second surface of the substrate and electrically connected to the substrate; Wherein the first chip includes at least one first through-silicon via, and the second chip includes at least one second through-silicon via. The at least one first through-silicon via passes through the first chip and is connected to one of the plurality of first pads. The at least one second through-silicon via passes through the second chip and is connected to one of the plurality of second pads. The first chip and the second chip are located between the bridge and the substrate, and the bridge is electrically connected to the at least one first through-silicon via and the at least one second through-silicon via through the plurality of third bumps; And A chipset disposed on the bridge and electrically connected to the at least one first through-silicon via of the first chip through the bridge and the plurality of third bumps.

2. The chip packaging structure according to claim 1, characterized in that, The plurality of third bumps have the same size as the plurality of first bumps.

3. The chip packaging structure according to claim 1, characterized in that, The plurality of third bumps have a different size from the plurality of first bumps.

4. The chip packaging structure according to claim 1, wherein, The orthographic projection of the bridge on the substrate partially overlaps the orthographic projections of the first chip and the second chip on the substrate.

5. The chip packaging structure according to claim 1, characterized in that, Further comprising: A first reconfiguration circuit layer disposed on the first surface of the substrate and located between the first chip and the substrate and between the second chip and the substrate, wherein the first chip is electrically connected to the substrate through the plurality of first bumps and the first reconfiguration circuit layer.

6. The chip packaging structure according to claim 5, characterized in that, Further comprising: The second reconfigured wiring layer is disposed on the second surface of the substrate and located between the substrate and the plurality of solder balls. The plurality of solder balls are electrically connected to the substrate through the second reconfigured wiring layer. Wherein the substrate includes at least one conductive via hole for electrically connecting the first reconfigured wiring layer and the second reconfigured wiring layer, and the second chip is electrically connected to the substrate through the plurality of second bumps and the second reconfigured wiring layer.

7. The chip packaging structure according to claim 5, wherein, Further included is: An integrated passive component, disposed on the bridge and electrically connected to the at least one second silicon via of the second chip through the bridge and the plurality of third bumps.

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