An adaptive synchronous rectification chip

Abstract

The application discloses a kind of self-adapting synchronous rectification chips, comprising: demagnetization detection circuit, pre-shutoff signal generation module, logic control module, drive module, synchronous rectification tube and internal power generation module;Wherein, the demagnetization detection circuit, pre-shutoff signal generation module, logic control module, drive module, internal power generation module are mutually connected two by two, the gate of the synchronous rectification tube is connected drive module, drain is connected demagnetization detection circuit, internal power generation module, source is connected demagnetization detection circuit, pre-shutoff signal generation module, logic control module and drive module.Adopting the self-adapting synchronous rectification pre-shutoff technology of the CCM mode of the present application, the synchronous rectification tube is turned off in advance before the end of the cycle by using pre-shutoff signal generation module control.This can effectively avoid the primary side switch tube, secondary side synchronous rectification switch tube simultaneously conducting and appearing primary side and secondary side through, primary side high spike even the case of machine explosion.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of synchronous rectification circuit, more particularly to an adaptive synchronous rectification chip in CCM mode. BACKGROUND

[0002] In a switching power supply as shown in Figure 1 , the traditional rectification technology uses Schottky diode, but the resistance of Schottky diode is relatively large, and the power consumption is large and the efficiency is low when large current is output, and the synchronous rectification technology solves the above problems.

[0003] In the synchronous rectification technology, the time of opening and closing of the synchronous rectification switch is very strict, especially the time of closing, which is more stringent than the time of opening. The synchronous rectification switch must be immediately opened or closed after the primary side switch is closed or opened, so as to ensure the normal demagnetization or excitation of the transformer. If the synchronous rectification switch is not synchronized with the closing of the primary side switch, especially in the CCM mode (Continuous Conduction Mode), the synchronous rectification switch may not be turned off in time, and at this time the primary side switch and the synchronous rectification switch are turned on at the same time, causing a very high peak voltage on the primary side, and even a machine explosion.

[0004] In the synchronous rectification chip waveform diagram as shown in Figure 2 , Figure 3 , Vds is the voltage between the synchronous rectification switch D and S, Vgs_sec is the gate voltage of the synchronous rectification switch, and Vgs_pri is the gate voltage of the primary side switch. The opening and closing of the traditional synchronous rectification switch is usually a passive turn-off mechanism, which usually judges the voltage at the D end (drain end) of the synchronous rectification switch. When the voltage at the D end of the synchronous rectification switch changes from negative to positive, the synchronous rectification switch is turned off. However, due to the influence of system delay, it takes a certain time from the time when the synchronous rectification chip detects that the voltage at the D end changes from negative to positive to the time when the synchronous rectification switch is turned off. In the DCM mode (Discontinuous Conduction Mode), the primary side switch is in the closed state during this period, and the primary side switch and the synchronous rectification switch will not be turned on at the same time. But in the CCM mode, the primary side switch is already in the open state and the synchronous rectification switch is also in the open state during this period, so a very high peak voltage will appear between the source and the drain of the primary side switch and the synchronous rectification switch, and even a machine explosion may occur. SUMMARY

[0005] The purpose of the present application is achieved by the following technical solutions.

[0006] In view of the problem that the primary side switch tube and the synchronous rectification switch tube are simultaneously turned on due to passive closing of the synchronous rectification switch tube, the application discloses a pre-closing technology, which is different from the passive closing mechanism of the traditional synchronous rectification switch and provides an active mechanism to actively pre-close the synchronous rectification tube, thereby avoiding the problem caused by simultaneous turning on of the primary side switch tube and the synchronous rectification switch tube.

[0007] The technical scheme adopted by the application to solve the technical problem is: a self-adaptive synchronous rectification chip is constructed, comprising: a demagnetization detection circuit, a pre-closing signal generation module, a logic control module, a driving module, a synchronous rectification tube, and an internal power supply generation module; wherein the demagnetization detection circuit, the pre-closing signal generation module, the logic control module, the driving module, and the internal power supply generation module are connected with each other in pairs, the gate of the synchronous rectification tube is connected with the driving module, the drain is connected with the demagnetization detection circuit and the internal power supply generation module, and the source is connected with the demagnetization detection circuit, the pre-closing signal generation module, the logic control module, and the driving module.

[0008] The demagnetization detection circuit is used for detecting the demagnetization time of the transformer and judging the working period of the synchronous rectification chip.

[0009] The pre-closing signal generation module generates the pre-closing signal of the current period based on the previous working period.

[0010] The logic control module is used for generating the timing control signal of the entire synchronous rectification tube.

[0011] The driving module is used for controlling the conduction and closing of the synchronous rectification switch tube.

[0012] The synchronous rectification tube is used for completing the synchronous rectification function.

[0013] The internal power supply generation module is used for generating the power supply, reference voltage, and current source required for the operation of each module inside the synchronous rectification chip.

[0014] The self-adaptive synchronous rectification chip disclosed by the application connects the D end of the synchronous rectification chip with the demagnetization detection circuit to detect the demagnetization time of the synchronous rectification transformer by detecting the rising edge of the D end voltage and judge the working period of the synchronous rectification chip.

[0015] The self-adaptive synchronous rectification chip disclosed by the application, the pre-closing signal generation module comprises a control signal generation circuit and a demagnetization time timing circuit; the control signal generation circuit is used for generating the control signal required by the demagnetization time timing circuit and generating the pre-closing signal of the current period; and the demagnetization time timing circuit counts the demagnetization time of the current period in the current period and calculates the 98% demagnetization time in the previous working period in the current period.

[0016] The adaptive synchronous rectification chip, the pre-shutoff signal generation module includes a control signal generation circuit and a demagnetization time timing circuit; the first input end of the control signal generation circuit is connected with the first output end of the demagnetization detection circuit, and the second input end of the control signal generation circuit is connected with the first output end of the demagnetization time timing circuit; the first output end of the control signal generation circuit is connected with the first input end of the demagnetization time timing circuit, and the second output end of the control signal generation circuit is connected with the first input end of the logic control module.

[0017] The adaptive synchronous rectification chip, the pre-shutoff signal generation module includes a control signal generation circuit and a demagnetization time timing circuit.

[0018] The demagnetization time timing circuit includes a first fixed current source, a second fixed current source, a first capacitor, a first switch tube, a second switch tube and a comparator, the first end of the first fixed current source is connected with a power supply, and the second end is connected with the first end of the first switch tube; the second end of the second fixed current source is connected with the ground, and the first end is connected with the second end of the second switch tube; the second end of the first switch tube and the first end of the second switch tube are connected with the ground through the first capacitor; the third end of the first switch tube is connected with an output end of the control signal generation circuit as the first input end of the demagnetization time timing circuit; the third end of the second switch tube is connected with an output end of the control signal generation circuit as the second input end of the demagnetization time timing circuit; the first input end of the comparator is connected with a 1.0V reference voltage, the second input end of the comparator is connected with the first end of the first capacitor, and the first output end of the comparator is connected with an input end of the control signal generation circuit as the first output end of the demagnetization time timing circuit.

[0019] The adaptive synchronous rectification chip, the logic control module is used for generating timing control signals of the whole synchronous rectification chip, including control signals of the demagnetization time timing circuit, control signals of the pre-shutoff control module and control signals of the driving circuit, and finally completes the opening and shutoff functions of the synchronous rectification tube.

[0020] The adaptive synchronous rectification chip, the driving module provides driving capacity for the opening and shutoff of the synchronous rectification tube; the input end of the driving module is connected with the output end of the logic control module, and the output end of the driving module is connected with the input end of the synchronous rectification tube.

[0021] The adaptive synchronous rectification chip, the input end of the synchronous rectification tube is connected with the output end of the driving circuit, and the synchronous rectification function is completed through the opening and shutoff of the synchronous rectification tube.

[0022] The internal power generation module is used for generating power, reference voltage and current source required by each module of the adaptive synchronous rectification chip.

[0023] The adaptive synchronous rectification chip of the present application has the advantage that the pre-off signal generation module is used to control the synchronous rectification tube to be turned off in advance before the end of the period, so that the primary side and secondary side through-penetration, primary side high spike and even machine explosion caused by the simultaneous conduction of the primary side switch tube and the secondary side synchronous rectification switch tube can be effectively avoided. BRIEF DESCRIPTION OF DRAWINGS

[0024] Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The detailed description is made with reference to the accompanying drawings.

[0025] Figure 1 : application circuit schematic diagram of traditional synchronous rectification chip;

[0026] Figure 2 : working waveform diagram of traditional synchronous rectification chip in DCM mode;

[0027] Figure 3 : working waveform diagram of traditional synchronous rectification chip in CCM mode;

[0028] Figure 4 : working waveform diagram of adaptive synchronous rectification chip of the present application;

[0029] Figure 5 : logic block diagram of the first embodiment of the adaptive synchronous rectification chip of the present application;

[0030] Figure 6 : timing circuit diagram of the first embodiment of the adaptive synchronous rectification chip of the present application;

[0031] Figure 7 : logic block diagram of the second embodiment of the adaptive synchronous rectification chip of the present application;

[0032] Figure 8 : working waveform diagram of the second embodiment of the adaptive synchronous rectification chip of the present application;

[0033] Figure 9 : circuit diagram of a first embodiment of the demagnetization detection circuit of the adaptive synchronous rectification chip of the present application;

[0034] Figure 10 : circuit diagram of a first embodiment of the logic control module of the adaptive synchronous rectification chip of the present application;

[0035] Figure 11 Figure 1 is a circuit diagram of an embodiment of a driving module of the adaptive synchronous rectification chip of the present application;

[0036] Figure 12 Figure 2 is a circuit diagram of an embodiment of an internal power supply generation module of the adaptive synchronous rectification chip of the present application;

[0037] Figure 13 Figure 3 is a circuit diagram of an embodiment of a control signal generation circuit of the adaptive synchronous rectification pre-shutoff technology in CCM mode of the present application. DETAILED DESCRIPTION

[0038] Exemplary embodiments of the present disclosure will be described below in greater detail with reference to the accompanying drawings. Although exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the embodiments set forth herein. Rather, these embodiments are provided so that the present disclosure can be more thoroughly understood and the scope of the present disclosure can be accurately conveyed to those skilled in the art.

[0039] In the working waveform diagram as shown in Figure 4 , Vds is the voltage across the synchronous rectification switch D, S, Vgs_sec is the gate voltage of the synchronous rectification tube, Vgs_pri is the gate voltage of the primary side switch, and Tdem is the demagnetization time of the secondary side winding. When the turn-on time of the synchronous rectification switch is 98% of the demagnetization time in the previous cycle, the synchronous rectification switch is actively turned off, and the remaining time is maintained by the body diode of the synchronous rectification switch, thereby maintaining the demagnetization of the secondary side winding. In this way, after the primary side switch is turned on, the secondary side synchronous rectification switch can be synchronously turned off, and the shoot-through problem caused by the simultaneous conduction of the primary side switch and the secondary side synchronous rectification switch can be avoided, thereby avoiding the occurrence of a very high peak voltage across the source and drain of the switch.

[0040] In each cycle, due to the change in line voltage and the change in load, the demagnetization time of the secondary side winding is variable. By real-time monitoring, the point of 98% of the demagnetization time of the secondary side winding in the previous cycle can be accurately calculated. Through this active closing mechanism, the closing time of the synchronous rectification switch can be very close to the opening time of the primary side switch, so that neither the problem of excessive conduction time of the body diode due to premature closing, nor the problem of simultaneous conduction of the primary side and the secondary side due to late closing occurs.

[0041] Figure 5 Figure 1 is a logic block diagram of the first embodiment of the adaptive synchronous rectification chip of the present application. As shown in Figure 5As shown, the adaptive synchronous rectification chip of the present application comprises a demagnetization detection circuit 100, a pre-off signal generation module 200, a logic control module 300, a driving module 400, an internal power supply generation module 500, and a synchronous rectification switch tube MOSFET. Among them, the demagnetization detection circuit, the pre-off signal generation module, the logic control module, the driving module, and the internal power supply generation module are connected with each other in pairs, the gate of the synchronous rectification tube is connected with the driving module, the drain is connected with the demagnetization detection circuit and the internal power supply generation module, and the source is connected with the demagnetization detection circuit, the pre-off signal generation module, the logic control module, and the driving module.

[0042] The demagnetization detection circuit 100 is connected with the D end of the synchronous rectification chip to detect the demagnetization start time of the synchronous rectification transformer by detecting the falling edge of the D end voltage, to detect the demagnetization end time of the synchronous rectification transformer by detecting the rising edge of the D end voltage, and to judge the working period of the synchronous rectification chip by detecting the D end voltage.

[0043] The demagnetization detection circuit 100 generates the first working period signal when detecting the falling edge of the D end voltage of the synchronous rectification switch tube, and generates the second working period signal when detecting the rising edge of the D end voltage.

[0044] The pre-off signal generation module 200 comprises a control signal generation circuit 210 and a first demagnetization time timing circuit 220; the control signal generation circuit 210 is used to generate the control signal required by the first demagnetization time timing circuit 220, and to generate the pre-off signal (pre_off) of the current period; the first demagnetization time timing circuit 220 completes the timing of the demagnetization time of the current period, and calculates the 98% demagnetization time of the demagnetization time of the previous period.

[0045] Figure 6Is the timing circuit 220 of the adaptive synchronous rectifier chip of the present application. The first demagnetization time timing circuit 220 comprises: a first fixed current source I1, a second fixed current source I2, a first capacitor C1, a first switch tube NM1, a second switch tube NM2 and a comparator COMP1, the first end of the first fixed current source I1 is connected to the power supply, and the second end is connected to the first end of the first switch tube NM1; The second end of the second fixed current source I2 is connected to the ground, and the first end is connected to the second end of the second switch tube NM2; The second end of the first switch tube NM1 and the first end of the second switch tube NM2 are grounded through the first capacitor C1; The third end of the first switch tube NM1 is connected to an output end of the control signal generation circuit 210 as the first input end of the demagnetization time timing circuit; The third end of the second switch tube NM2 is connected to an output end of the control signal generation circuit 210 as the second input end of the demagnetization time timing circuit; The first input end of the comparator COMP1 is connected to a 1.0V reference voltage, the second input end of the comparator COMP1 is connected to the first end of the first capacitor C1, and the first output end of the comparator COMP1 is connected to an input end of the control signal generation circuit 210 as the first output end of the demagnetization time timing circuit.

[0046] Figure 7is a logic block diagram of a second embodiment of the adaptive synchronous rectification chip of the present application. It comprises a demagnetization detection circuit 100, a pre-shutoff signal generation module 200, a logic control module 300, a driving module 400, an internal power supply generation module 500 (not shown), and a synchronous rectification switch tube. The pre-shutoff signal generation module 200 comprises a control signal generation circuit 210, a first demagnetization time counting circuit 220, and a second demagnetization time counting circuit 230; the first demagnetization time counting circuit 220 and the second demagnetization time counting circuit 230 comprise a first fixed current source I1, a second fixed current source I2, a first capacitor C1, a first switch tube NM1, a second switch tube NM2, and a comparator COMP1, a first end of the first fixed current source I1 is connected to a power supply, and a second end thereof is connected to a first end of the first switch tube NM1; a second end of the second fixed current source I2 is connected to a ground, and a first end thereof is connected to a second end of the second switch tube NM2; a second end of the first switch tube NM1 and a first end of the second switch tube NM2 are grounded via the first capacitor C1; a third end of the first switch tube NM1 serves as a first input end of the demagnetization time counting circuit and is connected to an output end of the control signal generation circuit 210; a third end of the second switch tube NM2 serves as a second input end of the demagnetization time counting circuit and is connected to an output end of the control signal generation circuit 210; a first input end of the comparator COMP1 is connected to a 1.0V reference voltage, a second input end of the comparator COMP1 is connected to a first end of the first capacitor C1, and a first output end of the comparator COMP1 serves as a first output end of the demagnetization time counting circuit and is connected to an input end of the control signal generation circuit 210.

[0047] The first input end of the control signal generation circuit 210 is connected with the first output end of the demagnetization detection circuit 100, the second input end of the control signal generation circuit 210 is connected with the first output end of the first demagnetization time counting circuit 220, and the third input end of the control signal generation circuit 210 is connected with the first output end of the second demagnetization time counting circuit 230; the first output end of the control signal generation circuit 210 is connected with the first input end of the first demagnetization time counting circuit 220, the second output end of the control signal generation circuit 210 is connected with the second input end of the first demagnetization time counting circuit 220; the fifth output end of the control signal generation circuit 210 is connected with the first input end of the second demagnetization time counting circuit 230, and the sixth output end of the control signal generation circuit 210 is connected with the second input end of the second demagnetization time counting circuit 230; the third output end of the control signal generation circuit 210 is connected with the first input end of the logic control module 300, and the fourth output end of the control signal generation circuit 210 is connected with the second input end of the logic control module 300; the second input end of the first demagnetization time counting circuit 220 and the second input end of the second demagnetization time counting circuit 230 are connected with a 1.0V reference voltage.

[0048] In the embodiment block diagram as shown in the figure, the logic control module 300 is used for generating timing control signals of the whole synchronous rectification chip, including control signals of the first demagnetization time counting circuit 220 and the second demagnetization time counting circuit 230, control signals of the pre-shutoff control module 200, and control signals of the driving circuit 400, so as to finally complete the opening and shutoff functions of the synchronous rectification tube. Figures 5-7

[0049] The driving module 400 provides driving capacity for the opening and shutoff of the synchronous rectification tube; the input end of the driving module 400 is connected with the output end of the logic control module 300, and the output end of the driving module 400 is connected with the input end of the synchronous rectification tube.

[0050] The demagnetization detection circuit 100 generates the first working cycle signal when detecting the falling edge of the D end voltage of the synchronous rectification switch tube, and generates the second working cycle signal when detecting the rising edge of the D end voltage.

[0051] The input end of the synchronous rectification tube is connected with the output end of the driving circuit 400, and the synchronous rectification function is completed through the opening and shutoff of the synchronous rectification tube.

[0052] The internal power supply generation module 500 is used for generating power supply, reference voltage and current source required by each module of the synchronous rectification chip. The 1.0V reference voltage connected with the demagnetization time counting circuit is generated by the internal power supply generation module 500. ​

[0053] Figure 8 yes Figure 7 The diagram shows the operating waveforms of an embodiment of the synchronous rectification cycle pre-turn-off technology. Those skilled in the art will understand that each module of the synchronous rectification cycle pre-turn-off circuit of the present invention can be designed using the structures described in the various embodiments of the present invention. Figure 7 The circuit design of the preferred pre-shutdown signal generation module of the present invention is shown only.

[0054] The following is combined with Figures 7-8 The principle of the adaptive synchronous rectification chip of the present invention is explained below.

[0055] In such Figure 7In the second embodiment shown, the pre-off signal generation module 200 includes a control signal generation circuit 210 and a first demagnetization time counting circuit 220 and a second demagnetization time counting circuit 230. The module counts the demagnetization time in the current period while calculating the 98% demagnetization time in the previous working period in the current period. To achieve the counting function, two groups of the first demagnetization time counting circuit 220 and the second demagnetization time counting circuit 230 are used. When the secondary winding starts demagnetization, detected by the demagnetization detection circuit 100, in the current period, the first group of the first demagnetization time counting circuit 220 charges the timing capacitor C1 therein, and the second group of the second demagnetization time counting circuit 230 discharges the timing capacitor C1 therein. The first switch tube NM1 in the first group of the first demagnetization time counting circuit 220 is turned on, the second switch tube NM2 is turned off, and the first current source I1 charges the first capacitor C1 until the demagnetization ends. The voltage on the first capacitor C1 remains unchanged at the value at the end of demagnetization until the next demagnetization period starts. The voltage on the first capacitor C1 in the first group of the first demagnetization time counting circuit 220 is recorded as VC1. The first switch tube NM1 in the second group of the second demagnetization time counting circuit 230 is turned off, the second switch tube NM2 is turned on, and the second current source I2 discharges the first capacitor C1 until the voltage on the capacitor is lower than the reference voltage (1.0V) and is turned off. The voltage on the first capacitor C1 remains unchanged at 1.0V until the next demagnetization period starts. The voltage on the first capacitor C1 in the second group of the second demagnetization time counting circuit 230 is recorded as VC2. After the next demagnetization period starts, the first group of the first demagnetization time counting circuit 220 discharges the timing capacitor C1 therein, and the second group of the second demagnetization time counting circuit 230 charges the timing capacitor C1 therein. The first switch tube NM1 in the first group of the first demagnetization time counting circuit 220 is turned off, the second switch tube NM2 is turned on, and the second current source I2 discharges the first capacitor C1 until the voltage on the capacitor C1 is lower than the reference voltage 1.0V and is turned off. The voltage on the first capacitor C1 remains unchanged at 1.0V until the next demagnetization period starts. The first switch tube NM1 in the second group of the second demagnetization time counting circuit 230 is turned on, the second switch tube NM2 is turned off, and the first current source I1 charges the first capacitor C1 until the demagnetization ends. The voltage on the first capacitor C1 remains unchanged at the value at the end of demagnetization.

[0056] The pre-off point of the pre-off technology is at the 98% time of the previous demagnetization time, and the counting is achieved by charging and discharging the first capacitor C1. The formula for calculating the charging and discharging time of the capacitor is:

[0057] If the amount of charge is the same during the capacitor's charging and discharging periods, the duration of the charging and discharging times is determined by the charging and discharging currents. The pre-shutdown point of the pre-shutdown technology described in this invention is at 98% of the previous demagnetization time. During charging, the demagnetization time timing circuit considers the entire demagnetization time as 100%, and the discharging time as 98% of the entire demagnetization time. Therefore, the charging and discharging current ratio is 98%:100% = 49:50. The charging current of the demagnetization time timing circuit is I1, and the discharging current is I2. Therefore, I1:I2 = 49:50. The pre-shutdown time can be set by those skilled in the art according to actual circuit requirements. By adjusting the ratio of I1 and I2, the desired pre-shutdown time can be obtained.

[0058] In such Figure 8 In the working waveform diagram of the second embodiment of the adaptive synchronous rectification chip of the present invention, during the first cycle of the secondary winding demagnetization time tdem, the gate signal chg1 of the first switch NM1 of the first group of the first demagnetization time timing circuit 220 is at a high level, the gate signal dis_chg1 of the second switch NM2 is at a low level, the first capacitor C1 is charged, the initial voltage is 1.0V, and it continues to charge until the demagnetization ends, that is, tdem becomes a low level position, the voltage across the capacitor is VC1, and it remains unchanged until the second demagnetization cycle begins.

[0059] During the first cycle of the secondary winding demagnetization time tdem, the gate signal chg2 of the first switch NM1 of the second group of the second demagnetization time timing circuit 230 is at ground level, and the gate signal dis_chg2 of the second switch NM2 is at high level. The first capacitor C1 discharges, and the initial voltage VC2 is at the level at the end of the previous cycle. It continues to discharge until the capacitor voltage is 1.0V. The voltage across capacitor C1 is 1.0V and remains unchanged until the second demagnetization cycle begins.

[0060] In such Figures 5-7 In the block diagram of the embodiment shown, the pre-off signal pre_off generated by the pre-off signal generation module 200 is sent to the logic control module 300. After passing through the logic control module 300 and the driving module 400, the synchronous rectifier switch gate control signal Vgs_sec is output. Finally, the driving module 400 completes the turning on and off of the synchronous rectifier.

[0061] Figure 9is an embodiment of the demagnetization detection circuit, the input end of the demagnetization detection circuit is connected with the D end of the synchronous rectification chip, and the output end outputs a signal tdem and is connected with the logic control module 300. The noninverting input end of the first comparator 101 is connected with the D end of the synchronous rectification chip through a 350 mV voltage source, the noninverting input end of the second comparator 102 is connected with the D end of the synchronous rectification chip through a 2 mV voltage source, and the inverting input ends of the first comparator 101 and the second comparator 102 are connected with a 0 V voltage source. The output end of the first comparator 101 is connected with the first input end of the second input NAND gate 105, and the output end of the second comparator 102 is connected with the first input end of the first input NAND gate 104 through the fourth inverter 103. The first input NAND gate 104 and the second input NAND gate 105 constitute an RS flip-flop, the output end of the second input NAND gate 105 is the output end of the RS flip-flop and also the output end of the demagnetization detection circuit, and outputs a demagnetization detection signal tdem. After the primary side switch is turned off, the voltage of the D end of the synchronous rectification chip is reversed, and the value of Vds is detected through the first comparator 101 and the second comparator 102. When the first comparator 101 detects that the Vds voltage is lower than -350 mV, a low level is output, the demagnetization detection circuit output signal tdem changes from low to high, the MOSFET inside the secondary side synchronous rectification chip is turned on, the transformer starts to demagnetize, and Vds starts to rise. After Vds is higher than -2 mV, the second comparator 102 is reversed, the demagnetization detection circuit output signal tdem changes from high to low, and if the pre-shutoff module 200 does not turn off the MOSFET inside the synchronous rectification chip before the tdem is reversed, the synchronous rectification MOSFET is turned off by the signal tdem through the logic control module 300 and the driving module 400.

[0062] Figure 10 is an embodiment of the logic control function module. The output signals pre_off1 and pre_off2 of the pre-shutoff module 200 are connected with the first input end and the second input end of the third input NAND gate 301, the output end is connected with the first input end of the fourth input NAND gate 302, the demagnetization detection circuit output signal tdem is connected with the second input end of the fourth input NAND gate 302, and the output end of the fourth input NAND gate 302 is connected with one input end of the fifth input NAND gate 305 through the fifth inverter 304. The demagnetization detection circuit output signal tdem is also connected with another input end of the sixth input NAND gate 306 through the sixth inverter 303. The fifth input NAND gate 305 and the sixth input NAND gate 306 constitute an RS flip-flop, the output end of the fifth input NAND gate 305 which is the output end of the RS flip-flop is connected with the input end of the seventh inverter 307, and the output end of the seventh inverter 307 is the output end of the logic control module 300 and outputs a signal Vsw. The Vsw is sent to the input end of the driving module 400.

[0063] Figure 11is an embodiment of the drive control module. The eighth inverter 401 is a small size device, the input end is connected to the output end Vsw of the logic control module 300, the output end of the eighth inverter 401 is connected to the input end of the ninth inverter 402, the output end of the ninth inverter 402 is connected to the gate Vgs_sec of the MOSFET. The ninth inverter 402 is a large size device, which provides sufficient driving capacity to ensure the rapid and reliable opening and closing of the MOSFET.

[0064] Figure 12 is an embodiment of the internal power generation module. In the application, the D end of the synchronous rectification chip is connected to the anti-phase end of the secondary winding of the transformer, and the VDD end is connected to a capacitor. Since the voltage at the D end is not a direct current, it cannot power the chip. In this embodiment, a self-power supply technology is used. When the D end is at a high level, the capacitor connected to the VDD is charged, and the current required for the operation of the chip is provided at the same time. When the D end is at a low voltage, the capacitor connected to the VDD supplies power to the chip. In this embodiment, the input end of the diode D501 and one end of the resistor R501 are connected together and connected to the D end of the synchronous rectification chip. The output end of the diode D501 is connected to the drain of N502, the other end of the resistor R501 is connected to the gate of N502 and the drain of N501, the source of N502 is connected to one end of the resistor R502 and connected to the VDD port of the synchronous rectification, and the VDD is connected to a capacitor in application. The other end of the resistor R502 is connected to the same input end of the operational amplifier OP1 and connected to the ground through the resistor R503. The resistor R502 and R503 sample the VDD. The opposite input end of the operational amplifier is connected to a direct current 2.5V power supply. The output end of the operational amplifier OP1 is connected to the gate of N501, and the source of N501 is connected to the ground. After the primary side switch is turned on, the D end of the synchronous rectification chip is at a high level. If the sampling value of the VDD is lower than the reference voltage of 2.5V, the OP1 output is low, N501 is off, the gate of N502 is high, and N502 is on. The synchronous rectification chip charges the capacitor connected to the VDD through the diode D501 and N502. When the sampling value of the VDD sampled by the resistor R502 and R503 is higher than 2.5V, N501 is on, the gate of N502 is pulled low, N502 is off, and the charging of the capacitor connected to the VDD is stopped. After the sampling voltage is lower than 2.5V, N501 is off, N502 is on, and the charging of the capacitor connected to the VDD is continued. This process is repeated to ensure the normal power supply of the chip.

[0065] Figure 13The circuit diagram of an embodiment of the control signal generation circuit of the adaptive synchronous rectification pre-shutoff technology in the CCM mode of the present application is shown in the figure. The demagnetization detection output circuit 100 outputs a signal tdem, which is connected to the clock input end C of a D flip-flop 2102 through a first inverter 2101. The input end D of the D flip-flop is connected to its output end Qb, forming a frequency dividing circuit. The output end Q of the D flip-flop is connected to one input end of a two-input NAND gate 2103, and the tdem signal is connected to the other input end of the NAND gate 2103. The output end of the NAND gate 2103 provides a charging control signal chg1 required by a first demagnetization time counting circuit 220. The output end of the NAND gate 2103 is also connected to one input end of a third NAND gate 2105, and the output end of the second demagnetization time counting circuit 230 is connected to the other input end of the third NAND gate 2105. The output end of the third NAND gate 2105 outputs a discharging control signal dischg2 required by the second demagnetization time counting circuit 230 through a second inverter 2107. The output of the second inverter 2107 is also connected to a first falling edge detection circuit 2109, which outputs a pre-shutoff signal pre_off2. The other output end Qb of the D flip-flop is connected to one input end of a two-input NAND gate 2104, and the tdem signal is connected to the other input end of the NAND gate 2104. The output end of the NAND gate 2104 provides a charging control signal chg2 required by the second demagnetization time counting circuit 230. The output end of the NAND gate 2104 is also connected to one input end of a fourth NAND gate 2106, and the output end of the first demagnetization time counting circuit 220 is connected to the other input end of the fourth NAND gate 2106. The output end of the fourth NAND gate 2106 outputs a discharging control signal dischg1 required by the first demagnetization time counting circuit 220 through a third inverter 2108. The output of the third inverter 2108 is also connected to a second falling edge detection circuit 2110, which outputs a pre-shutoff signal pre_off1.

[0066] The adaptive synchronous rectification chip of the present application is controlled by the pre-shutoff signal generation module to shut off the synchronous rectification tube at 98% of the previous demagnetization time. This can effectively avoid the primary side and secondary side through-penetration, primary side high spike, and even the explosion of the machine due to the untimely shut-off.

[0067] The above description is only a preferred embodiment of the present application, and the protection scope of the present application is not limited thereto. Any changes or replacements within the technical scope disclosed by the present application can be easily thought of by those skilled in the art, and should be covered within the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. An adaptive synchronous rectification chip, characterized in that, Comprise: Demagnetization detection circuit, pre-shutoff signal generation module, logic control module, drive module, synchronous rectifier tube, and internal power generation module; wherein, The demagnetization detection circuit, pre-shutoff signal generation module, logic control module, drive module, internal power generation module are connected with each other in pairs, the gate of the synchronous rectifier tube is connected with the drive module, the drain is connected with the demagnetization detection circuit and the internal power generation module, and the source is connected with the demagnetization detection circuit, pre-shutoff signal generation module, logic control module, and drive module; The demagnetization detection circuit is used for detecting the demagnetization time of an external synchronous rectification transformer and judging the working period of a synchronous rectification chip; The pre-shutoff signal generation module generates a pre-shutoff signal of the current period based on the demagnetization time of the previous period; The logic control module is used for generating timing control signals of the whole synchronous rectification chip; The drive module is used for controlling the conduction and shutoff of the synchronous rectification switch tube; The synchronous rectifier tube is used for completing the synchronous rectification function; The internal power generation module is used for generating power, reference voltage and required current source required by each module inside the synchronous rectification chip; The demagnetization detection circuit is connected with the D end of the synchronous rectification chip; the falling edge of the D end voltage is detected to detect the demagnetization start time of the external synchronous rectification transformer, the rising edge of the D end voltage is detected to detect the demagnetization end time of the synchronous rectification transformer, and the working period of the synchronous rectification chip is judged through the detection of the D end voltage; The pre-shutoff signal generation module comprises a control signal generation circuit and a demagnetization time timing circuit; the control signal generation circuit is used for generating the control signal required by the demagnetization time timing circuit and generating the pre-shutoff signal of the current period; and the demagnetization time timing circuit counts the demagnetization time of the current period in the current period and calculates the 98% demagnetization time in the previous working period; The first input end of the control signal generation circuit is connected with the first output end of the demagnetization detection circuit, the second input end of the control signal generation circuit is connected with the first output end of the demagnetization time timing circuit, the first output end of the control signal generation circuit is connected with the first input end of the demagnetization time timing circuit, and the second output end of the control signal generation circuit is connected with the first input end of the logic control module; The demagnetization time timing circuit comprises a first fixed current source, a second fixed current source, a first capacitor, a first switch tube, a second switch tube and a comparator; the first end of the first fixed current source is connected with a power supply, and the second end is connected with the first end of the first switch tube; the second end of the second fixed current source is connected with the ground, and the first end is connected with the second end of the second switch tube; the second end of the first switch tube and the first end of the second switch tube are grounded through the first capacitor; the third end of the first switch tube serves as the first input end of the demagnetization time timing circuit and is connected with an output end of the control signal generation circuit; and the third end of the second switch tube serves as the second input end of the demagnetization time timing circuit and is connected with an output end of the control signal generation circuit. The first input end of the comparator is connected with a reference voltage, the second input end of the comparator is connected with the first end of the first capacitor, and the first output end of the comparator is connected with an input end of the control signal generation circuit as a first output end of the demagnetization time counting circuit; The logic control module is used for generating timing control signals of the whole synchronous rectification chip, including control signals of the demagnetization time counting circuit, control signals of the pre-off signal generation module and control signals of the driving module, so as to complete the opening and closing functions of the synchronous rectification tube. The driving module provides driving capability for the opening and closing of the synchronous rectification tube, the input end of the driving module is connected with the output end of the logic control module, and the output end of the driving module is connected with the input end of the synchronous rectification tube. The input end of the synchronous rectification tube is connected with the output end of the driving module, and the synchronous rectification function is completed through the opening and closing of the synchronous rectification tube.

2. The adaptive synchronous rectification chip of claim 1, wherein, The demagnetization detection output circuit output signal tdem is connected with the clock input end C of the D flip-flop (2102) through the first inverter (2101), the input end D of the D flip-flop is connected with the output end Qb of the D flip-flop, and a two-frequency dividing circuit is formed; The output end Q of the D flip-flop is connected with one input end of the two-input first NAND gate (2103), the tdem signal is connected with the other input end of the first NAND gate (2103), the output end of the first NAND gate (2103) provides the charging control signal chg1 required by the first demagnetization time counting circuit (220), the output end of the first NAND gate (2103) is simultaneously connected with one input end of the third NAND gate (2105), the other input end of the third NAND gate (2105) is connected with the output end of the second demagnetization time counting circuit (230), the output end of the third NAND gate (2105) outputs the discharging control signal dischg2 required by the second demagnetization time counting circuit (230) through the output of the second inverter (2107), and the output of the second inverter (2107) is simultaneously connected with a first falling edge detection circuit (2109), the first falling edge detection circuit (2109) outputs the pre-off signal pre_off2; the other output end Qb of the D flip-flop is connected with one input end of the two-input second NAND gate (2104), the tdem signal is connected with the other input end of the second NAND gate (2104), the output end of the second NAND gate (2104) provides the charging control signal chg2 required by the second demagnetization time counting circuit (230), and the output end of the second NAND gate (2104) is simultaneously connected with one input end of the fourth NAND gate (2106), the other input end of the fourth NAND gate (2106) is connected with the output end of the first demagnetization time counting circuit (220), the output end of the fourth NAND gate (2106) outputs the discharging control signal dischg1 required by the first demagnetization time counting circuit (220) through the output of the third inverter (2108), and the output of the third inverter (2108) is simultaneously connected with a second falling edge detection circuit (2110), the second falling edge detection circuit (2110) outputs the pre-off signal pre_off1.

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