Channel Mismatch Calibration Method and Circuit Based on Low-Frequency Reference Clock

Abstract

The present application discloses a method and circuit for channel mismatch calibration in a time-interleaved system based on a low-frequency reference clock. The method includes: generating a plurality of sampling clocks and a low-frequency reference clock signal, where the frequency of the low-frequency reference clock signal is lower than that of the plurality of sampling clocks; sampling the low-frequency reference clock signal at a sampling rate, wherein the ratio between the frequency of the low-frequency reference clock signal and the sampling rate is set to be a prime number relative to the number of the plurality of sampling clocks; performing analog-to-digital conversion on the sampled low-frequency reference clock signal, and comparing the voltage value of the sampled signal with a threshold voltage to determine whether the digital signal corresponding to the voltage value is an edge signal, and simultaneously outputting an edge detection value; calibrating the phases of the plurality of sampling clocks according to the edge signal and the edge detection value respectively.

Description

Technical Field

[0001] The present invention generally relates to the field of integrated circuit technology, and particularly to a method and circuit for channel mismatch calibration in a time-interleaved system based on a low-frequency reference clock. Background Art

[0002] Time-interleaved (TI) analog-to-digital converters (ADCs) have been widely adopted in high-speed communication systems, thus achieving accurate data recovery with reasonable power consumption. The TI architecture utilizes power-efficient sub-ADCs by relaxing the operating speed of each channel, while its inherent channel mismatches (offset, gain, and skew errors) limit the overall ADC performance. In addition, as the ADC conversion speed reaches above 50 GHz, even in the most advanced process technologies, it is impossible to drive a single-phase high-frequency clock source as the sampling clock for each channel ADC. Therefore, recent ultra-high-speed ADCs generate sampling phases from multiple master clock sources with different phases (i.e., differential-phase or quadrature-phase clock sources), which introduces significant skew errors in TI ADCs.

[0003] Various calibration algorithms have been developed in the background or foreground manner to address channel mismatches. In the background method, the channel ADC outputs are compensated by using an additional reference channel or expected input statistics. The reference-channel-based technique can ensure high calibration performance but results in additional hardware complexity associated with the reference channel. On the other hand, when calibration depends on input statistics, the ADC performance may be affected by the characteristics of the input signal such as frequency, amplitude, distortion, etc., which are difficult to predict in many applications. As a result, although the background method can adapt to the operation of the ADC according to process, voltage, and temperature (PVT) variations without interrupting data conversion, it is not very popular in the industry.

[0004] On the other hand, the front-end method using known reference signals and dedicated time slots can provide flexibility and robustness in error detection and compensation. Although it has a long history, a comprehensive front-end method for calibrating TIADC has not been established, especially when dealing with skew errors. Recently, an intuitive solution was published in "T. Miki, "A 2-GS / s 8-bit Time-Interleaved SAR ADC for Millimeter-Wave Pulsed Radar Baseband SoC", IEEE J. Solid-State Circuits." This method uses a full-rate reference clock to detect skew errors between sub-channels. Gain and offset errors can be corrected by applying a DC input using a separate procedure. Since the main clock is used as a reference, it can provide built-in test functions. However, for conversion speeds exceeding 50 GS / s, the CMOS process technology cannot withstand full-rate clock processing, so it is difficult to directly apply it to future high-speed TI ADCs. In addition, the maximum slope detection proposed in "T. Miki, "A 2-GS / s 8-bit Time-Interleaved SAR ADC for Millimeter-Wave Pulsed Radar Baseband SoC", IEEE J. Solid-State Circuits." is vulnerable to jitter and the rise / fall time of the reference clock. SUMMARY OF THE INVENTION

[0005] An object of the present invention is to provide a channel mismatch calibration method and circuit based on a low-frequency reference clock, which relaxes the speed requirement of the TI structure for the clock source and can make it widely used in ultra-high-speed TI ADCs.

[0006] The present application discloses a channel mismatch calibration circuit based on a low-frequency reference clock, comprising:

[0007] A clock generation circuit for generating a low-frequency reference clock signal and a plurality of sampling clocks, wherein the frequency of the low-frequency reference clock signal is lower than that of the plurality of sampling clocks;

[0008] A plurality of sampling circuits, each receiving one of the low-frequency reference clock signal and the plurality of sampling clocks, and the plurality of sampling circuits sample the low-frequency reference clock signal at a sampling rate respectively, wherein the ratio between the frequency of the low-frequency reference clock signal and the sampling rate is set to be a prime number relative to the number of the plurality of sampling clocks;

[0009] Multiple sub-ADC circuits, each of the sampling circuits is respectively connected to one or more sub-ADC circuits and outputs a sampling signal to the connected one or more sub-ADC circuits. The connected one or more sub-ADC circuits perform analog-to-digital conversion on the sampled low-frequency reference clock signal, and compare the voltage value of the sampled signal with a threshold voltage to determine whether the digital signal corresponding to the voltage value is an edge signal, and simultaneously output an edge detection value;

[0010] Multiple skew calibration circuits, which are respectively connected to the connected one or more sub-ADC circuits, are used to receive the converted digital signal and calibrate the phases of the multiple sampling clocks respectively according to the edge signal and the edge detection value.

[0011] In a preferred example, it further includes: a perturbation injection circuit, which is connected to the clock generation circuit and is used to add pseudo-random noise to the low-frequency reference clock signal.

[0012] In a preferred example, when the voltage value of the sampled low-frequency reference clock signal is within the threshold range Vth~-Vth, the edge detection value is 0. When the voltage value of the low-frequency reference clock signal is greater than the threshold Vth, the edge detection value is 1. When the voltage value of the low-frequency reference clock signal is less than the threshold -Vth, the edge detection value is -1. The channel mismatch calibration circuit further includes: a threshold voltage adjustment circuit, which is connected to the multiple sub-ADC circuits and receives the edge detection value. When the edge detection values are -1 and 1 in sequence, the threshold voltage is increased. When the edge detection values are 0 and 0 in sequence, the threshold voltage is decreased.

[0013] In a preferred example, it further includes: a reference clock adjustment circuit, which is used to receive the edge signals of the multiple sub-ADC circuits and calculate the absolute values of each edge signal within a plurality of clock cycles of the low-frequency reference clock signal in sequence, select the largest one among the absolute values, and adjust the phase of the low-frequency reference clock signal until the absolute value reaches the minimum value.

[0014] In a preferred example, the number of the multiple sampling clocks is 2 n , and the ratio between the frequency of the low-frequency reference clock signal and the sampling rate is set to any odd number.

[0015] In a preferred example, it further includes: multiple gain calibration circuits, which are respectively connected to a sub-ADC circuit and adjust the gain according to the digital signal output by the sub-ADC circuit.

[0016] In a preferred example, it further includes: multiple offset calibration circuits, which are respectively connected to a sub-ADC circuit and adjust the offset according to the digital signal output by the sub-ADC circuit.

[0017] The present application also discloses a channel mismatch calibration method based on a low-frequency reference clock, including:

[0018] Generating a plurality of sampling clocks and a low-frequency reference clock signal, wherein the frequency of the low-frequency reference clock signal is lower than that of the plurality of sampling clocks;

[0019] Sampling the low-frequency reference clock signal at a sampling rate, wherein the ratio between the frequency of the low-frequency reference clock signal and the sampling rate is set to be a prime number relative to the number of the plurality of sampling clocks;

[0020] Performing analog-to-digital conversion on the sampled low-frequency reference clock signal, comparing the voltage value of the sampled signal with a threshold voltage to determine whether the digital signal corresponding to the voltage value is an edge signal, and outputting an edge detection value at the same time;

[0021] Calibrating the phases of the plurality of sampling clocks according to the edge signal and the edge detection value respectively.

[0022] In a preferred example, pseudo-random noise is added to the low-frequency reference clock signal.

[0023] In a preferred example, when the voltage value of the sampled low-frequency reference clock signal is within the threshold range Vth~-Vth, the edge detection value is 0; when the voltage value of the low-frequency reference clock signal is greater than the threshold Vth, the edge detection value is 1; when the voltage value of the low-frequency reference clock signal is less than the threshold -Vth, the edge detection value is -1; when the edge detection values are -1 and 1 in sequence, the threshold voltage is increased; when the edge detection values are 0 and 0 in sequence, the threshold voltage is decreased.

[0024] In a preferred example, calculating the absolute values of the edge signals of the plurality of sub-ADC circuits within a plurality of clock cycles of the low-frequency reference clock signal, and selecting the largest one among the absolute values; adjusting the phase of the low-frequency reference clock signal until the absolute value reaches the minimum value.

[0025] The present application also discloses a channel mismatch calibration circuit based on a low-frequency reference clock, including:

[0026] A clock generation circuit for generating a low-frequency reference clock signal and a plurality of sampling clocks, wherein the frequency of the low-frequency reference clock signal is lower than that of the plurality of sampling clocks;

[0027] A plurality of sub-DAC circuits for receiving the plurality of sampling clocks and performing digital-to-analog conversion to output an analog signal;

[0028] An ADC circuit for receiving the analog signal and the low-frequency reference clock signal, sampling the analog signal at a sampling rate and performing analog-to-digital conversion, and comparing the voltage value of the sampled signal with a threshold voltage to determine whether the digital signal corresponding to the voltage value is an edge signal, and outputting an edge detection value, wherein the ratio between the frequency of the low-frequency reference clock signal and the sampling rate is set to be a prime number relative to the number of the multiplexed sampling clocks;

[0029] A plurality of skew calibration circuits for calibrating the phases of the multiplexed sampling clocks according to the edge signal and the edge detection value respectively.

[0030] The proposed scheme uses a reference clock much lower than the ADC sampling frequency to compensate for offset, gain, and skew mismatches simultaneously. The low-frequency reference clock allows the use of multiple low-speed clock sources to calibrate TI ADCs exceeding 50 GHz. For skew calibration, the edge detection method adaptively trains the edge window to enhance flexibility and robustness in implementation. The essence of this method is that it greatly relaxes the speed requirements of the TI structure for clock sources and can make it widely used in ultra-high-speed TI ADCs. The design of an 80 GS / s 8-bit time-interleaved pipelined SAR ADC verifies the effectiveness of the proposed technique. Behavioral simulation results show that this method can increase the SNDR by an average of 22 dB. Description of the Drawings

[0031] The non-limiting and non-exhaustive embodiments of the present application are described with reference to the following drawings, wherein the same reference numerals refer to the same parts in each drawing unless otherwise specified.

[0032] Figure 1 The circuit diagram of the channel mismatch calibration circuit based on a low-frequency reference clock in an embodiment of the present application is shown.

[0033] Figure 2 The schematic diagram of the time-interleaved DAC framework in an embodiment of the present application is shown.

[0034] Figure 3 The basic schematic diagram of the edge calibration in an embodiment of the present application is shown.

[0035] Figure 4 The schematic diagram of the threshold voltage adaptation process in an embodiment of the present application is shown.

[0036] Figure 5 The schematic diagram of injecting pseudo-random noise in the edge calibration in an embodiment of the present application is shown.

[0037] Figure 6 The schematic diagram of the reference clock calibration in an embodiment of the present application is shown.

[0038] Figure 7 The flowchart of the reference clock calibration method in an embodiment of the present application is shown.

[0039] Figure 8 The schematic diagrams of the FFT before and after calibration in an embodiment of the present application are shown.

[0040] Figure 9 The schematic diagrams of the Monte Carlo simulation before and after calibration in an embodiment of the present application are shown.

[0041] Figure 10 The flowchart of the channel mismatch calibration method based on a low-frequency reference clock in an embodiment of the present application is shown.

[0042] Figure 11 The circuit diagram of the channel mismatch calibration circuit based on a low-frequency reference clock in another embodiment of the present application is shown. Detailed implementation manners

[0043] Aspects and examples of the present application will now be described. The following description provides specific details for a thorough understanding and implementation of the descriptions of these examples. However, those skilled in the art will understand that the present application can be practiced without many of these details.

[0044] In addition, some well-known structures or functions may not be shown or described in detail in order to be concise and avoid unnecessarily obscuring the relevant descriptions.

[0045] The terms used in the following description are intended to be interpreted in the broadest reasonable manner, even when used in conjunction with the detailed description of certain specific examples of the present application. The following may even emphasize certain terms. However, any terms intended to be interpreted in a restricted manner will be clearly and specifically defined in this detailed description section.

[0046] Part of the innovation of the present invention lies in:

[0047] In the present invention, for channel mismatch calibration based on a low-frequency reference clock, first, multiple sampling clocks and a low-frequency reference clock signal are generated. The multiple sampling clocks sample the low-frequency reference clock signal at a sampling rate, and the ratio between the frequency of the low-frequency reference clock signal and the sampling rate is set to be a prime number relative to the number of the multiple sampling clocks. The voltage value of the sampled signal is compared with a threshold voltage to determine whether the digital signal corresponding to the voltage value is an edge signal, and the multiple sampling clocks are calibrated respectively according to the edge signal, so as to achieve skew calibration.

[0048] The present invention uses a low-frequency reference clock as an input to compensate for gain, offset, and skew errors in a single process. The lower-frequency reference clock not only reduces the complexity and power consumption required for high-speed calibration but also enables TI ADC operation to use a multi-phase low-frequency clock source instead of a single high-speed clock source. When the sampling clock rate reaches several tens of GHz, ensuring a sufficient tuning range for the skew control circuit with small jitter becomes another design challenge. In the proposed algorithm, the reference clock skew calibration, as a rough version of the skew calibration, greatly relaxes the tuning range requirements in each sub-ADC clock path. In addition, to achieve flexibility and robustness, an edge window adaptive method is introduced in the skew error detection. Finally, a pseudo-random noise (PN) signal is injected through the reference clock path, which can accelerate the convergence time and reduce the bandwidth requirements of the reference clock path.

[0049] Embodiment 1

[0050] Embodiment 1 of the present application discloses a channel mismatch calibration circuit based on a low-frequency reference clock. Figure 1 A schematic structural diagram of the calibration circuit is shown, including a clock generation circuit 10, a plurality of sampling circuits 20, a plurality of sub-ADC (SUB-ADC) circuits 30, and a plurality of skew calibration circuits 40.

[0051] The clock generation circuit 10 is used to generate a low-frequency reference clock signal (reference clock) and a plurality of sampling clocks (sampling clock), for example, n sampling clocks, and the plurality of sampling clocks correspond to the number of the plurality of sampling circuits. The frequency of the low-frequency reference clock signal is lower than that of the plurality of sampling clocks.

[0052] Each of the plurality of sampling circuits 20 receives one of the low-frequency reference clock signal and the plurality of sampling clocks, and the plurality of sampling circuits sample the low-frequency reference clock signal at a sampling rate respectively. Among them, the ratio between the frequency of the low-frequency reference clock signal and the sampling rate is set to be a prime number relative to the number of the plurality of sampling clocks. In one embodiment, the number of the plurality of sampling clocks is 2 n , for example, 4, 16, 64, etc., and the ratio between the frequency of the low-frequency reference clock signal and the sampling rate is set to be any odd number, for example, 9, 27, etc.

[0053] Among multiple sub-ADC circuits 30, each of the sampling circuits 20 is respectively connected to one or more sub-ADC circuits 30 and outputs a sampling signal to the connected one or more sub-ADC circuits 30. The connected one or more sub-ADC circuits 30 perform analog-to-digital conversion on the sampled low-frequency reference clock signal (i.e., the sampled voltage Vi), and compare the voltage value Vi of the sampled signal with the threshold voltage Vth to determine whether the digital signal Dch(i) corresponding to this voltage value is an edge signal Dedge(i), and at the same time output an edge detection value Sch(i). Here, i represents the corresponding channel number. Figure 1 In the example of Figure 1 , taking the case where one sampling circuit is connected to one sub-ADC circuit as an example, it should be understood that one sampling circuit can be connected to multiple sub-ADC circuits, for example, 2, 4, etc.

[0054] Multiple skew calibration circuits 41 are respectively connected to the connected one or more sub-ADC circuits 20, and are used to receive the converted digital signal Dch(i) and calibrate the phase of the multiplexed sampling clock according to the edge signal Dedge(i) and the edge detection value Sch(i) respectively.

[0055] In one embodiment, the calibration circuit further includes multiple gain calibration circuits 41, which are respectively connected to one sub-ADC circuit 30 and adjust the gain according to the digital signal Dch(i) output by the sub-ADC circuit 30.

[0056] In one embodiment, the calibration circuit further includes multiple offset calibration circuits, which are respectively connected to one sub-ADC circuit 30 and adjust the offset according to the digital signal Dch(i) output by the sub-ADC circuit 30.

[0057] It should be noted that when one sampling circuit is connected to multiple sub-ADC circuits, these multiple sub-ADC circuits are commonly connected to the same skew calibration circuit, while each sub-ADC circuit is respectively connected to one gain calibration circuit and one offset calibration circuit.

[0058] In one embodiment, the calibration circuit further includes a perturbation injection circuit 50, which is connected to the clock generation circuit 10 and is used to add pseudo-random noise (PN) to the low-frequency reference clock signal. It should be understood that any existing or future-known injection technology can be used for the injection of pseudo-random noise.

[0059] In one embodiment, when the voltage value of the sampled low-frequency reference clock signal is within the threshold range Vth to -Vth, the edge detection value Sch(i) is 0; when the voltage value of the low-frequency reference clock signal is greater than the threshold Vth, the edge detection value Sch(i) is 1; when the voltage value of the low-frequency reference clock signal is less than the threshold -Vth, the edge detection value Sch(i) is -1. The channel mismatch calibration circuit further includes a threshold voltage adjustment circuit (not shown in the figure), which is connected to the multiple sub-ADC circuits and receives the edge detection value Sch(i). When the edge detection values Sch(i) are -1 and 1 in sequence, the threshold voltage Vth is increased; when the edge detection values Sch(i) are 0 and 0 in sequence, the threshold voltage Vth is decreased.

[0060] In one embodiment, the calibration circuit further includes a reference clock adjustment circuit (not shown in the figure) for adjusting the phase of the reference clock. The purpose of adjusting the reference clock is to minimize the adjustment range of clock skew in the ADC sampling circuit. The specific implementation method is to obtain the edge signals Dedge(i) of each channel, and sequentially calculate the absolute values of the edge signals Dedge(i) within a plurality of clock cycles of the low-frequency reference clock signal, and select the largest absolute value MAX(ABS[Dedge(i)]) among the absolute values, that is, MAX(ABS[Dedge(i)]) is used as the evaluation criterion for the relative position of the reference clock with respect to the sampling clock. By scanning the phase settings of all reference clocks or using the binary search method to search for the phase settings of the reference clock until the phase setting of the reference clock with the smallest value among all evaluation criteria MAX(ABS[Dedge(i)]) is found. It should be noted that when adjusting the phase of the reference clock, it should be ensured that each channel samples one or more edge signals Dedge(i) to ensure the reliability of the phase adjustment.

[0061] Figure 2A block diagram of an 80 GS / s TI ADC with digital calibration function is shown. The TI ADC includes M identical sub-ADC circuits 205, typically implemented in a successive approximation register (SAR) or pipeline structure. An analog multiplexer (MUX) 203 placed at the front end selects the input between an external analog signal and a low-frequency reference clock. The reference clock is generated by a phase-locked loop (PLL) 202 from one of the master clock sources of the clock generator 201. The ratio between the reference clock and the sampling rate is set to a relatively prime number of the number of sampling circuits, so that each sampling circuit has the opportunity to sample the edge of the reference clock. Following the analog MUX, the input signal is sampled and buffered to drive multiple sub-ADC circuits (in this case, each sampling circuit drives 4 sub-ADCs). The sampling clock is generated from multiple external clock sources of the clock generator 201, and these external clock sources should have a uniform sampling delay and be evenly spaced between consecutive clock phases. In other words, the proposed TI ADC architecture can achieve 80 GHz sampling using a 4-phase 20 GHz clock source instead of a single 80 GHz high-speed clock. To ensure the overall ADC performance, a reference clock of 2.96 GHz (1 / 27 of the full-rate sampling frequency) can be used to compensate for the sampling skew error. Free from the full-rate clock, the ADC design can be greatly simplified, saving a large amount of power and area. Also, the number of skew control modules (i.e., skew calibration circuits) in the digital calibration circuit 206 is consistent with the number of the first-stage sampling circuits, Figure 2 The mid-tuning amount Dt represents the tuning result of the sampling clock of each skew calibration circuit, while the offset and gain errors are adjusted for each sub-ADC channel respectively, that is, the number of gain and offset calibration circuits is consistent with the number of sub-ADC channels.

[0062] The phase difference between consecutive sampling clocks should be kept consistent. Therefore, the full-rate clock would be the preferred choice for skew calibration to provide an accurate sampling time reference. However, when the conversion rate is higher than dozens of GS / s, the generation of the full-rate clock will significantly increase the power consumption and limit the conversion speed of the TI ADC. The present invention uses a low-frequency reference clock as the reference signal for skew calibration to increase the ADC speed and alleviate the design challenges in high-speed clock circuits.

[0063] When the full-rate clock is divided by a relatively prime number (K) divided by the number of sampling circuits (N) and used as the input of the sampling circuit, statistically, each sampling circuit will observe the same input with a certain delay. Conversely, if the sampling intervals between the sampling clocks are consistent, in every K×N samplings, all sampling circuits will obtain the same analog value from the reference clock. In particular, when using the rising or falling edge of the clock as the reference point, the difference in the sampling values can be used as a measure of skew detection.

[0064] AsFigure 2 and Figure 3 As shown, a 9-divided reference clock is used to calibrate a TI ADC with four sampling circuits. Clock Q1 samples the falling edge of the reference clock at the third sampling point. After nine samplings, clock Q2 samples the falling edge, and so on. Thus, all four sampling clocks alternately sample one clock edge every nine samplings, and the sampled data provides the phase information of each clock. The skew error can be eliminated by adjusting the delay of each sampling clock until all sub-ADCs output the same data. To make it more general, each sampling circuit finds its own time window in every K×N for skew calibration.

[0065] Assume Dedge(i) is the delay control code of the i-th sampling clock path, then the control code is modified as follows by the gradient descent method:

[0066] D skew(i),n+1 = D skew(i),u - u * D edge(i)

[0067] where u is determined by the gear-shifting method to balance the convergence speed and accuracy, D skew(i),n is the n-th output of the i-th skew calibration circuit, D skew(i),n+1 is the (n + 1)-th output of the i-th skew calibration circuit.

[0068] One of the key points of the proposed skew calibration circuit is how to identify the valid edge sampling from the ADC outputs of the sequence. From the inherent characteristics of the reference clock frequency, it is possible that we can pick out the edge samples from the first edge sample. However, in practice, due to the uncertainty of the reference clock delay to the sampling point, the first edge sampling is not so obvious. In addition, according to the slope of the reference clock, all sampling circuits may miss the transition sampling (steep slope), or multiple sampling circuits may sample the reference clock during the transition (slow slope).

[0069] To simplify the implementation, the present invention proposes the concept of a threshold-based edge window in edge detection. As Figure 3 shown, in this method, the edge detection value Sch(i) of the sequence of TI ADC outputs will be further quantized to 1.5 bits (i.e., [-1, 0, 1]) by two threshold voltages Vth and -Vth. The data pattern filter identifies the transition pattern [-1, 0, 1] (rising pattern) or [1, 0, -1] (falling pattern) from this output. It is certain that the output corresponding to the re-quantized code 0 is regarded as the edge position, and the edge detection value Sch(i) of this output is used for skew correction.

[0070] Obviously, the functionality of this method now depends on the choice of the threshold voltage. Currently, the threshold voltage is adjusted by monitoring the ADC output. Once the [-1, 1] data pattern is observed, it is considered that the threshold voltage with respect to the edge slope is too small, so Vth is increased. Conversely, when multiple 0s are observed, Vth is decreased, as Figure 4 shown. Therefore, threshold adaptation greatly relaxes the requirements for the reference clock and makes the calibration algorithm less sensitive to the properties of the reference clock under this PVT variation.

[0071] Another way to determine the edge position is to search for the maximum output code change ΔV(= Dch(i + 1)-Dch(i)) and consider the one with the smaller absolute value of either of the two samplings as the edge sampling. Setting this position as the starting point, the next edge can be found after N samplings of channel number mod(N, M)+i.

[0072] When the slope of the input reference clock is very slow, due to quantization noise, it is not possible to well distinguish the converted skew error into an amplitude that is less than the LSB of the sub-ADC. To mitigate this fundamental limitation of the skew calibration performance, as Figure 5 shown, pseudo-random noise (PN) is injected into the reference clock path. The PN signal randomizes the input data and mitigates the bias convergence caused by quantization noise. This circuit is implemented by controlling the delay of the reference clock path with a PN pattern, i.e., the pseudo-random noise generator 501 controls the delay line 502 of the reference clock. The data applied to the tunable delay line can be a single bit or multiple bits. The multi-bit PN code can introduce more different inputs into the sampling circuit and further improve the calibration accuracy according to the same quantization noise.

[0073] One of the common problems in skew calibration is the trade-off between power consumption and adjustment range in the skew control circuit. In principle, the skew control range determined by the slope of the sampling clock edge also has a great impact on the jitter performance. Therefore, a larger tuning range will result in higher power consumption to maintain a similar jitter performance level. On the other hand, when there is a skew error between the reference clock path and the sampling clock path, each skew control circuit requires a wide tuning range to align the sampling point with the transition point of the reference clock.

[0074] In Figure 6 , all edge samplings from the sampling circuit are wrapped within a reference clock falling edge to show their variations. Initially, the edge samplings may be far from the optimal edge position, which may saturate some skew control codes to one side but still not reach the center of the edge. The reference clock skew calibration moves the edge to the optimal skew calibration window by adjusting the delay of the reference clock path.

[0075] As Figure 7As shown, the reference clock skew calibration uses a method similar to skew calibration and has edge detection and threshold voltage Vth adaptation functions. Considering the large skew between the reference clock path and the sampling clock path, the phase adjustment step is greater than the phase adjustment step of the skew control step in the sampling clock path. The goal of calibration is to make the edge center as close as possible to all sampling edges, that is, to find the minimum value of MAX(ABS[Dedge(i)]). The simplest method is to test all valid reference clock skew control codes Dref_skew one by one and use the minimum value of the evaluation criterion MAX(ABS[Dedge(i)]) as the best reference skew control code. This brute-force search method results in a long calibration time. Another method is to perform a binary search, with each round of search halving, and the search direction is determined by meeting the criterion MAX(ABS[Dedge(i)]).

[0076] The gain and offset errors mainly come from the flat part of the reference clock, which is not used for skew calibration. By driving the statistical information of each sub-ADC output to a single target, these errors can be corrected. Both gain and offset calibration use a data-based gradient descent method as follows:

[0077] D ost(i),n+1 = D ost(i),n - u * (D ch(i) - D TO )

[0078] D gain(i),n+1 = D gain(i),n - u * (abs(D ch(i) ) - D TG )

[0079] Similar to skew calibration, the update step size u is dynamically changed by the gear-shifting method to balance the convergence speed and accuracy. D ost(i),n is the nth output of the ith offset calibration circuit, D ost(i),n+1 is the (n + 1)th output of the ith offset calibration circuit, D TO is the offset calibration target, D gain(i),n is the nth output of the ith gain calibration circuit, D gain(i),n+1 is the (n + 1)th output of the ith gain calibration circuit, D TG is the offset calibration target. And, the calibration target D TO 、D TG of the sub-ADC output can be configured as a constant value or an average value of the ADC output.

[0080] Table 1 summarizes the error residues. The proposed calibration scheme can correct the gain, offset, and skew errors to the limit of the analog circuit adjustment step.

[0081] Table 1 Error comparison before and after TI ADC calibration

[0082]

[0083] Figure 8 The FFT spectra before and after calibration are shown. Obviously, the spurs caused by offset error will be significantly attenuated after calibration. Monte Carlo simulations with over 500 tests were performed. Figure 9 It shows that, on average, the proposed calibration scheme improves the ENOB (Effective Number of Bits) by 3.65 bits. In other words, the SNDR is increased by 22 dB.

[0084] Embodiment 2

[0085] A channel mismatch calibration method based on a low-frequency reference clock is disclosed in Embodiment 2 of the present application. Figure 10 The flowchart of the channel mismatch calibration method is shown. The method includes:

[0086] Step 1001: Generate multiple sampling clocks and a low-frequency reference clock signal, where the frequency of the low-frequency reference clock signal is lower than that of the multiple sampling clocks;

[0087] Step 1002: Sample the low-frequency reference clock signal at a sampling rate, where the ratio between the frequency of the low-frequency reference clock signal and the sampling rate is set as a prime number relative to the number of the multiple sampling clocks;

[0088] Step 1003: Perform analog-to-digital conversion on the sampled low-frequency reference clock signal, and compare the voltage value of the sampled signal with a threshold voltage to determine whether the digital signal corresponding to the voltage value is an edge signal, and output an edge detection value at the same time;

[0089] Step 1004: Calibrate the phases of the multiple sampling clocks according to the edge signal and the edge detection value respectively.

[0090] In a preferred example, pseudo-random noise is added to the low-frequency reference clock signal.

[0091] In a preferred example, when the voltage value of the sampled low-frequency reference clock signal is within the threshold range Vth~-Vth, the edge detection value is 0. When the voltage value of the low-frequency reference clock signal is greater than the threshold Vth, the edge detection value is 1. When the voltage value of the low-frequency reference clock signal is less than the threshold -Vth, the edge detection value is -1; when the edge detection values are -1 and 1 in sequence, increase the threshold voltage; when the edge detection values are 0 and 0 in sequence, decrease the threshold voltage.

[0092] In a preferred example, the absolute values of the edge signals of the multiple sub-ADC circuits within a certain number of clock cycles of the low-frequency reference clock signal are calculated, and the largest one among the absolute values is selected; the phase of the low-frequency reference clock signal is adjusted until the absolute value reaches the minimum value.

[0093] Embodiment III

[0094] A channel mismatch calibration circuit based on a low-frequency reference clock is disclosed in Embodiment III of the present application. Different from Embodiment I, this embodiment is applicable to a TI DAC circuit. The calibration circuit includes a clock generation circuit, multiple sub-DAC circuits, an ADC circuit, and multiple skew calibration circuits. Among them, the clock generation circuit is used to generate a low-frequency reference clock signal and multiple sampling clocks, and the frequency of the low-frequency reference clock signal is lower than that of the multiple sampling clocks. The multiple sub-DAC circuits are used to receive the multiple sampling clocks and perform digital-to-analog conversion to output analog signals. The ADC circuit is used to receive the analog signal and the low-frequency reference clock signal, sample the analog signal at a sampling rate and perform analog-to-digital conversion, and compare the voltage value of the sampled signal with a threshold voltage to determine whether the digital signal corresponding to the voltage value is an edge signal, and at the same time output an edge detection value. Among them, the ratio between the frequency of the low-frequency reference clock signal and the sampling rate is set to be a prime number relative to the number of the multiple sampling clocks. The multiple skew calibration circuits are used to calibrate the phases of the multiple sampling clocks according to the edge signal and the edge detection value respectively.

[0095] Figure 11 The block diagram of a TI DAC with digital calibration function is shown. Similar to a time-interleaved ADC, skew variations between sub-DAC channels will also introduce the same distortion in the final DAC output. To eliminate this error, an additional low-speed auxiliary ADC can be added to sample the DAC output and convert it into a digital signal. The ADC can be implemented using different architectures, such as SAR, pipelined, or flash, etc. The ADC output can be fed to the same skew calibration module as in Embodiment I above to correct the skew error. To facilitate edge detection in a time-interleaved DAC architecture, the digital inputs of the sub-DAC channels should be programmed to generate full-range edges. Similarly, each sub-channel should be able to generate rising and falling edge transitions in a random manner (PRBS mode) or a rotating manner (fixed mode). The sampling clock of the ADC is set to fs / K, and K is a prime number of M. In this setting, the auxiliary ADC sequentially samples the edges generated from the sub-DAC channels, and the skew calibration engine will correct the skew error by forcing the edges to zero.

[0096] The reference clock calibration scheme proposed by the present invention for time-interleaved ADCs can also be implemented here. Using Figure 11The digital control delay line module shown can adjust the phase of the ADC sampling clock to reduce the tuning range requirements for skew control of each sub-DAC channel. Additionally, pseudo-random noise can be injected to further enhance the skew calibration performance.

[0097] It should be noted that in the application documents of this patent, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the term "comprising", "including" or any other variant thereof is intended to cover non-exclusive inclusion, such that a process, method, article or device comprising a series of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "comprising one" does not exclude the presence of additional identical elements in the process, method, article or device comprising the said element. In the application documents of this patent, if it is mentioned that an act is performed according to a certain element, it means performing the act according to at least that element, including two cases: performing the act only according to that element and performing the act according to that element and other elements. Expressions such as multiple, many times, various include 2, 2 times, 2 kinds, as well as more than 2, more than 2 times, more than 2 kinds.

[0098] All documents mentioned in this specification are considered to be integrally included in the disclosure content of this application so that they can be used as a basis for modification if necessary. In addition, it should be understood that the above are only preferred embodiments of this specification and are not used to limit the protection scope of this specification. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of one or more embodiments of this specification shall be included within the protection scope of one or more embodiments of this specification.

[0099] In some cases, the actions or steps recited in the claims can be performed in a different order than in the embodiments and still achieve the desired result. Additionally, the processes depicted in the figures do not necessarily require the specific order or sequential order shown to achieve the desired result. In certain embodiments, multitasking and parallel processing are also possible or may be advantageous.

Claims

1. A channel mismatch calibration circuit based on a low-frequency reference clock, characterized in that, it includes: A clock generation circuit for generating a low-frequency reference clock signal and a plurality of sampling clocks, wherein the frequency of the low-frequency reference clock signal is lower than that of the plurality of sampling clocks; A plurality of sampling circuits respectively receiving the low-frequency reference clock signal and one of the plurality of sampling clocks, and the plurality of sampling circuits sample the low-frequency reference clock signal at a sampling rate respectively, wherein the ratio between the frequency of the low-frequency reference clock signal and the sampling rate is set to be a prime number relative to the number of the plurality of sampling clocks; A plurality of sub-ADC circuits, each of the sampling circuits is respectively connected to one or more sub-ADC circuits and outputs a sampling signal to the connected one or more sub-ADC circuits, and the connected one or more sub-ADC circuits perform analog-to-digital conversion on the sampled low-frequency reference clock signal, and compare the voltage value of the sampled signal with a threshold voltage to determine whether the digital signal corresponding to the voltage value is an edge signal, and output an edge detection value at the same time, wherein when the voltage value of the sampled low-frequency reference clock signal is within the threshold range Vth~-Vth, the edge detection value is 0, when the voltage value of the low-frequency reference clock signal is greater than the threshold Vth, the edge detection value is 1, and when the voltage value of the low-frequency reference clock signal is less than the threshold -Vth, the edge detection value is -1; A plurality of skew calibration circuits are respectively connected to the connected one or more sub-ADC circuits, and are used for receiving the converted digital signal and calibrating the phase of the plurality of sampling clocks respectively according to the edge signal and the edge detection value.

2. The channel mismatch calibration circuit based on a low-frequency reference clock according to claim 1, characterized in that, it further includes: A perturbation injection circuit connected to the clock generation circuit and used for adding pseudo-random noise to the low-frequency reference clock signal.

3. The channel mismatch calibration circuit based on a low-frequency reference clock according to claim 1, characterized in that, The channel mismatch calibration circuit further includes: a threshold voltage adjustment circuit connected to the plurality of sub-ADC circuits and receiving the edge detection value, and increasing the threshold voltage when the edge detection values are -1 and 1 in sequence; and decreasing the threshold voltage when the edge detection values are 0 and 0 in sequence.

4. The channel mismatch calibration circuit based on a low-frequency reference clock according to claim 1, characterized in that, it further includes: A reference clock adjustment circuit for receiving the edge signals of the plurality of sub-ADC circuits and calculating the absolute values of the respective edge signals within a plurality of clock cycles of the low-frequency reference clock signal in sequence, selecting the largest one of the respective absolute values, and adjusting the phase of the low-frequency reference clock signal until the absolute value reaches the minimum value.

5. The channel mismatch calibration circuit based on a low-frequency reference clock according to claim 1, characterized in that, The number of the multiplexed sampling clocks is 2 n , and the ratio between the frequency of the low-frequency reference clock signal and the sampling rate is set to any odd number.

6. The channel mismatch calibration circuit based on a low-frequency reference clock according to claim 1, characterized in that, it further includes: Multiple gain calibration circuits, each connected to a sub-ADC circuit and adjusting the gain according to the digital signal output by the sub-ADC circuit.

7. The channel mismatch calibration circuit based on a low-frequency reference clock according to claim 1, wherein, it further includes: Multiple offset calibration circuits, each connected to a sub-ADC circuit and adjusting the offset according to the digital signal output by the sub-ADC circuit.

8. A channel mismatch calibration method based on a low-frequency reference clock, wherein, it includes: Generating a plurality of sampling clocks and a low-frequency reference clock signal, the frequency of the low-frequency reference clock signal being lower than that of the plurality of sampling clocks; Sampling the low-frequency reference clock signal at a sampling rate, wherein the ratio between the frequency of the low-frequency reference clock signal and the sampling rate is set to be a prime number relative to the number of the plurality of sampling clocks; Performing analog-to-digital conversion on the sampled low-frequency reference clock signal, and comparing the voltage value of the sampled signal with a threshold voltage to determine whether the digital signal corresponding to the voltage value is an edge signal, and simultaneously outputting an edge detection value, wherein when the voltage value of the sampled low-frequency reference clock signal is within the threshold range Vth~-Vth, the edge detection value is 0, when the voltage value of the low-frequency reference clock signal is greater than the threshold Vth, the edge detection value is 1, and when the voltage value of the low-frequency reference clock signal is less than the threshold -Vth, the edge detection value is -1; Calibrating the phases of the plurality of sampling clocks according to the edge signal and the edge detection value respectively.

9. The channel mismatch calibration method based on a low-frequency reference clock according to claim 8, wherein, Adding pseudo-random noise to the low-frequency reference clock signal.

10. The channel mismatch calibration method based on a low-frequency reference clock according to claim 8, wherein, When the edge detection values are -1 and 1 in sequence, increasing the threshold voltage; when the edge detection values are 0 and 0 in sequence, decreasing the threshold voltage.

11. The channel mismatch calibration method based on a low-frequency reference clock according to claim 8, wherein, Calculating the absolute values of the edge signals of multiple sub-ADC circuits within a plurality of clock cycles of the low-frequency reference clock signal, and selecting the largest one among the absolute values; adjusting the phase of the low-frequency reference clock signal until the absolute value reaches the minimum value.

12. A channel mismatch calibration circuit based on a low-frequency reference clock, wherein, it includes: A clock generation circuit for generating a low-frequency reference clock signal and a plurality of sampling clocks, the frequency of the low-frequency reference clock signal being lower than that of the plurality of sampling clocks; Multiple sub-DAC circuits for receiving the plurality of sampling clocks and performing digital-to-analog conversion to output an analog signal; An ADC circuit is used to receive the analog signal and the low-frequency reference clock signal, sample the analog signal at a sampling rate and perform analog-to-digital conversion, and compare the voltage value of the sampled signal with a threshold voltage to determine whether the digital signal corresponding to the voltage value is an edge signal, and at the same time output an edge detection value. When the voltage value of the sampled low-frequency reference clock signal is within the threshold range Vth to -Vth, the edge detection value is 0. When the voltage value of the low-frequency reference clock signal is greater than the threshold Vth, the edge detection value is 1. When the voltage value of the low-frequency reference clock signal is less than the threshold -Vth, the edge detection value is -1. Wherein, the ratio between the frequency of the low-frequency reference clock signal and the sampling rate is set to be a prime number relative to the number of the multi-channel sampling clocks; A plurality of skew calibration circuits are used to calibrate the phases of the multi-channel sampling clocks according to the edge signal and the edge detection value respectively.

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