Analog front-end circuit that can be used in a sensor system

Abstract

During the sampling phase, the analog front-end circuit connects the input of the first sampling capacitor to the analog input signal and the input of the second sampling capacitor to the reference signal, and connects the first holding capacitor and the second holding capacitor to ground. During the partial tracking phase, the input of the first sampling capacitor is connected to the reference voltage, and the input of the second sampling capacitor is connected to the analog input signal. The first holding capacitor is connected to the first output of the gain amplifier, and the second holding capacitor is connected to the second output of the gain amplifier. The output of the first sampling capacitor is coupled to the first input of the amplifier, and the output of the second sampling capacitor is coupled to the second input of the amplifier.

Description

Technical Field

[0001] The present disclosure generally relates to integrated circuits, and more particularly, to analog front-end circuits. Background Art

[0002] Analog front-end circuits are typically used in integrated circuits (ICs) to receive analog signals and convert the analog signals into digital inputs for use within the IC. Analog front-end circuits typically include amplifiers and analog-to-digital converters (ADCs). These analog front-end circuits can be used, for example, in biomedical applications or audio applications, where the analog front-end circuits can convert low-frequency and low-amplitude signals into high-resolution digital signals. These types of analog front-end circuits are also typically used in portable battery-powered devices. Thus, such analog front-end circuits need to reduce cost (e.g., area) and power consumption while still maintaining the accuracy of the analog front-end. Summary of the Invention

[0003] The following are various embodiments of the present invention.

[0004] In one embodiment, a sensor system includes: an amplifier having a first input, a second input, a first output, and a second output; a first sampling capacitor coupled between a first set of switches and the first input of the amplifier, the first set of switches operable to couple the first sampling capacitor to an output of a sensor during a sampling phase and to a reference voltage during a partial tracking phase; a second sampling capacitor coupled between a second set of switches and the second input of the amplifier, the second set of switches operable to couple the second sampling capacitor to the reference voltage during the sampling phase and to the output of the sensor during the partial tracking phase; and an analog to digital converter (ADC) circuit having a low-pass transfer function, the ADC circuit having an input coupled to the output of the amplifier. In one aspect, the ADC converter circuit is a Σ-Δ converter circuit. In another aspect, during the partial tracking phase, the ADC converter circuit samples the output of the amplifier at a frequency higher than the sampling frequencies of the first sampling capacitor and the second sampling capacitor. In another aspect of the above embodiment, the first sampling capacitor is coupled to a first output of the sensor during the sampling phase, and the first sampling capacitor is coupled to one of a power supply voltage and a second output of the sensor during the partial tracking phase. In another aspect, the second sampling capacitor is coupled to the one of the power supply voltage and the second output of the sensor during the sampling phase, and the second sampling capacitor is coupled to the first output of the sensor during the partial tracking phase. In yet another aspect, the sensor system further includes a third sampling capacitor having a first end coupled to the first output of the amplifier and a second end coupled to the first input of the amplifier during the sampling phase and to a second power supply voltage during the partial tracking phase. In yet another aspect, the sensor system further includes a fourth sampling capacitor having a first end coupled to the second output of the amplifier and a second end coupled to the second output of the amplifier during the sampling phase and to the second power supply voltage during the partial tracking phase. In yet another aspect, the third sampling capacitor and the fourth sampling capacitor are coupled to the second power supply voltage during the partial tracking phase to implement a correlated double sampling function.In yet another aspect, the first sampling capacitor, the second sampling capacitor, the third sampling capacitor, and the fourth sampling capacitor are coupled to the output of the amplifier using non-overlapping clock signals during one of the transitions from the sampling phase to the partial tracking phase and from the partial tracking phase to the sampling phase.

[0005] In another embodiment, a sensing device includes: a signal processing unit; an analog-to-digital converter having a sampling frequency higher than the sampling frequency of a first sampling capacitor, the analog-to-digital converter including a low-pass filter transfer function; an analog front-end circuit including: during a sampling phase, a first terminal of a first sampling capacitor is connected to an analog input signal, a first terminal of a second sampling capacitor is connected to a reference signal, and a first holding capacitor and a second holding capacitor are connected to ground; and during a partial tracking phase, the first terminal of the first sampling capacitor is connected to the reference voltage, the first terminal of the second sampling capacitor is connected to the analog input signal, the first holding capacitor is connected to a first output of an amplifier, and the second holding capacitor is connected to a second output of the amplifier, and a second terminal of the first sampling capacitor is coupled to a first input of the amplifier, and a second terminal of the second sampling capacitor is coupled to a second input of the amplifier.

[0006] In yet another embodiment, a method of operating a analog front-end circuit includes: during a sampling phase: connecting a first end of a first sampling capacitor to an analog input signal and connecting a first end of a second sampling capacitor to a first reference voltage, and connecting a first holding capacitor and a second holding capacitor to one of a first power supply voltage and a second reference voltage; and during a partial tracking phase: connecting the first end of the first sampling capacitor to the first reference voltage and connecting the first end of the second sampling capacitor to the analog input signal; connecting a first end of the first holding capacitor to a first output of an amplifier, and connecting a first end of the second holding capacitor to a second output of the amplifier; and coupling an analog-to-digital converter to the first output and the second output of the amplifier during the partial tracking phase, and decoupling the analog-to-digital converter from the first output and the second output of the amplifier during the sampling phase, wherein a second end of the first sampling capacitor is coupled to a first input of the amplifier, and a second end of the second sampling capacitor is coupled to a second input of the amplifier. In one aspect, the first sampling capacitor is coupled to a first output of a sensor during the sampling phase, and the first sampling capacitor is coupled to one of a second power supply voltage and a second output of the sensor during the partial tracking phase. In another aspect, the second sampling capacitor is coupled to one of the second power supply voltage or the second output of the sensor during the sampling phase, and the second sampling capacitor is coupled to the first output of the sensor during the partial tracking phase. In yet another aspect of yet another embodiment, the method further includes: low-pass filtering the first output and the second output of the amplifier in a low-pass filter circuit; and converting an output from the low-pass filter circuit from an analog signal to a digital signal using an analog-to-digital converter. In another aspect, the method further includes converting the first output and the second output of the amplifier from an analog signal to a digital signal using a Σ-Δ analog-to-digital converter (ADC) circuit. In yet another aspect of yet another embodiment, the method further includes: during the sampling phase: coupling a third capacitor between the first input and the first output of the amplifier; and coupling a fourth capacitor between the second input and the second output of the amplifier. In another aspect, the method further includes coupling the third capacitor and the fourth capacitor to a second power supply voltage during the partial tracking phase to perform correlated double sampling.In another aspect, the amplifier is coupled to the analog input signal during the partial tracking phase, and the output of the amplifier tracks the analog input signal with a gain that depends on the ratio of one of the first sampling capacitor and the first holding capacitor and the second sampling capacitor and the second holding capacitor. In another aspect, the method further includes using one of a low-pass filter circuit and a Σ-Δ analog-to-digital converter to remove distortion in the first output and the second output of the gain amplifier. In another aspect, during the partial tracking phase, the ADC circuit samples the first output and the second output of the amplifier at a frequency higher than the sampling frequencies of the first sampling capacitor and the second sampling capacitor. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The present invention is illustrated by way of example and is not limited by the accompanying drawings, in which like reference numerals indicate like elements. The elements in the drawings are shown for simplicity and clarity and are not necessarily drawn to scale.

[0008] Figure 1 A system according to an embodiment of the present invention is shown in block diagram form, the system including a sensor coupled to an integrated circuit (IC) having an analog front-end circuit.

[0009] Figure 2 A more detailed view of an analog-to-digital converter (ADC) circuit system according to an embodiment of the present invention is shown in block diagram form Figure 1 of.

[0010] Figure 3 A more detailed view of an analog-to-digital converter (ADC) circuit system according to an embodiment of the present invention is shown in block diagram form Figure 1 of.

[0011] Figure 4 A more detailed view of a switched capacitor programmable gain amplifier (SC PGA) according to an embodiment of the present invention is shown in partial schematic and partial block diagram form Figure 1 of.

[0012] Figure 5 Various signals of a system according to an embodiment of the present invention are shown in timing diagram form Figure 1 of.

[0013] Figure 6Shown Figure 1 Example frequency domain inputs and outputs of the system shown.

[0014] Figure 7 Shown in block diagram form is a more detailed view of the Figure 3 ADC circuit system according to one embodiment of the present invention. Detailed Description

[0015] In one aspect, the analog front end circuit of an IC includes a programmable gain amplifier (PGA) and an analog-to-digital converter (ADC) circuit system, where the PGA samples at a rate lower than that of the ADC. This allows both the power and size of the operational amplifier of the PGA to be reduced. Additionally, the PGA uses a sampling and partial tracking phase (as opposed to a sample and hold phase or a sample and track phase), which allows the size of the sampling capacitor and the power of the PGA to be reduced for a given PGA noise level. However, sampling and partial tracking introduces distortion at higher frequencies. Thus, by using the ADC circuit system with filtering (by using a sigma-delta (SD) ADC or a low pass filter with any type of ADC), the introduced distortion and noise are filtered out by the ADC circuit system. In this way, a smaller PGA can be implemented while still maintaining accurate ADC conversion.

[0016] Figure 1A sensor system 100 including a sensor 102 coupled to an IC 120 is shown in block diagram form. In the illustrated embodiment, the sensor 102 is shown as being external to the IC 120, but alternatively, it may be within the IC 120. In one embodiment, the sensor 102 is a medical sensor, such as a heart rate monitor. The sensor 102 is coupled to receive the sensed input and is coupled to provide the sensor output to the SC PGA 104 (also referred to herein as PGA104) via terminals 112 and 114. In many applications, the sensor output provides a low frequency and low amplitude signal. A first input of the PGA 104 (referred to as INP) is coupled to terminal 112, and a second input of the PGA 104 (referred to as INM) is coupled to terminal 114. INP and INM correspond to differential inputs to the PGA 104. The PGA 104 provides an amplified analog differential output, namely signals OUTP and OUTM, which are provided as differential inputs to the ADC circuitry 106. The ADC circuitry 106 converts the analog differential input into a digital data stream output Dout, which is provided to the processor 108 for further processing. The PGA104 and the ADC circuitry 106 form the analog front end circuitry 110 of the IC 120. In the illustrated embodiment, the processor 108 can be any type of data processor.

[0017] In one embodiment, the sensor 102 provides an analog differential signal as INP and INM to the PGA 104 via terminals 112 and 114, respectively. Alternatively, the sensor 102 may be coupled to provide a single-ended analog signal to one of terminals 112 or 114, while the other of terminals 112 or 114 may receive a reference voltage or may be coupled to a voltage supply terminal, such as VDD or VSS. Thus, INP and INM may be collectively referred to as differential signals, or one of INP or INM may be referred to as the input analog signal and the other of INP or INM may be referred to as the reference signal.

[0018] Figure 4 A PGA 104 according to an embodiment of the present invention is shown in partial block diagram and partial schematic form. The PGA 104 includes an amplifier 400, sampling capacitors C sample 410 and C sample 412, partial tracking capacitors C pt 420 and C pt426, capacitors 418 and 436, PGA control circuit 450, and switches 402, 404, 406, 408, 414, 416, 422, 424, 432, 434, 428, and 430. The PGA control circuit 450 receives a PGA clock signal and provides control signals φpt and φs based on the PGA clock signal. The assertion of φs corresponds to the sampling phase of the PGA 104, and the assertion of φpt corresponds to the partial tracking phase of the PGA 104. Each switch in the PGA 104 receives either φs or φpt at the control input of the switch, where the assertion of the received control signal closes the corresponding switch such that the switch conducts between its two data terminals, and the negation of the control signal opens the corresponding switch such that the switch does not conduct between its two data terminals.

[0019] INP is provided to the first input of the PGA 104 and INM is provided to the second input of the PGA 104. The first input is coupled to the first data terminal of switch 402 and the first data terminal of switch 406. The second input is coupled to the first data terminal of switch 404 and the first data terminal of switch 408. The second data terminal of switch 402 and the second data terminal of switch 404 are coupled to the first end of C sample 410. The second data terminal of switch 406 and the second data terminal of switch 408 are coupled to the first end of C sample 412. Switches 402 and 408 receive φs at their control inputs, and switches 404 and 406 receive φpt at their control inputs. The second end of C sample 410 is coupled to circuit node 438 at the first input (e.g., non-inverting input) of the amplifier 400, and the second end of C sample 412 is coupled to circuit node 440 at the second input (e.g., inverting input) of the amplifier 400. Circuit node 442 at the first output (e.g., inverting output) of the amplifier 400 provides the first output OUTP of the PGA 104. Circuit node 444 at the second output (e.g., non-inverting output) of the amplifier 400 provides the second output OUTM of the PGA 104. The amplifier 400 can be implemented as an operational amplifier (Opamp).

[0020] Still referring to Figure 4 , circuit node 438 is coupled to the first data terminal of switch 416 and the first end of C pt 420. Circuit node 440 is coupled to the first data terminal of switch 428 and the first end of C ptThe first terminal of 426. The second data terminal of switch 416 is coupled to the first data terminal of switch 414 and the first terminal of capacitor 418. The second data terminal of switch 414 is coupled to ground. The control input of switch 414 is coupled to receive φpt, and the control input of switch 416 is coupled to receive φs. The second data terminal of switch 428 is coupled to the first data terminal of switch 430 and the first terminal of capacitor 436. The second data terminal of switch 430 is coupled to ground. The control input of switch 430 is coupled to receive φpt, and the control input of switch 428 is coupled to receive φs. The second terminal of capacitor 418 is coupled to circuit node 442. C pt The second terminal of 420 is coupled to the first data terminal of switch 422 and the first data terminal of switch 424. The second data terminal of switch 422 is coupled to ground, and the second terminal of switch 424 is coupled to circuit node 442. The second terminal of capacitor 436 is coupled to circuit node 444. C pt The second terminal of 426 is coupled to the first data terminal of switch 434 and the first data terminal of switch 432. The second data terminal of switch 434 is coupled to ground, and the second terminal of switch 432 is coupled to circuit node 444. It should be noted that the second data terminal of each of switches 414 and 430 is coupled to ground. In one embodiment, this ground can be an analog ground, i.e., a stable voltage between the positive and negative power supplies, and this stable voltage serves as the reference voltage for the analog circuit. Alternatively, this ground can be the positive power supply, the negative power supply, or a common ground.

[0021] In operation, PGA 104 is a switched capacitor PGA (SC PGA), which amplifies the input signal, and the gain of the SC PGA can be programmed digitally. In the illustrated embodiment, PGA 104 utilizes correlated double sampling (CDS) and a double sampling scheme, and the double sampling scheme operates in the following two phases: a sampling phase (corresponding to φs) and a partial tracking phase (corresponding to φpt). It should be noted that φs is asserted during the sampling phase and φpt is asserted during the partial tracking phase, so only one of φs and φpt is asserted at any given time. In one embodiment, φs and φpt can be referred to as clock signals. Currently known SC PGAs typically operate using a sample and hold scheme or a sample and track (with a one-to-one gain) scheme. However, by implementing double sampling and a partial tracking scheme (with partial gain), the size of the sampling capacitor can be smaller compared to using one of the currently known SC PGAs, and the power requirements of the amplifier can be reduced.

[0022] Reference Figure 4, for the sampling phase of the PGA 104, assert φs such that switches 402, 408, 416, 422, 428, and 434 are closed and the remaining switches are open. In this way, the sampling capacitors are connected to the input (e.g., C sample 410 is connected to INP via the closed switch 402, and C sample 412 is connected to INM via the closed switch 408), and the partial tracking capacitors are connected to ground (e.g., C pt 420 is connected between C sample 410 and ground via the closed switch 422, and C pt 426 is connected between C sample 412 and ground via the closed switch 434). (It should be noted that this ground can be an analog ground, or alternatively, this ground can be a positive power supply, a negative power supply, or a common ground.) As part of the CDS scheme, capacitors 420 and 426 store the offset, low-frequency noise, and finite gain error of the amplifier during this phase. The sampling capacitors C sample 410 and C sample 412 are charged differentially with the input signal Vin, where Vin is the voltage at INP (Vinp) minus the voltage at INM (Vinm). During the sampling phase, capacitor 418 is connected between the first input (circuit node 438) of amplifier 400 and the first output (circuit node 442) of amplifier 400 via the closed switch 416. Similarly, capacitor 436 is connected between the second input (circuit node 440) of amplifier 400 and the second output (circuit node 444) of amplifier 400 via the closed switch 428. As part of the CDS scheme, capacitors 418 and 436 hold the output voltage.

[0023] For the partial tracking phase of the PGA 104, assert φpt such that switches 404, 406, 414, 424, 432, and 430 are now closed and the remaining switches are open. In this way, the sampling capacitors are connected in reverse to the inputs INP and INM, and the partial tracking capacitors (also referred to as hold capacitors) are connected to the outputs OUTP and OUTM. That is, instead of disconnecting C sample 410 and C sample 412 from the inputs INP and INM as would be done in a PGA using a sample-and-hold scheme, C sample 410 is actually connected to INM via the closed switch 404, and C sample 412 is actually connected to INP via the closed switch 406. C pt 420 is connected between circuit node 438 and OUTP (at circuit node 442) via the closed switch 424, and Cpt 426 is connected between circuit node 440 and OUTM (at circuit node 444) via a closed switch 432. In this configuration, capacitors 420 and 426 subtract the amplifier error stored during the sampling phase. Capacitors 418 and 436 are now connected to ground via closed switches 414 and 430. (As described above, this ground can be an analog ground, but can also be a positive supply voltage, a negative supply voltage, or a common ground.) In this configuration, capacitors 418 and 436 sample the output voltage as part of the CDS scheme.

[0024] During the partial tracking phase, the sampling capacitors C sample 410 and C sample 412 are charged differentially using the reverse input signal Vin. The charge change is transferred to the partial tracking capacitors (e.g., from C sample 410 to C pt 420 and from C sample 412 to C pt 426) and an output voltage Vout is generated, where Vout is the voltage at OUTP (Voutp) minus the voltage at OUTM (Voutm). Thus, Vout can be expressed as Vout = (Vin - (-Vin)*C sample / C pt = Vin*(2C sample / C pt ). If the input signal changes by ΔVin during the partial tracking phase, then the charge on the sampling capacitors will change by ΔVin*C sample , and this portion of the charge will also be transferred to the partial tracking capacitors, resulting in an output voltage Vout = Vin*(2C sample / C pt + ΔVin*C sample / C pt ). This is partial tracking because, for example, when the gain of PGA 104 is one, C sample is equal to a fraction of C pt , e.g., C sample = 0.5*C pt , such that the output Vout tracks by a fraction of ΔVin, e.g., by 0.5*ΔVin. Thus, it should be noted that the partial tracking phase provides gain to the amplified signal based on the ratio of the sampling capacitors to the partial tracking capacitors. In the illustrated embodiment, each of the sampling capacitors and the partial tracking capacitors is implemented as a variable capacitor that can be set to a desired capacitance to achieve the desired gain.

[0025] In the case of the illustrated SC PGA 104 utilizing partial tracking, it should be noted that the sampling capacitor is smaller compared to currently known sample-and-hold and sample-and-track PGAs because dual sampling requires less circuit area for a given noise level, thus saving cost. Additionally, there is no additional circuitry in the tracking phase to adjust the gain to match the overall PGA gain. However, compared to currently known PGAs, the output of PGA 104 may include more distortion by using partial tracking and a smaller sampling capacitor. However, in the case where the ADC sampling rate is appropriately selected relative to the PGA sampling rate, this distortion can be placed at a higher out-of-band frequency, which, as will be described below, can be filtered out by the ADC circuitry 106.

[0026] Figure 2 and 3 An embodiment of the ADC circuitry 106 is illustrated in block diagram form. In one embodiment, as described above, when amplifying the received differential signal, the PGA 104 introduces high-frequency distortion in the signal path. This distortion is thus removed by the ADC circuitry 106. In an example Figure 2 such as the one illustrated, the ADC circuitry 106 can be implemented together with the ADC 204 and the low-pass filter 202. In this example, the low-pass filter 202 removes the high-frequency distortion so that it can be converted into a digital signal by the ADC 204 with higher accuracy, and the ADC 204 can be implemented with any type of ADC.

[0027] In an example Figure 3 such as the one illustrated, the ADC circuitry 106 can be implemented by a ∑-Δ (sigma delta, SD) ADC 302. As is known in the art, an SD ADC typically includes a ∑-Δ modulator in series with a digital filter. The modulator converts the analog input signal into a pulse-wave representation. The modulator produces a noise-shaped output. In one embodiment, a second-order modulator is used to further shape any noise into higher frequencies. In the modulator, the number of integrators and thus the feedback loops indicates the order of the SD ADC. In an SD ADC, the digital filter is already essential for removing out-of-band noise that has been shaped from lower frequencies to higher frequencies. This digital filter also removes the high-frequency distortion caused by partial tracking. In the illustrated embodiment, the SD ADC 302 has a high input sampling rate greater than the sampling rate of the PGA 104. A decimator can also be used as part of the digital filter to downsample the output of the low-pass filter in order to slow down the output data rate. It should be noted that for this embodiment, any known SD ADC circuitry can be used to implement the ADC circuitry 106.

[0028] Figure 7A more detailed view of an embodiment of SD ADC 302 (implemented as a second-order SD ADC) is shown in block diagram form, including coefficients 304 to 307, summing nodes 310, 312, and 309, integrators 314 and 316, quantizer 318, and digital filter 320. Coefficients 304 to 307 scale the corresponding input or output signals. SD ADC 302 receives OUTP - OUTM as an input and provides Dout as an output. Summing node 310 receives b1*(OUTP - OUTM) at the summing input and a1*(the output of quantizer 318) at the subtraction input. Summing node 310 provides its result to integrator 314 (also referred to as integrator 1). The output of integrator 314 is scaled by c1 and provided to the first summing input of summing node 312. Summing node 312 receives b2*(OUTP - OUTM) at the second summing input and a2*(the output of quantizer 318) at the subtraction input. Summing node 312 provides its result to integrator 316 (also referred to as integrator 2). The output of integrator 316 is scaled by c2 and provided to quantizer 318. The output of quantizer 318 is fed back to coefficients 304 and 305 and is also provided to digital filter 320, and digital filter 320 provides Dout. Coefficients 304 to 307, summing nodes 310 and 312, integrators 314 and 316, and quantizer 318 implement a second-order modulator that provides a noise-shaped output to digital filter 320 (due to two integrator / feedback loops). As discussed above with respect to Figure 3 As discussed, digital filter 320 includes a low-pass filter for removing out-of-band noise that has been shaped to higher frequencies by the modulator, and digital filter 320 may also include a decimator.

[0029] Figure 5 A timing diagram of various signals of system 100 according to an embodiment of the present invention is shown. The sampling and partial tracking phases of PGA 104 are generated based on, for example, the PGA clock received by PGA control circuit 450. The sampling phase during which φs is asserted occurs during one phase of the PGA clock cycle (in the example shown, the high phase of ts corresponding to between time t0 and time t2), and the partial tracking phase during which φpt is asserted occurs during another phase of the PGA clock cycle (in the example shown, the low phase of tpt corresponding to between time t2 and time t5). In one embodiment, ts < tpt. As Figure 5As shown, the PGA sampling phase corresponds to φs being asserted, and the partial tracking phase corresponds to φpt being asserted. In one example, each of the PGA partial tracking phase and the PGA sampling phase is delayed with respect to the edge of the PGA clock. For example, φs is asserted at time t1, which occurs after a delay from time t0, and φpt is asserted at time t3, which occurs after a delay time (td) from time t2.

[0030] During the PGA sampling phase of the PGA 104, the ADC circuit system 106 is deactivated, that is, sampling and conversion are not performed. For example, the sampling phase of the ADC circuit system 106 occurs only during the partial tracking phase of the PGA 104 (during the time period tpt, specifically, during the time between t3 and t5). In the illustrated embodiment, 3 ADC sampling phases are shown for the ADC circuit system 106; however, there may be more sampling phases, such as 8 sampling phases. Thus, it can be seen that the sampling rate of the ADC circuit system 106 is greater than the sampling rate of the PGA 104 (e.g., 3 to 1 in the illustrated example).

[0031] Figure 5 Also shown is the PGA input signal corresponding to Vin = Vinp - Vinm, and the PGA output signal corresponding to Vout = Voutp - Voutm (using partial tracking as described above). During the PGA sampling phase, Vout remains stable until the end of the sampling phase and enters the partial tracking phase, where Vout tracks Vin using the partial gain.

[0032] Figure 6 Various frequency domain graphs of the system 100 according to an embodiment of the present invention are shown. The first graph corresponds to Vin of the PGA 104 and includes a fundamental frequency component 600 at the frequency Fin, where Fin is the input frequency. The second graph corresponds to Vout of the PGA 104 and includes a frequency component 602 at the frequency Fin, and also includes frequency components 604 occurring at higher frequencies in the frequency domain. These frequency components correspond to the distortion introduced by the PGA 104, and the frequencies of the frequency components are based on the number of ADC samples per PGA sample (e.g., F(N) = k*(Fs / N)+ / -Fin, where N is the number of ADC samples per PGA sample, k = positive integer, and Fs is the effective ADC sampling frequency N / (ts + tpt)). However, the ADC circuit system 106 (due to, for example Figure 2 a low-pass filter in or due to, for example Figure 3filtered out by the digital filter of the SD ADC in [reference], i.e., these distortion components are removed, thereby generating a third curve graph corresponding to the ADC output. This curve graph includes the fundamental frequency component 606 at the frequency Fin, but does not have distortion components. In this way, the high-frequency distortion introduced by the partial tracking scheme of the PGA 104 is resolved by the ADC circuit system.

[0033] Therefore, it can be understood how cost (circuit area) and power can be saved in the analog front-end circuit by using sampling and partial tracking PGA, while maintaining accuracy by using an SD ADC or other ADC and a low-pass filter. In this way, the analog front-end circuit system can convert low-frequency and low-amplitude signals into high-resolution digital signals while saving cost and power.

[0034] In this article, the terms "assert" or "set" and "negate" (or "de-assert" or "clear") are used respectively when referring to making a signal, status bit, or similar device present its logical true or logical false state. If the logical true state is logic level one, then the logical false state is logic level zero. And if the logical true state is logic level zero, then the logical false state is logic level one.

[0035] Each signal described in this article can be designed as positive logic or negative logic, where negative logic can be represented by a bar over the signal name or an asterisk (*) after the name. In the case of a negative logic signal, the signal is active low, where the logical true state corresponds to logic level zero. In the case of a positive logic signal, the signal is active high, where the logical true state corresponds to logic level one. It should be noted that any signal described in this article can be designed as a negative logic signal or a positive logic signal. Therefore, in an alternative embodiment, those signals described as positive logic signals can be implemented as negative logic signals, and those signals described as negative logic signals can be implemented as positive logic signals.

[0036] Since the devices implementing the present invention are mostly composed of electronic components and circuits known to those skilled in the art, in order to understand and comprehend the basic concepts of the present invention and in order not to confuse or deviate from the teachings of the present invention, the circuit details will not be elaborated to a greater extent than considered necessary as shown above.

[0037] In addition, the terms "front", "rear", "top", "bottom", "upper", "lower", etc. in the specification and claims, if any, are used for descriptive purposes and do not necessarily describe a permanent relative position. It should be understood that such terms can be interchanged where appropriate, such that the embodiments of the present invention described herein, for example, can operate in other orientations than those shown or otherwise described herein.

[0038] Where appropriate, some of the above embodiments may be implemented using a variety of different information processing systems. For example, although Figure 1 and its discussion describe an exemplary information processing architecture, presenting such an exemplary architecture is only for providing a useful reference when discussing various aspects of the present invention. Of course, for the purpose of discussion, the description of the architecture has been simplified, and the architecture is only one of many different types of suitable architectures that can be used according to the present invention. Those skilled in the art will recognize that the boundaries between the logic blocks are only illustrative, and alternative embodiments may combine the logic blocks or circuit elements, or impose alternative decompositions of functionality on various logic blocks or circuit elements.

[0039] In addition, those skilled in the art will recognize that the boundaries between the functionality of the above operations are only illustrative. The functionality of multiple operations can be combined into a single operation, and / or the functionality of a single operation can be distributed among additional operations. In addition, alternative embodiments may include multiple instances of a particular operation, and the order of operations may be changed in various other embodiments.

[0040] Although the present invention has been described herein with reference to specific embodiments, various modifications and changes can be made without departing from the scope of the present invention as set forth in the appended claims. For example, the analog front-end circuit 110 can be used in a variety of applications and is not limited to only receiving and processing signals from sensors. Therefore, the specification and drawings should be regarded in an illustrative sense rather than a restrictive sense, and all such modifications are intended to be included within the scope of the present invention. It is not intended that any of the benefits, advantages, or solutions to problems described herein with respect to a particular embodiment be construed as a critical, required, or essential feature or element of any or all of the claims.

[0041] As used herein, the term "coupled" is not intended to be limited to direct coupling or mechanical coupling.

[0042] Furthermore, as used herein, the term "a" is defined as one or more than one. And, the use of introductory phrases such as "at least one" and "one or more" in the claims should not be construed to imply that another claim element led by the indefinite article "a" will limit any particular claim containing such led claim element to an invention that includes only one such element, even when the same claim includes the introductory phrases "one or more" or "at least one" and the indefinite article such as "a". The same applies to the use of the definite article.

[0043] Unless otherwise stated, terms such as "first" and "second" are used arbitrarily to distinguish the elements so described. Therefore, these terms are not necessarily intended to indicate a temporal or other precedence of these elements.

Claims

1. A sensor system, characterized in that, Comprising: An amplifier having a first input, a second input, a first output, and a second output; A first sampling capacitor coupled between a first set of switches and the first input of the amplifier, the first set of switches operable to couple the first sampling capacitor to the output of a sensor during a sampling phase and to a reference voltage during a partial tracking phase; A second sampling capacitor coupled between a second set of switches and the second input of the amplifier, the second set of switches operable to couple the second sampling capacitor to the reference voltage during the sampling phase and to the output of the sensor during the partial tracking phase; A first holding capacitor coupled between a third set of switches and the first sampling capacitor, the third set of switches operable to connect the first holding capacitor to ground during sampling and to the first output of the amplifier during the partial tracking phase; A second holding capacitor coupled between a fourth set of switches and the second sampling capacitor, the fourth set of switches operable to connect the second holding capacitor to ground during sampling and to the second output of the amplifier during the partial tracking phase; And An analog-to-digital converter ADC circuit having a low-pass transfer function, the analog-to-digital converter circuit having an input coupled to the output of the amplifier.

2. The sensor system according to claim 1, wherein The analog-to-digital converter ADC circuit is a Σ-Δ converter circuit.

3. The sensor system according to claim 1, characterized in that, The first sampling capacitor is coupled to a first output of a sensor during the sampling phase and to one of a supply voltage and a second output of the sensor during the partial tracking phase.

4. A sensing device, characterized in that, Comprising: A signal processing unit; An analog-to-digital converter having a sampling frequency higher than the sampling frequency of the first sampling capacitor, the analog-to-digital converter including a low-pass filter transfer function; An analog front-end circuit, the analog front-end circuit comprising: During a sampling phase, a first end of the first sampling capacitor is connected to an analog input signal, a first end of the second sampling capacitor is connected to a reference signal, and the first holding capacitor and the second holding capacitor are connected to ground; During a partial tracking phase, The first end of the first sampling capacitor is connected to the reference signal, The first end of the second sampling capacitor is connected to the analog input signal, The first holding capacitor is connected to a first output of the amplifier, and the second holding capacitor is connected to a second output of the amplifier, and A second end of the first sampling capacitor is coupled to the first input of the amplifier, and a second end of the second sampling capacitor is coupled to the second input of the amplifier.

5. A method for operating an analog front-end circuit, characterized in that, The method includes: During a sampling phase: Connecting a first end of a first sampling capacitor to an analog input signal and connecting a first end of a second sampling capacitor to a first reference voltage; Connect the first holding capacitor and the second holding capacitor to one of a first power supply voltage and a second reference voltage; and During a partial tracking phase: Connect the first end of the first sampling capacitor to the first reference voltage and connect the first end of the second sampling capacitor to the analog input signal; Connect the first end of the first holding capacitor to the first output of the amplifier, and connect the first end of the second holding capacitor to the second output of the amplifier; and During the partial tracking phase, couple an analog-to-digital converter to the first output and the second output of the amplifier, and during the sampling phase, decouple the analog-to-digital converter from the first output and the second output of the amplifier; Wherein the second end of the first sampling capacitor is coupled to the first input of the amplifier, and the second end of the second sampling capacitor is coupled to the second input of the amplifier.

6. The method according to claim 5, wherein The first sampling capacitor is coupled to the first output of the sensor during the sampling phase, and the first sampling capacitor is coupled to one of a second power supply voltage and a second output of the sensor during the partial tracking phase.

7. The method according to claim 5, characterized in that Further comprising: Perform low-pass filtering on the first output and the second output of the amplifier in a low-pass filter circuit; And Use an analog-to-digital converter to convert the output from the low-pass filter circuit from an analog signal to a digital signal.

8. The method according to claim 5, characterized in that, Further comprising: Use a Σ-Δ analog-to-digital converter ADC circuit to convert the first output and the second output of the amplifier from an analog signal to a digital signal.

9. The method according to claim 5, wherein Further comprising: During the sampling phase: Couple a third capacitor between the first input and the first output of the amplifier; And Couple a fourth capacitor between the second input and the second output of the amplifier.

10. The method according to claim 8, wherein During the partial tracking phase, the Σ-Δ analog-to-digital converter ADC circuit samples the first output and the second output of the amplifier at a frequency higher than the sampling frequency of the first sampling capacitor and the second sampling capacitor.

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