Multi-level Σ-Δ ADC with dithering

Abstract

The present disclosure relates to multi-stage Σ-Δ analog-to-digital converters with dithering. Techniques for implementing subtractive dithering in a multi-stage ADC are provided. Subtractive dithering involves adding a first dithering signal at a first node and a second dithering signal at a second node (which may be the same as the first node), where the first and second dithering signals combine and their sum is approximately zero. By using subtractive dithering in a multi-stage ADC, the headroom requirements of the loop filter in the ADC's main loop and the range requirements of the feedback DAC in the main loop can be relaxed.

Description

Technical Field

[0001] This document relates generally, but not by way of limitation, to integrated circuits and, more particularly, to analog-to-digital converter circuits and systems. Background Art

[0002] In many electronic applications, analog input signals are converted to digital output signals (e.g., for further digital signal processing). For example, in precision measurement systems, electronic devices may be equipped with one or more sensors for measurement, and these sensors may generate analog signals. The analog signals may then be provided as input to an analog-to-digital converter (ADC) to generate digital output signals for further processing. In another example, in a mobile device receiver, an antenna may generate analog signals based on electromagnetic waves that carry information / signals in the air. The analog signals generated by the antenna may then be provided as input to an ADC to generate digital output signals for further processing.

[0003] The difference between the ADC's input voltage and output voltage can correspond to the ADC's quantization error. In some ADCs, the quantization error can be further processed by the ADC circuitry to "shape" the quantization error, which manifests as quantization noise in the frequency domain. For example, noise shaping techniques can push the quantization noise out of the signal band of interest and toward higher frequencies.

[0004] A Σ-Δ operator is a feedback system that can generate high-resolution digital signals. Σ-Δ operators have been implemented in various electronic circuits, including but not limited to analog-to-digital converters (ADCs), digital-to-analog converters (DACs), frequency synthesizers, and other electronic circuits.

[0005] ADCs based on Σ-Δ modulation are widely used in digital audio and high-precision instrumentation systems. Typically, a Σ-Δ ADC uses a Σ-Δ modulator (e.g., using a low-resolution ADC such as a 1-bit ADC, a flash ADC, or a flash quantizer) to encode the analog signal. A digital filter is then applied to the Σ-Δ modulator output, if applicable, to produce a higher-resolution digital output. A loop filter can be provided to provide error feedback to the Σ-Δ modulator. A characteristic of the Σ-Δ modulator is its noise shaping capability. Therefore, Σ-Δ ADCs are typically capable of achieving high-resolution analog-to-digital conversion. Summary of the Invention

[0006] This disclosure describes various techniques for implementing subtractive dithering in a multi-stage ADC. Subtractive dithering involves adding a first dithering signal at a first node and a second dithering signal at a second node (which can be the same as the first node), where the first and second dithering signals combine and sum to approximately zero. By using subtractive dithering in a multi-stage ADC, the headroom requirements of the loop filter in the ADC's main loop and the range requirements of the feedback DAC in the main loop can be relaxed.

[0007] In some aspects, the present disclosure relates to a multi-stage Σ-Δ analog-to-digital converter (ADC) configured to receive an analog input signal at an input and generate a digital output signal, the multi-stage Σ-Δ ADC comprising: an input summing node configured to receive and combine the analog input signal and an output of at least one digital-to-analog converter (DAC) circuit; a first-stage ADC configured to receive the analog input signal and a first dithered signal and generate a first output to the at least one digital-to-analog converter (DAC) circuit; and a second-stage Σ-Δ modulator configured to receive the output of the input summing node and a second dithered signal and generate a second output to the at least one digital-to-analog converter (DAC) circuit, wherein the first dithered signal and the second dithered signal are offset from each other at a node coupled to an input of the at least one DAC circuit.

[0008] In some aspects, the present disclosure relates to a method of using a multi-stage Σ-Δ analog-to-digital converter (ADC), the converter being configured to receive an analog input signal at an input and generate a digital output signal, the method comprising: receiving and combining the analog input signal and an output of at least one digital-to-analog converter (DAC) circuit at an input summing node; receiving the analog input signal and a first dithered signal via a first-stage ADC and generating a first output to the at least one digital-to-analog converter (DAC) circuit; and receiving the output of the input summing node and a second dithered signal via a second-stage Σ-Δ modulator and generating a second output to the at least one digital-to-analog converter (DAC) circuit, wherein the first dithered signal and the second dithered signal are offset from each other at a node coupled to an input of the at least one DAC circuit.

[0009] In some aspects, the present disclosure relates to a multi-stage Σ-Δ analog-to-digital converter (ADC) configured to receive an analog input signal at an input and generate a digital output signal, the multi-stage Σ-Δ ADC comprising: means for receiving and combining the analog input signal and an output of at least one digital-to-analog converter (DAC) circuit; means for receiving the analog input signal and a first dithered signal via a first-stage ADC and generating a first output to the at least one digital-to-analog converter (DAC) circuit; and means for receiving the output of the input summing node and a second dithered signal via a second-stage Σ-Δ modulator and generating a second output to the at least one digital-to-analog converter (DAC) circuit, wherein the first dithered signal and the second dithered signal are offset from each other at a node coupled to an input of the at least one DAC circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] In the accompanying drawings, which are not necessarily drawn to scale, like numbers may describe similar parts in different views. The same numbers with different letter suffixes may represent different instances of similar components. The accompanying drawings generally illustrate various embodiments discussed in this document by way of example and not limitation.

[0011] Figure 1 is a schematic block diagram of an example of a data acquisition system that can implement a sigma-delta modulator.

[0012] Figure 2 is a block diagram of an example of a first-order single-bit Σ-Δ ADC.

[0013] Figure 3 is a block diagram of an example of a multi-stage sigma-delta ADC circuit in which the various techniques of this disclosure may be implemented.

[0014] Figure 4 According to various technologies disclosed in this disclosure Figure 3 Simplified block diagram of an example of a multi-stage sigma-delta ADC circuit where dither is added to both the first and second stages.

[0015] Figure 5 is a simplified block diagram of an example of a multi-stage sigma-delta ADC circuit with shaped dither added to the second stage to substantially cancel the dither added to the first stage, in accordance with various techniques of this disclosure.

[0016] Figure 6 is a block diagram of an example of a multi-stage Σ-Δ ADC circuit in which the various techniques of this disclosure may be implemented.

[0017] Figure 7 is a block diagram depicting an example of a dither signal generation circuit.

[0018] Figure 8is a block diagram of an example of a multi-stage Σ-Δ ADC circuit in a feed-forward configuration in which the various techniques of this disclosure may be implemented.

[0019] Figure 9 is a block diagram of an example of a multi-stage Σ-Δ ADC circuit in a feedback configuration in which the various techniques of this disclosure may be implemented. DETAILED DESCRIPTION

[0020] Σ-Δ modulators operating at low input values ​​or DC input can exhibit tonal behavior. For example, the output spectrum may exhibit a loud tonal pattern, which degrades the signal-to-noise ratio (SNR). Dither, an intentionally applied form of noise, can be introduced to break up this tonal pattern. For example, dithering can cause the tonal pattern to spread out and become white noise, resulting in the absence of tones at specific frequencies.

[0021] However, the introduction of dither may require a loop filter with additional headroom. For example, if dither is introduced before the quantizer, it increases the quantization noise, thereby increasing the noise margin and requiring additional headroom. In addition, if a loop is used, the feedback digital-to-analog converter (DAC) often requires additional levels due to the added dither, which increases the complexity of the DAC.

[0022] This disclosure relates to various techniques for implementing subtractive dithering in a multi-stage ADC. Subtractive dithering involves adding a first dithering signal at a first node and a second dithering signal at a second node (which may be the same as the first node), where the first and second dithering signals combine and their sum is approximately zero. By using subtractive dithering in a multi-stage ADC, the headroom requirements of the loop filter in the ADC's main loop and the range requirements of the feedback DAC in the main loop can be relaxed.

[0023] Figure 1 is a schematic block diagram of an example of a data acquisition system 10 that can implement a sigma-delta modulator. The data acquisition system 10 can be an electronic device (including electronic circuitry and / or one or more components) configured to convert a signal (e.g., an analog signal) into a usable form. In various embodiments, the data acquisition system 10 can convert a physical condition into a digital form that can be stored and / or analyzed. For clarity, Figure 1 Additional features may be added to the data acquisition system 10 , and some of the described features may be replaced or eliminated in other embodiments of the data acquisition system 10 .

[0024] exist Figure 1In the embodiment of the present invention, the data acquisition system 10 may include an input signal 15 representing a physical condition, such as temperature, pressure, velocity, flow rate, position, other physical conditions, or a combination thereof. The sensor circuit block 20 may receive the input signal 15 and convert the physical condition (represented by the input signal 15) into an electrical signal, such as an analog signal 25. The analog signal 25 may be a voltage or current representing the physical condition (represented by the input signal 15).

[0025] Signal conditioning circuit block 30 can receive and condition analog signal 25 within an acceptable range of an analog-to-digital converter (ADC), providing a conditioned analog signal 35. Conditioned analog signal 35 can be provided to ADC circuit block 40, such that signal conditioning circuit block 30 can act as an interface between sensor circuit block 20 and ADC circuit block 40, conditioning analog signal 25 (and thereby providing conditioned analog signal 35) before digitizing the analog signal at ADC circuit block 40. Signal conditioning circuit block 30 can amplify, attenuate, filter, and / or perform other conditioning functions on analog signal 25. ADC circuit block 40 can receive conditioned analog signal 35 and convert it to digital form, providing digital signal 45. Digital signal 45 can represent a physical quantity received by the sensor via input signal 15. Digital signal processor (DSP) circuit block 50 can receive and process digital signal 45.

[0026] The ADC circuit block 40 may include a Σ-Δ ADC that generates a digital signal using a feedback technique, wherein the Σ-Δ ADC may oversample its input signal (here, the conditioned analog signal 35) and perform noise shaping to achieve a high-resolution digital signal (here, the digital signal 45). The Σ-Δ ADC may include a Σ-Δ modulator 60 and a digital filter / decimator 70. The Σ-Δ modulator 60 may use oversampling (e.g., a sampling rate higher than the Nyquist rate) and filtering to generate a digital signal that represents the input signal received by the Σ-Δ ADC (e.g., the conditioned analog signal 35).

[0027] In various embodiments, the Σ-Δ ADC feedback loop forces the modulator output to be a good representation of the input signal within the bandwidth of interest. A digital filter / decimator 70 can attenuate noise and / or slow down the data rate of the digital signal (e.g., to the Nyquist sampling rate), providing a digital signal 45. The digital filter / decimator 70 can include a digital filter, a decimator, or both. The digital filter can attenuate the digital signal received from the Σ-Δ modulator 60, and the decimator can reduce the sampling rate of the digital signal received from the Σ-Δ modulator 60.

[0028] Figure 2 is a block diagram of an example of a first order single sigma delta ADC. The sigma delta modulator 100 may be Figure 1The Σ-Δ modulator 100 can be used with a sampling clock frequency Kf S The input signal (Vin) is converted into a continuous serial stream of 1s and 0s at a determined rate. A one-bit digital-to-analog converter (DAC) 102 can be driven by the serial output data stream to generate a feedback signal. The output of the digital-to-analog converter (DAC) 102 can be subtracted from the input signal using a summing element 104. The summing element 104 can be implemented as the summing node of an operational amplifier (opamp), such as the opamp of integrator 106.

[0029] The integrator 106 may integrate the output of the summing element 104, and the output of the integrator 106 may be applied to a clock latched comparator 108. For a zero input signal, the comparator output may include approximately equal numbers of ones and zeros. For a positive input voltage, the comparator output may include more ones than zeros. For a negative input voltage, the comparator output may include more zeros than ones. The average of the comparator output over a plurality of cycles represents the input voltage. The comparator output may be applied to a digital filter and decimator 110 that averages every M cycles, where M is a positive integer greater than 1. The digital filter and decimator 110 may be Figure 1 An example of a digital filter / decimator 70. The decimator reduces the effective sampling rate at the output to f S .

[0030] Figure 3 is a block diagram of an example of a multi-stage sigma-delta ADC circuit 200 in which various techniques of the present disclosure may be implemented. The multi-stage sigma-delta ADC circuit 200 may be Figure 1 The multi-stage Σ-Δ ADC 200 may include a first-stage ADC 202 and a second-stage Σ-Δ modulator 204 .

[0031] The multi-stage Σ-Δ ADC 200 may receive an analog input signal U at an input terminal 201. The analog input signal U may be fed to an optional pre-filter circuit 206 and a first-stage ADC 202. Figure 2 In the Σ-Δ modulator 100 , the first stage ADC 202 may include an integrator 208 , a first ADC circuit 210 ( ADC1 , a first quantizer), and a first DAC circuit 212 ( DAC1 ).

[0032] The first-stage ADC 202 may include an input summing node 214 configured to receive and combine the analog input signal U and the output of the first DAC circuit 212. The integrator 208 may integrate the output of the input summing node 214, and the output of the integrator 208 may be applied to the first ADC circuit 210. The first-stage ADC 202 may generate a digital output V1 that is a rough approximation of the analog input signal U. The digital output V1 may be combined with the digital output V2 of the second stage via a summing node 224, converted back to the analog domain by the DAC 2, and subtracted from the pre-filtered analog input signal U at an input summing node 222 of the second-stage Σ-Δ modulator 204.

[0033] In some examples, the multi-stage Σ-Δ ADC 200 may include a pre-filter circuit 206, such as an RC circuit, an RLC circuit, or a delay line. The analog input signal U may be altered when generating the digital output V1. The pre-filter circuit 206 may optionally be included to better align the analog input signal U with the approximate digital output V1 in time / phase and thereby better cancel the analog input signal U. Due to this cancellation, the signal processed by the second-stage Σ-Δ modulator 204 may be subject to jitter and quantization noise.

[0034] The second-stage sigma-delta modulator 204 may include a loop filter 216, such as a first-order (or higher) integrator circuit, a second ADC circuit 218 (ADC2, a second quantizer), and a second DAC circuit 220 (DAC2). The second-stage sigma-delta modulator 204 may receive an analog input signal U, or a filtered version of the analog input signal U by the pre-filter circuit 206, at an input summing node 222. The input summing node 222 may be configured to receive and combine the analog input signal U (or the filtered version of the analog input signal U) with the output of the second DAC circuit 220. The loop filter 216 may integrate the output of the input summing node 222, and the output of the loop filter 216 may be applied to the second ADC circuit 218, which may generate a digital output V2. The digital output V2 may be combined with the digital output V1 from the first-stage ADC 202 at a summing node 224 coupled to the input of the second DAC circuit 220. The digital output V of the multi-stage sigma-delta ADC 200 may be taken from the input of the second DAC circuit 220.

[0035] In some embodiments, a third DAC circuit may be included, such as Figure 9 For example, instead of applying the output V1 of the first stage ADC 202 to the summing node 224, a third DAC circuit can be coupled in parallel with the second DAC circuit 220 (DAC2) to receive and convert the output V1.

[0036] Figure 4According to various technologies disclosed in this disclosure Figure 3 A simplified block diagram of an example of a multi-stage Σ-Δ ADC circuit where dither is added to both the first and second stages. For simplicity, Figure 3 All optional pre-filter circuits 206, first DAC circuits 212, and second DAC circuits 220 have been replaced by corresponding short circuits. Figure 3 The quantizers of the multi-stage Σ-Δ ADC circuit 200, namely the first ADC circuit 210 (ADC1, the first quantizer) of the first stage and the second ADC circuit 218 (ADC2, the second quantizer) of the second stage, have been modeled by summing nodes 302 and 304, respectively, which add corresponding quantization noise and dither. Specifically, the quantization noise Q1 and the dither signal D1 are added to the first stage ADC 306 by the summing node 302, and the quantization noise Q2 and the dither signal D2 are added to the second stage Σ-Δ modulator 308 by the summing node 304. For example, in Figure 3 The dither signal D1 is added before the first ADC circuit 210, and the Figure 3 The dither signal D2 is added before the second ADC circuit 218 .

[0037] In some examples, the first stage ADC 306 may be a flash ADC. In other examples, the first stage ADC 306 may be a Σ-Δ ADC, such as a continuous time Σ-Δ ADC.

[0038] If the first-stage ADC 306 is a first-order continuous-time Σ-Δ ADC, the digital output V1 of the first-stage ADC is given by the following equation 1:

[0039] V1=STF1*U+(1-z -1 )*(Q1+D1), formula 1

[0040] Where Q1 and D1 are the quantization noise and dither signal of the first stage, respectively, STF1 is the signal transfer function (STF) of the first stage ADC 306, (1-z -1 ) is the Z-domain transfer function, and the symbol * represents the multiplication operation.

[0041] Similarly, the digital output V2 of the primary loop (second stage Σ-Δ modulator 308) is given by the following equation 2:

[0042] V2=STF2*(U-V1)+NTF2*(Q2+D2), Formula 2

[0043] Where Q2 and D2 are the quantization noise and dither signal of the second stage, respectively. STF2 and NTF2 are the signal transfer function and noise transfer function (NTF) of the second stage, respectively.

[0044] The recombined digital output V is given by Equation 3 below:

[0045] V=V1+V2=(STF2+STF1*(1-STF2))*U+(1-STF2)*(1-z -1 )*(Q1+D1)+NTF2*(Q2+D2) Formula 3

[0046] For in-band signals, STF2 = 1, so the in-band recombined digital output V can be written as the following formula 4:

[0047] V = V1 + V2 = U + NTF2 * (Q2 + D2) Formula 4

[0048] like Figure 3 As shown, the digital output V is also the input to the second DAC circuit 220 ( DAC2 ) of the second stage Σ-Δ modulator 204 .

[0049] From Equation 3, we can see that Figure 3 The second DAC circuit 220 (DAC2) should be designed to have sufficient range to accommodate the signal U plus dither, such as the shaping dither and quantization noise from the two stages. However, according to various techniques of the present disclosure, a second dither signal (D2) can be added to the second-stage sigma-delta modulator 308 to cancel the first dither signal (D1) of the first-stage ADC 306 to substantially cancel the two dither signals. For example, in Figure 3 The two added dither signals may be combined and summed to approximately zero (referred to as subtractive dithering in this disclosure) before the second DAC circuit 220 of the second stage sigma-delta modulator 204. The term offset does not mean a DC offset.

[0050] Figure 5 is a simplified block diagram of an example of a multi-stage sigma-delta ADC circuit with shaped dither added to the second stage to substantially cancel the dither added to the first stage, in accordance with various techniques of this disclosure. Figure 5 The multi-stage Σ-Δ ADC circuit 400 is similar to Figure 4 , where the shaped jitter signal (D1*(1-z -1 )) replaced in level 2 Figure 4 In some examples, Figure 5 The multi-stage Σ-Δ ADC circuit 400 may be a continuous-time Σ-Δ ADC circuit.

[0051] like Figure 5 As seen in FIG. 1 , the first dithered signal D1 may be added to the first stage ADC 306, for example, by coupling to Figure 3 The summing node of the input of the first ADC circuit 210 and the second dithering signal (-D1*(1-z -1)) can be added to the second stage Σ-Δ modulator 308, for example, coupled to Figure 3 The summing node of the input of the second ADC circuit 218, where the first and second dithering signals can be combined and coupled to the second DAC circuit (e.g. Figure 3 The sum at the node of the input of the second DAC circuit 220 of the second stage sigma-delta modulator 204 is approximately zero (referred to as subtraction dither in this disclosure).

[0052] exist Figure 5 In the embodiment of the present invention, the second dither signal can be shaped by the NTF of the first stage so that the first and second dither signals are substantially canceled at the summing node 224. Figure 5 In the example, the second dither signal is shaped by the first-order NTF because the first stage is a first-order ADC. If the first stage is a second-order ADC, then the second dither signal will be shaped by the second-order NTF, and so on.

[0053] By using subtractive dithering in a multi-stage ADC, the margin requirements of the loop filter 216 in the main loop of the ADC 400, e.g. Figure 6 The second-stage Σ-Δ modulator 504 and the range requirements of the feedback DAC in the main loop, such as Figure 6 of the second DAC circuit 220, both can be relaxed.

[0054] Figure 6 is a block diagram of an example of a multi-stage sigma-delta ADC circuit 500 that may implement various techniques of the present disclosure. The multi-stage sigma-delta ADC circuit 500 may be Figure 1 An example of a sigma-delta modulator 60 is shown.

[0055] The multi-stage Σ-Δ ADC circuit 500 may include an input summing node 222 configured to receive and combine an analog input signal U and the output of one or more DAC circuits, such as the second DAC circuit 220 (DAC2). The multi-stage Σ-Δ ADC circuit 500 may also include a first-stage ADC 502 configured to receive the analog input signal U and the first dithered signal D1 and generate a first digital output V1 that is applied to the input of the second DAC circuit 220 (DAC2). In some examples, the first-stage ADC 502 may include an integrator 208, a first ADC circuit 210 (ADC1, a first quantizer), and a first DAC circuit 212 (DAC1). Although in Figure 6 5. A first-order Σ-Δ ADC is shown in FIG. 5 , but the first-stage ADC 502 can be a higher-order Σ-Δ ADC or a Nyquist-rate ADC, such as a flash ADC or a successive approximation register (SAR) ADC. In this disclosure, a Nyquist-rate ADC includes any ADC used at the Nyquist rate (non-oversampling converter).

[0056] The multi-stage Σ-Δ ADC circuit 500 may further include a second-stage Σ-Δ modulator 504 configured to receive the output of the input summing node 222 and a second dither signal, such as a noise-shaped dither signal, such as the dither signal (-D1*(1-z -1 )) and generates a second digital output V2 which is applied to the input of the second DAC circuit 220 (DAC2). The first dithering signal D1 and the second dithering signal (-D1*(1-z -1 )) can be offset from each other at a summing node 224 coupled to the input of a second DAC circuit 220 (DAC2), where the first and second dithered signals can be combined and summed to approximately zero (referred to as subtractive dithering in this disclosure) prior to the second DAC circuit 220 of the second stage Σ-Δ modulator 504.

[0057] like Figure 6 As shown in the example of FIG1 , a first dither signal D1 may be added before the first ADC circuit 210 (ADC1), and a second dither signal, such as a noise-shaped dither signal, may be added before the second ADC circuit 218 (ADC2). For example, the first dither signal D1 may be a digital code applied to a first dither DAC coupled to a summing node at the input of the first ADC circuit 210 (ADC1), and the second dither signal may be a digital code applied to a second dither DAC coupled to a summing node at the input of the second ADC circuit 218 (ADC2).

[0058] In some examples, the multi-stage Σ-Δ ADC circuit 500 can optionally include a pre-filter circuit 206 coupled between an input 201 configured to receive the analog input signal U and an input summing node 222 .

[0059] In some examples, the first-stage ADC may include a flash ADC or a SAR ADC. In some examples, the first-stage ADC may include a Σ-Δ ADC. In some examples, the first-stage ADC may include a first-order Σ-Δ modulator, and the second-stage Σ-Δ modulator may include a second-order Σ-Δ modulator. In other examples, the first-stage ADC may include a second-order (or higher) Σ-Δ modulator, and the second-stage Σ-Δ modulator may include a third-order (or higher) Σ-Δ modulator.

[0060] Figure 7 is a block diagram depicting an example of a dither signal generation circuit. Figure 7 The jitter signal generating circuit 600 may include a control circuit 602 configured to control a jitter generator 604, such as a pseudo-random number generator, to generate a jitter signal. The jitter generator 604 may generate a first jitter signal, such as a first jitter signal D1.

[0061] For example, the first jitter signal D1 may be a digital code that can be applied to Figure 6 The first-stage ADC 502 is coupled to a dither DAC. Furthermore, the first dither signal D1 (code) may be applied to a digital inverter 606, which changes the sign of the dither signal D1. The inverted first dither signal D1 may be applied to a digital filter 608, such as an FIR filter, which may perform noise shaping on the inverted first dither signal D1. The digital filter 608 may shape the inverted first dither signal D1 using the NTF of the first stage and apply the noise-shaped, inverted first dither signal D1 (the second dither signal) to the second stage.

[0062] The above dither subtraction technique is applicable to both feed-forward and feedback configurations. An example of a feed-forward configuration using dither subtraction is Figure 8 An example feedback configuration using subtractive dithering is shown in Figure 9 shown.

[0063] Figure 8 is a block diagram of an example of a multi-stage sigma-delta ADC circuit 700 in a feed-forward configuration in which various techniques of the present disclosure may be implemented. The multi-stage sigma-delta ADC circuit 700 may be Figure 1 An example of a sigma-delta modulator 60 is shown.

[0064] The multi-stage Σ-Δ ADC circuit 700 may include an input summing node 222 configured to receive and combine an analog input signal U and the output of one or more DAC circuits, such as the second DAC circuit 220 (DAC2). The multi-stage Σ-Δ ADC circuit 700 may include a first-stage ADC 702 configured to receive the analog input signal U and a first dithered signal D1 and generate a first digital output V1 that is applied to the input of the second DAC circuit 220 (DAC2).

[0065] Figure 8 The first stage ADC 702 is similar to Figure 6 The first stage ADC 502, but with a first dither DAC 704, as described above with respect to Figure 7 As described above, it is clearly shown that the first jitter signal D1 can be a signal such as Figure 7 A dither generator, such as the dither generator 604 , generates and applies a digital code to the first dither DAC 704 .

[0066] Similar to Figure 2In the sigma-delta modulator 100, the first stage ADC 702 may include an integrator 208, a first ADC circuit 210 (ADC1, a first quantizer), and a first DAC circuit 212 (DAC1). The first dither DAC 704 may be coupled to the input of the first ADC circuit 210 (ADC1) via a summing node 706. Figure 8 7. The first stage ADC 702 is shown as a first order Σ-Δ ADC, but the first stage ADC 702 may be a higher order Σ-Δ ADC or a flash ADC.

[0067] The multi-stage Σ-Δ ADC circuit 700 may further include a second-stage Σ-Δ modulator 708 configured to receive the output of the input summing node 222 and the second dithered signal. The second-stage Σ-Δ modulator 708 may include a first integrator 710, a second integrator 712, a second ADC circuit 218 (ADC2, a second quantizer), and a second DAC circuit 220 (DAC2).

[0068] In the feedforward configuration shown, the output of the first integrator 710 of the second-stage sigma-delta modulator 708 is fed forward to a summing node 714 using a first feedforward coefficient a1, and the output of the second integrator 712 of the second-stage sigma-delta modulator 708 is fed forward to the summing node 714 using a second feedforward coefficient a2. The output y of the summing node 714 is fed to a summing node 716.

[0069] As mentioned above about Figure 7 As described, the dither code D2=-D1 can be applied to a filter 718, such as an FIR filter, and then applied to the second dither DAC 720. The filter 718 can shape the dither signal according to the NTF of the first stage ADC 702, such as (1-z in the first order example shown. -1 ).

[0070] The second dither DAC 720 can be coupled to the input of the second ADC circuit 218 (ADC2) via the summing node 716, combined with the output y from the summing node 714, and the second ADC circuit 218 (ADC2) can generate a second digital output V2 applied to the input of the second DAC circuit 220 (DAC2). The first dither signal and the second dither signal can be offset from each other at the summing node 224 coupled to the input of the second DAC circuit 220 (DAC2), where the first and second dither signals can be combined and summed to approximately zero (referred to as subtractive dithering in this disclosure) before the second DAC circuit 220 of the second stage Σ-Δ modulator 708. Although in Figure 8 A second-order sigma-delta modulator is shown in FIG, but the second stage can be a first-order or third-order or higher-order sigma-delta modulator.

[0071] Figure 9is a block diagram of an example of a multi-stage Σ-Δ ADC circuit 800 in a feedback configuration in which various techniques of the present invention may be implemented. The multi-stage Σ-Δ ADC circuit 800 may be Figure 1 An example of a sigma-delta modulator 60 is shown.

[0072] The multi-stage Σ-Δ ADC circuit 800 may include an input summing node 222 configured to receive and combine an analog input signal U and the output of one or more DAC circuits, such as DAC circuit 220 (DAC2). The multi-stage Σ-Δ ADC circuit 800 may include a first-stage ADC 802 configured to receive the analog input signal U and a first dithered signal D1 and generate a first digital output V1 that is applied to the input of a DAC circuit 804 (DAC2).

[0073] Figure 9 The first stage ADC 802 is similar to Figure 8 The first stage ADC 702. The first jitter signal D1 can be generated by a jitter generator (eg Figure 7 The digital code is generated by the dither generator 604 of FIG. 1 and applied to the first dither DAC 704.

[0074] Similar to Figure 2 In the sigma-delta modulator 100, the first stage ADC 802 may include an integrator 208, a first ADC circuit 210 (first quantizer), and a first DAC circuit 212 (DAC1). The first dither DAC 704 may be coupled to the input of the first ADC circuit 210 via a summing node 706. Figure 9 8. The first stage ADC 802 is shown as a first order Σ-Δ ADC, but the first stage ADC 802 may be a higher order Σ-Δ ADC or a flash ADC.

[0075] The multi-stage sigma-delta ADC circuit 800 may further include a second-stage sigma-delta modulator 806 configured to receive the output of the input summing node 222 and the second dithered signal. The second-stage sigma-delta modulator 806 may include a first integrator 710, a second integrator 712, a second ADC circuit 218 (a second quantizer), and a third DAC circuit 220 (DAC3).

[0076] In the feedback configuration shown, the output of the first integrator 710 of the second stage sigma-delta modulator 708 is fed forward to a summing node 808 and combined with the output of the third DAC circuit 220 (DAC3). The output of the summing node 808 is fed to a second integrator 712. The output y of the second integrator 712 of the second stage sigma-delta modulator 708 is fed to a summing node 714.

[0077] As mentioned above about Figure 7As described, the dither code D2=-D1 can be applied to a filter 718, such as an FIR filter, and then applied to the second dither DAC 720. The filter 718 can shape the dither signal according to the NTF of the first stage ADC 802, such as (1-z in the first order example shown. -1 ).

[0078] The second dither DAC 720 may be coupled to the input of the second ADC circuit 218 via the summing node 714 , combined with the output y from the second integrator 712 , and the second ADC circuit 218 may generate a second digital output V2 .

[0079] The second dithered signal from the filter 718 is combined with the second digital output V2 at a summing node 812 coupled to the input of the third DAC circuit 220 (DAC3). The third DAC circuit 220 (DAC3) converts the combined signal and then feeds it to a summing node 808 at the input of the second integrator 712.

[0080] The second digital output V2 includes a second dithered signal D2. Adding dither may require additional DAC levels, which increases the complexity of the DAC. However, here, the second dithered signal D2 is subtracted from the second digital output V2 at a summing node 812 coupled to the input of the third DAC circuit 220 (DAC3). In this way, the third DAC circuit 220 (DAC3) can be driven by a dither-free signal, and no additional DAC levels are required in the third DAC circuit 220 (DAC3).

[0081] The first digital output V1 is combined with the second digital output V2 at a summing node 814 coupled to the input of the second DAC circuit 804 (DAC2). At the summing node 814, the first dithered signal and the second dithered signal can be offset from each other, where the first and second dithered signals can be combined and added to approximately zero (referred to as subtraction dithering in this disclosure). The second DAC circuit 804 (DAC2) converts the combined signal and then feeds it to the summing node 222 at the input of the first integrator 710.

[0082] Finally, the first digital output V1 is delayed by the delay element 810 and then combined with the second digital output V2 at the summing node 816 to generate a recombined digital output V.

[0083] Despite Figure 9 The second stage is shown as a second order sigma-delta modulator, but the second stage can be a first order or third order or higher order sigma-delta modulator. In addition, in some embodiments, Figure 9 The feedback configuration shown in may include direct feedback—sometimes referred to as through-loop delay compensation—that includes an through-loop delay DAC (ELDDAC).

[0084] Various annotations

[0085] Each non-limiting aspect or example described herein may stand on its own, or may be combined in various permutations or combinations with one or more of the other examples.

[0086] The above detailed description includes reference to the accompanying drawings, which form a part of the detailed description. The accompanying drawings show, by way of illustration, specific embodiments in which the present invention may be practiced. These embodiments are also referred to herein as "examples." Such examples may include elements other than those shown or described. However, the present inventors also contemplate providing examples of only those elements shown or described. In addition, the present inventors also contemplate examples using any combination or arrangement of those elements shown or described (or one or more aspects thereof), or with respect to specific examples (or one or more aspects thereof), or with respect to other examples shown or described herein (or one or more aspects thereof).

[0087] In the event of a conflicting usage between this document and any document incorporated by reference, the usage in this document controls.

[0088] In this document, the terms "a" and "an" are common in patent documents and are used to include one or more, independent of any other instances or uses of "at least one" or "one or more." In this document, unless otherwise stated, the term "or" is used to refer to a non-exclusive or, for example, "A or B" includes "A but not B," "B but not A," and "A and B." In this document, the terms "including" and "in which" are used as equivalents of the respective terms "comprising" and "wherein." In addition, in the following claims, the terms "including" and "comprising" are open-ended, i.e., systems, devices, articles, compositions, formulas, or processes that include elements in addition to the elements listed after such terms in a claim are still considered to fall within the scope of the claim. In addition, in the appended claims, the terms "first," "second," "third," etc. are used merely as labels and are not intended to impose numerical requirements on their objects.

[0089] The method examples described herein may be at least partially machine or computer implemented. Some examples may include a computer-readable medium or machine-readable medium encoded with instructions that are operable to configure an electronic device to perform the methods described in the above examples. The implementation of such methods may include code, such as microcode, assembly language code, high-level language code, etc. Such code may include computer-readable instructions for performing various methods. The code may form part of a computer program product. In addition, in one example, the code may be tangibly stored on one or more volatile, non-transitory or non-volatile tangible computer-readable media, such as during execution or at other times. Examples of these tangible computer-readable media may include, but are not limited to, hard disks, removable disks, removable optical disks (e.g., compact disks and digital video disks), magnetic tapes, memory cards or memory sticks, random access memories (RAMs), read-only memories (ROMs), etc.

[0090] The above description is intended to be illustrative and not restrictive. For example, the above examples (or one or more aspects thereof) may be used in combination with each other. Other embodiments may be used, such as by a person of ordinary skill in the art after reading the above description. The abstract is provided to comply with 37 CFR § 1.72 (b), allowing the reader to quickly determine the nature of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. In addition, in the above detailed description, various features may be combined together to simplify the disclosure. This should not be interpreted as intending that unclaimed disclosed features are essential to any claim. On the contrary, the subject matter of the present invention may lie in less than all the features of a particular disclosed embodiment. Therefore, the following claims are hereby incorporated into the detailed description as examples or embodiments, each claim independently as a separate embodiment, and it is expected that these embodiments can be combined with each other in various combinations or arrangements. The scope of the present invention should be determined with reference to the appended claims and the full scope of equivalents to which these claims are entitled.

Claims

1. A multi-stage Σ-Δ analog-to-digital converter configured to receive an analog input signal at an input terminal and generate a digital output signal, the multi-stage Σ-Δ analog-to-digital converter comprising: A first-stage analog-to-digital converter configured to receive the analog input signal and a first dithering signal and generate a first output; and a second stage sigma-delta modulator comprising at least one digital-to-analog converter circuit and an input summing node configured to receive and combine the analog input signal and an output of the at least one digital-to-analog converter circuit, wherein the second stage Σ-Δ modulator is configured to receive a second dithered signal and generate a second output based on the output of the input summing node and the second dithered signal; as well as a first summing node coupled to an input of the at least one digital-to-analog converter circuit, wherein the first summing node is configured to receive and combine the first output and the second output to generate a combined output and provide the combined output to the at least one digital-to-analog converter circuit, Wherein, in use, the first dithering signal and the second dithering signal substantially cancel each other at the first summing node. 2 . The multi-level Σ-Δ ADC of claim 1 , wherein the second dither signal is a noise-shaped dither signal. 3 . The multi-stage Σ-Δ ADC of claim 1 , wherein the second dither signal is a noise-shaped dither signal shaped by a noise transfer function of the first-stage ADC.

4. The multi-level Σ-Δ analog-to-digital converter according to claim 1 , comprising: A pre-filter circuit is coupled between the input and the input summing node. 5 . The multi-level Σ-Δ ADC of claim 1 , wherein the second-stage Σ-Δ modulator is configured in a feed-forward configuration. 6 . The multi-level Σ-Δ ADC of claim 1 , wherein the second-stage Σ-Δ modulator is configured in a feedback configuration.

7. The multi-stage Σ-Δ ADC of claim 1 , wherein the first stage ADC comprises a first-order Σ-Δ modulator, and wherein the second stage Σ-Δ modulator comprises a second-order Σ-Δ modulator.

8. The multi-stage Σ-Δ ADC of claim 7 , wherein the first-stage Σ-Δ modulator comprises a first ADC, wherein the second-stage Σ-Δ modulator comprises a second ADC, wherein the first dithering signal is applied to a second summing node coupled to an input of the first ADC, and wherein the second dithering signal is applied to a third summing node coupled to an input of the second ADC.

9. The multi-stage Σ-Δ analog-to-digital converter of claim 1, wherein: In use, the first dither signal and the second dither signal sum to approximately zero at the first summing node.

10. The multi-stage Σ-Δ ADC of claim 1, wherein the Σ-Δ ADC is a continuous-time ADC.

11. The multi-stage Σ-Δ ADC of claim 1 , wherein the first stage ADC comprises a Nyquist rate ADC. 12 . The multi-stage Σ-Δ ADC of claim 1 , wherein the first-stage ADC comprises a Σ-Δ ADC.

13. A method of using a multi-stage sigma-delta analog-to-digital converter, the converter being configured to receive an analog input signal at an input and generate a digital output signal, the method comprising: receiving the analog input signal and the first dithering signal through a first-stage analog-to-digital converter and generating a first output; receiving and combining the analog input signal and the output of at least one digital-to-analog converter circuit at an input summing node; receiving a second dithered signal via a second stage Σ-Δ modulator and generating a second output based on the output of the input summing node and the second dithered signal; as well as receiving and combining the first and second outputs at a first summing node coupled to an input of the at least one digital-to-analog converter circuit to produce a combined output and providing the combined output to the at least one digital-to-analog converter circuit, Wherein, in use, the first dithering signal and the second dithering signal substantially cancel each other at the first summing node.

14. The method according to claim 13, comprising: The second dithered signal is noise-shaped by the noise transfer function of the first-stage analog-to-digital converter.

15. The method according to claim 13, comprising: The analog input signal is prefiltered between the input terminal and the input summing node.

16. The method according to claim 13, comprising: In the second stage sigma-delta modulator, the feedforward coefficient is applied in a feedforward configuration.

17. The method according to claim 13, comprising: In the second stage sigma-delta modulator, a feedback coefficient is applied in a feedback configuration.

18. The method of claim 13, wherein the first stage analog-to-digital converter comprises a first-order sigma-delta modulator, and wherein the second stage sigma-delta modulator comprises a second-order sigma-delta modulator.

19. A multi-stage Σ-Δ analog-to-digital converter configured to receive an analog input signal at an input terminal and generate a digital output signal, the multi-stage Σ-Δ analog-to-digital converter comprising: A component for receiving the analog input signal and the first dithering signal through a first-stage analog-to-digital converter and generating a first output; means for receiving and combining the analog input signal and an output of at least one digital-to-analog converter circuit at an input summing node; means for receiving a second dithered signal via a second-stage Σ-Δ modulator and generating a second output based on the output of the input summing node and the second dithered signal; as well as means for receiving and combining the first output and the second output at a first summing node coupled to an input of the at least one digital-to-analog converter circuit to produce a combined output and providing the combined output to the at least one digital-to-analog converter circuit, Wherein, in use, the first dithering signal and the second dithering signal substantially cancel each other at the first summing node.

20. The multi-stage Σ-Δ ADC of claim 19 , comprising: means for noise shaping the second dithered signal by a noise transfer function of the first stage analog-to-digital converter.

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