Switching networks for quantum computing

Abstract

A quantum computer and a method for operating the quantum computer, enabling it to fully simulate molecular chemistry, are described. Compared to conventional quantum computing methods, the circuit depth of the quantum computer is reduced by at least an order of magnitude. Parallelized qubits, or fermion-swapping networks, are employed to localize the nonlocal terms of the second-order quantized Hamiltonian across the computer's consecutive qubits. Thus, nonlocal quantum dynamics are presented as local. By localizing nonlocal interactions, quantum computing can be significantly parallelized, and a single template circuit simulating the time evolution operator for a 4-qubit interaction can be applied to a localized grouping of four qubits. Beyond chemistry, the quantum computer and the method for operating it can be employed to localize any many-body interactions while simultaneously reducing the required circuit depth through parallelization of the localized computation.

Description

Background Art

[0001] An application of quantum computing is the evaluation (or simulation) of quantum systems. For example, it has been shown that quantum information and quantum computing methods can be employed to determine various properties of complex chemical compounds. Because the behavior of both quantum mechanical many-body systems and the ensemble of interacting qubits within a quantum register is subject to the mechanics of the quantum system, various quantum mechanical properties of materials (e.g., materials including chemical compounds) can be simulated via quantum computing. More succinctly, a system of N qubits can be employed to simulate the dynamics of a quantum mechanical many-body system, where N scales linearly with the number of interacting particles.

[0002] The circuit depth required to fully simulate a chemical system using N qubits using conventional quantum computing methods is measured as or It depends on the implementation details. Many applications of interest in quantum computing simulations, such as chemistry, involve systems with significantly large numbers of interacting particles. For example, large molecules may include tens or even hundreds of occupied orbitals. Even though the measure of circuit depth via traditional quantum computing methods is polynomial, for quantum computations requiring even modest values ​​of N qubits, circuit depth quickly becomes impractical. Summary of the invention

[0003] This Summary is provided to introduce a selection of concepts in a simplified form that are further described below in the Detailed Description. This Summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter.

[0004] Various embodiments are directed to quantum computers and methods of operating quantum computers to simulate the dynamics of multi-body systems, such as, but not limited to, systems of non-local interactions of fermions (e.g., electrons). As a non-limiting example of application, embodiments may be employed to simulate (or calculate) the time evolution of electron orbits in molecular chemistry via quantum circuits (i.e., configurations of quantum logic gates) acting on qubits of a register. More specifically, embodiments include a network of exchange gates that perform parallelized exchange operations on qubits or fermion orbits, which implements the simulation of non-local multi-body interactions via localized groupings of qubits within a quantum register. Via the exchange gate network, the computation of many multi-body terms can be parallelized within a quantum computer, resulting in a significantly reduced circuit depth of the computer. The exchange gate network implements the iterative application of a small number of circuit templates or even a single template, thereby acting on localized groupings of qubits to simulate the time evolution of non-localized interacting quantum particles (such as, but not limited to, fermions).

[0005] One embodiment includes quantum hardware, a computer, or a system configured to operate a network of quantum gates that operate on a set of qubits to perform a method. The quantum gates may include qubit swap gates. The set of qubits defines a plurality of 4-qubit combinations. For example, if the cardinality of the set is indicated by a positive integer N, then the set of qubits may define unique 4-qubit combinations. The set may be an ordered set. The method may include iteratively updating the order of the qubit set via a plurality of qubit swap operations. The qubit swap operations may be implemented by a quantum gate network. Via the iterative swap operations, each of the 4-qubit combinations is represented as a continuous 4-qubit grouping within the order of the qubit set at least once during the plurality of swap operations. That is, Each unique 4-qubit combination in the plurality of unique 4-qubit combinations is rendered as a contiguous 4-qubit grouping within the ordered set at least once by a swap operation. Each pair of qubits swapped in each swap operation in the plurality of swap operations may be separated by at most three qubits within the order of the qubit set.

[0006] In at least some of the embodiments, the qubit set may also define multiple 2-qubit combinations. For example, unique 2-qubit combinations can be defined by the set. The order of the set can be iteratively updated by additional qubit swap operations. Via the additional swap operations, each 2-qubit combination in the 2-qubit combination is represented as a consecutive 2-qubit grouping within the order of the qubit set at least once during the additional swap operations. That is, Each unique 2-qubit combination in the unique 2-qubit combinations is presented at least once as a nearest neighbor 2-qubit pairing within the ordered set by the additional swap operations. Each pair of qubits swapped in each of the additional swap operations can be a nearest neighbor pair or qubit within the order of the set of qubits. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Various aspects of the present disclosure are described in detail below with reference to the accompanying drawings, in which:

[0008] Figure 1A to Figure 1B Provide a schematic diagram of a quantum gate suitable for use in implementing this embodiment;

[0009] Figure 1C shows one embodiment of a matrix representation of one embodiment of a 2-body time evolution operator consistent with various embodiments;

[0010] FIG. 2A to FIG. 2E Five alternative embodiments for a 4-qubit quantum circuit implementing a 4-qubit time-evolving operator consistent with various embodiments are shown;

[0011] Figure 3A providing a flow chart illustrating a process for a qubit swap operation implemented by a 2-qubit pair swap network consistent with various embodiments;

[0012] Figure 3B providing a flow chart illustrating a process for a qubit swap operation implemented by a round swap network consistent with various embodiments;

[0013] Figure 3C 1 and 2 for N=4, N=5, N=10, and N=11 qubit registers or qubit wheels as implemented via one or more qubit switching networks. FIG. 3A to FIG. 3B The rotation operation of the process;

[0014] Figure 4A providing a table illustrating various properties for class types of 3-qubit interactions consistent with various embodiments presented herein;

[0015] Figure 4B providing a table illustrating vectorization of configurations for 3-qubit combinations (where 5≤N≤10) consistent with various embodiments presented herein;

[0016] Figure 4C providing a table illustrating a non-limiting example of vectorization of 3-qubit combinations of category 1 for N=14, 15, 16, 18, and 19;

[0017] Figure 4D Provides a table illustrating other non-limiting embodiments of vectorization of 3-qubit combinations of category 1 for N=14, 15, 16, 18, and 19;

[0018] Figure 5A A flow chart illustrating a process of implementing a qubit swap operation to localize all 3-qubit combinations of kind 0 within a quantum computer is provided;

[0019] Figure 5B The exchange operation of the process for an N=8 qubit quantum computer is shown;

[0020] Figure 5C A flow chart illustrating a process of localizing all 3-qubit combinations of kind 1 within a quantum computer is provided;

[0021] Figure 5D The diagram is consistent with various embodiments. Figure 5C Embodiments of 2D qubit configurations utilized in the process;

[0022] Figure 5E Provides an indication that the circuit depth of the switching network for a 3-qubit operator is approximately measured as Plotting of numerical results;

[0023] Fig. 6A providing a table illustrating various properties for class types of 4-qubit interactions consistent with various embodiments presented herein;

[0024] Figure 6B providing a table illustrating vectorization of configurations for 4-qubit combinations (where 5≤N≤10) consistent with various embodiments presented herein;

[0025] Figure 6C A flow chart is provided illustrating a process 620 of a swap operation implemented by a 2-qubit time-slot network employed in the 4-qubit embodiments discussed herein;

[0026] Fig. 7A An overview showing the types of swap operations employed in at least one embodiment to generate localized 4-qubit combinations;

[0027] Figure 7B A flow chart illustrating a process for localizing all 4-qubit combinations within a quantum computer is provided;

[0028] Figure 7C A flow chart illustrating a process for localizing all types of 0-4 qubit combinations within a quantum computer is provided;

[0029] Fig.7D For a quantum computer with N = 10 qubits Figure 7B The exchange operation of the process;

[0030] Fig. 7E Provides an indication that the circuit depth of the switching network for a 4-qubit operator is approximately measured as Plotting of numerical results;

[0031] Figure 8 is a block diagram of an exemplary quantum computing environment suitable for use in implementing embodiments of the present disclosure; and

[0032] Fig. 9 is a block diagram of an exemplary classical computing environment suitable for use in implementing embodiments of the present disclosure. DETAILED DESCRIPTION

[0033] The subject matter of various aspects of the present disclosure is described in detail herein to meet statutory requirements. However, this specification itself is not intended to limit the scope of this patent. On the contrary, the inventors have foreseen that the claimed subject matter may also be embodied in other ways in combination with other current or future technologies to include different steps or combinations of steps similar to the steps described herein. In addition, although the terms "step" and / or "frame" may be used herein to imply different units of the method adopted, these terms should not be interpreted as implying any particular order among or between the various steps disclosed herein, unless and except when the order of the individual steps is explicitly described. Each method described herein may include a quantum computing process, a classical computing process, and / or a combination thereof, which may be performed using any combination of quantum and / or classical hardware, firmware, and / or software. For example, various functions may be performed by a processor that executes instructions stored in a memory. These methods may also be embodied as computer-usable instructions stored on a computer storage medium. These methods may be provided by a standalone application, a service, or a hosted service (standalone or in combination with another hosted service) or a plug-in to another product (to name a few).

[0034] As used herein, the term "set" can be adopted to refer to an ordered (i.e., sequential) or unordered (i.e., non-sequential) collection of objects (or elements) (such as, but not limited to, qubits). A set can include N elements (e.g., qubits), where N is any non-negative integer. That is, a set can include 0, 1, 2, 3, ..., N objects and / or elements, where N is a positive integer without an upper bound. Therefore, as used herein, a set can be an empty set (i.e., an empty set) that does not include any elements. A set can include only a single element. In other embodiments, a set can include many elements that are significantly greater than one, two, or three elements. As used herein, the term "subset" is a set included in another set. A subset can be, but is not required to be, a true subset or a strict subset of other sets in which the subset is included. That is, if set B is a subset of set A, then in some embodiments, set B is a true subset or a strict subset of set A. In other embodiments, set B is a subset of set A, but is not a true subset or a strict subset of set A.

[0035] Various embodiments are directed to quantum computers and methods of operating quantum computers to simulate the dynamics of multi-body systems, such as but not limited to systems of non-local interactions of fermions (e.g., electrons). As a non-limiting example of application, embodiments may be employed to simulate (or calculate) the time evolution of electron orbitals in molecular chemistry via quantum circuits (i.e., configurations of quantum logic gates) acting on qubits of a register. More specifically, embodiments include a network of exchange gates that perform parallelized exchange operations, which implement simulations of non-local multi-body interactions. In some embodiments, the exchange operation includes a qubit exchange operation that localizes a grouping of qubits within a quantum register. In other embodiments, the exchange operation is employed to exchange fermion orbitals. That is, an exchange operation including a fermion exchange operation can exchange Hamiltonian terms to implement localized grouping of terms in the Hamiltonian.

[0036] In the second quantized form, the mapping between the Hamiltonian corresponding to the multi-body interaction of the electron orbit and the Hamiltonian corresponding to the multi-body interaction of the quantum bit of the quantum computer can be generated via regular creation and annihilation operators. Due to this mapping of the Hamiltonian, quantum circuits designed to simulate the properties of the time evolution operators of the various terms of the Hamiltonian of the orbit can be operated on the quantum bit. The second quantized Hamiltonian of the orbit includes both one-body terms and two-body terms. The Hamiltonian is non-local and the one-body term corresponds to the 2-qubit interaction between each possible pairing of the two qubits in the quantum register. Therefore, in order to evaluate all one-body terms, the circuit corresponding to the one-body time evolution operator must operate on each possible pairing of the qubit. The two-body term corresponds to the 4-qubit interaction between each possible grouping of the four qubits in the register. In order to evaluate all two-body terms, the circuit corresponding to the two-body time evolution operator must operate on each possible grouping of the four qubits.

[0037] The combination of 4-qubit configurations scales significantly faster than the combination of 2-qubit terms, and thus 4-qubit terms dominate the circuit depth for such computational schemes. Via conventional quantum computing methods, the circuit depth required to fully simulate a chemical system using N qubits scales to Many applications of interest in quantum computing simulations, such as chemistry, involve systems with significantly large numbers of interacting particles. For example, large molecules may include tens or even hundreds of occupied orbitals. Even though the measure of circuit depth via conventional quantum computing methods is polynomial, for quantum computations requiring even modest values ​​of N qubits, circuit depth quickly becomes impractical. As discussed below, the circuit depth of at least some of the various enhanced embodiments herein is measured approximately as Thereby providing at least an order of magnitude reduction in circuit depth.Thus, the various embodiments clearly provide significant improvements in the performance, functionality and efficiency of quantum computers and methods of operating quantum computers.

[0038] As noted above, embodiments include a qubit exchange network that includes a plurality of exchange gates. Although many of the embodiments discussed herein are directed to an exchange network for exchanging qubits of a quantum register, other embodiments are not so limited. The exchange operation can be easily adopted as a fermion exchange operation via a fermion exchange operation. It should be understood that any exchange operation discussed herein as a qubit exchange operation can be easily generalized to include a fermion exchange operation. That is, any of the exchange networks and / or exchange gates discussed herein can be used as a fermion exchange operator for exchanging fermion orbitals and / or a Hamiltonian term representing a fermion orbital. Similar to the qubit exchange operation, the fermion exchange operation can be a parallelized exchange operation.

[0039] Through localized grouping of qubits and / or localized grouping of fermion orbitals within a quantum register, qubit and / or fermion orbital exchange operations enable simulation of non-local many-body interactions. Through a network of exchange gates, the computation of many many-body terms can be parallelized within a quantum computer, resulting in a significantly reduced circuit depth for the computer. The network of exchange gates enables iterative application of a small number of circuit templates, or even a single template, acting on localized groupings of qubits to simulate the time evolution of non-localized interacting quantum particles (such as, but not limited to, fermions). In the traditional approach to constructing a quantum computer for such a simulation scheme, the circuit depth of the computer is dominated by the 2-body Hamiltonian corresponding to the 4-qubit interaction and is measured as like Fig. 7E As shown in , through the circuit parallelization achieved by the switching network, the circuit depth of the enhanced embodiment of this invention is measured as Thus, various embodiments provide at least an order of magnitude reduction in the scale of the depth of the circuitry required from simulation.

[0040] Many of the various embodiments discussed herein are directed to simulating Hamiltonian terms associated with non-local 1-body fermion interactions and 2-body fermion interactions. That is, when simulating the effects of Hamiltonian, higher-order terms are ignored. However, the embodiments are not so limited, and the embodiments can be generalized to include higher-order terms by including k-body interactions, where k is any integer greater than 1. For example, in order to calculate 3-body Hamiltonian terms, the switching network (and other circuits) and the various methods, processes, and computing systems discussed herein can be expanded upward to incorporate 8-qubit (or any other high-order) interactions into quantum circuits. Such embodiments may include appropriately scaled switching networks to localize all possible 8-qubit groupings. The embodiments can also be generalized to simulate similar Hamiltonians for bosons. The disclosed methods and systems can be applied to various physical implementations and / or instantiations of qubits, such as systems based on trapped particles, cold atoms, Josephson junction devices, solid-state spins, Majorana fermions, photon polarization, etc. In some applications, so-called topologically protected qubits are preferred to provide fault tolerance.

[0041] As discussed herein, a quantum computer or one or more quantum registers within the computer may include one or more sets of qubits. At least one of the one or more sets included in the computer includes N qubits, where N is any positive integer greater than 1. In various embodiments, the qubit set may be an ordered qubit set. In some embodiments of the embodiments, the order of the set may be a logical and / or virtualized order. The logical and / or virtualized order of qubits may or may not be similar to any physical order, configuration, and / or arrangement of physical instances of qubits. When discussing the order of any set of qubits, unless otherwise stated, it is the logical and / or virtualized order of qubits, which may be separated from any physical order of physical instances of qubits. Therefore, the term "logical" or "virtual" may be omitted when discussing the order of a set, because unless otherwise stated, it is implied that it is the logical and / or virtualized order of the set being discussed.

[0042] Various embodiments may iteratively update the order of a set via a qubit swap operation, such that the current order of the set may be updated many times during the methods and / or processes discussed herein. The logical and / or virtualized configuration and / or arrangement of qubits may indicate the current logical and / or virtual order of the set, and each qubit may be referenced and / or indicated via a unique integer index between 1 and N. Therefore, when discussing the logical and / or virtualized arrangement and / or configuration of qubits, the logical and / or virtualized arrangement and / or configuration may be discussed in the context of a 1D array, string, and / or lattice of qubits. For example, a logical and / or virtualized arrangement and / or configuration of N=10 qubits may be represented as a logical or virtual 1D array: (1, 2, 3, 4, 5, 6, 7, 8, 9, 10).

[0043] However, a physical instance of a set of qubits may include a physical arrangement and / or physical configuration of qubits that is not a 1D lattice or string of physical qubits. In some embodiments, a physical instance of a set of qubits may be physically arranged and / or configured in a 2D or 3D physical array, string, or lattice. In other embodiments, a physical instance of a qubit may be physically arranged and / or configured in a 1D physical array, string, or lattice. Therefore, when discussing embodiments, the logical and / or virtualized arrangement and / or configuration of qubits (which is a 1D array) may be different from the physical arrangement and / or configuration (which may include more than one dimension). Therefore, when discussing any arrangement, configuration, and / or order of qubits, unless otherwise indicated, a logical and / or virtualized arrangement and / or configuration is implied. That is, unless otherwise stated, when discussing an arrangement, configuration, and / or order of qubits, unless otherwise indicated, it is implied that a logical and / or virtualized arrangement, rather than a physical arrangement, is being referenced. Therefore, in the following discussion, the term logic and / or virtualization may be omitted as it is implied that it is the logical and / or virtualization arrangement and / or order that is being discussed.

[0044] The order of the set is indicated by the logical or virtual bit positions of the qubits within the logical or virtual 1D array. Thus, in the above example of N=10, qubit 1 (which may be indicated via the Dirac symbols: <1| or |1>, respectively) is in the 1st logical position of the array, qubit 2 is in the 2nd logical position of the array, and qubit 10 is in the 10th logical position of the array. As noted above, the logical order of the set may be updated, resulting in an update to the logical arrangement and / or logical configuration of the qubits.

[0045] As discussed throughout this document, reordering of a set can be achieved via one or more qubit swap operations. A qubit swap operation operating on a pair of qubits can "swap" the logical bit positions of the two qubits in the pair. Swapping the logical positions of the qubits can reorder or update the current order of the set. For example, a swap operation operating on qubits 1 and 2 can logically reorder the qubit set so that the logical arrangement and / or logical configuration is updated to: (2, 1, 3, 4, 5, 6, 7, 8, 9, 10), where qubit 2 is in the logical 1st bit position and qubit 1 is in the logical 2nd position of the set. In various embodiments, a swap operation can be parallelized across an ordered set of qubits such that the parallelized swap operation can simultaneously (or nearly simultaneously) reorder the previous array: (1, 2, 3, 4, 5, 6, 7, 8, 9, 10) → (2, 1, 4, 3, 6, 5, 8, 7, 10, 9), where the swap operation swaps qubits located in the following logical positions: {1, 2}, {3, 4}, {5, 6}, {7, 8}, and {9, 10}. Such a swap operation can be indicated in matrix notation as: Where the first row indicates the initial order of the collection, and the next row indicates the updated order resulting from the parallelized exchange operation.

[0046] In various embodiments, a network of qubit exchange gates (i.e., an exchange network) is employed to exchange the logical positions of two qubits that are logically located at specific logical positions within a set. Such a qubit exchange gate combines at least Figure 1B to discuss. It should be noted that exchanging the logical bit positions of qubits via a swap operation can preserve the physical arrangement and / or physical order of the physical instance of the qubit. More specifically, the qubit swap operation can swap the quantum states of the two affected qubits without affecting any physically observable configuration of the physical instance of the qubit. In the above swap operation on qubits 1 and 2, the qubit initially in the 1st logical position of the array can be in a quantum state represented as follows (i.e., a superposition of two eigenstates of the qubit): |1>=α|↑>+β|↓>. The qubit in the 2nd logical bit position of the array can be in a second quantum state represented as follows: |2>=α′|↑>+β′|↓>. (|↑>, |↓>) includes an orthogonal basis for the qubits, α, β, α′ and β′ are complex amplitudes (or coefficients), and |α| 2 +|β| 2 =|α′| 2 +|β′| 2=<↑|↑>=<↓|↓>=1 and <↑|↓>=<↓|↑>=0. After the swap operation operates on the qubits in the 1st position and the 2nd position of the array, the qubit in the 1st position is in the quantum state: |2>=α′|↑>+β′|↓>, and the qubit in the 2nd position of the array is in the quantum state: |1>=α|↑>+β|↓>. Therefore, it can be said that the order and / or position of qubits 1 and 2 have been logically swapped. Note that in order for the quantum states of the qubits to be logically swapped, any physical order or configuration of the physical instances does not need to be swapped.

[0047] Physics of Molecular Chemical Dynamics

[0048] The disclosed methods and systems generally relate to quantum computing based on a quadratic quantized Hamiltonian associated with a material of interest. The quadratic quantized Hamiltonian can be mapped to qubits, and the logical state of each qubit can be associated with the occupation of a single electron spin orbital, where 0 represents occupied and 1 represents unoccupied. A system with multiple single electron spin orbitals can be represented by N qubits within a quantum computer. Systems with any number of electrons can be represented by appropriately scaling the value of N. In the following discussion, N can be any integer greater than 1. That is, N is not associated with an upper bound. In some embodiments, N is greater than 50. In some embodiments, N is significantly greater than 100 or even 1000.

[0049] Jordan-Wigner transformations can be used to transform creation and annihilation operators so as to be represented using Pauli spin matrices. Although general time evolution operators for multi-body systems may not be easily representable as a sequence of gates, the quadratic quantized Hamiltonian can be represented as the sum of one electronic term and two electronic terms. The time evolution operator for each of these terms can be physically implemented via a sequence of quantum logic gates. The associated unary time evolution operator can be approximated using the Trotter-Suzuki relation based on the time evolution of a non-commutative operator.

[0050] Quantum computations for many-body systems can be formulated in a second quantization form, where the Hamiltonian operator is expressed as:

[0051]

[0052] and where p, q, r, and s are indices identifying molecular orbitals, each of which is occupied by either a spin-up or a spin-down particle, or both, or neither. pq and h pqrs The coefficients are the amplitudes associated with the various wave functions. The and a operators are respectively the canonical particle creation and annihilation operators of the second quantized form of quantum mechanics. Higher-order terms are ignored in this formula. However, it should be noted that these terms can be included in various embodiments by adopting an exchange network directed to k-body interactions, where k is greater than 4.

[0053] h pq and h pqrs The coefficients can be determined exactly or approximated. For example, these coefficients can be approximated by performing appropriate integration of the Hartree-Fock method. For ease of description, h pq and h pqrs The coefficients may be referred to herein as 1-body Hamiltonian coefficients and 2-body Hamiltonian coefficients, respectively. These coefficients are complex coefficients for wave functions that couple ground states p and q and p, q, r, and s, respectively, where p, q, r, and s are integer exponents. These 1-body Hamiltonian coefficients and 2-body Hamiltonian coefficients may be obtained in a variety of different ways using, for example, conventional computer programs that perform calculations such as spatial integration under the Hartree-Fock approximation. The coefficients obtained in any manner may be used in the examples below. It should be noted that the creation and annihilation operators may be represented via Hermitian matrices and unary 2×2 Pauli spin matrices, referenced herein as X, Y, and Z.

[0054] For the purpose of quantum computing, each orbital is mapped to two qubits, where The term operates on pairs of qubits indexed as p and q (representing an electron), and The terms operate on groups of four qubits indexed as p, q, r, and s (representing two electrons).

[0055] The time evolution of the orbit is calculated by the unary time evolution operator U(t)=e acting on the wave function of the orbit -iHt Therefore, given the initial wave function for the orbit (ψ(t=0)), the time evolution of the orbit can be determined as: ψ(t)=e -iHt ψ(0). Note that, in general, the terms of the Hamiltonian are not commutative. However, the evaluation of U(t) can be approximated via discrete evaluation iterated over time (e.g., Trotter steps) as:

[0056]

[0057] where M is the number of Trotter steps, Δt is the Trotter step length, and H j is the term of the Hamiltonian. Therefore, the time evolution operator can be approximated at each Trotter step as:

[0058]

[0059] in and Therefore, the time evolution of such orbits can be simulated via a quantum computing system comprising gates operating on qubits via exponentiation operations of the Hamiltonian.

[0060] Note that the Hamiltonian includes all nonlocal interactions for the electrons. Therefore, when mapped to N qubits, there are the required Individual time evolution operations and 2-body time evolution operations. For each such operation a quantum circuit is required, where each circuit consists of one or more quantum gates. Since the 1-body Hamiltonian term measures And the two-body Hamiltonian term is measured as So 2-body terms dominate the circuit depth required for quantum computation. Therefore, the following discussion of quantum circuits and gates for computing these terms will refer to 2-body terms. However, other quantum circuits and gates can be included for computation of 1-body terms.

[0061] As noted above, in general, the terms of the Hamiltonian do not commutate. So, originally, implicitly involves the summation of 4! = 24 permutation terms. However, by requiring the coefficients to be real-valued and exploiting the 8-fold rotational symmetry in the Hartree-Frock integral, there are only three unique terms: as well as The Kronecker delta function is applied to the spin state of the orbital and is obtained from the integration of the inner product of the spin wave functions of the two orbitals. Therefore, when mapped to qubits, in order for the term to be non-zero, the states of the two inner qubits must be equivalent and the states of the outer two qubits must be equivalent. When represented in matrix form, this property increases the sparsity of the matrix. For clarity in the following discussion, the delta direct function will be omitted, but will be understood to be included.

[0062] By expressing the creation and annihilation operators as Pauli spin matrices via the Jordan-Wigner transformation, it can be expressed as:

[0063]

[0064] Where X i , Y i and Z iis the Pauli spin matrix acting on the corresponding qubit. The summation on the left hand side of the above equation is over the spin state of the orbital (or the state of the corresponding qubit). As noted above, the symmetry requirements of the state of the two inner qubits and the symmetry requirements of the state of the two outer qubits are implied, which, as shown on the right hand side of the above equation, significantly reduces the number of non-zero terms. Each of the three terms on the right represents two rotation operations on each of the four qubits. Therefore, the calculation of each two-body term requires six rotation operations on the four corresponding qubits.

[0065] Each qubit is a superposition of two states, and Operating on a general entangled 4-qubit combination: therefore, is represented as a 16×16 rotation matrix where exponentiation is applied to the matrix elements. Similarly, is represented as a 4×4 rotation matrix. Figure 1C A 2-body time evolution operator (ie, ) is an embodiment of a matrix representation 140. Figure 1C The exponentiation matrix 140 is shown in FIG. 140 , due to the symmetry requirements on the spin states of the orbitals, Many, but not all, of the off-diagonal entries of the matrix are all 0. Note that the t factor in each of the matrix elements is implied, but not explicitly shown.

[0066] Various enhanced quantum circuits and quantum circuits for simulating the time evolution of the wave function of the orbits associated with the two-body term of the Hamiltonian are combined with at least Figure 1A to Figure 1B and FIG. 2A to FIG. 2E Let's discuss. FIG. 2A to FIG. 2D Each of the quantum circuits shown in FIG. 6 distributes six rotations among four interacting qubits without requiring an auxiliary qubit. These embodiments are not so constrained, and other embodiments may include circuits that do not employ auxiliary qubits. A non-limiting example of a circuit that employs auxiliary qubits is represented by Figure 2E supply.

[0067] Note that the 2-body term is maximally nonlocal, and the circuit performing the rotation must act on the qubit The traditional approach to designing quantum circuits to act on each 4-tuple of qubits is to measure the circuit depth as However, in various enhanced embodiments herein, a network of qubit switching gates is employed to render each of the nonlocal interactions as local. That is, via the various switching networks discussed herein, a quantum circuit for computing a two-body term can operate only on groups of four nearest neighbor qubits. Thus, a circuit template (e.g., Figure 1A 1D) can be iteratively employed on groups of four nearest neighbor qubits. In addition, the exchange operation and circuit template can be parallelized, as in Fig.7D As shown in the numerical results of

[0068] Examples of quantum gates and quantum circuits

[0069] Figure 1A to Figure 1B A schematic diagram of a quantum gate suitable for use in implementing an embodiment of the present disclosure is provided. More specifically, Figure 1A Various circuit schematic symbols are provided for single-qubit gates employed in various embodiments. Figure 1B Provides schematic notation for multi-qubit gates. Figure 1A X gate 102, Y gate 104, Z gate 106, H gate 108, S gate 110, Gate 112 (i.e., S conjugate transpose or S Sword gate), T gate 114, and exponential gate 116. Each of these gates is used to rotate a single qubit (e.g., rotation around a Bloch sphere). X gate 102, Y gate 104, and Z gate 106 may be collectively or individually referred to as Pauli spin gates and / or matrices. H gate 108 may be referred to as a Hadamard gate or a square root of a NOT gate. Via qubit rotation, each of gates 102 to 116 introduces a relative phase difference into the state of the qubit. The 2×2 matrix form of each of gates 102 to 116 written in the standard basis is as follows: X gate Y-Gate Z-Gate H-Gate S-Gate Door T-Gate And the index gate where A is a 2×2 matrix.

[0070] Figure 1BA multi-bit quantum gate is shown: a C-not gate 120 and four swap gates 130, 132, 134 and 136. C-not gate 120 (controlled NOT gate) and swap gate 130 act on two qubits labeled via the Dirac symbols |1> and |2>. Swap gates 132, 134 and 136 act on three, four and five bits, respectively, with the additional qubits labeled |3>, |4> and |5>, respectively. The labels on the inputs and outputs on the qubit rows explicitly indicate the exchange of the quantum states of the qubits. Multiple qubits may or may not be entangled. The 4×4 matrix form of C-not gate 120 and 2-qubit swap gate 130 written in the standard basis is as follows: C-not gate And switch gate

[0071] For brevity, the 8×8, 16×16, and 32×32 matrices of exchange gates 132, 134, and 136 are omitted. However, these matrices can be generated similarly. In the quantum bit exchange notation used throughout this document, exchange gate 130 can be employed to exchange nearest neighbor quantum bits (1, 2) → (2, 1). Using multiple instances of the nearest neighbor exchange gate 130, non-adjacent quantum bits can be exchanged. More specifically, any quantum bit pair (where the degree of locality is indicated by a positive integer k) can be exchanged by using multiple instances of the nearest neighbor exchange gate 130 (where k=1, indicating nearest neighbor quantum bit exchange). For exchange gate 132: k=2, for exchange gate 134: k=3, and for exchange gate 136: k=4. In the qubit swap notation used throughout this document, swap gate 132 swaps qubits: (1, 2, 3) → (3, 2, 1), swap gate 134 swaps qubits: (1, 2, 3, 4) → (4, 2, 3, 1), and swap gate 136 swaps qubits: (1, 2, 3, 4, 5) → (5, 2, 3, 4, 1). For each of the embodiments of fermion swap networks discussed herein: 1 ≤ k ≤ 4, however, swap gates 132 through 136 illustrate how any pair of qubits can be swapped using only multiple instances of the nearest neighbor swap gate 130. That is, k has no upper limit for the various embodiments.

[0072] Figure 1A to Figure 1B Various combinations of any of the quantum gates shown in the diagram may be employed to construct quantum circuits utilized in various embodiments. Additional quantum gates, such as but not limited to controlled Z gates, controlled Bipartite gates, Toffoli gates, Fredkin gates, measurement gates, etc. may be used in various embodiments with Figure 1A to Figure 1B door combination.

[0073] As pointed out above, in order to fully simulate quantum chemistry, the 1-body time evolution operator Must be in every Operate on the quantum bit, and the two-body time evolution operator Must be in 4 qubits Each of the groups When discussing applications to quantum bits, the 1-body time evolution operator can be called a 2-qubit operator. Similarly, the 2-body time evolution operator can be called a 4-qubit operator. Each of the 2-qubit operator and the 4-qubit operator corresponds to a 2-qubit quantum circuit and a 4-qubit quantum circuit, respectively. These quantum circuits can be obtained by combining Figure 1A to Figure 1B The various combinations of quantum gates discussed. As pointed out above, Figure 1C Show that the two-body time evolution operator An embodiment of a matrix representation 140 of , wherein a t factor in each of the matrix elements is implied.

[0074] FIG. 2A to FIG. 2E For the 4-qubit time evolution operator Five alternative embodiments of the corresponding 4-qubit quantum circuit. Although not shown, a similar 2-qubit quantum circuit can be adopted for the 2-qubit time-evolving operator Because the implementation of 4-qubit operators dominates the circuit depth of the computation, the following discussion will focus on the implementation of 4-qubit algorithms.

[0075] FIG. 2A to FIG. 2E Each of the four circuits 210, 220, 230, 240 and 250 includes four qubit inputs and four qubit outputs, respectively, where the four qubits are represented as |p>, |q>, |r>, and |s>. Each of the circuits 210, 220, 230, and 240 is converted to an integer by an exponential operator (e.g., Figure 1A The exponential operator 116 of 210 performs six rotations of the 2-body time evolution operator distributed over four qubits. However, circuits 210, 220, 230, and 240 differ in the rotation depth (i.e., the maximum number of rotations performed on a single qubit). The circuits also differ in the required two-qubit gates (e.g., Figure 1B The number of C NOT gates 120) is different. Various implementation tradeoffs can be achieved by changing the rotation depth and number of 2-qubit gates in the embodiment. More specifically, Figure 2AQuantum circuit 210 of FIG. 210 balances 6 rotations between 4 qubits (i.e., two rotations for each of the following qubits: |p>, |q>, and |s>, and no rotation for qubit |r>). The rotation depth of a circuit may be the maximum number of rotations for any qubit in the circuit. Thus, circuit 210 has a rotation depth of 2 and utilizes 18 2-qubit gates. Figure 2B The quantum circuit 220 has a rotation depth of 2 and utilizes 14 2-qubit gates. Figure 2D The quantum circuit 240 has a rotation depth of 3 and utilizes 12 2-qubit gates. Figure 2E Quantum circuit 250 of 200 employs three attached qubits. Through various manipulations, it can be shown that quantum circuit 250 can be transformed and / or reduced to any of quantum circuits 200, 210, 230, or 240.

[0076] Examples of Fermion Exchange Networks

[0077] As noted above, in order to simulate quantum chemistry and other multi-body quantum systems, multiple quantum bodies are mapped to N qubits, where N is an unrestricted integer greater than 1. The embodiments discussed herein will consider the 1-body and 2-body local and non-local terms of the second quantized Hamiltonian. Note that (1-body time evolution operator The) 1 body item can be obtained by The 2-qubit operator operating on the qubit is simulated, and (the 2-body time-evolving operator The 2-body term can be obtained by Each of the operators operating on 4 qubits is grouped to simulate. FIG. 2A to FIG. 2E Various embodiments of quantum circuits for implementing these 4-qubit operators are shown.

[0078] A "quantum register" or simply a "register" may include or represent a set of N qubits, where N is any integer greater than 1. N may be referred to as the depth of the register. As noted above, the set may include a logical order and the set may be logically configured as a logical 1D array, where each of the N qubits is associated with a logical position or location within the array. Because the logical positions of the qubits are iteratively exchanged, the order (or sequence) of the qubits is changed during the methods and processes discussed herein. For the following discussion, the qubits are logically arranged in a 1D array. However, other embodiments are not subject to such constraints, and the methods and operations discussed may be generalized to 2D and 3D arrays of qubits. An ordered string of qubits may be a reference symbol: (1, 2, 3, 4, ... N-3, N-2, N-1, N), where the integer refers to a unique index for each qubit. In addition to the index, each qubit has a logical position within the register. The current position of the qubit in the register depends on the current order of the string of qubits. As discussed throughout this article, the swap operation is iteratively performed on the qubits so that the position of the qubit in the register (and therefore the order of the qubits) is iteratively updated, but its unique index is constant. In the above 1D array, the qubit indexed as 1 is in the 1st position, and the qubit indexed as 2 is in the 2nd position. If qubits 1 and 2 are swapped, the order of updates to the register will be marked as: (2, 1, 3, 4, ... N-3, N-2, N-1, N), where the integers refer to the indices of the qubits. Qubit 2 is now in position 1, and qubit 1 is now in position 2.

[0079] A "nearest neighbor" qubit is two logically consecutive qubits in a register. Thus, the two nearest neighbor qubit pairs in both of the above register arrangements include the following two qubit pairs: (1, 2) and (N-1, N-2). For a positive integer k such that 2≤k≤N, a local grouping of k qubits includes a combination of k logically consecutive qubits (within a register). Thus, the local grouping of four qubits in the initial register arrangement includes four qubit groups of (1, 2, 3, 4) and (N-3, N-2, N-1, N).

[0080] A "qubit wheel" or simply a "wheel" may be a logically ordered grouping of qubits within a quantum register. Thus, a wheel may be a logical structure rather than a physical grouping of qubits. As described below, a wheel may include a subset of a set of qubits within a register. In some embodiments, a wheel includes a subset of N qubits within a register. The cardinality of the ordered subset of qubits included in a wheel may be indicated as n, where 1≤n≤N. n may be referred to as the depth of the wheel. For some wheels, the qubits of the wheel may be logically consecutive qubits in a 1D array representing the logical order of the register. For other wheels, the qubits of the wheel may be separated by one or more qubits within the array of registers. That is, via the ordering of registers, a wheel may not be a local grouping of qubits. Similar to registers, registers within a wheel are ordered. Thus, a qubit included in a wheel may have a position in the wheel as well as a position within a register. A qubit may have a first position as the position of the qubit within the register and a second position as the position of the qubit within the wheel. Because qubits are iteratively exchanged, the position of the qubit within the wheel (and therefore the order of the wheel) may be iteratively updated. Note that two qubits included in the same round can be nearest neighbor qubits within a round, but not nearest neighbor qubits within a register. Two qubits can be nearest neighbor qubits within a register, but not included in the same round. As discussed below, in some embodiments, the ordered set of qubits of a register is subdivided into k ordered rounds of approximately equal depth or cardinality. Each of the k rounds includes a subset of the set of qubits. Each subset of the subsets of qubits can be disjoint from all other subsets of qubits. That is, each qubit of a register can be assigned to exactly 1 of the k rounds.

[0081] The qubits within a register and / or a round can be exchanged. The exchange operation of qubits can be referred to as the rotation of a register (or round). The symbol {i, j} (where 1≤i≠j≤N) is adopted to refer to the qubit exchange operation of exchanging the qubits in the i-th logical position and the j-th logical position within the register (or round). That is, depending on the context, the symbol {i, j} can refer to the position within the round or register. In some embodiments, part of the iterative qubit exchange is parallelized. That is, multiple pairs of qubits can be exchanged in the same exchange (or rotation) operation. Parallelized qubit exchanges can be marked as: {{i, j}, {j, k}}, where the double {{}} indicates multiple (or parallelized) exchanges in the same exchange or rotation operation. In some embodiments, alternating pairs of nearest neighbors (within a register or about a round) are iteratively exchanged. For example, consider an initially sorted 10-qubit register: (1, 2, 3, 4, 5, 6, 7, 8, 9, 10). During the first swap (or rotation) operation, each of the following swap operations is performed: {{1,2}, {3,4}, {5,6}, {7,8}, {9,10}}, where the integers refer to the positions of the pairs of qubits being swapped simultaneously. After the first swap operation, the order of updates to the register is: (2, 1, 4, 3, 6, 5, 8, 7, 10, 9). The swap operation may be referred to as an odd-pair swap operation because the lower-positioned qubit in each nearest neighbor pair of swapped bits is positioned at an odd position within the register, and the higher-positioned qubit is positioned at an even position. The next swap operation may swap the alternating positions of the qubits: {{2,3}, {4,5}, {6,7}, {8,9}}, where the integers refer to the positions of the pairs of qubits being swapped simultaneously. After the second swap operation, the order of updates to the register is: (2, 4, 1, 6, 3, 8, 5, 10, 7, 9). These swap operations can be referred to as even-pair swap operations, since the lower-positioned qubit in each nearest-neighbor pair of bits swapped is located at an even position within the register, and the higher-positioned qubit is located at an odd position. The evolution of the logical ordering of the register can be notated as: Because the descending rows show the updating of the order of the qubit set. Similar operations, notations, and techniques can be employed when discussing rotation or swap operations.

[0082] Various embodiments iteratively apply a commutation operator that can be used on N qubits. Figure 1B The switching gates 130 to 136 are implemented. The switching gates may be implemented in one or more networks of switching gates (i.e., switching networks). The iterative switching operation and / or the switching network may be configured to convert the possible Each of the two qubit pairs The 2-qubit pair appears as a logical nearest neighbor pair at least once, and the possible Each of the 4-qubit combinations The 4-qubit combination appears as a grouping of four logically continuous qubits. Therefore, the Hamiltonian operator needs to operate only on groups of local qubits (e.g., pairs of nearest neighbor qubits and / or groups of four continuous qubits). That is, the 2-qubit (non-local) time evolution operator applied to simulate the non-local 1-body Hamiltonian term only needs to operate on the two nearest neighbor pairs of qubits. Similarly, the 4-qubit (non-local) time evolution operator applied to simulate the non-local 2-body Hamiltonian term only needs to operate on the four nearest neighbor pairs of qubits. That is, the 2-qubit and 4-qubit quantum circuits only need to act on local pairs of four qubits (i.e., nearest neighbor qubits) or localized groups (i.e., positionally continuous).

[0083] In addition, the commutation operator only needs to act locally on a number of qubits that are logically composed of at most three qubits (i.e., k ≤ 4, as in Figure 1B The exchange operator can also be localized to some extent. More specifically, all non-local multi-body interactions can be calculated via local 2-qubit and 4-qubit quantum circuits and nearest neighbor exchange gates (e.g., exchange gates 130 to 136). By configuring an exchange network for parallel qubit exchange and localizing the circuits and gates, the simulation of non-local interactions can be parallelized, thereby reducing circuit depth and computation time. The architecture for qubit exchange operations is discussed below for 2-body, 3-body, and 4-body interaction operators. However, other embodiments are not subject to such constraints, and high-order terms can be calculated via networks that generalize the exchange operations discussed herein. That is, various embodiments can be easily generalized for k-body interactions, where k is any integer greater than 1.

[0084] Localize a 2-qubit pair (i.e., k=2)

[0085] The following discussion of embodiments with k=2 involves qubit swapping operations. However, as noted throughout this document, various embodiments are not so constrained, and the swapping operations may include fermion swapping operations. Various qubit swapping networks will now be discussed. The swapping network may include a plurality of swapping gates (e.g., Figure 1B The switching network may include parallelized switching gates to simultaneously (or nearly simultaneously) switch multiple pairs of qubits. Each discrete switching gate may act on two of the N qubit rows in the quantum circuit.

[0086] Figure 3AA flow chart is provided illustrating a process 300 of operation of a 2-qubit pair switching network. Figure 3B A flow chart illustrating a process 320 of the operation of a round-switch network is provided. As noted, both the 2-body switching network and the round-switch network can be implemented via Figure 1B That is, each of the processes 300 and 320 can be physically implemented by implanting a corresponding configuration of the switching gates (i.e., the switching network) into a quantum computer used to simulate the time evolution operator discussed herein. The processes 300 and 320 will be combined with Figure 3C Let's discuss. Figure 3C The implementation for N=4, N=5, N=10 and N=11 qubits is shown. FIG. 3A to FIG. 3B The processes 300 and 320 of the invention are rotation operations of the qubit exchange network. The following discussion of the processes 300 and 320 is directed to qubit exchange operations. However, as noted throughout this document, various embodiments are not so constrained, and the exchange operations discussed throughout this document may include fermion exchange operations.

[0087] 2 quantum bit pair switching networks (such as those implementing Figure 3A The process 300 of ) applies a swap operation on the nearest neighbor pairs of the N qubits of the register (or the n qubits of the round) such that Each of the 2-qubit pairs is a nearest neighbor (or neighboring) pair at least once during process 300. Because each 2-qubit pair is a nearest neighbor pair at least once during implementation of process 300, the localized 2-qubit time-evolving circuit can be used in any possible The process 300 operates on each of the N pairs to simulate each of the non-local interactions via the localized qubit pairs. It can be shown that the exchange depth of the 2-qubit pair exchange network is: d2(N)=N-1. That is, by the process 300, when the register (or wheel) is rotated through N-1 configurations (including its initial configuration), each of the N qubits will have become a nearest neighbor with respect to each of the other N-1 qubits.

[0088] Round-trip network (such as implementing Figure 3BThe process 320 of ) applies a swap operation on a pair of n qubits of the round so that each of the n qubits reaches each of the n positions within the round at least once. Each of the swap operations is performed on a nearest neighbor pair within the round. However, the nearest neighbor pair within the round may not be the nearest neighbor pair within the register. That is, the round swap network can operate on non-adjacent bits within the register. However, in an embodiment where 2≤k≤4, the two nearest neighbor qubits of the round are separated by at most 3 intermediate qubits. Therefore, swap gates 130 to 136 can be used to implement the round swap network. It can be shown that the swap depth of the round swap network is: That is, via process 320, as the register (or wheel) is rotated through 2n-2+mod(n,2) configurations (including its initial configuration), each of the n qubits will have been at each of the logical n positions of the wheel at least once during implementation of process 320.

[0089] Processes 300 and 320 are similar processes in that each process 300 and 320 iteratively applies parallelized alternating odd-pair and even-pair swap operations on qubits. Processes 300 and 320 differ in their termination criteria. Process 300 may be terminated when each qubit has become the nearest neighbor qubit to every other qubit at least once: s (N) = N-1. Process 320 may be terminated when each qubit has visited each position within its round at least once: d w (n) = 2n-2 + mod (n, 2). Each of processes 300 and 320 includes an iterative loop that alternates between odd-numbered pair swap operations and even-numbered pair swap operations. As noted, the termination condition for the iterative loop of process 300 is that each qubit has become a nearest neighbor qubit with respect to each other qubit at least once during process 300, which occurs deterministically with the following swap depth: d s (N) = N-1. The termination condition for the iterative loop of process 320 is that each qubit has been to each position within its round at least once during process 320, which occurs deterministically with the following exchange depth: d w (n) = 2n-2 + mod (n, 2). Figure 3A and 3BAs shown in , processes 300 and 320 include decision blocks (i.e., blocks 306 and 312 for process 300 and blocks 326 and 332 for process 320) that check whether the termination condition is satisfied. Because the termination condition occurs via a deterministically determined exchange depth, these decision blocks are optional. That is, processes 300 and 320 do not need to check whether the termination condition has occurred, because it occurs deterministically via the above corresponding exchange depth. These decision blocks are included for illustrative purposes and do not need to be implemented.

[0090] Process 300 begins at block 302 after a start gate, where each odd pair of nearest neighbor pairs of qubits are swapped. Multiple swaps may be parallelized via a parallelized 2-qubit pair swap network. For example, on a first iteration of block 302 implemented via a parallelized 2-qubit pair swap network for N=10 registers, the registers are transformed from their initial order (1, 2, 3, 4, 5, 6, 7, 8, 9, 10) to an updated order (2, 1, 4, 3, 6, 5, 8, 7, 10, 9) where a swap operation has been applied to each of the odd pairs of nearest neighbor qubits. At optional block 304, a 2-qubit operator (such as, but not limited to, ) may be applied to each nearest neighbor pair of qubits. At decision block 306, the termination condition for the 2-qubit pair exchange network is checked. That is, at decision block 306, it may be determined whether each qubit has become a nearest neighbor (or adjacent to) to each other qubit in the register. As discussed above, this occurs after d2(N)=N-1 configurations of the register. If the termination condition is not met, then process 300 flows to block 308. Otherwise, process 300 may terminate at the end block.

[0091] At box 308, each even pair of nearest neighbor pairs of qubits can be exchanged. Similar to odd pair exchanges, multiple even pair exchanges can be parallelized. Continuing the above example, the first iteration of box 308 transforms the register from its second arrangement (2, 1, 4, 3, 6, 5, 8, 7, 10, 9) to a third arrangement (2, 4, 1, 6, 3, 8, 5, 10, 7, 9), where the exchange operation has been applied to each even pair of even pairs of nearest neighbor qubits. At optional box 310, the 2-qubit operator can be applied to each nearest neighbor pair of qubits. At decision box 312, the termination condition for the 2-qubit pair exchange network is checked. If the termination condition is not met, then process 300 returns to box 302. Otherwise, process 300 can terminate at the termination box.

[0092] Process 320 begins at block 302 after a start gate, where each odd number of pairs of qubits in a round are swapped. At optional block 324, a k-qubit operator (such as, but not limited to, ) can be applied to localized groups of k qubits. Such operators can be applied via quantum circuits such as, but not limited to, FIG. 2A to FIG. 2E At decision block 326, the termination condition for the round exchange network is checked. That is, at decision block 326, it can be determined whether each qubit has visited each position within the round. As discussed above, this occurs at the d w (n) = 2n - 2 + mod (n, 2) configurations later. If the termination condition is not met, then the process 320 flows to block 328. Otherwise, the process 320 may terminate at the end block.

[0093] At block 328, each even pair of nearest neighbor pairs of qubits may be swapped. Similar to the odd pair swaps, multiple even pair swaps may be parallelized. At optional block 330, similar to optional block 324, the k-qubit operator may be applied. At decision block 322, the termination condition for the round swap network is checked. If the termination condition is not met, then process 320 returns to block 322. Otherwise, process 320 may terminate at the termination block.

[0094] Figure 3C Rotation (or parallelized swap) operations are shown for both processes 300 and 320 as implemented via a 2-qubit pair swap network and a round swap network for N=4, N=5, N=10, and N=11 qubit registers and / or rounds, respectively. More specifically, swap or rotation operation 330 is for N=4, swap operation 340 is for N=5, swap operation 360 is for N=10, and swap operation 380 is for N=11. Within the various matrices, the rows indicate the arrangement (or logical order) of the qubits within the registers and / or rounds, where the integers indicate the qubit index. The transition from one row to the row directly below the row indicates a rotation operation implemented via a 2-qubit swap network or a round swap network, for example, blocks 302 or 308 of process 300 and / or blocks 322 or 328 of process 320. When discussing a 2-qubit swap network and / or process 300, these rows may indicate the arrangement of register qubits. When discussing a round-switching network, these rows may indicate the arrangement of the rounds of qubits.

[0095] For operation 330 of N=4, d2(4)=3 and d wd(4)=6. Horizontal bar 334 and horizontal bar 332 indicate the termination of process 300 (e.g., operation of a 2-qubit exchange network) and process 320 (e.g., operation of a round exchange network), respectively, for N=4. The additional rotation operations below horizontal bar 332 indicate how additional rotation operations can return registers and / or rounds to their original arrangement of qubits. For operation 340 for N=5, d2(5)=4 and d w d(5)=9. Horizontal bars 344 and 342 indicate the termination of process 300 and process 320, respectively, for N=5. The additional rotation operations below horizontal bar 342 indicate how additional rotation operations can return registers and / or rounds to their original arrangement of qubits. Operation 360 for N=10, d2(10)=9 and d w (10) = 19. Horizontal bar 364 indicates the termination of process 300. For operation 360, process 320 terminates in the last row. For operation 380 with N = 11, d2(11) = 10 and d w (11) = 21. Horizontal bar 384 indicates the termination of process 300. For operation 380, process 320 terminates in the last row.

[0096] Note the general pattern in these register / wheel rotations, where initially odd-index qubits travel toward the Nth position within the wheel, and even-index qubits travel toward the 1st position within the wheel. When a qubit reaches the 1st or Nth (i.e., boundary) position of a register / wheel, the qubit is at the boundary position for two swap iterations, and then returns to travel toward the opposite boundary position in the register / wheel. When the qubit travels toward the Nth position of the register / wheel, the qubit can be referred to as an incoming qubit, and when the qubit travels toward the 1st position of the register / wheel, the qubit can be referred to as an outgoing qubit. Note also that when each qubit reaches the 1st or Nth position of the register / wheel, the qubit is at that position for two swap operations and then changes direction of travel.

[0097] Via process 300 implemented by a 2-qubit exchange network, each qubit will be the nearest neighbor of every other qubit within a rotation depth of N-1 at least once. Via process 320 implemented by a round exchange network, when the second to last initially entering qubit reaches the Nth position, each qubit will reach every position within the register / round at least once. The initially entering qubits are even-indexed qubits. Therefore, when the second to last even-indexed position reaches the Nth position, each qubit will have visited every position. For N=4, the second to last even-indexed qubit is qubit 2, for N=5, the second to last even-indexed qubit is qubit 4, for N=10, the second to last even-indexed qubit is qubit 8, and for N=10, the second to last even-indexed qubit is qubit 10. Therefore, the rotation of the register / round via process 320 can be terminated when qubit 2, 4, 8, or 10 reaches the Nth bit position for N=4, 5, 10, or 11 registers / rounds, respectively. The rotations below horizontal rows 332 and 334 indicate that additional register / wheel rotations are taken to return the ordering of the qubits to their original ordering. It should be noted that in embodiments it may not be required to return the qubits to their original positions.

[0098] Through each of processes 300 and 302, each 2-qubit term can be operated via nearest neighbor pairs for all N qubits. In addition, the operations can be parallelized via a network of parallelized exchange gates to reduce circuit depth. The embodiments of processes 300 and 320 discussed in conjunction with 2-qubit exchange networks and round exchange networks can be recursively employed to achieve k-qubit non-local interactions via localized groupings of qubits, where k is an integer greater than 2. More specifically, the concepts of 2-qubit pairs and round exchange networks can be combined with vectorization of qubits and rotation / permutation of vectorized configurations of qubits via localized (i.e., positionally continuous) groupings of k-qubits to achieve non-local interactions.

[0099] Localizing a 3-qubit combination (i.e., k=3)

[0100] The following discussion of embodiments with k=3 involves qubit swapping operations. However, as noted throughout this document, various embodiments are not so constrained, and the swapping operations may include fermion swapping operations. Three-qubit interactions (i.e., k=3) will now be discussed. For a three-qubit interaction, consider the three qubits Each of the unique combinations Unique combination. Similar to the k=2 embodiment, a switching network is employed to iteratively exchange qubits so that each non-local 3-qubit interaction is presented as a local interaction via three local (i.e., logically continuous) qubits. As discussed below, the k=3 embodiment can be recursively employed to present all non-local 4-qubit (i.e., k=4) interactions as local interactions via four local (i.e., logically continuous) qubits. As discussed above, molecular chemical orbital simulations can be implemented via summations over k=2 and k=4 terms. The k=2, k=3, and k=4 embodiments can be generalized to any higher value of k.

[0101] For k>2, the qubits of the register can be arranged into a vectorized configuration. For such a vectorized configuration, each of the N qubits can be classified as belonging to one of the k categories. Therefore, each qubit is marked with a unique index and a category label, where the index of the qubit is the unique ID of each qubit in the N qubits, and one or more qubits are assigned to each qubit category in the k qubit categories. Compared to the unique qubit index, multiple qubits can be marked with the same category. Therefore, there are N unique qubit indices and k categories of qubits, where k<N. Therefore, for k=3, in addition to the unique qubit index, each qubit will be assigned to one of categories 1, 2, or 3. The qubits will be marked in a cyclic manner. For a 14-qubit register, the 14 qubits may be labeled and ordered as (11, 22, 33, 41, 52, 63, 71, 82, 93, 101, 112, 123, 131, 142), where the normal font size integers indicate the unique index of the qubit and the subscripted integers indicate the class of the qubit (i.e., 1, 2, or 3).

[0102] A separate qubit wheel may be formed for each category, including the qubits assigned to that category. Because each qubit is assigned exactly one category, the formation of categories generates k disjoint subsets of N qubits. For example, for a 14-qubit register, a category 1 wheel includes qubits: (11, 41, 71, 101, 131), a category 2 wheel includes qubits: (22, 52, 82, 112, 142), and a category 3 wheel includes qubits: (33, 63, 93, 123). For an N-qubit register, the depth of qubit wheel_1 is calculated as: The depth of qubitwheel_2 is: And the depth of qubit wheel_3 is: Note that for all N, n1≥n2≥n3.

[0103] Each of the 3-qubit interactions can be calculated via grouping of local (i.e., logically contiguous within a register) 3-qubit combinations. For example, all unique combinations of one qubit from category 1, one qubit from category 2, and one qubit from category 3 must be acted upon by simulating a quantum circuit for the time-evolving operator for k=3. The notation of 123 is adopted to indicate a particular type of 3-qubit combination, where one qubit is from category 1, one qubit is from category 2, and one qubit is from category 3. For example, the combination of (1, 2, 3), (4, 5, 6), and (7, 8, 9) is a 3-qubit combination of the type of 3-qubit combination indicated as 123, as well as the combination of (1, 5, 9), (4, 8, 12), and (13, 11, 3). Note that there are n1·n2·n3 unique combinations of qubits in the 123 type 3-qubit combination. Generalizing this notation, all unique 3-qubit combinations of combination types 122 (e.g., (4, 2, 11)) and 133 (e.g., (10, 3, 9)) must be acted upon by the time evolution operator implemented via a quantum circuit, as well as the combination classes of 211 (e.g., (8, 4, 13)), 233 (e.g., (14, 6, 12)), 311 (e.g., (6, 1, 10)), and 322 (e.g., (12, 52, 14)) qubits. Similarly, all combinations of combination types 111 (e.g., (4, 10, 13)), 222 (e.g., (2, 8, 11)), and 333 (e.g., (3, 6, 9)) must be acted upon via a quantum circuit.

[0104] 3 The qubit combination types can be classified into five categories based on the symmetry of the qubit combination types of the qubit category. For example, in view of the symmetry between qubit combination types 122 and 133, these qubit combination types can be classified into categories having member qubit combination types 122 and 133. Similarly, qubit combination types 211 and 233 can be classified together, qubit combination types 311 and 322 can be classified together, and qubit combination types 111, 222, and 333 can be classified together.

[0105] Figure 4AA table 400 is provided illustrating various properties of class types for 3-qubit interactions consistent with various embodiments presented herein. More specifically, each row of table 400 corresponds to a class of qubit combination types. Note that for k=3, class 0 corresponds to the 123 type combination and class 4 includes member types 111, 222, and 333. Classes 1, 2, 3, each include member types having a single qubit from the round indicated by the class and two qubits from one of the other two rounds. The first column of table 400 indicates the class of 3-qubit combination types. The second column of table 400 indicates the combination type members included in the class of the row. The third column of table 400 indicates the number of unique 3-qubit combinations included in the class. Note that the calculations in this column assume N divided by 3. For large N, and thus any error due to this assumption is small. The fourth column of table 400 indicates the ratio of 3-qubit combinations for a class (as indicated by column 3) to the total number of 3-qubit combinations for large N. As will be explained below, the fifth column of table 400 indicates the depth of a round rotation (e.g., a qubit swap operation) that renders all 3-qubit combinations as groups of three localized (i.e., continuous) qubits.

[0106] Figure 4B A table 410 is provided that illustrates vectorization for 3-qubit configurations for 5≤N≤10 consistent with various embodiments presented herein. Each row of table 410 corresponds to a separate value of N, where the value of N is indicated in the first column. The second, third, fourth, and fifth columns of table 410 correspond to class 0, class 1, class 2, and class 3 of 3-qubit combination types. Each entry in the table provides a vector (of length N) of combination type classes for a corresponding value of N. As will be discussed below, the vector indicates an arrangement of combination types to achieve Each of the three qubit interactions interacts with each other.

[0107] Briefly stated here, the vectorization for the class of combination types indicates the class of qubits that should be arranged (or swapped) into corresponding bits of the register to implement for each of the many unique 3-qubit combinations of the combination type that are members of the corresponding class of combination types. For example, as follows in combination with at least FIG. 5A to FIG. 5BAs discussed, to achieve each of the possible 3-qubit combinations, via local grouping of 3-qubits, for N=8, the 8 qubits are arranged such that the qubit categories within the register are ordered via the following vector: [1, 2, 3, 1, 2, 3, 1, 2], where the integers indicate the qubit type, not the qubit index. One possible such arrangement of qubits within an 8-qubit register is the following initial qubit ordering: (1, 2, 3, 4, 5, 6, 7, 8), where the integers refer to the qubit index. As another example, for category 1 with N=8, the 8 qubits are arranged such that the qubit categories within the register are ordered as the following vector: [1, 2, 2, 1, 2, 3, 3, 1]. One possible such arrangement of qubits within an 8-qubit register is the following initial qubit ordering: (1, 2, 5, 4, 8, 3, 6, 7). The vectorization patterns of the various combination types (and categories) are apparent from the symmetry of Table 410. Figure 4C Table 420 of FIG. 4 shows a non-limiting example of vectorization for category 1 with N=14, 15, 16, 17, 18, and 19. That is, Table 420 provides vectorization for the vectors provided in Figure 4A Various embodiments of vectorization for larger values ​​of N in Table 400. Figure 4D Table 430 of FIG. 4 shows additional non-limiting embodiments of vectorization for category 1 for N=14, 15, 16, 17, 18, and 19. The vectorizations shown in Tables 420 and 430 are non-limiting, and other vectorizations may be employed. For example, in an alternative vectorization for N=17 (not shown in FIG. 4 ), Figure 4C or Figure 4D In the above figure, it is {1,2,2,1,2,2,1,2,2,1,3,3,1,3,3,1,3}.

[0108] Notice, Figure 4B The embodiment of the 3-qubit vector shown in Table 410 of is non-limiting, and other vectors are possible. Therefore, the embodiments are not constrained via the vectors shown in Table 410. As a non-limiting example, in some embodiments, the vectors for N=6, type 1 may include the vector: [1, 3, 3, 1, 2, 2], rather than the vector: [1, 2, 2, 1, 3, 3], as shown in Table 410. As an additional non-limiting example, the vectors for N=10, type 2 may alternatively include the vector: [1, 1, 2, 1, 1, 2, 3, 3, 2, 3], and the vectors for N=10, type 3 may alternatively include the vector: [1, 1, 3, 1, 1, 3, 2, 2, 3, 2]. That is, for types 2 and / or 3, the pattern "1, 2, 2" may be repeated until the round_2 qubits are exhausted, and then the pattern of "3, 3, 1" is adopted.

[0109] Figure 5A A flow chart is provided illustrating a process 500 of operation of a round-switch network that localizes all 123 types of 3-qubit combinations (ie, type 0) within a quantum computer. Figure 5B Operations of process 500 are shown for an N=8 qubit quantum computer. FIG. 5A to FIG. 5B will be discussed together. FIG. 5A to FIG. 5B The following discussion of refers to qubit swap operations. However, as noted throughout this document, various embodiments are not so constrained, and the swap operations may include fermion swap operations.

[0110] Figure 5B The swap operation 520 shows the iterative wheel rotation operation of process 500 on an N=8 qubit register subdivided into 3 qubit wheels. The matrix symbol of operation 520 indicates the dynamics of the qubit swaps (i.e., rotations) for each iterative step of process 500 for N=8. In the following discussion, a single rotation operation of a wheel may refer to a parallelized odd-pair or even-pair swap of nearest neighbor pairs within the wheel. That is, a single wheel rotation may include a parallelized odd-pair or even-pair swap operation of a run of wheels corresponding to one of the following: box 322 or box 328, Figure 3B Each process in process 320. A full rotation of the wheel may correspond to a full run of process 320. If the depth of the wheel is d w (n), then the wheel must transition through n arrangements (or reorderings) for a complete rotation. Thus, starting from the initial arrangement (or order), it generally takes n-1 single swap operations for each qubit to visit each position within the wheel.

[0111] Process 500 includes an iterative loop that alternates between odd-pair and even-pair swap operations. As noted, the termination condition for the iterative loop for process 500 is that each qubit has been to each position within its round at least once during process 500, which occurs deterministically with the following swap depth: d w (n) = 2n-2 + mod (n, 2). Figure 5A As shown in , process 500 includes a decision box (i.e., box 504) that checks whether the termination condition is satisfied. Because the termination condition occurs via a deterministically determined exchange depth, this decision box is optional. That is, process 500 does not need to check whether the termination condition has occurred because it occurs deterministically via a deterministically determined exchange depth. This decision box is included for illustrative purposes and does not need to be implemented.

[0112] Process 500 begins at block 502 after a start block, where each of the N qubits is assigned to one of rounds ROUND_1, ROUND_2, or ROUND_3. Figure 5BAs shown in , for N=8, round_1 530 includes qubits [1,4,7], round_2 540 includes qubits [2,5,8], and round_3 560 includes qubits [3,6]. Therefore, n1=3, n2=3, and n3=2. The corresponding dynamics of qubit exchange at the level of each round are shown in the corresponding rows and columns to the right of operation 520. Process 500 includes iteratively operating on round_1 and round_2 to implement each type 0 3 qubit combination as a round exchange network of local groups. As shown in FIG. 5A to FIG. 5B As shown in , the round-swapping network operating on wheel_1 can be nested and / or run as a subroutine of the round-swapping network operating on wheel_2. In order to achieve each unique 3-qubit type 0 combination, wheel_3 does not need to be required to be rotated.

[0113] Because the wheel swap network operated on wheel_1 is a subroutine of the wheel swap network operated on wheel_2, wheel_1 is fully rotated for each placement (i.e., reordering) of wheel_2 (within the wheel depth of wheel_2). That is, for each update of the order of wheel_2, wheel_1 is rotated via Figure 3B The process 320 of is fully rotated so that each qubit in round_1 visits every position within round_1 at least once. For N=8, the round depth for round_1 530 and round_2 540 is: d w (n1) = d w (n2) = d w (3) = 5. Therefore, in order to make a qubit access to each position in wheel_1 540 or wheel_2 540, the corresponding wheel must pass through 5 arrangement (or ordering) transitions, which generally requires 5-1 = 4 single parallelized odd-pair or even-pair swap operations, i.e., a single rotation. Figure 5B 530, the boxes grouping the five reorderings of wheel_1 530 indicate a full rotation of wheel_1 530. Note that four parallelized swap operations (or four single rotations) of wheel_1 530 are required to fully rotate wheel_1 530. For wheel_2 540, the boxes group a single swap operation (i.e., a single rotation) of wheel_2 540. Note that similar to wheel_1 530, for a full rotation of wheel_2 540, four single parallelized swap operations (or single rotations) are required for each qubit to access each bit position within wheel_2 540. The boxes for wheel_1 530 and wheel_2 540 indicate that a rotation of wheel_1 530 is a subroutine of a rotation of wheel_2 540. A full cycle of swap operations on a wheel may include a full rotation of the wheel and / or a full run of process 320 on the wheel.

[0114] If still Figure 5BAs shown in , the rotation of wheel_1 540 cycles with the following 6 rotation periods: [1, 4, 7] → [4, 1, 7] → [4, 7, 1] → [7, 4, 1] → [7, 1, 4] → [1, 7, 4] → [1, 4, 7]. Through the symmetry about wheel_1 530, the rotation of wheel_2 540 also cycles with the following 6 rotation periods: [2, 5, 8] → [5, 2, 8] → [5, 8, 2] → [8, 5, 2] → [8, 2, 5] → [2, 5, 8] → [2, 5, 8]. Figure 5B In operation 520 of , and for N=8, all n1·n2·n3=12 of the 123 type (i.e., category 0) qubit combinations are implemented. Figure 4A As shown in the fifth column of Table 400, the depth of the nested rotations of wheel_1 and wheel_2 in process 500 (for category 0 combination) is d w (n1)·d w (n2).

[0115] At decision block 504, it is determined whether the termination condition for rotating wheel_2 is satisfied. Figure 3B As discussed in decision block 326 of , at block 504, it is determined whether each qubit in round_2 has visited each position within round_2. As noted, round_2 has d w (3)=5 swap depth. Therefore, the termination condition for wheel_2 is satisfied after four rotations of wheel_2. If wheel_2 has not been fully rotated, then process 500 flows to block 506. Otherwise, process 500 flows to block 510.

[0116] At block 506, wheel_1 is fully rotated. Various embodiments for rotating wheel_1 incorporate at least Figure 3B As noted above, Figure 5B The box grouping the reordering of wheel_1 530 in FIG. 5 shows a full rotation of wheel_1 530. At box 508, wheel_2 is rotated via one swap operation (via parallelized odd-pair or even-pair qubit swap operations). The box grouping a single swap operation (or wheel rotation) of wheel_2 540 shows one rotation of wheel_1. Process 500 returns to decision box 504. At box 510, another full cycle of swap operations and / or full rotation of the wheel is required to generate all kinds of 0-3 qubit combinations. Process 500 then terminates.

[0117] like Figure 5B As shown in , process 500 implements the generation of 3-qubit combinations of each type 0. 3-qubit combinations of types 1, 2, 3, and 4 may also be generated. Figure 5CA flow chart illustrating a process 580 for localizing all class 1 3-qubit combinations within a quantum computer is provided. Due to the symmetry between classes 1, 2, and 3, process 580 can be generalized to find all 3-qubit combinations of classes 2 and 3 that replace corresponding rounds of those classes. Class 4 3-qubit combinations are discussed below.

[0118] Figure 5D The diagram is consistent with various embodiments. Figure 5C An embodiment of a 2D qubit configuration utilized in process 580. Note that Figure 5D The 2D nature of the qubit configuration shown in need not be a physical configuration of the qubits, but can instead be a logical structure. Figure 5D Will combine Figure 5C The process of 580 is discussed. FIG. 5C to FIG. 5D The following discussion of is directed to qubit swap operations. However, as noted throughout this document, various embodiments are not so constrained, and the swap operations may include fermion swap operations. Process 580 includes an iterative loop that alternates between odd-pair swap operations and even-pair swap operations. As noted, the termination condition for the iterative loop of process 580 is that each qubit has been to each position within its round at least once during process 580, which occurs deterministically with the following swap depth: d w (n) = 2n-2 + mod (n, 2). Figure 5C As shown in , process 580 includes a decision box (i.e., box 588) that checks whether the termination condition is satisfied. Because the termination condition occurs via a deterministically determined exchange depth, this decision box is optional. That is, process 580 does not need to check whether the termination condition has occurred because it occurs deterministically via a deterministically determined exchange depth. This decision box is included for illustrative purposes and does not need to be implemented.

[0119] After a start block, process 580 begins at block 582 where the qubits are sorted into a vector of kind 1 and / or an order based thereon. Figure 4B , Figure 4C and Figure 4D Vectors for class 1 are shown. The patterns for these vectors can be generalized to higher values ​​of N. Any qubit sorting routine can be employed to sort the qubits via a qubit swap operation. For example, after termination of process 500, the qubits will be sorted such that the rounds are interleaved. A bubble sort algorithm can be employed to sort the qubits into an order based on the vectors for class 1. Figure 5D A non-limiting example is shown for N=18. The qubits assigned to each of the three rounds are shown. Figure 4CAs indicated in Table 420, the vector of N=18 for category 1 may be: {1, 2, 2, 1, 3, 3, 1, 2, 2, 1, 3, 3, 1, 2, 2, 1, 3, 3}. Figure 4D Other alternating vectors are possible as indicated in Table 430 in . The sorted registers show one possible sorting of the qubits based on the vector. Other sortings of the registers are possible. In one embodiment, prior to block 582, the qubits may be returned to their initial positions via additional wheel rotations and then sorted based on the vector. Figure 5D , the arrows grouping boxes of the same round qubits in the kind 1 vector and boxes in the sorted registers show the correspondence between the vectors and the sorted registers, as generated via box 582. For N=18, n1=n2=n3=6.

[0120] Process 580 generates every possible 122 and every possible 133 type combination. In various embodiments of process 580, round 1 is generated by Figure 5B The process 520 is rotated. Wheel_2 and Wheel_3 can be configured as a 2D qubit configuration. The 2D qubit configuration for Wheel_2 and Wheel_3 is shown in Figure 5D A 2D qubit configuration is a logical or virtual arrangement of qubits that does not require a physical arrangement of physical instances of qubits. Figure 5D As shown in , a 2D qubit configuration may include a 2D logical arrangement of qubits, the 2D logical arrangement including 2 columns and The last row will consist of only a single qubit, where n is the number of qubits in the round. If n is an odd number, then the last row will consist of only a single qubit.

[0121] The 2D qubit configuration can be somewhat analogous to a 2-wheel vending machine, where the vertical columns of 2D qubits are analogous to the wheels of the vending machine, and the horizontal rows correspond to the coin slots of the vending machine. Each of the horizontal rows corresponds to one of the wheels in the nearest neighbor pair within the register. Figure 5D As shown in , for N=18, there are three horizontal rows for each of rounds 2 and 3. Each of the horizontal rows corresponds to one of the two qubit pairs of qubits from the same round of the vector based on species 1. Figure 5D In FIG, the arrows between the 2-qubit pairs in the sorted register and the horizontal rows indicate the correspondence.

[0122] Round_1 is rotated via parallelized swap operations so that each qubit in round_1 accesses each position in the register corresponding to a vector of type 1 at least once. Figure 5DIn the example, the parallelized odd-pair and even-pair swapping operations of round_1 are shown as arrows in the type 1 vector. To achieve each 122 type combination, the possible Each of the 2-qubit pairs must appear consecutively in one of the horizontal rows of the round_2 2D qubit configurations at least once during each arrangement of round_1. Similarly, to generate each 133 type combination, the possible round_3 Each of the 2-qubit pairs must appear consecutive in one of the horizontal rows of the 2D qubit configuration in round_2 at least once during each arrangement of round_1. Thus, the qubits of the 2D qubit configuration may be (e.g., respectively) Figure 3A and Figure 3B Process 300 or process 320) are gradually exchanged so that each pair in the wheel appears continuous at one of the horizontal rows.

[0123] Therefore, in process 580, round_1 passes Figure 3B The process 320 of is rotated. As a subroutine of the swap operation of wheel_1, the 2D qubit configurations of wheel_2 and wheel_3 can be added in parallel, generating 3-qubit combinations of each type 122 and 133. It should be understood that the process 580 can generate each of the 112, 233, 311 and 322 combinations by rearranging the rotated wheels, and the two wheels are arranged on the 2D qubit configuration. Therefore, all 3-qubit combinations for types 1, 2 and 3 can be generated via process 580.

[0124] Return to Figure 5C At block 584, round_2 is logically arranged into a 2D qubit configuration. At block 586, round_3 is logically arranged into a 2D qubit configuration. One embodiment of a 2D qubit configuration for round_2 and round_3 is shown in Figure 5D At decision block 588, it is determined whether the termination condition has been met for round_1. That is, at block 588, it is determined whether each qubit within round_1 has reached each position of round_1. If so, then process 580 flows to block 594. Otherwise, process 580 flows to block 590. At block 590, the 2D qubit configurations of each of rounds 2 and 3 are incremented via the swap operation so that the possible positions of round_2 are Each of the 2-qubit pairs in round_2 appears as a continuous pair in one of the horizontal rows of the 2D qubit configurations of round_3, and the possible Each of the 2-qubit pairs appears as a consecutive pair in one of the horizontal rows of the 2D qubit configuration of round_3. Various embodiments of process 300 or process 320 may be employed to increase the 2D qubit configuration via alternating parallelized odd-pair and even-pair swap operations such that each pair in the round is a nearest neighbor pair at least once and is adjacent in one of the horizontal rows. As noted, the additions to round_2 and round_3 may be parallelized such that round_2 and round_3 are increased together.

[0125] At block 592, a rotation operation is performed on wheel_1 via a parallelized odd-pair swap operation and a parallelized even-pair swap operation. Figure 3B At least a portion of process 320 may be employed to perform a rotation operation on wheel_1. Process 580 returns to decision block 588. At block 594, to generate the remaining 122 and 133 types of 3-qubit groupings associated with the final arrangement of wheel_1, the 2D qubit configurations of each of wheel_2 and wheel_3 are increased via swap operations so that the possible 122 and 133 types of 3-qubit groupings of wheel_2 are increased to 122 and 133 types of 3-qubit groupings of wheel_1. Each of the 2-qubit pairs in round_2 appears as a continuous pair in one of the horizontal rows of the 2D qubit configurations of round_3, and the possible Each of the 2-qubit pairs appears as a consecutive pair in one of the horizontal rows of the 2D qubit configurations of round_3. Once all localized 3-qubit groups of type 1 have been generated, process 580 can terminate. Note that because the addition of round_2 and round_3 is parallelized in blocks 590 and 594, the 122 and 133 type combinations are generated in parallel.

[0126] Class 2 and class 3 localized 3-qubit combinations can be generated via a similar process of rearranging the rounds. Thus, process 500 can generate class 0 combinations, and process 580 (and variations thereof) can generate class 1, 2, and 3 combinations. Class 4 combinations can be generated by recursively employing processes 500 and 580. In an exemplary and non-limiting embodiment. After generating each of the class 0, 1, 2, and 3 combinations, the register can be sorted (e.g., parallel bubble sort) based on the following class 4 vectors: {1, 1, 1, ... 1, 1, 1, 2, 2, 2, ..., 2, 2, 2, 3, 3, 3, ..., 3, 3, 3}. That is, the register can be sorted into three sub-registers, each of which stores the qubits of one of the three rounds. Processes 500 and 580 can be recursively applied to each of these sub-registers, thereby generating sub-sub-registers. The recursive application can continue until all class 4 localized 3-qubit combinations have been localized within each of these sub-registers. Note that the recursive application of processes 500 and 580 to generate class 0, 1, 2, and 3 localized combinations within a subregister can be parallelized to improve efficiency and reduce the depth of the switching network required to generate the localized 3-qubit combinations. After terminating the recursion, each of the class 0, 1, 2, 3, and 4 localized combinations for 3 qubits has been generated.

[0127] Note that in order to implement the recursion required to generate category 4 combinations, it can be shown that the depth of the required switching network is determined as: Therefore, if combined with at least Figure 5E As described, the required switching network depth is measured as

[0128] Figure 5E Provides an indication that the circuit depth of the switching network for a 3-qubit operator is approximately measured as 596. For the solid circle discrete data points (●), the depth of the network as a function of N is calculated by simulating the swap operations using a complete swap network including the parallel bubble sort operations required to transition between swap operations for various types of combinations. That is, for the solid data points, the depth of the network as a function of N is calculated by simulating the swap operations using a complete swap network including the parallel bubble sort operations required to transition between swap operations for various types of combinations. FIG. 5A to FIG. 5D The discussed exchange operation has been numerically simulated to generate possible For each of the localized (i.e., logically consecutive) 3-qubit pairs in the register. For non-solid data points (○), the depth of the network is calculated by Figure 4AThe expressions for the depth of the required swap operations for the various categories shown in the fifth column of Table 400 are determined analytically. For the non-solid data points, the contribution of the parallel bubble sort operations has been ignored. The solid line indicates the double logarithmic linear regression fit to the solid data points. The dashed line indicates the double logarithmic linear regression fit to the non-solid data points. For the solid line, the double logarithmic linear fit is: (1.19 ± 0.03) · 10 2.007±0.004 For the dashed line, the double logarithmic linear fit is: (1.10±0.03)·10 2.020±0.005 The linear fits to both methods (numerical simulation and analytical calculation) show that the depth of the switching network (or the parallelized switching operations) is approximately measured as And parallel bubble sort does not drive scaling of required circuit depth.

[0129] Localizing a 4-qubit combination (i.e., k=4)

[0130] The discussion below for embodiments where k=4 is directed to qubit swap operations. However, as noted throughout this document, various embodiments are not so constrained, and the swap operation may include a fermion swap operation. Possible Each of the 4-qubit combinations can be localized by recursively generating localized 2-qubit and 3-qubit combinations as now discussed. That is, combining at least FIG. 3A to FIG. 5E The various embodiments discussed can be applied iteratively and recursively to localize 4-qubit combinations. For k=4, the N qubits can be subdivided into four rounds: round_1, round_2, round_3, and round_4. The process of assigning qubits to four rounds can be generalized from the process of assigning qubits to three rounds. In addition, 4-qubit combination types can be generated via four rounds, similar to the one discussed with respect to 3-qubit combination types. For example, 4-qubit combination types include, but are not limited to: 1234, 1122, 1134, 1113, and 1111. Similar to the types of 3-qubit combinations, 4-qubit types can be organized into various classes by exploiting the symmetry of the combination types. Note that for embodiments where k=3, the third wheel does not need to be rotated, i.e., the swap operation does not need to be performed on the qubits included in round_3. Similarly, for embodiments where k=4, the swap operation does not need to be performed on the qubits of round_4. Therefore, in some embodiments, the generation of round_4 is not required.

[0131] Fig. 6A A table 600 is provided illustrating various properties for a class type of 4-qubit interactions consistent with various embodiments presented herein. Table 600 is similar to Figure 4ATable 400 is similar to Table 400, but for 4-qubit combinations rather than 3-qubit combinations. The first column of Table 600 shows that there are 15 categories of combination types for 4-qubit combinations, and the second column indicates the members of each category. Each of the combination types can be referenced as: 1234, XXYY, XXYZ, XXXY, and XXXX, where the variables X, Y, and Z can take on values ​​of 1, 2, 3, or 4.

[0132] Figure 6B Table 610 is provided that illustrates vectorization of 4-qubit configurations consistent with various embodiments presented herein for 5≤N≤10. Each row of table 610 corresponds to a separated N value, where the value of N is indicated in the first column. The second, third, fourth, and fifth columns of table 610 correspond to category 1, category 2 (and categories 3 and 4), category 5 (and categories 6-10), and category 11 (and categories 12-14) of 4-qubit combination types. Each entry in the table provides a vector (of length N) for a corresponding N value and combination type category. As will be discussed below, the vector indicates an arrangement of combination types to achieve Each of the 4-qubit interactions interacts with each other.

[0133] Figure 6C A flow chart illustrating a process 620 of a swap operation implemented by a 2-qubit time-slot network employed in the 4-qubit embodiments discussed herein is provided. As will be discussed below, a 2-qubit time-slot network (such as that implemented via process 620) is employed to generate a 4-qubit interaction such as Fig. 6A The types 2, 3, and 4 of Table 600 combine types of interactions. Similar to other processes discussed throughout this document, even though the discussion of process 620 is directed to qubit swap operations, embodiments are not so limited, and the swap operation can be applied to fermion orbitals. Process 620 can be a recursive process. Process 620 begins at block 622 after a start block, where qubits (or fermion orbitals) are divided into two groups: group_0 and group_1. Qubits can be members of a wheel. If a wheel has n qubits, then group_0 can include qubits and group_1 may include A quantum bit.

[0134] At block 624, a parallel bubble sort is applied so that the qubits in each group are adjacent to the qubits with corresponding indices in other groups. At block 626, a round-trip network is applied to cycle through the label assignments in group_1. At decision block 628, a determination is made as to whether a termination condition has been met. In some embodiments, a termination condition for process 620 may include Is it true. If the termination condition is met, then process 620 can terminate. Otherwise, process 620 can return to box 622 for a recursive call to process 620. The double return arrow indicates that each group in group_0 and group_1 recursively calls process 620. In the recursive call, each group is further subdivided, thereby reducing the current value of n in each recursive call. Note that with respect to other embodiments, the number of recursive calls is deterministic, so decision box 628 may not need to be called. It can be shown that the circuit depth of the 2-qubit time slot network implementing process 620 is: like Fig. 6A As indicated in Table 600 of , this switching network depth is employed in types 1, 2, and 3 qubit combinations.

[0135] Fig. 7A A schematic overview of the combination of switching networks that localize each type of 4-qubit combination is provided. More specifically, Fig. 7A An overview of the types of swap operations employed in at least one embodiment to generate localized 4-qubit combinations for the following: 1234, XXYY, XXYZ, XXXY, and XXXX combination types. As shown, for the 1, 2, 3, 4 types, four instances of a round swap network are employed, where each of the 1, 2, 3, and 4 categories of qubits is included in one of the rounds. Similar to the 3-qubit combinations, rotations of the rounds are nested and can be run as multiple nested subroutines. Figure 7C Process 720 of shows one non-limiting embodiment of nesting. For XXYY type, a 2-qubit pair exchange network is utilized for each round in X rounds, and a 2-qubit time slot exchange network is utilized for each round in Y rounds. For XXXY type, a 3-qubit combination exchange network is utilized for each round in X rounds, and a round exchange network is utilized for each round in Y rounds. For XXYZ type, a 2-qubit time slot exchange network is utilized for each round in X rounds, a round exchange network is utilized for each round in Y rounds, and a round exchange network is utilized for each round in Z rounds. As also described in Fig. 7AAs shown in , the XXXX combination is generated from recursive calls to other types of combinations. Recursive calls are performed for each round. Therefore, four sub-wheels (e.g., wheel_1_1, wheel_1_2, wheel_1_3, and wheel_1_4) are generated for wheel_1, four sub-wheels (e.g., wheel_2_1, wheel_2_2, wheel_2_3, and wheel_2_4) are generated for wheel_2, four sub-wheels (e.g., wheel_3_1, wheel_3_2, wheel_3_3, and wheel_3_4) are generated for wheel_3, and four sub-wheels (e.g., wheel_4_1, wheel_4_2, wheel_4_3, and wheel_4_4) are generated for wheel_4. Recursion is terminated when each localized combination of 1111, 2222, 3333, and 4444 types has been generated. The recursive calls for each round (and each sub-wheel) can be parallelized to reduce the required circuit depth.

[0136] Figure 7B A flow chart illustrating a process 700 for localizing all 2-qubit and all 4-qubit combinations within a quantum computer is provided. More specifically, process 700 uses Fig. 7A Process 700 begins at block 702 after a start block, where each of the 2-qubit terms is generated by a 2-qubit pair network or round exchange network applied to a register. The network can perform multiple exchange operations on the register. At least in combination FIG. 3A to FIG. 3C Various embodiments of qubit pairs and round swapping operations are discussed. At block 704, qubits are subdivided into four rounds: round_1, round_2, round_3, and round_4. As discussed elsewhere herein, qubits included in round_4 do not need to be swapped. Therefore, in some embodiments, round_4 may not need to be generated, and qubits belonging to round_4 may be classified as not belonging to any of rounds in round_1, round_2, or round_3.

[0137] At block 706, localized combinations of type 1234 are generated via a round-swap operation applied through a round-swap network for each of the four rounds. Round-swap operations can be nested, similar to Figure 5A A non-limiting example of a nested round swap operation combines Figure 7C Therefore, at block 704, a category 1 (e.g. Figure 7C As shown in Table 600, for category 1, the depth of the swap operation can be determined by d w (n) Determined with certainty.

[0138] At block 708, the XXYY term is generated via a nested swap operation applied to the 2-qubit pair swap network of round X, and the 2-qubit slot network is applied to round Y. Various embodiments of these swap operations combine at least Figure 3A and Figure 6C Therefore, at block 708, each of the combinations of categories 2, 3, and 4 of table 600 is generated. As shown in table 600, for categories 2, 3, and 4, the depth of the swap operation can be determined by d w (n) and ds(n) are determined deterministically. Note that prior to generating the XXYY terms at block 708, sorting of the qubits may be performed to configure the qubits in the proper vectorization order. Various embodiments of qubit vectorization are shown in Figure 6B 610. For example, parallel bubble sort exchange operations can be performed.

[0139] At block 710, the XXYZ term is processed by a 2-qubit pair swap network operating on round X and a round swap network operating on each of rounds Y and Z (see, e.g., Figure 3B and FIG. 5A to FIG. 5D ) is generated. That is, the category 5 to 10 combination of table 600 is generated at block 710. As shown in table 610, for categories 5 to 10, the depth of the exchange operation can be determined via d2(n) and d w (n) is determined deterministically. Similar to the above, a parallelized bubble sort can be performed on the qubits to properly sort the qubits via an appropriate vectorized sort.

[0140] At block 712, XXXY terms are generated via a swap operation applied to the round swap network of round Y and the 3-qubit swap network of round X. That is, types 11 to 14 combinations are generated at block 712. More specifically, a 3-qubit structure is employed to cycle through each pair in the triplet pair and then rounds are used to cycle through the unpaired indices. Various embodiments for such a swap operation incorporate at least Figure 3B and FIG. 5A to FIG. 5D As shown in Table 610, for categories 11 to 14, the depth of the swap operation can be determined by applying d3(n) and d w (n) is determined deterministically. Note that prior to generating the XXXY terms at block 712, sorting of the qubits may be performed to configure the qubits in a suitable vectorized order. For example, parallel bubble sort swap operations may be performed.

[0141] To generate the type 15 combination, a recursive process similar to the type 4 combination for 3 qubits is used. Parallel bubble exchange can be used to sort the qubits into appropriate qubit vectors. At decision block 714, it is determined that each type combination in the XXXX type combination has been localized. If so, process 700 terminates. Otherwise, a recursive call is made for each of the four rounds. That is, each round is returned to block 704. The recursive call for the four rounds is shown via four return paths from block 714 to block 704. Similar to the respective return paths for Figure 3A , Figure 3B , Figure 5A and Figure 5C As discussed with respect to the decision blocks of processes 300, 320, 500, and 580, decision block 714 need not be implemented in various embodiments due to the deterministic swap depth required to satisfy the termination condition of the loop.

[0142] Figure 7C A flow chart illustrating a process 720 for localizing all type 0 (i.e., 1234 type combinations) 4 qubit combinations within a quantum computer is provided. Process 720 may be Figure 7B For example, process 720 may be called via the execution of block 706 of process 700. In process 720, a parallelized swap operation is performed on wheel_3 (via the wheel swap network) such that each qubit in wheel_3 visits each position in wheel_3. That is, wheel_3 is rotated completely through its depth. As a subroutine of the rotation of wheel_3, wheel_2 is rotated completely through its depth. As a subroutine of the rotation of wheel_2, wheel_1 is rotated completely through its depth. To generate a type 0 combination, wheel_4 does not need to be rotated. Thus, somewhat similar to Figure 5A , but involving four wheels instead of three.

[0143] For illustrative purposes, and because the wheel is rotating via nested rotations and / or subroutines, the concept of a round counter has been introduced into process 720. These round counters can be considered similar to the loop counters (or loop indexes) in the for-loop process. Because the loop of process 720 is run as a subroutine, once the nested loop has been completed, these round counters are increased and reset. The increase of the round counter is inferred and process 720 includes an explicit box (e.g., box 734 and 736) that resets the round counter. Note that these round (or loop) counters are only for illustrative purposes and do not need to be implemented due to the deterministically determinable depth of the exchange operation. In addition, similarly to as discussed above, the decision box (e.g., box 722, 724, and 726) that checks the termination condition of the loop does not need to be explicitly implemented due to the deterministic nature of the exchange operation.

[0144] Process 720 begins at decision block 722 after the start block, where it is determined that each qubit in wheel_3 has visited each position in wheel_3 at least once. If the termination condition for wheel_3 is met, then process 720 flows to block 738. At block 738, wheel_2 is fully rotated again and wheel_1 is rotated to a subroutine of the rotation of wheel_2. One embodiment of the subroutine for rotating wheel_1 to fully rotate wheel_2 incorporates at least Figure 5A These final rotations of wheel_1 and wheel_2 will complete the generation of all 1234 type combinations. Therefore, process 720 can terminate after running block 738. If the termination condition for wheel_3 is not met, process 720 flows to decision block 724.

[0145] At decision block 724, it is determined that each qubit in round_2 has visited each position in round_2 because the counter for round_2 has been reset. If the termination condition for round_2 is met, then process 720 flows to block 736, otherwise the process flows to decision block 726. At block 736, the termination condition for round_2 is reset and process 720 flows to block 732. At block 732, a parallelized exchange operation is performed on round_3. Various embodiments for performing parallelized exchange operations on rounds at least in combination Figure 3B However, in brief description herein, round_3 is rotated via an odd-pair or even-pair parallelized qubit swap operation. Process 720 then returns to decision block 722.

[0146] At decision block 726, it is determined that each qubit in round_1 has visited each position in round_1 because the counter for round_1 has been reset. If the termination condition for round_1 is met, then process 720 flows to block 734, otherwise the process flows to decision block 728. At block 734, the termination condition for round_1 is reset and process 720 flows to block 730. At block 730, a parallelized exchange operation is performed on round_2. Various embodiments for performing parallelized exchange operations on rounds combine at least Figure 3B However, in this article, for simplicity, round_2 is rotated via an odd-pair or even-pair parallelized qubit swap operation. Process 720 then returns to decision block 724.

[0147] At block 728, a parallelized exchange operation is performed on round_1. Various embodiments for performing a parallelized exchange operation on a round combine at least Figure 3B However, for simplicity, round_1 is rotated via an odd-pair or even-pair parallelized qubit swap operation. Process 720 then returns to decision block 726.

[0148] Fig.7D For a quantum computer with N = 10 qubits Figure 7B 700 of process 700. More specifically, swap operation 740 shows how each of the possible 4-qubit combinations can be localized. The arrows between the columns show the order in which the matrix is ​​split to fit on a single page.

[0149] Fig. 7E Provides an indication that the circuit depth of the switching network for a 4-qubit operator is approximately measured as 760. For the solid circle discrete data points (●), the depth of the network as a function of N is calculated by simulating the swap operations using a complete swap network including the parallel bubble sort operations required to transition between swap operations for various types of combinations. That is, for the solid data points, the depth of the network as a function of N is calculated by simulating the swap operations using a complete swap network including the parallel bubble sort operations required to transition between swap operations for various types of combinations. FIG. 7A to FIG. 7D The discussed exchange operation has been numerically simulated to generate possible For each of the 4-qubit pairs that are localized (i.e., logically contiguous in the register), the depth of the network is calculated by Fig. 6A The expressions for the depth of the required swap operations for the various categories shown in the fifth column of Table 600 are determined analytically. For the non-solid data points, the contribution of the parallel bubble sort operations has been ignored. The solid line indicates the double logarithmic linear regression fit to the solid data points. The dashed line indicates the double logarithmic linear regression fit to the non-solid data points. For the solid line, the double logarithmic linear fit is: (0.69 ± 0.09) · 10 3.06±0.03 For the dashed line, the double logarithmic linear fit is: (0.76±0.03)·10 3.04±0.01 The linear fits to both methods (numerical simulation and analytical calculation) show that the depth of the switching network (or the parallelized switching operations) is approximately measured as And parallel bubble sort does not drive scaling of required circuit depth.

[0150] Fig. 7E Provides an indication that the circuit depth of the switching network for a 4-qubit operator is approximately measured as Plot 760 of the numerical results. Combined with at least FIG. 7A to FIG. 7D The discussed exchange operation has been numerically simulated to generate possible Each qubit pair in the 4-qubit pair is localized (i.e., logically contiguous in the register). Note that plot 760 is a log-log plot. The log-log regression fit suggests that the depth of the switching network (or parallelized switching operation) is approximately measured as Therefore, with approximately Various enhanced embodiments provide at least an order of magnitude reduction in circuit depth compared to conventional approaches.

[0151] Quantum computing environment

[0152] Figure 8 800 is a block diagram of an exemplary quantum computing environment 800 suitable for use in implementing embodiments of the present disclosure. The quantum computing environment 800 includes quantum hardware, such as, but not limited to, a quantum processing unit 802, a quantum register, and one or more monitoring / measurement devices 846. The quantum register 848 may include a physical implementation of N quantum bits. The quantum bits may be monitored, measured, observed, or otherwise probed via the measurement and monitoring device 846. The quantum processor 802 runs a quantum circuit (e.g., a circuit implementing the time evolution operator and the parallelized switching network discussed herein). The circuit may be precompiled by the classical compiler unit 820 using one or more classical processors 810. The compiled quantum circuit may be downloaded to the quantum processing unit via the quantum bus 806. In some cases, the quantum circuit or a portion thereof is predefined in the device memory 821 and stored as a quantum circuit definition. For example, a quantum circuit associated with a secondary quantum representation of Hamilton and a quantum circuit implementing a quantum bit switching network or other functions and processes or portions thereof of the application described above may be stored in a library. The classical computer 860 may be arranged to control a quantum computer or one or more quantum circuits thereof. The classical computer 860 may receive outputs from a classical or quantum computer. Based on the received outputs, the classical computer indicates which quantum circuits are to be used in subsequent quantum computations, provides definitions of suitable quantum circuits, or, in some cases, controls additional classical computations. The particular architecture depends on the number of qubits, as well as other design considerations. Thus, the switching network design module 863 may at least partially automate some of the design work to derive a switching network definition based on one or more design parameters and / or design criteria. Various embodiments of the classical computing device and / or classical computing environment may incorporate at least Fig. 9 Let's discuss.

[0153] refer to Figure 8, the compilation of quantum circuits can include the process of converting a high-level description of a quantum algorithm into a sequence of quantum circuits. Such a high-level description can be stored on one or more external computers 860 outside the quantum computing environment 800 using one or more memories and / or storage devices 862 as appropriate, and then downloaded into the computing environment 800 via one or more communication connections 850 when necessary. The high-level description can be stored and interpreted classically, and the classical computer can control the sequence of gates defined in the quantum computer. The high-level description also controls the application of gates based on initial data values, intermediate data values, or final data values. In one example, the memory and / or storage device 862 stores computer executable instructions for coefficient sorting and adjustment as described above. Such instructions can also be provided to the classical processor 810.

[0154] Classic computing devices

[0155] refer to Fig. 9 , the classical computing device 900 includes a bus 910 that directly or indirectly couples the following devices: a memory 912, one or more processors 914, one or more presentation components 916, one or more input / output (I / O) ports 918, one or more I / O components 920, and an illustrative power supply 922. As shown in conjunction with Figure 8 As discussed, the classical computing device 900 may be employed in Figure 8 The quantum computing environment 800 of FIG. 8 is shown in FIG. 8 . Bus 910 represents what may be one or more buses (such as an address bus, a data bus, or a combination thereof). Fig. 9 The various blocks of the present invention are shown with lines for clarity, but in reality these blocks represent logical and not necessarily actual components. For example, a display component such as a display device can be considered an I / O component. In addition, the processor has memory. The inventors herein recognize that such is the nature of the art and reiterate that Fig. 9 The diagrams are merely illustrative of exemplary computing devices that may be used in conjunction with one or more embodiments of the present disclosure. No distinction is made between categories such as "workstation," "server," "laptop," "handheld device," etc., as all are contemplated in the context of the present disclosure. Fig. 9 within the scope of and with reference to a “computing device”.

[0156] The computing device 900 generally includes various computer-readable media. Computer-readable media can be any available media that can be accessed by the computing device 900 and include both volatile media and non-volatile media, removable media and non-removable media. For example, but not limited to, computer-readable media may include computer storage media and communication media. Computer storage media include both volatile media and non-volatile media, removable media and non-removable media implemented in any method or technology for storing information such as computer-readable instructions, data structures, program modules or other data. Computer-readable media include but are not limited to RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital versatile disk (DVD) or other optical disk storage, cassettes, tapes, disk storage or other magnetic storage devices, or any other medium that can be used to store desired information and can be accessed by the computing device 900. Computer storage media do not include the signal itself. Communication media generally embody computer-readable instructions, data structures, program modules or other data in modulated data signals (such as carrier waves or other transmission media) and include any information delivery media. The term "modulated data signal" means a signal that has one or more of its characteristics set or changed in such a manner as to encode information in the signal. For example, but not limited to, communication media includes wired media (such as a wired network or direct-wired connection) and wireless networks (such as acoustic, RF, infrared and other wireless media). Combinations of any of the above should also be included within the scope of computer-readable media.

[0157] Memory 912 includes computer storage media in the form of volatile memory and / or non-volatile memory. The memory may be removable, non-removable, or a combination thereof. Exemplary hardware devices include solid-state memory, hard disk drives, optical disk drives, etc. Computing device 900 includes one or more processors 914 that read data from various entities such as memory 912 or I / O components 920. (Multiple) presentation components 916 present data indications to a user or other device. In some implementations, presentation component 220 of system 200 may be embodied as presentation component 916. Other examples of presentation components may include a display device, a speaker, a printing component, a vibration component, etc.

[0158] I / O port 918 allows computing device 900 to be logically coupled to other devices, including I / O components 920, some of which may be built-in. Illustrative components include microphones, joysticks, game controllers, satellite antennas, scanners, printers, wireless devices, etc. I / O components 920 may provide a natural user interface (NUI) for processing air gestures, voice, or other physiological inputs generated by a user. In some instances, the input may be sent to an appropriate network element for further processing. NUI may implement any combination of voice recognition, touch and stylus recognition, facial recognition, biometric recognition, gesture recognition on and adjacent to the screen, air gestures, head and eye tracking, and touch recognition associated with the display on computing device 900. Computing device 900 may be equipped with a depth camera, such as a stereoscopic vision camera system, an infrared camera system, an RGB camera system, and a combination of these, for gesture detection and recognition. In addition, computing device 900 may be equipped with an accelerometer or gyroscope for realizing detection of motion. The output of the accelerometer or gyroscope may be provided to the display of computing device 900 to present immersive augmented reality or virtual reality.

[0159] Some embodiments of the computing device 900 may include one or more radio devices 924 (or similar wireless communication components). The radio device 924 sends and receives radio or wireless communications. The computing device 900 may be a wireless terminal suitable for receiving communications and media over various wireless networks. The computing device 900 may communicate via wireless protocols such as code division multiple access ("CDMA"), global system for mobile ("GSM"), or time division multiple access ("TDMA"), among others, to communicate with other devices. The radio communications may be short-range connections, long-range connections, or a combination of both short-range wireless telecommunications connections and long-range wireless telecommunications connections. When we refer to "short" and "long" types of connections, we are not referring to the spatial relationship between two devices. Instead, we generally refer to short-range and long-range being different kinds or types of connections (i.e., primary and secondary connections). Short-range connections may include, for example, but are not limited to, connections to devices (e.g., mobile hotspots) or to wireless devices. A connection that provides access to a wireless communication network, such as a WLAN connection using the 802.11 protocol; a Bluetooth connection to another computing device is a second example of a short-range connection or near-field communication connection. Long-range connections may include connections using, for example, but not limited to, one or more of the CDMA, GPRS, GSM, TDMA, and 802.16 protocols.

[0160] Many different arrangements of the various components depicted, as well as components not shown, are possible without departing from the scope of the claims below. The embodiments of the present disclosure have been described with illustrative, rather than restrictive, intent. Alternative embodiments become apparent to the reader of the present disclosure after and as a result of reading the present disclosure. Alternative ways of implementing the foregoing may be accomplished without departing from the scope of the claims below. Certain features and subcombinations are practical and may be employed without citing other features and subcombinations and are contemplated to be within the scope of the claims.

Claims

1. Quantum computing hardware configured to execute a network of quantum gates that operates on a set of qubits to perform a method, wherein the set of qubits defines a plurality of 4-qubit combinations, the method comprising: Iteratively updating the order of the qubit sets via a plurality of qubit swap operations such that each 4-qubit combination in the plurality of 4-qubit combinations is represented as a consecutive 4-qubit grouping within the order of the qubit sets at least once during the plurality of swap operations to generate a plurality of consecutive 4-qubit groups.

2. The quantum computing hardware of claim 1, wherein the set of qubits further defines a plurality of 2-qubit combinations and the method further comprises: Iteratively updating the order of the qubit sets via a second plurality of qubit swap operations such that each 2-qubit combination in the plurality of 2-qubit combinations is represented as a consecutive 2-qubit grouping within the order of the qubit sets at least once during the second plurality of swap operations to generate a plurality of consecutive 2-qubit groups.

3. Quantum computing hardware according to claim 1, wherein each pair of qubits exchanged in each of the plurality of exchange operations is separated by at most three qubits within the order of the set of qubits.

4. The quantum computing hardware of claim 1, wherein the method further comprises: subdividing the set of qubits into a first qubit wheel, a second qubit wheel, a third qubit wheel, and a fourth qubit wheel such that the first qubit wheel comprises a first subset of the set of qubits, the second qubit wheel comprises a second subset of the set of qubits, the third qubit wheel comprises a third subset of the set of qubits, and the fourth qubit wheel comprises a fourth subset of the set of qubits, wherein the first qubit subset, the second qubit subset, the third qubit subset, and the fourth qubit subset are disjoint subsets; as well as performing a portion of the plurality of qubit swap operations to generate a portion of the plurality of consecutive 4-qubit packets, wherein each consecutive 4-qubit packet of the portion of the plurality of consecutive 4-qubit packets includes a first qubit from the first qubit subset, a second qubit from the second qubit subset, a third qubit from the third qubit subset, and a fourth qubit from the fourth qubit subset.

5. The quantum computing hardware of claim 4, wherein performing the portion of the plurality of qubit swap operations comprises: performing a plurality of third rounds of nearest neighbor qubit exchanges such that each qubit in the third subset of qubits is located at least once at each position in the third rounds; In response to performing a third round of nearest neighbor qubit exchanges in the plurality of third rounds of nearest neighbor qubit exchanges, performing a plurality of second rounds of nearest neighbor qubit exchanges such that each qubit in the second subset of qubits is located at least once at each position in the second round; as well as In response to performing a second round of nearest neighbor qubit exchanges in the plurality of second rounds of nearest neighbor qubit exchanges, performing a plurality of first rounds of nearest neighbor qubit exchanges such that each qubit in the first subset of qubits is located at least once at each position of the first rounds.

6. The quantum computing hardware of claim 1, wherein the method further comprises: subdividing the set of qubits into a first qubit wheel, a second qubit wheel, a third qubit wheel, and a fourth qubit wheel such that the first qubit wheel comprises a first subset of the set of qubits, the second qubit wheel comprises a second subset of the set of qubits, the third qubit wheel comprises a third subset of the set of qubits, and the fourth qubit wheel comprises a fourth subset of the set of qubits, wherein the first qubit subset, the second qubit subset, the third qubit subset, and the fourth qubit subset are disjoint subsets; iteratively updating the order of the set of qubits via a first portion of the plurality of qubit exchange operations to generate a vectorization of the set of qubits corresponding to an instance of a round of a quantum gate network and an instance of a 2-slot exchange network of the quantum gate network; and Using the instance of the 2-qubit exchange network and the instance of the 2-qubit time-slot exchange network and based on the vectorization of the set of qubits, a second portion of the plurality of qubit exchange operations is performed to generate a portion of the plurality of consecutive 4-qubit groups, wherein each consecutive 4-qubit group of the portion of the plurality of consecutive 4-qubit groups includes a first qubit from the first qubit subset, and a second qubit from the first qubit subset, a third qubit from the second qubit subset, and a fourth qubit from the second qubit subset.

7. The quantum computing hardware of claim 1, wherein the method further comprises: subdividing the set of qubits into a first qubit wheel, a second qubit wheel, a third qubit wheel, and a fourth qubit wheel such that the first qubit wheel comprises a first subset of the set of qubits, the second qubit wheel comprises a second subset of the set of qubits, the third qubit wheel comprises a third subset of the set of qubits, and the fourth qubit wheel comprises a fourth subset of the set of qubits, wherein the first qubit subset, the second qubit subset, the third qubit subset, and the fourth qubit subset are disjoint subsets; iteratively updating the order of the set of qubits via a first portion of the plurality of qubit swap operations to generate a vectorization of the set of qubits corresponding to an instance of a round swap network of the quantum gate network and an instance of a 3-qubit swap network of the quantum gate network; and Using the instance of the round exchange network and the instance of the 3-qubit exchange network and based on the vectorization of the set of qubits, a portion of the plurality of qubit exchange operations is performed to generate a portion of the plurality of consecutive 4-qubit groups, wherein each consecutive 4-qubit group of the portion of the plurality of consecutive 4-qubit groups includes a first qubit from the first qubit subset, a second qubit from the first qubit subset, a third qubit from the first qubit subset, and a fourth qubit from the second qubit subset.

8. The quantum computing hardware of claim 1, wherein the method further comprises: subdividing the set of qubits into a first qubit wheel, a second qubit wheel, a third qubit wheel, and a fourth qubit wheel such that the first qubit wheel comprises a first subset of the set of qubits, the second qubit wheel comprises a second subset of the set of qubits, the third qubit wheel comprises a third subset of the set of qubits, and the fourth qubit wheel comprises a fourth subset of the set of qubits, wherein the first qubit subset, the second qubit subset, the third qubit subset, and the fourth qubit subset are disjoint subsets; performing a portion of the plurality of qubit swap operations to generate a portion of the plurality of consecutive qubit packets, wherein each consecutive 4-qubit packet of the portion of the plurality of consecutive 4-qubit packets includes a first qubit from the first qubit subset, a second qubit from the first qubit subset, a third qubit from the first qubit subset, and a fourth qubit from the first qubit subset.

9. A quantum computing system comprising: a quantum register comprising a plurality of qubits defining a plurality of 4-qubit combinations; as well as Quantum hardware configured to execute a network of quantum gates that operates on a collection of quantum bits to perform a method comprising: Iteratively updating the order of the qubit sets via a plurality of qubit swap operations such that each 4-qubit combination in the plurality of 4-qubit combinations is represented as a consecutive 4-qubit grouping within the order of the qubit sets at least once during the plurality of swap operations to generate a plurality of consecutive 4-qubit groups.

10. The quantum computing system of claim 9, wherein the set of qubits further defines a plurality of 2-qubit combinations and the method further comprises: Iteratively updating the order of the qubit sets via a second plurality of qubit swap operations such that each 2-qubit combination in the plurality of 2-qubit combinations is represented as a consecutive 2-qubit grouping within the order of the qubit sets at least once during the second plurality of swap operations to generate a plurality of consecutive 2-qubit groups.

11. The quantum computing system of claim 9, wherein each pair of qubits exchanged in each of the plurality of exchange operations is separated by at most three qubits within the order of the set of qubits.

12. The quantum computing system of claim 9, wherein the method further comprises: subdividing the set of qubits into a first qubit wheel, a second qubit wheel, a third qubit wheel, and a fourth qubit wheel such that the first qubit wheel comprises a first subset of the set of qubits, the second qubit wheel comprises a second subset of the set of qubits, the third qubit wheel comprises a third subset of the set of qubits, and the fourth qubit wheel comprises a fourth subset of the set of qubits, wherein the first qubit subset, the second qubit subset, the third qubit subset, and the fourth qubit subset are disjoint subsets; as well as performing a portion of the plurality of qubit swap operations to generate a portion of the plurality of consecutive 4-qubit packets, wherein each consecutive 4-qubit packet of the portion of the plurality of consecutive 4-qubit packets includes a first qubit from the first qubit subset, a second qubit from the second qubit subset, a third qubit from the third qubit subset, and a fourth qubit from the fourth qubit subset.

13. The quantum computing system of claim 12, wherein performing the portion of the plurality of qubit swap operations comprises: performing a plurality of third rounds of nearest neighbor qubit exchanges such that each qubit in the third subset of qubits is located at least once at each position in the third rounds; In response to performing a third round of nearest neighbor qubit exchanges in the plurality of third rounds of nearest neighbor qubit exchanges, performing a plurality of second rounds of nearest neighbor qubit exchanges such that each qubit in the second subset of qubits is located at least once at each position in the second round; as well as In response to performing a second round of nearest neighbor qubit exchanges in the plurality of second rounds of nearest neighbor qubit exchanges, performing a plurality of first rounds of nearest neighbor qubit exchanges such that each qubit in the first subset of qubits is located at least once at each position of the first rounds.

14. The quantum computing system of claim 9, wherein the method further comprises: subdividing the set of qubits into a first qubit wheel, a second qubit wheel, a third qubit wheel, and a fourth qubit wheel such that the first qubit wheel comprises a first subset of the set of qubits, the second qubit wheel comprises a second subset of the set of qubits, the third qubit wheel comprises a third subset of the set of qubits, and the fourth qubit wheel comprises a fourth subset of the set of qubits, wherein the first qubit subset, the second qubit subset, the third qubit subset, and the fourth qubit subset are disjoint subsets; iteratively updating the order of the set of qubits via a first portion of the plurality of qubit exchange operations to generate a vectorization of the set of qubits corresponding to an instance of a round of the quantum gate network and an instance of a 2-slot exchange network of the quantum gate network; and Using the instance of the 2-qubit exchange network and the instance of the 2-qubit time-slot exchange network and based on the vectorization of the set of qubits, a second portion of the plurality of qubit exchange operations is performed to generate a portion of the plurality of consecutive 4-qubit groups, wherein each consecutive 4-qubit group of the portion of the plurality of consecutive 4-qubit groups includes a first qubit from the first qubit subset, and a second qubit from the first qubit subset, a third qubit from the second qubit subset, and a fourth qubit from the second qubit subset.

15. The quantum computing system of claim 9, wherein the method further comprises: subdividing the set of qubits into a first qubit wheel, a second qubit wheel, a third qubit wheel, and a fourth qubit wheel such that the first qubit wheel comprises a first subset of the set of qubits, the second qubit wheel comprises a second subset of the set of qubits, the third qubit wheel comprises a third subset of the set of qubits, and the fourth qubit wheel comprises a fourth subset of the set of qubits, wherein the first qubit subset, the second qubit subset, the third qubit subset, and the fourth qubit subset are disjoint subsets; iteratively updating the order of the set of qubits via a first portion of the plurality of qubit swap operations to generate a vectorization of the set of qubits corresponding to an instance of a round swap network of the quantum gate network and an instance of a 3-qubit swap network of the quantum gate network; and Using the instance of the round exchange network and the instance of the 3-qubit exchange network and based on the vectorization of the set of qubits, a portion of the plurality of qubit exchange operations is performed to generate a portion of the plurality of consecutive 4-qubit groups, wherein each consecutive 4-qubit group of the portion of the plurality of consecutive 4-qubit groups includes a first qubit from the first qubit subset, a second qubit from the first qubit subset, a third qubit from the first qubit subset, and a fourth qubit from the second qubit subset.

16. A method implemented by a quantum computing device, the quantum computing device being configured to execute a quantum gate network, the quantum gate network operating on a set of qubits to execute the method, the quantum computing device comprising a set of qubits, the set of qubits defining a plurality of 4-qubit combinations, the method comprising: Iteratively updating the order of the qubit sets via a plurality of qubit swap operations such that each 4-qubit combination in the plurality of 4-qubit combinations is represented as a consecutive 4-qubit grouping within the order of the qubit sets at least once during the plurality of swap operations to generate a plurality of consecutive 4-qubit groups.

17. The method of claim 16, wherein the set of qubits further defines a plurality of 2-qubit combinations and the method further comprises: Iteratively updating the order of the qubit sets via a second plurality of qubit swap operations such that each 2-qubit combination in the plurality of 2-qubit combinations is represented as a consecutive 2-qubit grouping within the order of the qubit sets at least once during the second plurality of swap operations to generate a plurality of consecutive 2-qubit groups.

18. The method according to claim 16, further comprising: subdividing the set of qubits into a first qubit wheel, a second qubit wheel, a third qubit wheel, and a fourth qubit wheel such that the first qubit wheel comprises a first subset of the set of qubits, the second qubit wheel comprises a second subset of the set of qubits, the third qubit wheel comprises a third subset of the set of qubits, and the fourth qubit wheel comprises a fourth subset of the set of qubits, wherein the first qubit subset, the second qubit subset, the third qubit subset, and the fourth qubit subset are disjoint subsets; as well as performing a portion of the plurality of qubit swap operations to generate a portion of the plurality of consecutive qubit packets, wherein each consecutive 4-qubit packet of the portion of the plurality of consecutive 4-qubit packets includes a first qubit from the first qubit subset, a second qubit from the second qubit subset, a third qubit from the third qubit subset, and a fourth qubit from the fourth qubit subset.

19. The method of claim 18, wherein performing the portion of the plurality of qubit swap operations comprises: performing a plurality of third rounds of nearest neighbor qubit exchanges such that each qubit in the third subset of qubits is located at least once at each position in the third rounds; In response to performing a third round of nearest neighbor qubit exchanges in the plurality of third rounds of nearest neighbor qubit exchanges, performing a plurality of second rounds of nearest neighbor qubit exchanges such that each qubit in the second subset of qubits is located at least once at each position in the second round; as well as In response to performing a second round of nearest neighbor qubit exchanges in the plurality of second rounds of nearest neighbor qubit exchanges, performing a plurality of first rounds of nearest neighbor qubit exchanges such that each qubit in the first subset of qubits is located at least once at each position of the first rounds.

20. The method of claim 16, further comprising: subdividing the set of qubits into a first qubit wheel, a second qubit wheel, a third qubit wheel, and a fourth qubit wheel such that the first qubit wheel comprises a first subset of the set of qubits, the second qubit wheel comprises a second subset of the set of qubits, the third qubit wheel comprises a third subset of the set of qubits, and the fourth qubit wheel comprises a fourth subset of the set of qubits, wherein the first qubit subset, the second qubit subset, the third qubit subset, and the fourth qubit subset are disjoint subsets; iteratively updating the order of the set of qubits via a first portion of the plurality of qubit exchange operations to generate a vectorization of the set of qubits corresponding to an instance of a round of a quantum gate network and an instance of a 2-slot exchange network of the quantum gate network; and Using the instance of the 2-qubit exchange network and the instance of the 2-qubit time-slot exchange network and based on the vectorization of the set of qubits, a second portion of the plurality of qubit exchange operations is performed to generate a portion of the plurality of consecutive 4-qubit groups, wherein each consecutive 4-qubit group of the portion of the plurality of consecutive 4-qubit groups includes a first qubit from the first qubit subset, and a second qubit from the first qubit subset, a third qubit from the second qubit subset, and a fourth qubit from the second qubit subset.

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