Memory device with split pillar architecture

Abstract

This application relates to a memory device with split pillar architecture. A memory device can include a substrate arranged with conductive contacts in a pattern and openings through alternating layers of conductive and insulating material, which can reduce the spacing between the openings while maintaining a dielectric thickness so that voltage continues to be applied to the array. After etching the material, insulating material can be deposited in the trenches. Portions of the insulating material can be removed to form openings in which cell material is deposited. Conductive pillars can extend perpendicular to the plane of the conductive material and the substrate, and are coupled to the conductive contacts. The conductive pillars and the cell material can be divided to form first and second storage components and first and second pillars.

Description

[0001] Cross-reference

[0002] The present patent application claims priority to PCT Application No. PCT / US2020 / 038354 to Fratin et al., titled “MEMORY DEVICE WITH A SPLIT PILLAR ARCHITECTURE,” filed June 18, 2020, which claims priority to U.S. Patent Application No. 16 / 460,884 to Fratin et al., titled “MEMORY DEVICE WITH A SPLIT PILLAR ARCHITECTURE,” filed July 2, 2019, each of which is assigned to the assignee hereof and the entirety of each of which is expressly incorporated herein by reference. TECHNICAL FIELD

[0003] The present technical field relates to a memory device with a split pillar architecture. BACKGROUND

[0004] Memory devices are widely used to store information in various electronic devices such as computers, wireless communication devices, cameras, digital displays, and the like. Information is stored by programming different states of the memory device. For example, binary devices most commonly store one of two states, typically represented by a logic 1 or a logic 0. In other devices, more than two states can be stored. To access stored information, a component of a device can read or sense at least one storage state in the memory device. To store information, a component of a device can write or program a state in the memory device.

[0005] There are a variety of types of memory devices, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase change memory (PCM), other chalcogenide-based memories, and the like. Memory devices can be volatile or non-volatile.

[0006] Generally, improvements in memory devices can include increasing memory cell density, increasing read / write speeds, improving reliability, increasing data retention, reducing power consumption, or reducing manufacturing costs, among other metrics. Solutions that use three-dimensional vertical architectures can be desirable to save space for memory arrays, increase memory cell density, or reduce total power usage for memory arrays. SUMMARY

[0007] A method is described. The method can include forming a trench through a first dielectric layer, a first conductive layer, and a second dielectric layer, the trench exposing a substrate and separating the first conductive layer into a first portion associated with a first word line driver and a second portion associated with a second word line driver; depositing an insulating material into the trench; forming a first opening over a contact in contact with the substrate by etching a portion of the insulating material; depositing a chalcogenide material in contact with the first portion of the first conductive layer, the first dielectric layer, and the second dielectric layer into the first opening; depositing a conductive material for forming a pillar in contact with the chalcogenide material and in contact with the substrate into the first opening; and forming a second opening through the chalcogenide material and the conductive material to separate the chalcogenide material into a first chalcogenide component and a second chalcogenide component and to separate the pillar into a first pillar and a second pillar.

[0008] An apparatus is described. The apparatus can include a set of contacts associated with a set of digit lines and extending through a substrate; a first set of word line plates separated from a second set of word line plates by a trench; a pair of pillars configured as digit lines and each configured to interact with the first set of word line plates and the second set of word line plates; a dielectric material positioned between a first pillar of the pair of pillars and a second pillar of the pair of pillars; and a set of storage elements comprising a chalcogenide material and in contact with the dielectric material, a word line plate of the first set of word line plates or the second set of word line plates, and a pillar of the pair of pillars.

[0009] Another apparatus is described. The apparatus can include a first word line plate in a first layer of a memory device; a second word line plate in the first layer of the memory device, the second word line plate separated from the first word line plate; a first digit line extending from the first layer to at least a second layer of the memory device; a second digit line separated from the first digit line and extending from the first layer to at least the second layer; a first storage element in contact with the first word line plate and the first digit line; a second storage element in contact with the first word line plate and the second digit line; a third storage element in contact with the second word line plate and the first digit line; and a fourth storage element in contact with the second word line plate and the second digit line. BRIEF DESCRIPTION OF DRAWINGS

[0010] Figure 1 Examples of supporting memory arrays of memory devices having split pillar architecture in accordance with the examples disclosed herein are described.

[0011] Figures 2A to 2CVarious views illustrating example memory arrays supporting memory devices having split pillar architecture in accordance with the examples disclosed herein are described.

[0012] Figures 3A to 3E Various views illustrating example memory arrays supporting memory devices having split pillar architecture in accordance with the examples disclosed herein are described.

[0013] Figures 4A to 4G Various views illustrating example memory arrays supporting memory devices having split pillar architecture in accordance with the examples disclosed herein are described.

[0014] Figures 5A to 5E Various views illustrating example memory arrays supporting memory devices having split pillar architecture in accordance with the examples disclosed herein are described.

[0015] Figure 6A and 6B Various views illustrating example memory arrays supporting memory devices having split pillar architecture in accordance with the examples disclosed herein are described.

[0016] Figure 7A and 7B Various views illustrating example memory arrays supporting memory devices having split pillar architecture in accordance with the examples disclosed herein are described.

[0017] Figures 8 to 11 Flowcharts illustrating one or more methods supporting memory devices having split pillar architecture in accordance with the examples disclosed herein are shown. DETAILED DESCRIPTION

[0018] The present disclosure relates to a memory device having a split pillar architecture and processing methods thereof. The memory device can include an arrangement of conductive contacts and openings through alternating layers of conductive material and insulating material, which can reduce spacing between memory cells while maintaining dielectric thickness for voltage to be continuously applied to a memory array of the memory device.

[0019] In some examples, a memory device can include a substrate having a plurality of contacts arranged in a pattern (e.g., a geometric pattern) and a first insulating material (e.g., a dielectric material) formed on the substrate. A plurality of planes of conductive material can be separated from each other by a second insulating material (e.g., a dielectric material) and formed on the substrate material. The planes of conductive material can be examples of word lines.

[0020] During fabrication of a memory device, odd and even digit line planes can be separated to create shape formation trenches in a "comb-like" structure (e.g., a structure that looks like a tool with fingers and spaces between the fingers). The trenches can be in any geometric configuration and include odd and even groups of fingers of a comb facing each other at a fixed distance. In some examples, the trenches can be formed in a serpentine shape. The trenches can divide each plane of conductive material into two sections or two plates. Each plate of conductive material can be an example of a word line plate. In some examples, inside the trenches, the plane of conductive material can be etched in a way that a dielectric material and conductive material form a plurality of grooves, where each groove can be configured to receive a storage element material (e.g., a chalcogenide material). A sacrificial layer (e.g., a conformal material) can be deposited in the trenches and, in some cases, the sacrificial layer fills the grooves. An insulating material can be deposited in the trenches on top of the sacrificial layer. The sacrificial layer and the insulating layer can form a serpentine shape. In some examples, other geometric configurations of the trenches can be considered.

[0021] Portions of the sacrificial layer and the insulating material can be removed to form first openings. The first openings can expose portions of the substrate, the plurality of conductive contacts, and portions of the conductive material and the dielectric material. A storage element material (e.g., a chalcogenide material) can be deposited in the first openings. The storage element material can fill the grooves formed by the dielectric material and the conductive material. The storage element material can be removed from portions of the first openings, such that the storage element material in the grooves remains.

[0022] Conductive pillars can be formed in the first openings including the storage element material in the grooves. The conductive pillars can be examples of digit lines. The conductive pillars can be arranged to extend (e.g., substantially perpendicular) to the plane of the conductive material and the substrate. Each conductive pillar can be coupled with a different conductive contact. The pillars can be formed of a barrier material and a conductive material.

[0023] Portions of the storage element material and the conductive pillars can be removed to form second openings. The second openings can divide each storage element material in the grooves into a first storage element component and a second storage element component. The second openings can further divide each pillar into a first pillar and a second pillar. In some cases, each of the first and second pillars can be coupled with a different conductive contact on the substrate. In some other cases, each of the first pillars can be coupled with a different conductive contact on the substrate and each of the second pillars can be coupled with a different conductive contact on a second substrate formed above the first substrate.

[0024] Such configurations of memory arrays and fabrication methods can allow for increased memory cell density relative to previous solutions. Each memory cell (e.g., storage element material) can be recessed inside opposite sides of a first pillar or a second pillar to ensure cell isolation. This configuration can allow for tighter control of cell thickness and size relative to some previous solutions. Each plane of conductive material intersecting a conductive pillar can form two memory cells addressed by a first word line plate in the plane and a second word line plate in the plane. Each first and second pillar pair can form two memory cells addressed by the first and second pillars, respectively. Each pillar can be decoded by a transistor located at a bottom or a top of the memory array. The transistors can be examples of digit line selectors formed in a regular matrix.

[0025] Features of the disclosure are first described in the context of a memory array described with reference to Figure 1 Features of the disclosure are described in the context of different views of an example memory array during the process steps described with reference to Figures 2A to 7B Features of the disclosure are described in the context of different views of an example memory array during the process steps described with reference to Figures 8 to 11 These and other features of the disclosure are further illustrated and described with reference to a flowchart described with reference to

[0026] Figure 1 An example of a memory array 100 (e.g., a three-dimensional (3D) memory array) supporting a memory device having a split pillar architecture is illustrated in accordance with examples disclosed herein. The memory array 100 can include a first array or deck 105 of memory cells positioned above a substrate 104 and a second array or deck 108 of memory cells on top of the first array or deck 105.

[0027] The memory array 100 can include word lines 110 and digit lines 115. The memory cells of the first deck 105 and the second deck 108 can each have one or more self-selecting memory cells. Although Figure 1 Some elements included in the figures can be labeled with a digital identifier, other corresponding elements are not labeled with a digital identifier but are identical to or understood to be similar to the labeled element. Dashed lines shall indicate no limitation, dashed-and dotted lines shall indicate optional elements, lines created with dashes and dashes-dotted lines shall indicate one of

[0028] The stack of memory cells can include a first dielectric material 120, a storage element material 125 (e.g., a chalcogenide material), a second dielectric material 130, a storage element material 135 (e.g., a chalcogenide material), and a third dielectric material 140. In some examples, the self-selecting memory cells of the first deck 105 and the second deck 108 can have a common wire such that corresponding self-selecting memory cells of each deck 105 and 108 can share a digit line 115 or a word line 110.

[0029] In some examples, a memory cell can be programmed by providing an electrical pulse to the memory cell, which can include a memory storage element. The pulse can be provided via a first access line (e.g., word line 110) or a second access line (e.g., digit line 115), or a combination thereof. In some cases, after the pulse is provided, ions can migrate within the memory storage element, which depends on the polarity of the memory cell. Thus, the ion concentration with respect to a first side or a second side of the memory storage element can be based at least in part on the polarity of the voltage between the first access line and the second access line. In some cases, asymmetrically shaped memory storage elements can cause ions to be more concentrated at portions of the element having a greater area. Certain portions of the memory storage element can have a higher resistivity than other portions of the memory storage element and this can result in a higher threshold voltage than other portions of the memory storage element. This description of ion migration represents an example of a mechanism of a self-selecting memory cell for achieving the results described herein. This example of a mechanism should not be considered limiting. The present disclosure also includes other examples of mechanisms of a self-selecting memory cell for achieving the results described herein.

[0030] In some cases, the architecture of memory array 100 can be referred to as a cross-point architecture, where memory cells are formed at topological cross-points between word lines 110 and digit lines 115. This cross-point architecture can provide relatively high density data storage at lower production cost than other memory architectures. For example, a cross-point architecture can include memory cells having a reduced area, and thus an increased memory cell density, than other architectures.

[0031] Although Figure 1 Examples of memory array 100 show two memory decks 105 and 108, but other configurations are possible. In some examples, a single memory deck of self-selecting memory cells can be constructed over substrate 104, which can be referred to as two-dimensional memory. In some examples, three or four memory decks of memory cells can be configured in a similar manner in a three-dimensional cross-point architecture.

[0032] Memory array 100 can include substrate 104 having a plurality of contacts arranged in a grid or interlaced pattern. In some cases, the plurality of contacts can extend through the substrate to be coupled with access lines of memory array 100. Memory array 100 can include additional substrates 104 (e.g., positioned above two decks 105 and 108). The additional substrates 104 can have a plurality of contacts (e.g., extending through the substrate) and be coupled with access lines of memory array 100.

[0033] The memory array 100 can include a plurality of planes of conductive material separated from one another by a second insulative material formed over a first insulative material on a substrate material. Each of the plurality of planes of conductive material can include a plurality of recesses formed therein. The plurality of planes (e.g., corresponding to a word line plate of one or more word lines 110 on a same tier (e.g., memory tier 105, memory tier 108)) can be obtained by a replacement process by using a sacrificial layer (e.g., conformal layer) etched during a stack deposition process step, removing the conformal layer after cell definition, and replacing the conformal layer with a more conductive material.

[0034] The insulative material can form a serpentine shape through the second insulative material and the conductive material. A plurality of conductive pillars can be formed in the openings to extend substantially perpendicular to the plurality of planes of conductive material and the substrate. The plurality of conductive pillars can be divided into a plurality of pairs of pillars. Each pillar in a pair of pillars can be coupled to a different one of the conductive contacts. In some cases, each pillar in a pair of pillars can be coupled to a conductive contact on the substrate 104. Additionally or alternatively, one pillar in each pair of pillars can be coupled to a conductive contact on the substrate 104 and the other pillar of each pair of pillars can be coupled to a conductive contact on a different substrate 104 (e.g., positioned above memory tiers 105 and 108).

[0035] In some examples, the memory tiers 105 and 108 can include a chalcogenide material configured to store a logic state. For example, the memory cells of the memory tiers 105 and 108 can be examples of self-selecting memory cells. The chalcogenide material can be formed in the plurality of recesses such that the chalcogenide material in each respective one of the plurality of recesses is at least partially in contact with one pillar of the plurality of pairs of pillars.

[0036] Figure 2A A bottom view of an example memory array 200-a is illustrated in accordance with the examples disclosed herein. The memory array 200-a can include a plurality of conductive contacts 235 formed in a substrate 104-a that extend through the substrate 104-a to couple with the access lines of the memory array 100. The substrate 104 can be a dielectric material, such as a dielectric film.

[0037] Individual conductive contacts of the plurality of conductive contacts 235 can be configured to couple any individual vertical pillar with a transistor. For example, conductive contact 235-a can couple a first pillar of a pair of pillars (e.g., corresponding to a digit line) to a transistor and conductive contact 235-b can couple a second pillar of the pair of pillars to the transistor. Conductive contacts 235-c and 235-d can each couple one of a second pair of pillars to the transistor. The plurality of conductive contacts 235 can be arranged in a grid pattern. In some examples, respective ones of the plurality of conductive contacts 235 can be surrounded by up to eight other conductive contacts 235. In some examples, the plurality of conductive contacts 235 can be arranged in a staggered pattern or a hexagonal pattern. For example, respective ones of the plurality of conductive contacts 235 can be surrounded by up to six other conductive contacts 235.

[0038] Figure 2B A bottom view of an example memory array 200-b according to the examples disclosed herein is illustrated. The memory array 200-b can include a second substrate 104 positioned on a top of the memory array 200-b. For example, the second substrate 104 can be positioned on opposite sides of one or more memory decks of the memory array 200-b. Each substrate (e.g., substrate 104-b and the second substrate) can include a plurality of conductive contacts 235 formed in the substrate 104-b that extend through the substrate 104 to couple with access lines of the memory array 100.

[0039] Individual conductive contacts of the plurality of conductive contacts 235 can be configured to couple any individual vertical pillar with a transistor. For example, conductive contact 235-e can couple a first pillar of a pair of pillars (e.g., corresponding to a digit line) to a transistor. A second conductive contact on the second substrate can couple a second pillar of the pair of pillars to the transistor. Conductive contacts 235-f and a fourth conductive contact on the second substrate can each couple one of a second pair of pillars to the transistor. The plurality of conductive contacts 235 can be arranged in a grid pattern. In some examples, respective ones of the plurality of conductive contacts 235 can be surrounded by up to eight other conductive contacts 235. In some examples, the plurality of conductive contacts 235 can be arranged in a staggered pattern or a hexagonal pattern. For example, respective ones of the plurality of conductive contacts 235 can be surrounded by up to six other conductive contacts 235.

[0040] Figure 2CA side view of an example memory array 200-c according to the examples disclosed herein is illustrated. The memory array 200-c can include a plurality of conductive contacts 235 that can be formed in a substrate 104-c. The memory array 200-c can also include a plurality of stacked planes of insulating material 240 and a plurality of stacked planes of material 245 (e.g., word line planes or word line plates). The stacked planes of material 245 can be separated (e.g., vertically separated) from one another in the z-direction by the plurality of planes of insulating material 240. For example, a first plane (e.g., a bottom plane) of second insulating material 240 can be formed (e.g., deposited) on a plane of substrate 104-c, and then a plane of material 245 can be formed on the first plane of second insulating material 240. In some examples, a layer of first insulating material 240 can be deposited on substrate 104-c. In some examples, material 245 can be a conductive carbon layer or other conductive layer that is compatible with an active material. In some examples, material 245 can include a conductive layer separated by a protective barrier from an active material. Material 245 can be configured to function as at least one word line plate. In some other examples, material 245 can include a second insulating material (e.g., different from insulating material 240). In some examples, material 245 and insulating material 240 form a plurality of layers, such as alternating layers.

[0041] Additional planes of second insulating material 240 can be formed on material 245 in an alternating manner, as illustrated in Figure 2C Second insulating material 240 can be a dielectric material, such as a dielectric film or layer. In some examples, second insulating material 240 and substrate 104-c can be the same type of insulating material. Examples of insulating materials disclosed herein include, but are not limited to, dielectric materials, such as silicon oxide.

[0042] Each respective one of the plurality of planes of material 245 can be at (e.g., form) a different level of memory array 200-c. An individual plane of material that forms a memory cell can be referred to as a tier of 3D memory array 200-b. In some instances, material 245 can be a conductive material. Here, material 245 can include (e.g., be formed of) a metallic (or semi-metallic) material or a semiconductor material (e.g., a doped polysilicon material). In some examples, material 245 can be a plane of conductive carbon. In some other instances, material 245 can be a sacrificial insulating material. Here, memory array 200-c can include a set of stacked planes of sacrificial insulating material 245 and a set of stacked planes of insulating material 240. Sacrificial insulating material 245 can be a different material than insulating material 240 (e.g., an oxide material and a nitride material, respectively). In Figure 2CDuring process steps subsequent to those illustrated in FIG. 5, the sacrificial insulative material 245 can be removed and replaced with an electrically conductive material (e.g., an electrically conductive carbon layer or other electrically conductive layer compatible with the active material).

[0043] Figure 2C Six planes of material 245 and seven planes of second insulative material 240 are shown in FIG. 6. The seventh plane of second insulative material 240 can be the uppermost layer of memory array 200-c. The number of planes of material 245 and second insulative material 240 is not limited to Figure 2C the numbers illustrated in FIG. 6. Material 245 and second insulative material 240 can be arranged in more than six tiers or less than six tiers.

[0044] Figures 3A to 3E Various views of example memory arrays 200-c, 200-d, 200-e, and 200-f during a series of steps or processes that can be performed to form a stacked memory device in accordance with the examples disclosed herein are illustrated. Specifically, Figures 3A to 3E processes to form even and odd digit line planes are shown.

[0045] Figure 3A A top view of example memory array 200-c is illustrated, which can be subsequent to Figure 2C the example memory array 200-b illustrated in FIG. 5. Figure 3B A top view of example memory array 200-c is illustrated, which can be subsequent to Figure 3A the example memory array 200-b illustrated in FIG. 5. Figure 3C A cross-sectional view of example memory array 200-d along cross-sectional line A-A’ during process steps subsequent to those illustrated in FIG. 6 is illustrated. Figure 3B A cross-sectional view of example memory array 200-e along cross-sectional line A-A’ during process steps subsequent to those illustrated in FIG. 6 is illustrated. Figure 3D A cross-sectional view of example memory array 200-e along cross-sectional line A-A’ during process steps subsequent to those illustrated in FIG. 6 is illustrated. Figure 3C A cross-sectional view of example 3D memory array 200-f along cross-sectional line A-A’ during process steps subsequent to those illustrated in FIG. 6 is illustrated. Figure 3E A cross-sectional view of example 3D memory array 200-f along cross-sectional line A-A’ during process steps subsequent to those illustrated in FIG. 6 is illustrated. Figure 3C A top view of example 3D memory array 200-f along cross-sectional line B-B’ during process steps subsequent to those illustrated in FIG. 6 is illustrated. Figures 3A to 3E A series of steps or processes that can be performed to form a stacked memory device is illustrated.

[0046] Figure 3A A cross-sectional view of material 245 (e.g., an electrically conductive material, an insulative material) and second insulative material 240 (e.g., an insulative material) through memory array 200-c is illustrated in FIG. 7. Figure 3B A cross-sectional view of material 245 (e.g., an electrically conductive material, an insulative material) and second insulative material 240 (e.g., an insulative material) through memory array 200-c is illustrated in FIG. 7. Figure 3BThe alternating planes (shown in FIG. 3B) form trenches 350. The trenches 350 can expose the substrate 104 and the conductive contacts 235 (as previously shown in FIG. 3A) at the bottom of the trenches 350. Figures 2A to 2C

[0047] The trenches 350 can be etched from top to bottom and in a serpentine shape. For example, the trenches 350 can pass through a row of conductive contacts 235 in a first direction (e.g., from left to right) and then pass through an adjacent column of conductive contacts 235 in a second direction opposite the first direction (e.g., from right to left). With reference to the example of FIG. 3B, the trenches 350 pass from left to right through a first row of conductive contacts 235, then "turn" to pass from right to left through a next (second) row of conductive contacts 235 (adjacent to the first row). The trenches 350 again "turn" to pass from left to right through a next (third) row of conductive contacts 235 (adjacent to the second row). The trenches 350 again "turn" to pass from right to left through a next (fourth) row of conductive contacts 235 (adjacent to the third row) and then again "turn" to pass from left to right through a next (fifth) row of conductive contacts 235 (adjacent to the fourth row) at the bottom of the trenches 350. Figure 3A Figure 3A

[0048] The trenches 350 can bifurcate each plane of material 245 into at least two portions: a first portion 308 and a second portion 309. Each portion of a plane of material 245 can be a different access line (e.g., an even or odd digit line) of a deck. For example, the first portion 308 can be a first access line of a deck of the 3D memory array 200-c and the second portion 309 can be a second access line of the same deck of the 3D memory array 200-c. The extension of the fingers forming the even or odd planes can be defined based on the resistivity of the electrodes used and by the requested current delivery level. Specifically, the depth of the grooves can be defined depending on the thickness desired for the memory cells. In some cases, the material 245 can be a conductive material for different access lines. Additionally or alternatively, the material 245 can be a sacrificial insulating material that can be replaced by a conductive material for different access lines during process steps following the process steps described in FIG. 3B. Figure 3A

[0049] Figure 3B ​​​​A plurality of recesses 315 are formed in the material 245 in each of the planes of the memory array 200-d. For example, a selective etching operation can be performed in an isotropic manner to form the plurality of recesses 315 in the sidewalls 390 and 391 of the trench 350. In some examples, the trench 350 includes a first sidewall 390 spaced apart from a second sidewall 391, where a first portion 392 of the first sidewall 390 formed from the first insulating material 240 is spaced apart from a first portion 393 of the second sidewall 391 formed from the first insulating material 240 by a first distance. A second portion of the first sidewall 390 formed from the first material 245 can be spaced apart from a second portion of the second sidewall 391 formed from the first material 245 by a second distance that is greater than the first distance. In some examples, portions of the sidewalls 390 and 391 of the trench 350 formed from the first material 245 are recessed relative to portions of the sidewalls 390 and 391 of the trench 350 formed from the first insulating material 240.

[0050] The etching operation can include one or more vertical etching processes (e.g., anisotropic etching processes or dry etching processes or a combination thereof) or horizontal etching processes (e.g., isotropic etching processes) or a combination thereof. For example, a vertical etching process can be performed to vertically etch the trench 350, and a horizontal etching process can be used to form the at least one recess 315 in the at least one material 245. The etching parameters can be selected such that the material 245 is etched faster than, for example, the second insulating material 240. In some cases, the trench 350 can be vertical. In some other cases, the trench 350 can include sloped sidewalls (e.g., substantially vertical). For example, the trench 350 can be a V-shaped trench such that the trench 350 is wider at a top portion of the trench 350 than a bottom portion of the trench 350. Here, the sidewalls 390 and 391 can be more spaced apart from each other than the bottom walls 394 and 395.

[0051] Figure 3C A conformal material 320 (e.g., a sacrificial material or a sacrificial layer) is formed. The conformal material 320 can be deposited into the trench 350 of the memory array 200-e. The conformal material 320 can be formed in the recesses 315 by conformally depositing the conformal material 320 as Figure 3B The conformal material 320 contacts the first sidewall 390, the second sidewall 391, and the bottom wall 395 of each trench 350. Although Figure 3C Although it is shown that the conformal material 320 can be formed on the sidewalls of the trench 350 (e.g., on the surfaces of the second insulating material 240 and the material 245 in different layers facing the trench 350) during the formation of the conformal material 320 in the plurality of recesses 315, examples are not limited thereto. For example, in some cases, the conformal material 320 can be confined to the plurality of recesses 315 in the material 245 in different layers. In some cases, the conformal material 320 can be referred to as a conformal layer or a sacrificial layer.

[0052] In some cases, an etching operation can be performed after forming the conformal material 320. In the etching operation, the conformal material 320 can be etched to form an opening or trench 350. The etching operation can result in a surface of the conformal material 320 (e.g., a surface facing the trench 350) being spaced apart from a surface of the second insulating material 240 (e.g., a surface facing the trench 350). In some cases, the etching operation can result in a surface of the conformal material 320 (e.g., a surface facing the trench 350) being substantially coplanar with a surface of the second insulating material 240 (e.g., a surface facing the trench 350), and thereby forming a continuous sidewall of the trench. The etching operation described herein can be a vertical etching process (e.g., an anisotropic etching process, or a dry etching process, or a combination thereof) or a horizontal etching process (e.g., an isotropic etching process). For example, a vertical etching process can be performed to vertically etch the trench 350, and a horizontal etching process can be used to form at least one recess in the first material 245.

[0053] Figure 3D Deposition of a dielectric material 318 in the trench 350 on top of the conformal material 320 of the memory array 200-f is illustrated. The dielectric material 318 can contact the conformal material 320. The dielectric material 318 and the conformal material 320 can together fill the trench 350. In some cases, the dielectric material 318 can be an example of an insulating material. In some examples, the conformal material 320 can be selectively etched back to form a surface that is coplanar with the dielectric material 318. The depth of the recess can be defined depending on the desired thickness.

[0054] Figure 3E A top-down view of an example memory array 200-f after deposition of a dielectric material 318 (as shown in Figure 3D is illustrated. Figure 3E A cross-sectional view of the memory array 200-f along the cross-sectional line B-B’ illustrated in Figure 3D is illustrated. Figure 3E In

[0055] Figures 4A to 4G Various views of example memory arrays 200-g, 200-h, 200-i, 200-j, and 200-k during a series of steps or processes that can be performed to form a stacked memory device according to examples disclosed herein are illustrated. Specifically, Figures 4A to 4G A process for forming Figure 3D and 3E memory cells in the memory array 200-f illustrated in is illustrated.

[0056] Figure 4A A top view of the memory array 200-g is illustrated, which can be after forming openings 360 Figure 3E The example memory array 200-f illustrated in FIG. 2F. Figure 4B A cross-sectional view of an example memory array 200-g along section line A-A' during a process step after the process steps illustrated in Figure 4A A cross-sectional view of an example memory array 200-h along section line A-A' during a process step after the process steps illustrated in Figure 4C A cross-sectional view of an example memory array 200-i along section line A-A' during a process step after the process steps illustrated in Figure 4B A cross-sectional view of an example memory array 200-i along section line A-A' during a process step after the process steps illustrated in Figure 4D A cross-sectional view of an example memory array 200-j along section line A-A' during a process step after the process steps illustrated in Figure 4C A cross-sectional view of an example memory array 200-j along section line A-A' during a process step after the process steps illustrated in Figure 4E A top view of an example memory array 200-j along section line B-B' during a process step after the process steps illustrated in Figure 4C A top view of an example memory array 200-k along section line B-B' during a process step after the process steps illustrated in Figure 4F A top view of an example memory array 200-k along section line B-B' during a process step after the process steps illustrated in Figure 4E A top view of an example memory array 200-l along section line B-B' during a process step after the process steps illustrated in Figure 4G A top view of an example memory array 200-l along section line B-B' during a process step after the process steps illustrated in Figure 4F A top view of an example memory array 200-l along section line B-B' during a process step after the process steps illustrated in

[0057] Figure 4A A top view of an example memory array 200-g is illustrated. A plurality of openings 360 can be formed by etching away a portion of the dielectric material 318 and / or the conformal material 320. The openings 360 are desirably positioned in alignment with the plurality of conductive contacts 235, such that forming the openings 360 exposes at least a portion of the plurality of conductive contacts 235 (as shown in FIG. 2G) extending through the substrate 104 (as shown in FIG. 2H). Figure 4B A top view of an example memory array 200-g is illustrated. A plurality of openings 360 can be formed by etching away a portion of the dielectric material 318 and / or the conformal material 320. The openings 360 are desirably positioned in alignment with the plurality of conductive contacts 235, such that forming the openings 360 exposes at least a portion of the plurality of conductive contacts 235 (as shown in FIG. 2G) extending through the substrate 104 (as shown in FIG. 2H). Figure 4B The etching process can be a vertical etching process. In some examples, the etching operation can not etch away all portions of the conformal material 320, for example, at locations where the plurality of openings 360 are not formed.

[0058] Figure 4B A cross-sectional view of an example memory array 200-h is illustrated in accordance with the examples disclosed herein. As Figure 4BAs shown in the middle, a plurality of recesses 315 can be formed in the material 245 in each of the planes. For example, a selective etching operation can be performed to form the plurality of recesses 315 in a fully or partially isotropic manner. The etching chemistry can be selected to selectively reach the material 245. The conductive contacts 235 can be exposed by forming openings 360 in the trenches 350.

[0059] Figure 4C A cross-sectional view of an example memory array 200-i is illustrated in accordance with the examples disclosed herein. As shown in the left side of the figure, a plurality of recesses 315 can be formed in the material 245 in each of the planes. For example, a selective etching operation can be performed to form the plurality of recesses 315 in a fully or partially isotropic manner. The etching chemistry can be selected to selectively reach the material 245. The conductive contacts 235 can be exposed by forming openings 360 in the trenches 350. Figure 4C As shown in the middle, the storage element material 465 in the plurality of recesses 315 can be formed by conformally depositing the storage element material 465 into the trenches 350. The storage element material 465 can be deposited to contact the sidewalls 390 and 391 and the bottom wall 395 of the trenches 350 exposed by the etching of the conformal material 320. When the storage element material 465 contacts the bottom wall 395 of the trenches 350, the storage element material 465 covers the exposed conductive contacts 235.

[0060] The dimensions of the storage element material 465 can be based on the dimensions of other components of the memory array 200-i. For example, the height of the storage element material 465 can be controlled by depositing thicker or thinner layers of the material 245 and / or the insulating material 240. In another example, the depth of the storage element material 465 can be controlled by etching longer or shorter recesses (e.g., refer to recesses 315 described below). By controlling the dimensions of the other components of the memory array 200-i, the dimensions of the storage element material 465 can be controlled according to the desired dimensions of the memory cells associated with the memory array 200-i. Figure 4B The dimensions of the storage element material 465 can be based on the dimensions of other components of the memory array 200-i. For example, the height of the storage element material 465 can be controlled by depositing thicker or thinner layers of the material 245 and / or the insulating material 240. In another example, the depth of the storage element material 465 can be controlled by etching longer or shorter recesses (e.g., refer to recesses 315 described below). By controlling the dimensions of the other components of the memory array 200-i, the dimensions of the storage element material 465 can be controlled according to the desired dimensions of the memory cells associated with the memory array 200-i.

[0061] The storage element material 465 can be an example of a chalcogenide material (e.g., a chalcogenide alloy and / or glass) that can be used as a self-selecting storage element material (e.g., a material that can be used as both a selection device and a storage element). For example, the storage element material 465 can be responsive to an applied voltage (e.g., a programming pulse). For applied voltages less than a threshold voltage, the storage element material 465 can remain in a non-conductive state (e.g., an "off" state). Alternatively, in response to an applied voltage greater than the threshold voltage, the storage element material 465 can enter a conductive state (e.g., an "on" state).

[0062] Figure 4D A cross-sectional view of an example memory array 200-j is illustrated in accordance with the examples disclosed herein. An etching operation can be performed after forming the storage element material 465 such that a surface of the storage element material 465 (e.g., a surface facing the trenches 350) is substantially coplanar with a surface of the second insulating material 240 (e.g., a surface facing the trenches 350), as shown in the middle of the figure. Figure 4DAs explained in the text. Etching the memory element material 465 can form continuous sidewalls and remove the top layer 466 of the memory element material 465 (e.g., ...). Figure 4C (As shown in the diagram), thereby forming cells of storage element material 465 in the grooves. In each groove, each cell of storage element material 465 may contact a single material 245 (e.g., a single material 245 positioned adjacent to a cell of storage element material 465) and at least two dielectric layers (e.g., a top dielectric layer and a bottom dielectric layer positioned on the top and bottom of a cell of storage element material 465), as shown in the diagram. Figure 4D As shown in the diagram. Etching the memory element material 465 can provide a configuration in which the memory element materials 465 are separated from each other. Etching the memory element material 465 can also expose the conductive contacts 235 in the substrate 104. In some instances, portions of the sacrificial material can be located on either side of the cells of the memory element material 465 (e.g., Figure 4E (As shown in the image).

[0063] Figure 4E This describes a top view of instance memory array 200-j, based on the examples disclosed herein. (See attached image.) Figure 4E As explained, the conformal material 320 and the storage element material 465 formed in the groove 350 can bifurcate each plane of the material 245 into a first portion 308 and a second portion 309. Each portion of the plane can be an example of a word line board.

[0064] Figure 4F This describes a top view of the instance memory array 200-k based on the examples disclosed herein. (See attached image.) Figure 4F As shown, barrier material 470 is deposited into opening 360. In some embodiments, barrier material 470 contacts at least a portion of first insulating material 240, second insulating material 240, and storage element material 465, such as... Figure 4D As shown in the diagram. In some instances, the barrier material 470 is compatible with the active material. The barrier material 470 can be a conductive material (e.g., a conformal conductive material) or a barrier layer having a conductive material. For example, the barrier material 470 can comprise aluminum oxide. In some instances, an etching operation can be performed to create space in the trench 350 to deposit conductive material. In some cases, the barrier material 470 can be referred to as a barrier layer.

[0065] Material 475 can be deposited in the opening 360 to form a conductive pillar. Although Figure 4FMaterial 475 is illustrated as a dielectric material, but material 475 can be a metallic (or semi-metallic) material or a semiconductor material (e.g., doped polysilicon material, etc.). However, other metallic, semi-metallic, or semiconductor materials (metallic materials or dielectric materials) can be used. In some cases, the pillars can be partially filled with a metallic material and then filled with a dielectric material. In some cases, barrier material 470 can be the same material as material 475. For example, barrier material 470 and material 475 can correspond to conductive pillars that include a uniform conductive material.

[0066] The conductive pillars can include barrier material 470 and material 475. In some examples, the conductive pillars can be formed in contact with storage element material 465 on sidewalls 390 and 391 of trench 350 (as shown in Figure 4C The conductive pillars can be cylindrical. Although Figure 4F The conductive pillars are illustrated as solid pillars, but in some examples, the conductive pillars can be hollow cylinders or in the shape of a ring (e.g., a tube).

[0067] The conductive pillars formed in each respective one of the plurality of openings 360 are arranged to extend substantially orthogonal to alternating planes of material 245 and second insulative material 240, as shown in Figure 4D The storage element material 465 and the conductive pillars formed in each respective one of the plurality of openings 360 are formed in a substantially square shape. Examples of the present disclosure are not limited to precise or quasi-precise square shapes. For example, the storage element material 465 and the conductive pillars can be formed in any shape including, for example, a circular or elliptical shape.

[0068] Figure 4G A top view of example memory array 200-1 according to examples disclosed herein is illustrated. A plurality of second openings 490 in trench 350 can be formed by etching away a portion of material 475, barrier material 470, and storage element material 465.

[0069] The etching process can expose one or more surfaces of material 245 (e.g., corresponding to a word line plate) and insulative material 240. Reference is made to Figure 4B to illustrate and describe example diagrams showing details regarding the relationship between material 245 and insulative material 240 after the etching process. In some cases, the etching process can expose portions of the recesses filled by storage element material 465. The etching process can include a vertical etching process that occurs substantially orthogonal to alternating planes of material 245 and second insulative material 240, as shown in Figure 4DThe etch process can include a first dry etch process that etches a first portion of the material 475 (e.g., a portion of the material 475 that includes a dielectric material). The etch process can then include a selective wet etch process that etches a second portion of the material 475 (e.g., a portion of the material 475 that includes a conformal metal material). The etch process can further include a selective etch process of the storage element material 465 inside each of the plurality of recesses.

[0070] The etch process can separate the conductive pillar into a pair of pillars 485. In some examples, each pillar 485 of the pair of pillars can be a digit line. The etch process can separate each storage element material 465 into a pair of storage element assemblies 480. Thus, each recess can include a first storage element assembly 480 coupled with a first pillar 485 and a second storage element assembly 480 coupled with a second pillar 485. Each storage element assembly 480 can be coupled to a pillar 485 (e.g., of a pair of pillars 485) and an even or odd access line (e.g., the first portion 308 can be a first access line and the second portion 309 can be a second access line). Thus, each storage element assembly 480 can be individually addressed (e.g., by applying a voltage to an access line and a pillar 485). The storage element assembly 480 can enable the memory array 200-1 (and the memory array 200 formed by the process steps following the memory array 200-1) to store data. That is, the storage element assembly 480 can include a storage element material 465 and can be configured to store a logic state (e.g., a logic value of “0” or a logic value of “1”).

[0071] A storage element assembly 480 can be programmed to a target state by applying a pulse (e.g., a program pulse) that satisfies a program threshold. The amplitude, shape, or other characteristics of the program pulse can be configured to cause the storage element material 465 to exhibit the target state. For example, after applying the program pulse, ions of the storage element assembly 480 can be redistributed throughout the storage element to thereby alter the resistance of the memory cell detected when a read pulse is applied. In some cases, the threshold voltage of the storage element assembly 480 can change based on applying the program pulse.

[0072] A state stored by a storage element assembly 480 can be sensed, detected, or read by applying a read pulse to the storage element assembly 480. The amplitude, shape, or other characteristics of the read pulse can be configured to allow a sensing component to determine what state is stored on the storage element assembly 480. For example, in some cases, the amplitude of the read pulse is configured to be at a level that causes the storage element assembly 480 to be in an “on” state (e.g., current is conducted through the material) for a first state but to be in an “off’ state (e.g., little to no current is conducted through the material) for a second state.

[0073] In some cases, the polarity of a pulse (whether program or read) applied to the storage element assembly 480 affects the outcome of the operation performed. For example, if the storage element assembly 480 stores a first state, a read pulse of a first polarity can cause the storage element assembly 480 to exhibit an "on" state, while a read pulse of a second polarity can cause the storage element assembly 480 to exhibit an "off' state. This can be due to an asymmetric distribution of ions or other materials in the storage element assembly 480 as it stores a state. Similar principles apply to program pulses and other pulses or voltages.

[0074] Examples of chalcogenide materials that can be used as the storage element assembly 480 include indium (In)-antimony (Sb)-tellurium (Te) (IST) materials (e.g., In2Sb2Te5, In1Sb2Te4, In1Sb4Te7, etc.) and germanium (Ge)-antimony (Sb)-tellurium (Te) (GST) materials (e.g., Ge8Sb5Te8, Ge2Sb2Te5, Ge1Sb2Te4, Ge1Sb4Te7, Ge4Sb4Te7, etc.) and other chalcogenide materials, including, for example, alloys that do not phase change during operation (e.g., selenium-based chalcogenide alloys). In addition, the chalcogenide materials can include low concentrations of other dopant materials. Other examples of chalcogenide materials can include tellurium-arsenic (As)-germanium (OTS) materials, Ge, Sb, Te, silicon (Si), nickel (Ni), gallium (Ga), As, silver (Ag), tin (Sn), gold (Au), lead (Pb), bismuth (Bi), indium (In), selenium (Se), oxygen (O), sulfur (S), nitrogen (N), carbon (C), yttrium (Y), and scandium (Sc) materials, and combinations thereof. As used herein, a chemical composition symbol connected by a hyphen indicates the elements included in a particular mixture or compound and is intended to represent all stoichiometry involving the indicated elements. In some examples, the chalcogenide material can be a chalcogenide glass or amorphous chalcogenide material. In some examples, a chalcogenide material having primarily selenium (Se), arsenic (As), and germanium (Ge) can be referred to as a SAG alloy. In some examples, a SAG alloy can include silicon (Si) and such a chalcogenide material can be referred to as a SiSAG alloy. In some examples, a chalcogenide glass can include additional elements in atomic or molecular form, such as hydrogen (H), oxygen (O), nitrogen (N), chlorine (Cl), or fluorine (F). In some examples, the electrical conductivity can be controlled by doping with various chemical species. For example, doping can include incorporating a Group 3 element (e.g., boron (B), gallium (Ga), indium (In), aluminum (Al), etc.) or a Group 4 element (tin (Sn), carbon (C), silicon (Si), etc.) into the composition.

[0075] Figures 5A to 5E Various views of the memory array 200-m are illustrated. In particular, Figures 5A to 5EThe description in reference Figure 4G A view of a memory array 200-m formed after the second openings 490 in the memory array 200-l are described and after the insulating material 505 is deposited into the second openings 490. Figure 5A A top view of the memory array 200-m is described, which can be formed after the second openings 490 are formed in the memory array 200-l described in Figure 4G The example of the memory array 200-l described in Figures 5B to 5E may be during a process step after the process steps described in Figure 5A A cross-sectional view of the memory array 200-m taken along different cross-sectional lines during process steps after the process steps described in

[0076] Figure 5A A top view of the memory array 200-m is described in accordance with the examples disclosed herein. The memory array 200-m can be formed after the insulating material 505 is deposited into the openings 490 shown in Figure 4G The insulating material 505 can be a dielectric material. The insulating material 505 can contact the pillars 485 and the storage element assemblies 480. The insulating material 505 can isolate the pillars 485 within a pair of pillars from each other. For example, there can be a plurality of pillars along cross-sectional line B-B' and a corresponding pair of pillars along cross-sectional line E-E'. The insulating material 505 (e.g., portions along cross-sectional line A-A') can isolate the pillars along cross-sectional line B-B' from the pillars along cross-sectional line E-E'. This can reduce the impact of accessing the first storage element assembly 480 on the second storage element assembly 480 when the first and second storage element assemblies 480 are positioned in the same recess (e.g., formed from the same storage element material 465).

[0077] The memory array 200-m can further include a second substrate 104 formed over the first substrate 104 (as shown in Figures 2A to 2C In some cases, the second substrate 104 can include a plurality of conductive contacts (e.g., conductive contacts 235) formed in and extending through the substrate 104. Each pillar 485 can be in contact with a contact (e.g., of the first substrate 104 or the second substrate 104).

[0078] Figure 5B A cross-sectional view of the memory array 200-m along cross-sectional line A-A' is described. As described in Figure 5A The memory array 200-m can include a number of alternating layers of material 245 and insulating material 240, as described in Figure 5B The insulating material 505 can isolate the pillars within a pair of pillars. The insulating material 505 can extend to contact each pillar 485 of a pair of pillars, as shown in Figure 5A ​

[0079] Figure 5C Explanation along Figure 5A A cross-sectional view of the memory array 200-m along cross-section line B-B'. Pillar 485 contacts a conductive contact 235 associated with a substrate 104-b positioned below pillar 485. In some cases, conductive contact 235 may be associated with a substrate 104-a positioned above pillar 485. Pillar 485 may contact a memory element assembly 480 positioned in opposing recesses. For example, pillar 485 may contact memory element assemblies 480-a and 480-b. Materials 245-a and 245-b may be isolated from each other. For example, material 245-a may be associated with an odd-number line board and material 245-b may be associated with an even-number line board. In some cases, material 245-a may be a conductive material associated with the word line board. Alternatively or additionally, material 245-a may be a sacrificial insulating material. Here, material 245-a may subsequently (e.g., in...) Figure 5C The process steps described herein (during subsequent process steps) are removed and replaced with conductive material for the word line board.

[0080] Figure 5D Explanation along Figure 5A A cross-sectional view of the memory array 200-m with cross-section line C-C'. Figure 5D This can be illustrated by a pillar 485 that contacts the insulating material 505. The pillar 485 may contact a plurality of storage element assemblies 480 and a contact associated with a substrate 104-b located below the pillar 485.

[0081] Figure 5E Explanation along Figure 5A A cross-sectional view of the memory array 200-m with cross-sectional line D-D'. Figure 5E The conformal material 320 and dielectric material 318 may be described. The conformal material 320 may extend to contact two memory element assemblies 480 on the same layer and to contact the same word line board. The conformal material 320 may isolate the memory element assemblies 480 from each other. The dielectric material 318 may extend to contact two pillars. A first pillar may be associated with a first pair of pillars and a second pillar may be associated with a second pair of pillars.

[0082] Figure 6A and 6B This document describes an example of a memory array 200-n that supports a memory device with a split-pillar architecture, based on the examples disclosed herein. Figure 6A and 6B This describes the configuration of a memory device, in which each of a pair of pillars 485 contacts a conductive contact 235 on the same substrate 104. The substrate 104-b of the memory array 200-n may correspond to... Figure 2AThe memory array 200-a is illustrated herein. In some other cases, substrate 104-b may be positioned above each pillar 485. Here, the top view of memory array 200-n may correspond to... Figure 2A The memory array 200-a described herein.

[0083] Figure 6A Explanation along Figure 5A The image shows a cross-sectional view of the memory array 200-n along cross-section line B-B'. The memory array 200-n may include pillars 485-a in contact with conductive contacts 235-a of the substrate 104-b. Conductive contacts 235-a may couple pillars 485-a to transistors 605-a. Transistors 605-a may be an example of a digital line selector formed in a regular matrix. Activating transistor 605-a may trigger an access operation (e.g., read operation, write operation, refresh operation) on one of the memory element assemblies 480. For example, activating transistor 605-a and applying voltage to material 245 (e.g., via a word line driver) may access memory element assembly 480. That is, each of the memory element assemblies 480 may be individually addressed by activating transistor 605 and applying voltage to material 245. Material 245 may be a conductive material. In some cases, material 245 may have been deposited as a conductive material on a stack (e.g., in...). Figure 2C (During the process steps described above). In some other cases, material 245 may have been deposited onto the stack as a sacrificial insulating material. In subsequent process steps, material 245 may have been removed and replaced with a conductive material.

[0084] Figure 6B Explanation along Figure 5A The image shows a cross-sectional view of the memory array 200-n along section line E-E'. The memory array 200-n may include pillars 485-b in contact with conductive contacts 235-b of the substrate 104-b. Pillars 485-b and pillars 485-a (e.g., ...) Figure 6A (As shown in the diagram) can be a pair of pillars. That is, pillars 485-a and 485-b can be formed by etching the conductive pillars. Conductive contact 235-b can couple pillar 485-b to transistor 605-b, which can be an example of a digital line selector formed in a regular matrix. In some cases, transistor 605-b can be at the same level as transistor 605-a (e.g., part of the same matrix). In other cases, transistor 605-b can be offset from transistor 605-a. For example, transistor 605-b can be positioned below transistor 605-a.

[0085] Figure 7A and 7BThis document describes an example of a memory array 200-o that supports a memory device with a split-pillar architecture, based on the examples disclosed herein. Figure 7A and 7B The configuration of the memory device is described, wherein a second pillar 485 contacts a conductive contact 235 on a substrate 104 below the pillar 485, and a third pillar 485 contacts a conductive contact 235 on a substrate 104 above the pillar 485. Substrates 104-b and 104-a of the memory array 200-o may correspond to... Figure 2B The memory array 200-b is described in the document.

[0086] Figure 7A Explanation along Figure 5A The image shows a cross-sectional view of the memory array 200-o along cross-section line B-B'. The memory array 200-o may include pillars 485-c in contact with conductive contacts 235-c of the substrate 104-b. The conductive contacts 235-c couple pillars 485-c to transistors 705-a. Transistor 705-a may be an example of a digital line selector formed in a regular matrix. Activating transistor 705-a can trigger an access operation (e.g., read operation, write operation, refresh operation) on one of the memory element assemblies 480. For example, activating transistor 705-a and applying a voltage to material 245 (e.g., via a word line driver) can access the memory element assembly 480. Material 245 may be a conductive material. In some cases, material 245 may have been deposited as a conductive material on a stack (e.g., in...). Figure 2C (During the process steps described above). In some other cases, material 245 may have been deposited onto the stack as a sacrificial insulating material. In subsequent process steps, material 245 may have been removed and replaced with a conductive material.

[0087] Figure 7B Explanation along Figure 5A The image shows a cross-sectional view of the memory array 200-o along cross-section line E-E'. The memory array 200-o may include pillars 485-d that contact the conductive contacts 235-d of the substrate 104-a. Pillars 485-d and pillars 485-c (e.g., Figure 7A (As shown in the diagram) can be a pair of pillars. That is, pillars 485-c and 485-d can be formed when the conductive pillars are divided by an etching process. Conductive contact 235-d can couple pillar 485-d to transistor 705-b, which can be an example of a digital line selector formed in a regular matrix.

[0088] Figure 8A flow diagram illustrating a method 800 of supporting one or more memory devices having a split pillar architecture in accordance with the examples disclosed herein is shown. The operations of method 800 can be implemented by a manufacturing system or one or more controllers associated with a manufacturing system. In some examples, one or more controllers can execute a set of instructions to control the one or more functional elements of a manufacturing system to perform the described functions. Additionally or alternatively, one or more controllers can use special-purpose hardware to perform aspects of the described functions.

[0089] At 805, the method 800 can include forming a trench through the first dielectric layer, the first conductive layer, and the second dielectric layer, the trench exposing the substrate and dividing the first conductive layer into a first portion associated with the first word line driver and a second portion associated with the second word line driver. The operation 805 can be performed in accordance with the methods described herein.

[0090] At 810, the method 800 can include depositing an insulating material into the trench. The operation 810 can be performed in accordance with the methods described herein.

[0091] At 815, the method 800 can include forming a first opening over the contact with the substrate by etching a portion of the insulating material. The operation 815 can be performed in accordance with the methods described herein.

[0092] At 820, the method 800 can include depositing a chalcogenide material into the first opening in contact with the first portion of the first conductive layer, the first dielectric layer, and the second dielectric layer. The operation 820 can be performed in accordance with the methods described herein.

[0093] At 825, the method 800 can include depositing a conductive material into the first opening for forming a pillar that contacts the chalcogenide material and contacts the substrate. The operation 825 can be performed in accordance with the methods described herein.

[0094] At 830, the method 800 can include forming a second opening through the chalcogenide material and the conductive material to divide the chalcogenide material into a first chalcogenide component and a second chalcogenide component and to divide the pillar into a first pillar and a second pillar. The operation 830 can be performed in accordance with the methods described herein.

[0095] In some examples, an apparatus described herein can perform one or several methods (e.g., method 800). The apparatus can include features, means, or instructions for forming a trench through a first dielectric layer, a first conductive layer, and a second dielectric layer, the trench exposing a substrate and dividing the first conductive layer into a first portion associated with a first word line driver and a second portion associated with a second word line driver. The apparatus can further include features, means, or instructions for depositing an insulating material into the trench; forming a first opening over a contact in contact with the substrate by etching a portion of the insulating material; depositing a chalcogenide material in contact with the first portion of the first conductive layer, the first dielectric layer, and the second dielectric layer into the first opening; depositing a conductive material for forming a pillar in contact with the chalcogenide material and in contact with the substrate into the first opening; and forming a second opening through the chalcogenide material and the conductive material to divide the chalcogenide material into a first chalcogenide component and a second chalcogenide component and to divide the pillar into a first pillar and a second pillar.

[0096] Some examples of the method 800 and apparatus described herein can further include operations, features, means, or instructions for depositing a second insulating material in contact with the first chalcogenide component and the second chalcogenide component into the second opening. Some examples of the method 800 and apparatus described herein can further include operations, features, means, or instructions for depositing a conformal material in contact with first and second sidewalls of the trench, where depositing the insulating material into the trench can be based on depositing the conformal material.

[0097] In some cases of the method 800 and apparatus described herein, the first chalcogenide component includes a first wall in contact with the first conductive layer, a second wall in contact with the second insulating material, a third wall in contact with the first pillar, and a fourth wall in contact with the conformal material. In some examples of the method 800 and apparatus described herein, forming the second opening through the chalcogenide material and the conductive material can include operations, features, means, or instructions for performing a dry etch process to etch the second insulating material; performing a selective wet etch process to divide the conductive material into the first pillar and the second pillar; and performing a selective etch process to divide the chalcogenide material into the first chalcogenide component and the second chalcogenide component.

[0098] In some examples of the method 800 and apparatus described herein, the first pillar can be formed over a contact extending through the substrate, and the second pillar can be formed over a second contact extending through the substrate. Some cases of the method 800 and apparatus described herein can further include operations, features, means, or instructions for depositing a second substrate over the first dielectric layer, the second substrate being in contact with the first pillar and the second pillar, where the second substrate includes a second contact extending through the second substrate and in contact with the first pillar, where the second pillar can be in contact with the contact of the substrate.

[0099] Some examples of the method 800 and apparatus described herein can further include operations, features, means, or instructions for forming a set of contacts extending through the substrate, the set of contacts can be associated with a set of digit lines; forming a first dielectric layer on the substrate; forming a first conductive layer on the first dielectric layer, the first conductive layer configured as at least one word line plate; and forming a second dielectric layer on the first conductive layer, where forming the trench can be based on forming the second dielectric layer. In some examples of the method 800 and apparatus described herein, the first pillar contacts at least a portion of the first dielectric layer, the second dielectric layer, and a first chalcogenide component, and the second pillar contacts at least a portion of the first dielectric layer, the second dielectric layer, and a second chalcogenide component.

[0100] In some cases of the method 800 and apparatus described herein, the first pillar and the second pillar can be configured as digit lines. In some examples of the method 800 and apparatus described herein, forming the trench through the first dielectric layer can include operations, features, means, or instructions for performing a vertical etch process to vertically etch the trench; and performing a horizontal etch process after the vertical etch process to form at least one recess in the first conductive layer.

[0101] In some examples of the method 800 and apparatus described herein, the trench extends through the first conductive layer in a serpentine shape. In some cases of the method 800 and apparatus described herein, the first chalcogenide component and the second chalcogenide component each include a storage element for a self-selecting memory cell.

[0102] Figure 9 A flow diagram illustrating one or more methods 900 that support memory devices with split pillar architecture in accordance with the examples disclosed herein is shown. The operations of the method 900 can be implemented by a manufacturing system or one or more controllers associated with a manufacturing system. In some examples, one or more controllers can execute a set of instructions to control one or more functional elements of the manufacturing system to perform the described functions. Additionally or alternatively, one or more controllers can use special-purpose hardware to perform aspects of the described functions.

[0103] At 905, the method 900 can include forming a trench through the first dielectric layer, the first conductive layer, and the second dielectric layer, the trench exposing the substrate and dividing the first conductive layer into a first portion associated with the first word line driver and a second portion associated with the second word line driver. The operation 905 can be performed according to the methods described herein.

[0104] At 910, the method 900 can include depositing an insulating material into the trench. The operation 910 can be performed according to the methods described herein.

[0105] At 915, the method 900 can include forming a first opening over the contact with the substrate by etching a portion of the insulating material.

[0106] At 920, the method 900 can include depositing a chalcogenide material into the first opening in contact with the first portion of the first conductive layer, the first dielectric layer, and the second dielectric layer. The operation 920 can be performed according to the methods described herein.

[0107] At 925, the method 900 can include depositing a conductive material into the first opening for forming a pillar that contacts the chalcogenide material and contacts the substrate. The operation 925 can be performed according to the methods described herein.

[0108] At 930, the method 900 can include forming a second opening through the chalcogenide material and the conductive material to divide the chalcogenide material into a first chalcogenide component and a second chalcogenide component and to divide the pillar into a first pillar and a second pillar. The operation 930 can be performed according to the methods described herein.

[0109] At 935, the method 900 can include depositing a second insulating material into the second opening that contacts the first chalcogenide component and the second chalcogenide component. The operation 935 can be performed according to the methods described herein.

[0110] Figure 10 A flow diagram illustrating one or more methods 1000 of supporting a memory device having a split pillar architecture in accordance with examples as disclosed herein is shown. The operations of method 1000 can be implemented by a manufacturing system or one or more controllers associated with a manufacturing system. In some examples, one or more controllers can execute a set of instructions to control one or more functional elements of the manufacturing system to perform the described functions. Additionally or alternatively, one or more controllers can use special-purpose hardware to perform aspects of the described functions.

[0111] At 1005, the method 1000 can include forming a trench through the first dielectric layer, the first conductive layer, and the second dielectric layer, the trench exposing the substrate and dividing the first conductive layer into a first portion associated with the first word line driver and a second portion associated with the second word line driver. The operation 1005 can be performed according to the methods described herein.

[0112] At 1010, the method 1000 can include depositing a conformal material contacting first and second sidewalls of the trench. The operation 1010 can be performed according to the methods described herein.

[0113] At 1015, the method 1000 can include depositing an insulating material into the trench based on depositing the conformal material. The operation 1015 can be performed according to the methods described herein.

[0114] At 1020, the method 1000 can include forming a first opening over the contact with the substrate by etching a portion of the insulating material. The operation 1020 can be performed according to the methods described herein.

[0115] At 1025, the method 1000 can include depositing a chalcogenide material into the first opening in contact with the first portion of the first conductive layer, the first dielectric layer, and the second dielectric layer. The operation 1025 can be performed according to the methods described herein.

[0116] At 1030, the method 1000 can include depositing a conductive material into the first opening for forming a pillar contacting the chalcogenide material and contacting the substrate. The operation 1030 can be performed according to the methods described herein.

[0117] At 1035, the method 1000 can include forming a second opening through the chalcogenide material and the conductive material to divide the chalcogenide material into a first chalcogenide component and a second chalcogenide component and to divide the pillar into a first pillar and a second pillar. The operation 1035 can be performed according to the methods described herein.

[0118] Figure 11 A flow diagram illustrating one or more methods 1100 of supporting a memory device having a split pillar architecture in accordance with examples as disclosed herein is shown. The operations of method 1100 can be implemented by a manufacturing system or one or more controllers associated with a manufacturing system. In some examples, one or more controllers can execute a set of instructions to control one or more functional elements of the manufacturing system to perform the described functions. Additionally or alternatively, one or more controllers can use special-purpose hardware to perform aspects of the described functions.

[0119] At 1105, the method 1100 can include forming a trench through the first dielectric layer, the first conductive layer, and the second dielectric layer, the trench exposing the substrate and dividing the first conductive layer into a first portion associated with the first word line driver and a second portion associated with the second word line driver. The operation 1105 can be performed according to the methods described herein.

[0120] At 1110, the method 1100 can include depositing an insulating material into the trench. The operation 1110 can be performed according to the methods described herein.

[0121] At 1115, the method 1100 can include forming a first opening over the contact with the substrate by etching a portion of the insulating material. The operation 1115 can be performed according to the methods described herein.

[0122] At 1120, the method 1100 can include depositing a chalcogenide material into the first opening in contact with the first portion of the first conductive layer, the first dielectric layer, and the second dielectric layer. The operation 1120 can be performed according to the methods described herein.

[0123] At 1125, the method 1100 can include depositing a conductive material into the first opening for forming a pillar that contacts the chalcogenide material and contacts the substrate. The operation 1125 can be performed according to the methods described herein.

[0124] At 1130, the method 1100 can include performing a dry etch process to etch the second insulating material. The operation 1130 can be performed according to the methods described herein.

[0125] At 1135, the method 1100 can include performing a selective wet etch process to divide the conductive material into a first pillar and a second pillar. The operation 1135 can be performed according to the methods described herein.

[0126] At 1140, the method 1100 can include performing a selective etch process to divide the chalcogenide material into a first chalcogenide component and a second chalcogenide component. The operation 1140 can be performed according to the methods described herein.

[0127] It should be noted that the foregoing method descriptions may

[0128] An apparatus is described. The apparatus can include a set of contacts associated with a set of digit lines and extending through a substrate, a first set of word line plates separated from a second set of word line plates by a trench, and a pair of pillars configured as digit lines and each configured to interact with the first set of word line plates and the second set of word line plates. The apparatus can further include a dielectric material positioned between a first pillar of the pair of pillars and a second pillar of the pair of pillars, and a set of storage elements including a chalcogenide material and in contact with the dielectric material, a word line plate of the first set of word line plates or the second set of word line plates, and one of the pair of pillars.

[0129] Some examples of the apparatus can include a second pair of pillars configured as digit lines and each configured to interact with the first set of word line plates and the second set of word line plates, where a first distance between each pillar of the pair of pillars can be less than a second distance between the pair of pillars and the second pair of pillars.

[0130] Some cases of the apparatus can include a second dielectric material positioned between the first pillar of the pair of pillars and a third pillar of the second pair of pillars. In some examples, a first pair of storage elements can be in contact with the first pillar of the pair of pillars and a second pair of storage elements can be in contact with the second pillar of the pair of pillars.

[0131] Some examples of the apparatus can include a conformal material in contact with at least one word line plate and extending between a first storage element of the first pair of storage elements and a second storage element of the second pair of storage elements. In some examples, the set of storage elements can be positioned in a recess formed by the at least one word line plate and the at least one pillar of the pair of pillars. In some cases, the trench extends in a serpentine shape over the substrate. Some examples of the apparatus can include a second set of contacts associated with a second set of digit lines and extending through a second substrate, where the first pillar of the pair of pillars can be in contact with one of the set of contacts and the second pillar of the pair of pillars can be in contact with one of the second set of contacts.

[0132] A device is described. The device can include a first word line plate in a first tier of a memory device and a second word line plate in the first tier of the memory device, the second word line plate separate from the first word line plate. The device can further include a first digit line extending from the first tier to at least a second tier of the memory device and a second digit line separate from the first digit line and extending from the first tier to at least the second tier. The device can further include a first storage element in contact with the first word line plate and the first digit line, a second storage element in contact with the first word line plate and the second digit line, a third storage element in contact with the second word line plate and the first digit line, and a fourth storage element in contact with the second word line plate and the second digit line.

[0133] Some examples of the device can include a dielectric material in contact with the first word line plate, the second word line plate, the first digit line, and the second digit line. In some cases, the dielectric material can be in contact with the first storage element, the second storage element, the third storage element, and the fourth storage element. Some examples of the device can include a dielectric layer between the first tier and the second tier. The second tier can include a sixth storage element in contact with the third word line plate and the second digit line, a seventh storage element in contact with a fourth word line plate in the second tier and the first digit line, and an eighth storage element in contact with the fourth word line plate and the second digit line.

[0134] Information and signals described herein can be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that can be referenced throughout the above description can be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof. Some drawings can illustrate signals as single signals; however, it will be understood by one of ordinary skill in the art that the signals can represent a bus of signals, where the bus can have a variety of bit widths.

[0135] As used herein, the term "virtual ground" refers to a node of a circuit that maintains a voltage of approximately zero volts (0V) but is not directly coupled to ground. Thus, the voltage of a virtual ground can temporarily fluctuate and return to approximately 0V in steady state. A virtual ground can be implemented using various electronic circuit elements, such as a voltage divider consisting of an operational amplifier and resistors. Other implementations are also possible. "Virtual ground" or "virtual ground connection" means connected to approximately 0V.

[0136] The terms "in electronic communication," "in conductive contact," "connected," and "coupled" can refer to a relationship between components that supports the flow of signals between the components. Components are considered to be in electronic communication with each other (or in conductive contact, connected, or coupled with each other) if there exists any conductive path between the components that can support the flow of signals between the components at any time. The conductive path between components that are in electronic communication with each other (or in conductive contact or connected or coupled with each other) can be an open circuit or a closed circuit at any given time, based on the operation of the device that includes the connected components. The conductive path between connected components can be a direct conductive path between the components, or the conductive path between connected components can be an indirect conductive path that can include intervening components such as switches, transistors, or other components. In some cases, the flow of signals between connected components can be interrupted for a period of time, for example, using one or more intervening components such as switches or transistors.

[0137] The term "coupled" refers to the condition of components moving from an open circuit relationship between the components, in which signals cannot currently pass between the components through a conductive path, to a closed circuit relationship between the components, in which signals can pass between the components through a conductive path. When a component such as a controller couples other components together, the component causes a change that allows signals to flow between the other components through a conductive path that previously did not allow signal flow.

[0138] The term "isolated" refers to a relationship between components in which signals cannot currently flow between the components. Components are isolated from each other if there is an open circuit between the components. For example, two components that are separated by a switch that is open are isolated from each other. When a controller isolates two components, the controller effects a change that prevents signals from flowing between the components using a conductive path that previously allowed signal flow.

[0139] The term "layer" as used herein refers to a stratum or sheet of a geometric structure. Each layer can have three dimensions (e.g., height, width, and depth) and can cover at least a portion of a surface. For example, a layer can be a three-dimensional structure in which two dimensions are greater than the third dimension (e.g., a thin film). Layers can include different elements, components, and / or materials. In some cases, one layer can be composed of two or more sub-layers. In some figures, two dimensions of a three-dimensional layer are depicted for illustration.

[0140] As used herein, the term "substantially" means that the modified characteristic (e.g., a verb or adjective modified by the term "substantially") need not be absolute, but is close enough to the ideal characteristic to achieve the desired result.

[0141] As used herein, the term "electrode" can refer to an electrical conductor and, in some cases, can serve as an electrical contact to a memory cell or other component of a memory array. An electrode can include a trace, wire, lead, conductive layer, or the like that provides an electrically conductive path between elements or components of a memory array.

[0142] Devices discussed herein, including memory arrays, can be formed on a semiconductor substrate, such as silicon, germanium, silicon-germanium alloys, gallium arsenide, gallium nitride, and the like. In some cases, the substrate is a semiconductor wafer. In other cases, the substrate can be a silicon-on-insulator (SOI) substrate (such as silicon-on-glass (SOG) or silicon-on-sapphire (SOP)) or an epitaxial layer of semiconductor material on another substrate. The electrical conductivity of the substrate or sub-regions of the substrate can be controlled by doping using various chemical species, including but not limited to phosphorus, boron, or arsenic. Doping can be performed by ion implantation or any other doping means during initial formation or growth of the substrate.

[0143] Switching components or transistors discussed herein can represent field effect transistors (FETs) and include three-terminal devices (including a source, a drain, and a gate). The terminals can be connected to other electronic elements by conductive materials, such as metals. The source and drain can be electrically conductive and can include heavily doped (e.g., degenerate) semiconductor regions. The source and drain can be separated by a lightly doped semiconductor region or channel. If the channel is n-type (i.e., the majority carriers are electrons), the FET can be referred to as an n-type FET. If the channel is p-type (i.e., the majority carriers are holes), the FET can be referred to as a p-type FET. The channel can be covered by an insulating gate oxide. The channel conductivity can be controlled by applying a voltage to the gate. For example, applying a positive or negative voltage to an n-type or p-type FET, respectively, can cause the channel to become electrically conductive. A transistor can be "turned on" or "activated" when a voltage greater than or equal to the transistor threshold voltage is applied to the transistor gate. A transistor can be "turned off" or "deactivated" when a voltage less than the transistor threshold voltage is applied to the transistor gate.

[0144] The detailed description set forth below, in connection with the appended drawings, describes example configurations and does not represent all examples that can be implemented or that are within the scope of the claims. The term "exemplary" used herein means "serving as an example, instance, or illustration," and not "preferred" or "superior." The detailed description includes specific details for the purpose of providing an understanding of the described techniques. These techniques, however, can be practiced without these specific details. In some instances, well-known structures and devices are shown in block diagram form in order to avoid obscuring the concepts of the described examples.

[0145] In the drawings, like reference numerals can be used to denote similar components throughout the several views. Moreover, various components of the same type can be distinguished by following the convention of using the first three characters of the component's reference number to indicate that the component is one of a kind across the several figures. If a component has the same reference number in more than one figure, then the different instances can be distinguished by following the referenced convention, but also by the use of a lower-case letter following the component's reference number. Specifically, the first occurrence of the component in a figure can be designated as "A", the second occurrence as "B", and so on.

[0146] The various illustrative blocks and modules described in connection with the disclosure can be implemented or performed with a general-purpose processor, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general-purpose processor can be a microprocessor, but in the alternative, the processor can be any processor, controller, microcontroller, or state machine. A processor can also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration).

[0147] The functions described herein can be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the functions can be stored on or transmitted over as one or more instructions or program code on a computer-readable medium. Other examples and implementations are within the scope of the disclosure and appended claims. For example, due to the nature of software, functions described above can be implemented using software executed by a processor, hardware, firmware, hardwiring, or combinations of any of these. Features implementing functions can also be physically located at various positions, including being distributed such that portions of functions are implemented at different physical locations. Also, as used herein, including in the claims, "or" as used in a list of items (for example, a list of items prefaced by a phrase such as "at least one of" or "one or more of") indicates an inclusive list such that, for example, a list of at least one of A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Also, as used herein, the phrase "based on" shall not be construed as a reference to a closed set of conditions. For example, an exemplary step that is described as "based on condition A" can be based on both a condition A and a condition B without departing from the scope of the present disclosure. In other words, as used herein, the phrase "based on" shall be construed in the same manner as the phrase "based at least in part on."

[0148] The detailed description is presented to enable one of ordinary skill in the art to make and use the disclosure. Various modifications to the disclosure will be readily apparent to those skilled in the art, and the generic principles defined herein can be applied to other variations without departing from the scope of the disclosure. Thus, the disclosure is not to be limited to the examples and designs described herein but is to be accorded the broadest scope consistent with the principles and novel features disclosed herein.

Claims

1. A method for forming a memory device, comprising: forming a trench through a first dielectric layer, a first conductive layer, and a second dielectric layer, the trench exposing a first substrate and dividing the first conductive layer into a first portion associated with a first word line driver and a second portion associated with a second word line driver; depositing an insulating material into the trench; forming a first opening over a contact in contact with the first substrate by etching a portion of the insulating material; depositing a chalcogenide material in contact with the first portion of the first conductive layer, the first dielectric layer, and the second dielectric layer into the first opening; depositing a conductive material for forming a pillar in contact with the chalcogenide material and in contact with the first substrate into the first opening; and forming a second opening through the chalcogenide material and the conductive material to divide the chalcogenide material into a first chalcogenide component and a second chalcogenide component and to divide the pillar into a first pillar and a second pillar.

2. The method of claim 1, further comprising: depositing a second insulating material in contact with the first chalcogenide component and the second chalcogenide component into the second opening.

3. The method of claim 1, further comprising: depositing a conformal material in contact with first and second sidewalls of the trench, wherein depositing the insulating material into the trench is based at least in part on depositing the conformal material.

4. The method of claim 1, wherein the first chalcogenide component comprises a first wall in contact with the first conductive layer, a second wall in contact with a second insulating material, a third wall in contact with the first pillar, and a fourth wall in contact with a conformal material.

5. The method of claim 1, wherein forming the second opening through the chalcogenide material and the conductive material comprises: performing a dry etch process to etch a second insulating material; performing a selective wet etch process to divide the conductive material into the first pillar and the second pillar; and performing a selective etch process to divide the chalcogenide material into the first chalcogenide component and the second chalcogenide component.

6. The method of claim 1, wherein: the first pillar is formed over the contact extending through the first substrate; and the second pillar is formed over a second contact extending through the first substrate.

7. The method of claim 1, further comprising: depositing a second substrate over the first dielectric layer, the second substrate in contact with the first pillar and the second pillar, wherein the second substrate comprises a second contact extending through the second substrate and in contact with the first pillar, wherein the second pillar is in contact with the contact of the first substrate.

8. The method of claim 1, further comprising: forming a plurality of contacts extending through the first substrate, the plurality of contacts associated with a plurality of digit lines; forming the first dielectric layer on the first substrate; ​ forming the first conductive layer on the first dielectric layer, the first conductive layer configured as at least one word line plate; and forming the second dielectric layer on the first conductive layer, wherein forming the trench is based at least in part on forming the second dielectric layer.

9. The method of claim 1, wherein: the first pillar contacts at least a portion of the first dielectric layer, the second dielectric layer, and the first chalcogenide component; and the second pillar contacts at least a portion of the first dielectric layer, the second dielectric layer, and the second chalcogenide component.

10. The method of claim 1, wherein the first pillar and the second pillar are configured as digit lines.

11. The method of claim 1, wherein forming the trench through the first dielectric layer comprises: performing a vertical etch process to vertically etch the trench; and after the vertical etch process, performing a horizontal etch process to form at least one recess in the first conductive layer.

12. The method of claim 1, wherein the trench extends through the first conductive layer in a serpentine shape.

13. The method of claim 1, wherein the first chalcogenide component and the second chalcogenide component each comprise a storage element for a self-selecting memory cell.

14. A memory device comprising: a plurality of contacts associated with a plurality of digit lines and extending through a first substrate; a first plurality of word line plates separated from a second plurality of word line plates by a trench; a first pair of pillars comprising at least one pillar configured as a digit line of the plurality of digit lines, each pillar of the first pair of pillars configured to interact with the first plurality of word line plates and the second plurality of word line plates, and each pillar of the first pair of pillars extending between and contacting two insulating substrates; a dielectric material positioned between a first pillar of the first pair of pillars and a second pillar of the first pair of pillars; and a plurality of storage elements comprising a chalcogenide material and in contact with the dielectric material, a word line plate of the first plurality of word line plates or the second plurality of word line plates, and a pillar of the first pair of pillars.

15. The memory device of claim 14, further comprising: a second pair of pillars configured as digit lines and each configured to interact with both the first plurality of word line plates and the second plurality of word line plates, wherein a first distance between each pillar of the first pair of pillars is less than a second distance between the first pair of pillars and the second pair of pillars.

16. The memory device of claim 15, further comprising: a second dielectric material positioned between the first pillar of the first pair of pillars and a third pillar of the second pair of pillars.

17. The memory device of claim 14, wherein the plurality of storage elements further comprise: a first pair of storage elements in contact with the first pillar of the first pair of pillars; and a second pair of storage elements in contact with the second pillar of the first pair of pillars.

18. The memory device of claim 17, further comprising: a conformal material contacting at least one word line plate and extending between a first storage element of the first pair of storage elements and a second storage element of the second pair of storage elements.

19. The memory device of claim 14, wherein the plurality of storage elements are positioned in a recess formed by at least one word line plate and at least one pillar of the first pair of pillars.

20. The memory device of claim 14, wherein the trench extends in a serpentine shape over the first substrate.

21. The memory device of claim 14, further comprising: a second plurality of contacts associated with a second plurality of digit lines and extending through a second substrate, wherein the two insulating substrates comprise the first substrate and the second substrate, and wherein the first pillar of the first pair of pillars contacts one of the plurality of contacts extending through the first substrate and the second pillar of the first pair of pillars contacts one of the second plurality of contacts extending through the second substrate.

22. A memory device, comprising: a first word line plate in a first layer of a memory device; a second word line plate in the first layer of the memory device, the second word line plate separate from the first word line plate; a first digit line extending from the first layer to at least a second layer of the memory device; a second digit line separate from the first digit line and extending from the first layer to at least the second layer, the first digit line and the second digit line each extending between and contacting two insulating substrates; a first storage element contacting the first word line plate and the first digit line; a second storage element contacting the first word line plate and the second digit line; a third storage element contacting the second word line plate and the first digit line; and a fourth storage element contacting the second word line plate and the second digit line.

23. The memory device of claim 22, further comprising: a dielectric material contacting the first word line plate, the second word line plate, the first digit line, and the second digit line.

24. The memory device of claim 23, wherein the dielectric material contacts the first storage element, the second storage element, the third storage element, and the fourth storage element.

25. The memory device of claim 22, further comprising: a dielectric layer between the first layer and a second layer, the second layer comprising: a fifth storage element contacting a third word line plate in the second layer and the first digit line; a sixth storage element contacting the third word line plate and the second digit line; a seventh storage element contacting a fourth word line plate in the second layer and the first digit line; and an eighth storage element contacting the fourth word line plate and the second digit line. ​

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