Method for erasing memory data, storage device and storage system

Abstract

Embodiments of the present application disclose a memory data erasing method, a storage device and a storage system. The method comprises the following steps: obtaining an erasing pulse number N for data erasing of a target memory block; wherein N is an integer greater than or equal to 1; applying erasing pulses to the memory block in sequence according to the erasing pulse number N; and releasing erasing charges of the memory block after the Nth erasing pulse is applied.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to the field of memory, and relate to but are not limited to a memory data erasing method, a storage device and a storage system. BACKGROUND

[0002] The erasing process of memory data includes applying an erasing pulse to erase the data of the memory, performing erasing discharge on the electrons in the channel after erasing, performing erasing verification after completing the erasing discharge, and proving that the erasing operation is completed if the erasing verification is successful. If the erasing verification is not successful, the above erasing process needs to be continued until the erasing verification is successful.

[0003] A successful erasing operation often needs to go through the above erasing process for many times, resulting in too long erasing time. SUMMARY

[0004] Therefore, embodiments of the present application provide a memory data erasing method, a storage device and a storage system.

[0005] In a first aspect, embodiments of the present application provide a memory data erasing method, which comprises:

[0006] obtaining an erasing pulse number N for data erasing of a target storage block; wherein N is an integer greater than or equal to 1;

[0007] applying erasing pulses to the target storage block in turn according to the erasing pulse number N;

[0008] releasing erasing charges of the target storage block after applying the Nth erasing pulse.

[0009] In some embodiments, the method further comprises:

[0010] applying a verification pulse to the target storage block after releasing the erasing charges;

[0011] determining whether the data of the target storage block is successfully erased according to a verification result corresponding to the verification pulse. In some embodiments, the applying erasing pulses to the target storage block in turn according to the erasing pulse number N comprises:

[0012] applying an i-th erasing pulse to the target storage block; wherein i is an integer greater than or equal to 1 and less than or equal to N;

[0013] if the i is less than N, applying an i+1-th erasing pulse to the target storage block, wherein i+1 is less than or equal to N, and a voltage value of the i+1-th erasing pulse is greater than a voltage value of the i-th erasing pulse;

[0014] If the i is equal to N, then stopping applying the erase pulse.

[0015] In some embodiments, the applying the i-th erase pulse to the target memory block comprises:

[0016] If the i-th erase pulse is the first erase pulse, then boosting to a voltage amplitude of the first erase pulse by a step-up boosting.

[0017] In some embodiments, the applying the i-th erase pulse to the target memory block comprises:

[0018] If the i-th erase pulse is not the first erase pulse, then boosting to a voltage amplitude of the i-th erase pulse based on a voltage amplitude of the i-1-th erase pulse.

[0019] In some embodiments, the releasing the erase charges of the target memory block comprises:

[0020] Releasing the erase charges in the memory cells of the target memory block by turning on a bit line of the target memory block.

[0021] In some embodiments, the method further comprises:

[0022] Determining the number N of erase pulses by performing an erase test on the memory.

[0023] In some embodiments, the determining the number N of erase pulses by performing an erase test on the memory comprises:

[0024] Applying k erase pulses to a specified test memory block in sequence, wherein the k is an integer greater than or equal to 1;

[0025] Releasing erase charges of the test memory block;

[0026] Applying a verify pulse to the test memory block to obtain a verify result;

[0027] In response to the verify result being a successful erase, determining the value of the k to be the number N of erase pulses.

[0028] In some embodiments, the determining the number N of erase pulses by performing an erase test on the memory further comprises:

[0029] In response to the verify result being a failed erase, re-applying k+1 erase pulses to the test memory block in sequence.

[0030] In some embodiments, the erase pulses are generated by a pulse generation module and are applied to a substrate of a memory block.

[0031] In a second aspect, an embodiment of the present application provides a storage device, the device comprising:

[0032] a memory cell array comprising a plurality of memory cells;

[0033] a peripheral circuit configured to:

[0034] obtain a number N of erase pulses for data erasing of a target memory block; wherein N is an integer greater than or equal to 1;

[0035] apply erase pulses to the target memory block in sequence according to the number N of erase pulses;

[0036] after applying the Nth erase pulse, release the erase charge of the target memory block.

[0037] In a third aspect, an embodiment of the present application provides a storage system, the storage system comprising: a controller and a storage device;

[0038] the peripheral circuit of the storage device is configured to perform the method according to any of the above embodiments.

[0039] Through the technical solutions of the embodiments of the present application, in the process of erasing memory data, the number of erase pulses is first obtained, then N erase pulses are applied to the target memory block of the memory in sequence, and after N erase pulses, erase discharge is performed. In this way, compared with the process of performing discharge and verification once after each application of sequential erase pulse, the time of memory data erasing is effectively reduced, and the performance of the memory is improved. BRIEF DESCRIPTION OF DRAWINGS

[0040] Figure 1 a flowchart of a memory data erasing method provided by an embodiment of the present application;

[0041] Figure 2 a flowchart of another memory data erasing method provided by an embodiment of the present application;

[0042] Figure 3 a flowchart of yet another memory data erasing method provided by an embodiment of the present application;

[0043] Figure 4 a control module component diagram provided by an embodiment of the present application;

[0044] Figure 5 a flowchart of a memory data erasing method;

[0045] Figure 6 a waveform diagram of an erasing process of a memory data erasing method;

[0046] Figure 7A waveform diagram of an erasing process of a memory data erasing method provided by an embodiment of the present application;

[0047] Figure 8 An erasing verification process of a memory data erasing provided by an embodiment of the present application;

[0048] Figure 9 A structural schematic diagram of a storage device provided by an embodiment of the present application;

[0049] Figure 10 A structural schematic diagram of a storage system provided by an embodiment of the present application. DETAILED DESCRIPTION

[0050] In order to facilitate the understanding of the present application, the present application will be described in more detail below with reference to the relevant drawings. The preferred embodiments of the present application are shown in the drawings. However, the present application can be realized in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0051] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the present application belongs. The terms used in the specification of the present application are only for the purpose of describing the specific embodiments of the present application and are not intended to limit the present application. The term "and / or" used herein includes any and all combinations of one or more related listed items.

[0052] An embodiment of the present application provides a memory data erasing method, as shown in the accompanying drawings, the method comprises: Figure 1

[0053] Step S101, obtaining the number N of erasing pulses for data erasing of a target storage block; wherein N is an integer greater than or equal to 1;

[0054] Step S102, sequentially applying erasing pulses to the target storage block according to the number N of erasing pulses;

[0055] Step S103, releasing the erasing charge of the target storage block after applying the Nth erasing pulse.

[0056] ​The memory in this embodiment can be NAND flash memory, NOR flash memory, or dynamic random access memory (DRAM), etc. Taking NAND flash memory as an example, a block is the smallest unit of erasure in NAND. The erasure method is performed on the target storage block of the memory. The target storage block is the storage block that stores the data to be erased and contains multiple storage cells.

[0057] Here, the number of erase pulses N is the number of pulses that can successfully erase data after applying N erase pulses. Each erase pulse can have a different amplitude, for example, the voltage amplitude increases sequentially. The charge stored in the floating gate layer or CT (Charge Trap) of each memory cell in the memory is gradually removed under the action of multiple erase pulses, thereby realizing the erasure of data.

[0058] In this embodiment, the number of erase pulses N for erasing data from the target storage block can be pre-stored in the memory. Since the number of erase pulses N is affected by product manufacturing processes, materials, and performance, the number of erase pulses N may differ between different products. Therefore, the number of erase pulses can be determined through factory testing before the memory leaves the factory and used as a fixed attribute of the memory.

[0059] Therefore, in this embodiment, before erasing the data in the target storage block, the number of erase pulses N can be obtained first. Then, based on the number of erase pulses N, N erase pulses are applied to the target storage block. Since the number of erase pulses N is preset, it is not necessary to perform charge release and erase verification after each erase pulse; instead, the data erasure is completed after N erase pulses are applied consecutively. Of course, after completing N erase pulses, charge release and verification operations can still be performed to confirm whether the erasure was successful.

[0060] The method described in this application embodiment, which applies N erase pulses to the target storage block and then performs one erase discharge to complete the erase operation, reduces block erase time and improves product performance compared to the erase-discharge-verification cycle of each erase pulse. This improves product competitiveness.

[0061] In some embodiments, such as Figure 2 As shown, the method further includes:

[0062] Step S201: After releasing the erase charge, apply a verification pulse to the target memory block;

[0063] Step S202: Determine whether the data in the target storage block has been successfully erased based on the verification result corresponding to the verification pulse.

[0064] After each erase pulse is applied, some charge moves from the floating gate layer or CT to the channel. After the Nth erase pulse is applied, the electrons in the channel can be released by erase discharge, which facilitates subsequent erase verification.

[0065] Erasure verification involves applying a verification voltage to the control gate to verify whether the charge stored in the floating gate layer or CT has been successfully removed after the Nth erase. If the verification voltage is greater than the current actual threshold voltage of the memory cell, the memory cell will be turned on; if the verification voltage is less than the current actual threshold voltage of the memory cell, the memory cell will be in the off state.

[0066] For example, when the first verification voltage Vr1 is applied to the word line WL of the target memory block, the target memory block in the erase state E can be turned on, while the target memory block in the first programming state P1 or other programming states is turned off. When the target memory block is applied with the first verification voltage, it turns on, and current can flow through it, indicating that the target memory block has been successfully erased. If the target memory block does not turn on and no current flows through it, it means that the target memory block has not been successfully erased and needs to be erased further.

[0067] It should be noted that in this embodiment, most memory cells can be erased by applying N consecutive erase pulses. However, due to the potential non-uniformity of device characteristics, some memory cells may still remain unerased after N erase pulses. Therefore, a discharge and verification process can be used after erasure to determine whether the erasure was successful. If data in some memory cells remains unerased, one or more erase pulses can be applied again for erasure, i.e., a cyclical operation of erase pulse-discharge-verification pulse.

[0068] In some embodiments, applying erase pulses sequentially to the target memory block according to the erase pulse N includes:

[0069] Apply the i-th erase pulse to the target memory block; where i is an integer greater than or equal to 1 and less than or equal to N;

[0070] If i is less than N, then the (i+1)th erase pulse is applied to the target memory block, where i+1 is less than or equal to N; and the voltage value of the (i+1)th erase pulse is greater than the voltage value of the ith erase pulse.

[0071] If i equals N, then stop applying the erase pulse.

[0072] The analog module used to generate erase pulses can use a counter to count the number of erase pulses generated for each erase pulse. For example, the initial count value is 0, and the count value is incremented by 1 after an erase pulse is applied to the PN well. After the i-th erase pulse is applied to the PN well, the count value is i.

[0073] Before applying an erase pulse to the PN trap of the target erase block, the number of erase pulses i that have already been applied to the target erase block can be compared with the value N of the target erase pulse number.

[0074] When the count value i is less than the target erase count N, the simulation module can continue to apply the (i+1)th erase pulse to the target erase block.

[0075] If the voltage value of the (i+1)th erase pulse is greater than the voltage value of the ith erase pulse, and if the ith erase operation is applied to the PN trap, and there are memory cells that have not yet been properly erased, Vera(i) can be raised to Vera(i+1) to perform the erase operation again.

[0076] The voltage value of the (i+1)th erase pulse is greater than the voltage value of the ith erase pulse, causing the voltage difference between the control gate and the PN well region to gradually increase, eventually causing the charge stored in the floating gate layer or CT to be removed.

[0077] When the count value i equals the target erase count N, the simulation module stops applying erase pulses to the target erase block.

[0078] In this way, erase pulses can be applied sequentially by counting until N erase pulses are applied continuously. By applying N progressively increasing erase pulse voltages to the target erase block, the charge stored in the floating gate layer or CT can be removed, thus completing the erasure of the target erase block.

[0079] In some embodiments, applying the i-th erase pulse to the target storage block includes:

[0080] If the i-th erase pulse is the first erase pulse, the voltage before the first erase pulse can be boosted from a lower voltage, such as 5V, to the voltage amplitude of the first erase pulse in a step-boost manner.

[0081] The voltage value of the erase pulse can be generated by the initial voltage VL and the incremental step pulse (ISPE) erase, where the initial voltage VL is the voltage applied to the PN well by the first erase pulse, which is generated by the charge pump in the simulation module.

[0082] When the i-th erase pulse is the first erase pulse, it reaches an initial voltage VL, for example, 15V. Starting from a lower voltage, such as 5V, the voltage is boosted to the value of the first erase pulse using a charge pump in a step-boosting manner, which becomes the initial voltage VL. The magnitude of the voltage increase in each step-boost can be different; for example, the initial increase can be larger, and the increase smaller as it approaches the target value. Alternatively, the magnitude of the voltage increase in each step-boost can be the same, meaning the increase is identical each time.

[0083] Therefore, by using a stepped voltage boost for the first erase pulse, instead of a square wave boost, the threshold voltage Vt of the target memory block can be reduced from shifting in the positive direction, thus preventing over-erasure.

[0084] In some embodiments, applying the i-th erase pulse to the target storage block includes:

[0085] If the i-th erase pulse is not the first erase pulse, then the voltage is boosted to the voltage amplitude of the i-th erase pulse based on the voltage amplitude of the (i-1)-th erase pulse.

[0086] When the i-th erase pulse is not the first erase pulse, it does not need to start with a lower voltage, such as 5V, as in the first erase pulse. Instead, it is boosted to the i-th erase voltage amplitude using a single step-up method based on the voltage amplitude of the (i-1)-th erase pulse. When the i-th erase pulse is not the first erase pulse, the increase in amplitude for each step-up can be the same. The increase in amplitude for incremental pulse erasure is the erase voltage value Vera(i) of the i-th pulse minus the erase voltage value Vera(i-1) of the (i-1)-th pulse.

[0087] Thus, when the i-th erase pulse is not the first erase pulse, the erase pulse voltage can be increased to the value of the i-th erase pulse by an incremental step pulse based on the (i-1)-th erase pulse, instead of increasing the voltage from 5V through multiple incremental step pulses to the value of the i-th erase pulse. This saves the boosting time of the i-th erase pulse, thereby saving the erase time of the memory block.

[0088] In some embodiments, releasing the erase charge of the target storage block includes:

[0089] By turning on the bit lines of the target memory block, the erase charge in each memory cell of the target memory block is released.

[0090] Because charge moves from the floating gate layer or CT into the channel during an erase cycle, after N erase pulses on the target memory block, a large amount of charge accumulates in the channel, causing an increase in the threshold voltage between the source and drain. After the erase pulses are complete, an erase discharge operation is performed to discharge the substrate and gate to the target voltage level, allowing subsequent read or verification operations.

[0091] In some embodiments, such as Figure 3 As shown, the method further includes:

[0092] Step S301: Determine the number of erase pulses N by performing an erase test on the memory.

[0093] Because the number of erase pulses N is affected by product manufacturing processes, materials, and performance, the number of erase pulses N may vary between different products. Therefore, the number of erase pulses can be determined through factory testing before the memory leaves the factory and used as a fixed attribute of the memory.

[0094] The test method for obtaining the number of erase pulses can be silicon testing.

[0095] For example, an integer N = 1, 2, 3... is selected, that is, the sample memory is subjected to 1 erase pulse-discharge cycle, 2 erase pulse-discharge cycles, 3 erase pulse-discharge cycles, etc., until the erasure is successful. By using this method to erase the data in the sample memory, the required number of erase pulses can be verified.

[0096] In practical applications, an erase command can be applied to the test erase block. After applying a specified number of erase pulses, the system can return a result indicating whether the erase was successful. When the first successful erase signal is returned, the number of erase pulses used can be checked and defined as N. If the system returns a verification result indicating erase failure after applying the specified number of erase pulses, the test erase block can be reprogrammed, and the specified number of erase pulses can be updated before resuming the erase process until a successful erase signal is returned.

[0097] In this way, the required number of erase pulses N can be determined in advance through testing and stored in the memory. During the use of the memory, the determined number of erase pulses N can be directly obtained, and then the method in the above embodiment can be used to directly erase.

[0098] In some embodiments, determining the number of erase pulses N by performing an erase test on the memory includes:

[0099] A specified test memory block is sequentially subjected to k erase pulses; where k is an integer greater than or equal to 1;

[0100] Release the erase charge from the storage block;

[0101] A verification pulse is applied to the test memory block to obtain the verification result;

[0102] In response to the verification result indicating successful erasure, the value of k is determined to be the number of erasure pulses N.

[0103] Another method to obtain the number of erase pulses is to apply k erase pulses sequentially to a specified test memory block and then verify the result. If the verification is successful, the number of erase pulses N can be determined. If the verification fails, the test needs to be repeated.

[0104] For example, initially, k=1, meaning one erase pulse is applied to the test memory block and an erase verification is performed. The verification result is an erase failure. Then, k=2 is selected, and two more erase pulses are applied to the test memory block, and another erase verification is performed. The verification result is still an erase failure. Then, k=3 is selected, and three more erase pulses are applied to the test memory block, and another erase verification is performed. This process continues until the verification result is a successful erase. The corresponding k value is defined as the number of erase pulses N for the memory block.

[0105] It should be noted that, for the verification process described above, when performing erase verification with a new k value each time, different test memory blocks can be selected within the same memory. However, these test memory blocks should have the same manufacturing process parameters and materials. Alternatively, the same test memory block can be repeatedly tested. However, it is important to note that after each erase, the test memory block can be reprogrammed and data written back to ensure that the conditions for each erase verification process are consistent.

[0106] In this way, the value of N can be determined through a few simple erase and verification processes, which makes it easy for the memory to directly retrieve the number of erase pulses in subsequent use.

[0107] In some embodiments, determining the number of erase pulses N by performing an erase test on the memory further includes:

[0108] In response to the verification result being an erase failure, k+1 erase pulses are applied sequentially to the test storage block.

[0109] If the erase and verification process of the test storage block fails, the current k value cannot be used as the final erase pulse number N. The k value needs to be updated and the verification needs to be performed again.

[0110] For example, if k=1, and an erase pulse is applied, an erase verification is performed. If the verification result is that the erase failed, the value of k needs to be updated to k=k+1, i.e., k=2, and the verification is performed again. Then, two more erase pulses are applied consecutively to the test memory block, and the erase verification is performed again. If the verification result is still considered an erase failure, the value of k is updated again to k=k+1.

[0111] When the value of k reaches k=5, five more erase pulses are applied consecutively, and then verification is performed. If the verification result is successful, then there is no need to update the value of k. At this point, the value of k is the number of pulses that can be successfully erased. Therefore, k can be determined as the final number of erase pulses.

[0112] Verification using this method of updating the k-value can quickly perform multiple erase verification processes on the test memory block using only simple loop operations, and obtain the final N-value. This method is easy to implement and, due to its ease of programmability, can be applied to large-scale production for accurate verification of each memory or each batch of memory.

[0113] In some embodiments, the erase pulse is generated by a pulse generation module and applied to the substrate of the storage block.

[0114] The erase pulses used during the erasure process can all be generated by a pulse generation module. The pulse generation module consists of two parts: a regulator that provides a stable voltage and a charge pump that provides incremental step pulse boosting. The pulse generation module is part of the control module, which also includes a core module, the pulse generation module, and a logic module. Figure 4 As shown, the control module consists of a core module 401, a pulse generation module 402, and a logic module 403. The pulse generation module 402 may include a regulator and a charge pump, etc. The core module, pulse generation module, and logic module interact to control the erasure process. Their functions and relationships are as follows:

[0115] The core module generates control signals for other voltage sources, such as word line control signals in the X direction and bit line control signals in the Y direction of the three-dimensional memory.

[0116] The pulse generation module is used to generate bias voltages, such as turn-on voltage and erase voltage. Its main function is to generate different voltage sources during the erase process. The regulator within can be used as a charge pump to generate an incrementally stepped pulse-boosted erase voltage, which is applied to the PN trap and maintained for a period of time.

[0117] The logic module is used to generate digital control signals, which act on the core module.

[0118] The core module is the medium connecting the logic module and the pulse generation module. The core module can transmit the digital control signals generated by the logic module to the pulse generation module to control whether the voltage in the pulse generation module is allowed to be applied to the memory block, the discharge process, control the allowed on time of each signal, where it is allowed to be applied, and where it is not allowed to be applied, etc.

[0119] Can the control signals of the logic module control core module be used in the pulse generation module? The erase pulse generated by the erase module is applied to the substrate of the memory, so that the substrate has a high voltage relative to the control gate. Under multiple incremental erase pulses, the charge will gradually move from the floating gate layer or CT to the channel, thereby realizing the erasure of data.

[0120] This application also provides the following examples in its embodiments:

[0121] In one embodiment, such as Figure 5 As shown, the erase process for a storage block is as follows:

[0122] S501: Apply an erase pulse to the memory block;

[0123] S502: Erase and discharge the memory block;

[0124] S503: Apply an erase verification pulse to the storage block to perform erase verification;

[0125] Repeat the above process until the erasure verification is successful, and the erasure process is complete.

[0126] The waveform diagram of the erasure process is as follows: Figure 6 As shown. To prevent over-erasing and affecting device performance, the erase voltage applied during the first erase step in the above erase process should not be too high, such as... Figure 6 As shown, the erasure voltage should be gradually increased from the first erasure voltage, and the second and Nth erasures should be performed until the erasure is successful.

[0127] However, because the first erase voltage should not be too high, the first few erase verifications often failed. But the process of erasing and discharging and erasing verification was still performed multiple times, which affected the block erase time.

[0128] This application proposes the following erasure method to address the above-mentioned problems:

[0129] The waveform diagram of the erasure process is as follows: Figure 7As shown, data in the storage block is erased by sequentially applying multiple erase pulses (1, 2, 3, etc.). After applying multiple erase pulses, an erase discharge is performed, and a verification pulse is applied to confirm that the data erasure of the current storage block was successful.

[0130] In this way, compared with the method of performing erase discharge and verification after each erase pulse, the method in this embodiment can effectively save erasure time and improve memory performance.

[0131] In this embodiment of the application, the obtained number of erase pulses N can be verified as follows:

[0132] like Figure 8 As shown, a discontinuous erase pulse is first used for erasure, and verification is performed after each pulse until the erasure is successful. During this process, the number of consecutive erase pulses is N=0, and the current erase time is recorded.

[0133] Then, using N=2 consecutive erase pulses, if the verification fails, continue to apply discontinuous erase pulses until the erase is successful, and record the current erase time.

[0134] This process is repeated until all erase pulses have been applied consecutively. For example, if the number of consecutive erase pulses is N=5, the erase verification is successful, and the current erase time is recorded.

[0135] Thus, the test results are as follows:

[0136] The minimum number of erase pulses for the test memory block was found to be 5 through silicon testing, i.e., N=5.

[0137] The erase discharge and erase verification processes in the middle 1-4 of the 5 erase pulses were removed to obtain the improved block erase time. The results are shown in Table 1 below. It can be seen that when all 4 erase discharge and erase verification processes in the 5 erase pulses are removed, the block erase time required for this test is the least.

[0138]

[0139] Table 1

[0140] Therefore, in practical applications, the four erase discharge and erase verification processes included in the five erase pulses can be removed, thus saving more block erase time. Using the target block erase method of this application not only reduces block erase time but also does not affect other performance aspects of the storage block.

[0141] like Figure 9 As shown, this application embodiment provides a storage device 900, the device 900 including:

[0142] The memory cell array 910 includes multiple memory cells 911;

[0143] Peripheral circuit 920 is configured as follows:

[0144] Get the number of erase pulses N for erasing data from the target storage block; where N is an integer greater than or equal to 1;

[0145] Erasure pulses are applied sequentially to the target storage block according to the number of erase pulses N;

[0146] After the Nth erase pulse is applied, the erase charge of the target memory block is released.

[0147] In some embodiments, the storage device may be a non-volatile memory product such as a NAND chip.

[0148] like Figure 10 As shown, this application embodiment provides a storage system 1000, which includes: a controller 1001 and a storage device 1002;

[0149] The peripheral circuitry of the storage device is configured to perform the method described in any of the above embodiments.

[0150] In some embodiments, the storage system may be a product such as an SSD (Solid State Disk) or an electronic device containing a storage device, such as a computer device.

[0151] It should be understood that the phrase "one embodiment" or "an embodiment" throughout the specification means that a specific feature, structure, or characteristic related to the embodiment is included in at least one embodiment of this application. Therefore, "in one embodiment" or "in an embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that in the various embodiments of this application, the sequence numbers of the above-described processes do not imply a sequential order of execution; the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application. The sequence numbers of the above-described embodiments are merely descriptive and do not represent the superiority or inferiority of the embodiments.

[0152] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0153] The above description is merely an embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A method for erasing data in a memory, characterized in that, The method includes: Obtain the number of erase pulses N for erasing data on the target storage block; where N is an integer greater than or equal to 1, and the number of erase pulses N is the number of pulses that successfully erase the test storage block in the erase test; the erase test includes: applying k erase pulses continuously to the test storage block, where k is an integer greater than or equal to 1; releasing the erase charge of the test storage block; applying verification pulses to the test storage block to obtain a verification result; in response to the verification result being successful, determining that the value of k is the number of erase pulses N; in response to the verification result being unsuccessful, reapplying k+1 erase pulses continuously to the test storage block; Erasure pulses are applied sequentially to the target storage block according to the number of erase pulses N; After the Nth erase pulse is applied, the erase charge of the target memory block is released.

2. The method according to claim 1, characterized in that, The method further includes: After the erase charge is released, a verification pulse is applied to the target memory block; Based on the verification result corresponding to the verification pulse, it is determined whether the data in the target storage block has been successfully erased.

3. The method according to claim 1, characterized in that, The step of sequentially applying erase pulses to the target storage block according to the erase pulse N includes: Apply the i-th erase pulse to the target memory block; where i is an integer greater than or equal to 1 and less than or equal to N; If i is less than N, then the (i+1)th erase pulse is applied to the target memory block, where i+1 is less than or equal to N; and the voltage value of the (i+1)th erase pulse is greater than the voltage value of the ith erase pulse. If i equals N, then stop applying the erase pulse.

4. The method according to claim 3, characterized in that, Applying the i-th erase pulse to the target storage block includes: If the i-th erase pulse is the first erase pulse, then the voltage is boosted to the voltage amplitude of the first erase pulse through a step-up method.

5. The method according to claim 3, characterized in that, Applying the i-th erase pulse to the target storage block includes: If the i-th erase pulse is not the first erase pulse, then the voltage is boosted to the voltage amplitude of the i-th erase pulse based on the voltage amplitude of the (i-1)-th erase pulse.

6. The method according to claim 1, characterized in that, The process of releasing the erase charge from the target storage block includes: By turning on the bit lines of the target memory block, the erase charge in each memory cell of the target memory block is released.

7. The method according to claim 1, characterized in that, The method further includes: The number of erase pulses N is determined by performing the erase test on the memory.

8. A storage device, characterized in that, The device includes: A memory cell array, comprising multiple memory cells; The peripheral circuitry is configured as follows: Obtain the number of erase pulses N for erasing data on the target storage block; where N is an integer greater than or equal to 1, and the number of erase pulses N is the number of pulses that successfully erase the test storage block in the erase test; the erase test includes: applying k erase pulses continuously to the test storage block, where k is an integer greater than or equal to 1; releasing the erase charge of the test storage block; applying verification pulses to the test storage block to obtain a verification result; in response to the verification result being successful, determining that the value of k is the number of erase pulses N; in response to the verification result being unsuccessful, reapplying k+1 erase pulses continuously to the test storage block; Erasure pulses are applied sequentially to the target storage block according to the number of erase pulses N; After the Nth erase pulse is applied, the erase charge of the target memory block is released.

9. A storage system, characterized in that, The storage system includes: a controller and a storage device; the peripheral circuitry of the storage device is configured to perform the method as described in any one of claims 1 to 7.

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