A memory device, system, information processing method, and readable storage medium

Abstract

A memory device, system, information processing method and readable storage medium are disclosed. A controller in the memory performs the following operations: generating a first fixed format physical address using a first unencrypted physical address; the first fixed format physical address includes a first field storing a Token and a second field storing the first unencrypted physical address; obtaining first CRC data by performing CRC on the first fixed format physical address; replacing the Token with the first CRC data, so that the first fixed format physical address forms a second fixed format physical address; obtaining a first encrypted physical address by encrypting the second fixed format physical address; generating a first encrypted L2P pointer indicating the first encrypted physical address and a first logical address corresponding to the first unencrypted physical address; and sending the first encrypted L2P pointer to a host device, so that a memory cache of the host device caches the first encrypted L2P pointer.

Description

Technical Field

[0001] The present invention relates to the field of memory technology, and in particular to a memory device, system, information processing method and readable storage medium. Background Art

[0002] Memory systems are typically provided as internal semiconductor integrated circuits within computers or other electronic devices. There are many different types of memory, including volatile and non-volatile memory. Volatile memory requires power to maintain its data and includes Random Access Memory (RAM), Dynamic Random Access Memory (DRAM), or Synchronous Dynamic Random Access Memory (SDRAM), among others. Non-volatile memory can retain stored data when power is off, and includes flash memory (Flash Memory), read-only memory (ROM), electrically erasable programmable ROM (EEPROM), static random access memory (SRAM), erasable programmable ROM (EPROM), resistance variable memory such as phase change random access memory (PCRAM), resistive random access memory (RRAM), magnetoresistive random access memory (MRAM) or 3D XPointTM memory, etc.

[0003] Flash memory is used as non-volatile memory for a wide range of electronic applications. Flash memory systems typically include one or more groups of single-transistor, floating gate, or charge-trapping memory cells that allow for high memory density, high reliability, and low power consumption. Two common types of flash memory array architectures include NAND and NOR architectures, named for the logical arrangement of the basic memory cells of each architecture. The memory cells of a memory array are typically arranged in a matrix. In an example, the gate of each floating gate memory cell in a row of a memory array is coupled to an access line (e.g., a word line). In a NOR architecture, the drain of each memory cell in a column of a memory array is coupled to a data line (e.g., a bit line). In a NAND architecture, the drain of each memory cell in a string of a memory array is coupled together in series in a source-to-drain manner between a source line and a bit line. Both NOR and NAND architecture semiconductor memory arrays are accessed through a decoder that activates a particular memory cell by selecting the word line coupled to its gate. In a NOR architecture semiconductor memory array, once a selected memory cell is activated, its data value is placed on the bit line, resulting in different current flows depending on the state in which the particular cell is programmed. In a NAND architecture semiconductor memory array, a high bias voltage is applied to the drain-side select gate (SGD) line. The word line coupled to the gates of the unselected memory cells of each group is driven with a specific pass voltage (e.g., Vpass) to operate the unselected memory cells of each group as pass transistors (e.g., pass current in a manner that is not limited by the data value stored in them). Current then flows from the source line to the bit line through each series-coupled group, limited only by the selected memory cell of each group, placing the currently encoded data value of the selected memory cell on the bit line.

[0004] Each flash memory cell in a NOR or NAND architecture semiconductor memory array can be programmed individually or collectively to one or more programming states. For example, a single-level cell (SLC) can represent one of two programming states (e.g., 1 or 0), representing one data bit. However, a flash memory cell can also represent one of more than two programming states, thereby allowing the manufacture of higher density memories without increasing the number of memory cells because each cell can represent more than one binary digit (e.g., more than one bit). These cells may be referred to as multi-state memory cells, multi-bit cells, or multi-level cells (MLC). In some instances, an MLC may refer to a memory cell that can store two bits of data per cell (e.g., one of four programming states), a triple-level cell (TLC) may refer to a memory cell that can store three bits of data per cell (e.g., one of eight programming states), and a quad-level cell (QLC) may store four bits of data per cell. MLC is used herein in its broader context to refer to any memory cell that can store more than one data bit per cell (i.e., it can represent more than two programming states).

[0005] Such 3D NAND devices typically include a string of memory cells coupled in series (e.g., drain to source) between one or more source-side select gates (SGS) near the source and one or more drain-side select gates (SGD) near the bit line. In an example, the SGS or SGD may include one or more field effect transistors (FETs) or metal oxide semiconductor (MOS) structure devices, etc. In some examples, the string will extend vertically through multiple vertical spacer layers containing corresponding word lines. A semiconductor structure (e.g., a polysilicon structure) may extend adjacent to a string of memory cells to form a channel for the memory cells of the string. In the example of a vertical string, the polysilicon structure may be in the form of a vertically extending column. In some examples, the string may be "folded" and therefore arranged relative to a U-shaped column. In other examples, multiple vertical structures may be stacked on top of each other to form a stacked array of memory cell strings.

[0006] Memory arrays or devices can be combined together to form a storage volume of a memory system, such as a solid state drive (SSD), a universal flash storage (UFS™) device, a multimedia card (MMC) solid-state storage device, an embedded MMC device (eMMC™), etc. An SSD can be used as a main storage device for a computer and has advantages over traditional hard disk drives with moving parts in terms of, for example, performance, size, weight, durability, operating temperature range, and power consumption. For example, an SSD can have reduced seek time, latency, or other delays associated with a magnetic disk drive (e.g., electromechanical). An SSD uses non-volatile memory cells (such as flash memory cells) to eliminate the need for an internal battery power supply, thereby allowing the drive to be more versatile and compact.

[0007] An SSD may include several memory systems, including several dies or logical units (e.g., logical unit numbers or LUNs), and may include one or more processors or other controllers that perform the logic functions required to operate the memory systems or interface with external systems. Such an SSD may include one or more flash memory circuitry dies, wherein the flash memory circuitry dies include several memory arrays and peripheral circuitry thereon. The flash memory array may include several blocks of memory cells organized into several physical pages. In many instances, the SSD will also include DRAM or SRAM (or other forms of memory dies or other memory structures). The SSD may receive commands associated with memory operations from a host, such as read or write operations to transfer data (e.g., user data and associated integrity data, such as error data and address data) between the memory system and the host, or erase operations to erase data from the memory system. Summary of the Invention

[0008] In view of this, the main object of the present invention is to provide a memory device, system, information processing method and readable storage medium that can effectively protect the security of the L2P table and the integrity of data.

[0009] To achieve the above object, the technical solution of the present invention is achieved as follows:

[0010] In a first aspect, the present invention provides a memory device comprising a memory array having a plurality of memory cells, a plurality of word lines, a plurality of bit lines, and a control circuit coupled to the plurality of word lines and the plurality of bit lines; wherein,

[0011] The control circuit is configured to: in response to a first store instruction carrying a first encrypted L2P pointer, determine a selected word line from the plurality of word lines; determine a selected bit line from the plurality of bit lines; determine a selected first memory cell based on the selected word line and the selected word line; and store the first encrypted L2P pointer in the first memory cell;

[0012] Among them, the first encrypted L2P pointer is generated by the controller of the memory system based on the first encrypted physical address and the first logical address corresponding to the first unencrypted physical address; the first encrypted physical address is generated by the controller using the first unencrypted physical address to generate a first fixed format physical address, the first fixed format physical address at least includes a first field for storing a token Token and a second field for storing the first unencrypted physical address, a cyclic redundancy check CRC is performed on the first fixed format physical address to obtain first CRC data containing the same number of bits as the Token, the first CRC data is replaced with the Token in the first field, so that the first fixed format physical address forms a second fixed format physical address, and the second fixed format physical address is encrypted.

[0013] In a second aspect, an embodiment of the present invention further provides a memory system comprising: a memory device for storing data;

[0014] and a controller coupled to the memory device, wherein the controller is programmed to perform operations including:

[0015] Generate a first fixed-format physical address using the first unencrypted physical address; the first fixed-format physical address includes at least a first field for storing a token Token and a second field for storing the first unencrypted physical address;

[0016] Performing a cyclic redundancy check (CRC) on the first fixed-format physical address to obtain first CRC data having the same number of bits as the Token;

[0017] Replacing the Token in the first field with the first CRC data so that the first fixed-format physical address forms a second fixed-format physical address;

[0018] encrypting the second fixed-format physical address to obtain a first encrypted physical address;

[0019] A first encrypted L2P pointer is generated that indicates the first encrypted physical address and a first logical address corresponding to the first unencrypted physical address.

[0020] In a third aspect, the present invention further provides an information processing method, applied to a memory system including a memory device for storing data and a controller coupled to the memory device, the method comprising:

[0021] The controller in the memory system generates a first fixed-format physical address using the first unencrypted physical address; the first fixed-format physical address includes at least a first field for storing a token Token and a second field for storing the first unencrypted physical address;

[0022] The controller performs a cyclic redundancy check (CRC) on the first fixed-format physical address to obtain first CRC data having the same number of bits as the Token;

[0023] The controller replaces the token in the first field with the first CRC data, so that the first fixed-format physical address forms a second fixed-format physical address;

[0024] The controller encrypts the second fixed-format physical address to obtain a first encrypted physical address;

[0025] A first encrypted L2P pointer is generated by the controller indicating the first encrypted physical address and a first logical address corresponding to the first unencrypted physical address.

[0026] In a fourth aspect, an embodiment of the present invention further provides a computer-readable medium, including instructions thereon, which, when executed by a processor, cause the processor to perform the following operations, including:

[0027] Generate a first fixed-format physical address using the first unencrypted physical address; the first fixed-format physical address includes at least a first field for storing a token Token and a second field for storing the first unencrypted physical address;

[0028] Performing a cyclic redundancy check (CRC) on the first fixed-format physical address to obtain first CRC data having the same number of bits as the Token;

[0029] Replacing the Token in the first field with the first CRC data so that the first fixed-format physical address forms a second fixed-format physical address;

[0030] encrypting the second fixed-format physical address to obtain a first encrypted physical address;

[0031] generating a first encrypted L2P pointer indicating the first encrypted physical address and a first logical address corresponding to the first unencrypted physical address;

[0032] The first encrypted L2P pointer is sent to a host device, so that a memory of the host device caches the first encrypted L2P pointer; the host device is a device capable of communicating with the memory system.

[0033] Embodiments of the present invention provide a memory device, system, information processing method, and readable storage medium. The controller in the memory system is programmed to perform the following operations: generating a first fixed-format physical address using a first unencrypted physical address; the first fixed-format physical address comprising at least a first field for storing a token and a second field for storing the first unencrypted physical address; performing a cyclic redundancy check (CRC) on the first fixed-format physical address to obtain first CRC data having the same number of bits as the token; replacing the token in the first field with the first CRC data so that the first fixed-format physical address forms a second fixed-format physical address; encrypting the second fixed-format physical address to obtain a first encrypted physical address; generating a first encrypted L2P pointer indicating the first encrypted physical address and a first logical address corresponding to the first unencrypted physical address; and sending the first encrypted L2P pointer to a host device so that a memory of the host device caches the first encrypted L2P pointer. The host device is a device capable of communicating with the memory system. The memory system provided by the embodiment of the present invention defines L2P data into a fixed format that the memory can recognize. It implements certain data verification by verifying the legitimacy of different parts of the fixed format. It further ensures the security and integrity of the L2P data by performing CRC and encryption on the L2P data. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] In the accompanying drawings, which are not necessarily drawn to scale, like reference numerals may describe similar components in different views. Like numerals with different letter suffixes may represent different instances of similar components. The accompanying drawings generally illustrate various embodiments discussed in this document by way of example and not limitation.

[0035] Figure 1 An example of an environment including a host device and a memory system is provided for illustrating an embodiment of the present invention;

[0036] Figure 2 A schematic diagram of an exemplary memory device including peripheral circuits for some aspects of embodiments of the present invention;

[0037] Figure 3 A perspective view of a portion of an exemplary embodiment of a monolithic three-dimensional memory array provided in accordance with an embodiment of the present invention;

[0038] Figure 4A flowchart of a process 200 for generating an encrypted L2P pointer by the controller 1021 of the memory system 102 and caching the encrypted L2P pointer at the host device 101 according to an embodiment of the present invention is provided;

[0039] Figure 5 A schematic diagram of a process for encrypting a first unencrypted physical address according to an embodiment of the present invention;

[0040] Figure 6 A schematic diagram of the structure of a first fixed-format physical address provided by an embodiment of the present invention;

[0041] Figure 7 The embodiment of the present invention provides Figure 6 A schematic diagram of the encryption process of a physical address in a fixed format;

[0042] Figure 8 A flowchart of a processing flow 300 of a memory system 102 converting an existing first L2P pointer into a first encrypted L2P pointer for caching at a host device 101 according to an embodiment of the present invention is provided;

[0043] Figure 9 A schematic diagram of a process 400 for a memory system 102 to respond to a R / W request using an encrypted L2P pointer stored at the memory system 102 according to an embodiment of the present invention is provided;

[0044] Figure 10 A schematic diagram of a process for decrypting an encrypted physical address by the controller 1021 in the memory system 102 according to an embodiment of the present invention;

[0045] Figure 11 The embodiment of the present invention provides Figure 6 The physical address in the fixed format and the Figure 8 Schematic diagram of the decryption process corresponding to the encryption process in ;

[0046] Figure 12 A schematic diagram of another processing flow 500 of a memory system 102 using an encrypted L2P pointer to respond to a R / W request according to an embodiment of the present invention;

[0047] Figure 13 A schematic diagram of a read process 600 when an encrypted L2P pointer is not cached in the host device 101 according to an embodiment of the present invention;

[0048] Figure 14 A flowchart of an example of a process 700 that may be performed by a memory system and a host device to process a write request according to an embodiment of the present invention;

[0049] Figure 15A flowchart of an example of a process 800 that may be performed by a memory system and a host device to cache a set of L2P pointers at the host device according to an embodiment of the present invention;

[0050] Figure 16 A schematic structural diagram of an application scenario of a memory system 102 and a host device provided by an embodiment of the present invention;

[0051] Figure 17 A block diagram of an example machine 1000 upon which any one or more of the techniques discussed herein may be performed is provided for embodiments of the present invention. DETAILED DESCRIPTION

[0052] Aspects of the present invention relate to a memory system capable of secure caching by a host device, which can be configured to maintain L2P pointers. The L2P pointers associate physical addresses at a memory array in the memory system with logical addresses used by the host device. The L2P pointers can be stored in the memory system using a common data structure, such as an L2P table. Read and write requests made by the host device include logical addresses associated with data units to be read or written. The memory system generates an L2P pointer using the logical addresses and / or accesses a previously generated L2P pointer that associates a logical address with one or more physical addresses in the memory array.

[0053] To maintain persistence, the L2P pointer may be stored in the memory array of the memory system. During the use of the memory system, the L2P pointer is read directly from the memory array. It should be understood that reading the L2P pointer from the memory array takes a long time, and the read and write operations have a large latency. In order to reduce latency, the memory system may also include RAM, and some or all of the L2P pointers may be stored in the controller of the memory system during use to shorten latency. It should be noted that the read operation of accessing the L2P pointer at the controller RAM of the memory system is faster than the read operation of accessing the L2P pointer out of the memory array. It should be noted that for some embodiments, the controller's RAM is relatively small and cannot load the complete L2P table of the memory array. In addition, the controller of some memory systems does not include RAM.

[0054] Based on this, in some embodiments, the memory system is configured to cache part or all of the L2P table at the host device. That is, the L2P pointer may be stored in the host device's RAM. When a read request is made at a logical address, the host device determines whether an L2P pointer corresponding to the logical address is cached. If so, the cached L2P pointer is used to resolve the physical address corresponding to the logical address in the memory system. The host device uses the read request containing the physical address. The memory system responds with the data stored at the physical address.

[0055] Caching the L2P pointer at the host device has the following advantages: it allows faster retrieval of data because the memory system does not need to perform a separate read operation on the memory array to obtain the L2P pointer; it reduces the need for RAM at the memory system because the memory system does not need to separately cache the L2P pointer already cached by the host device.

[0056] However, it should be understood that caching L2P pointers in a host device also poses the risk of exposing physical address results in the memory system. For example, the host device could use cached, unencrypted L2P pointers to infer the memory system's internal read / write algorithms, and thus access unexpected data in the memory system using the physical address in the L2P pointer. Another example is the host device using an invalid L2P pointer, which could cause unexpected changes in the memory system. Invalid L2P pointers can arise from two main sources: intentional or unintentional use of an incorrect L2P pointer by the user; or erroneous transmission of data during the data transmission process, where some portion of the L2P pointer is incorrectly transmitted.

[0057] Aspects of the present invention address this risk by encrypting the L2P pointer cached by the host device. The key concept is that to ensure the data integrity of the L2P pointer, the physical address in the L2P pointer is set to a fixed format recognized by the memory system, encrypted, and CRC-checked to generate an encrypted L2P pointer that can be cached in the host device.

[0058] The host device uses an unencrypted (or plaintext) logical address to access the encrypted L2P pointer cached in the host device, obtaining the encrypted physical address corresponding to the unencrypted logical address. The host device uses the encrypted physical address to make a read or write request (read / write request) to the memory system. Upon receiving the read / write request, the memory system decrypts the encrypted physical address to generate an unencrypted physical address, and then uses the unencrypted physical address to perform the related read and write operations. Because the host device is not granted access to the unencrypted physical address, it is difficult for the host device to infer the memory system's read and write algorithms, derive the memory system's physical address, access meaningless data, or maliciously modify the memory system.

[0059] It should be noted that the unencrypted physical address can also be referred to as the plaintext physical address. The plaintext logical address is also the unencrypted logical address.

[0060] Figure 1An example environment including a host device and a memory system is provided for illustrating embodiments of the present invention. This example environment 100 includes a host device 101 and a memory system 102; the host device 101 communicates with the memory system 102 via a communication interface. The host device 101 and / or the memory system 102 can be included in various products, such as Internet of Things (IoT) devices, such as refrigerators or other devices, sensors, motors, mobile communication devices, automobiles, and autonomous vehicles, to support product processing, communication, or control.

[0061] The memory system 102 includes a controller 1021 and a memory device 1022. Figure 2 As shown, a memory array 1022-1 including a plurality of stacked individual memory dies and a control circuit 1022-2 coupled to the periphery of the memory array 1022-1 is shown, wherein the memory array can be stacked in two dimensions or three dimensions (3D), for example, a stack of two-dimensional or three-dimensional (3D) NAND dies. An illustrative embodiment of the present invention is as follows: Figure 3 shown. Figure 3 A perspective view of a portion of an exemplary solution of a single-block three-dimensional memory array provided by an embodiment of the present invention is shown. It should be noted that the memory array includes multiple memory blocks. Figure 2 Shown is one of the blocks. Figure 3 The memory block 30 includes a plurality of layers stacked on a substrate (not shown) and parallel to the substrate surface. Figure 3 Four word lines (WL) on four layers are shown, which may be denoted as WL0 to WL3. The memory block 30 is also arranged with a plurality of through-holes perpendicular to the word lines. The intersection of a word line and a through-hole forms a memory cell, so a through-hole can also be referred to as a memory cell string. It should be understood by those skilled in the art that the number of word lines of the memory block 30 and the number of memory cell strings are not limited to specific values. For example, the memory block 30 may include 64 word lines, and 64 word lines intersect with a memory cell string to form 64 memory cells along the memory cell string. For another example, the number of memory cell strings included in the memory block 30 may be calculated in the order of hundreds of thousands, millions, or even larger. A word line includes millions of memory cells formed by its intersection with, for example, millions of memory cell strings. The memory cells in the memory block 30 may be single-level memory cells or multi-level memory cells, wherein the single-level memory cells may be single-level cells (SLC) capable of storing 1 bit; the multi-level memory cells may be multi-level cells (MLC) capable of storing 2 bits, triple-level cells (TLC) capable of storing 3 bits, quad-level cells (QLC) capable of storing 4 bits, and quintuple-level cells (PLC) capable of storing 5 bits. Figure 2As shown, the memory block 200 also includes a bit line (BL), a bit line selector (BLS, also known as a top selection gate line SGDL), a source line (SL), and a source selection line (SLS, also known as a bottom selection gate line SGSL). These circuit lines and the word line (WL) together can realize the addressing of any memory cell in the memory block 30.

[0062] In some embodiments, the memory device 1022 further includes a read / write circuit, a row decoder, and a column decoder. In some embodiments, access to the memory array 1022-1 by various peripheral circuits is implemented in a symmetrical manner on opposite sides of the memory array 1022-1, so that the density of access circuits on each side is reduced by half. The read / write circuit includes a plurality of sense blocks SB for reading or programming pages of the memory array 1022-1 in parallel. The memory array 1022-1 can be addressed by word lines via row decoders and bit lines via column decoders. In some embodiments, the memory array 1022-1, the control circuit 1022-2, the read / write circuit, the row decoder, and the column decoder can be manufactured on a chip, wherein Figure 2 The dashed box may also represent a chip, and is transmitted between the controller 1021 and the chip via the signal line 1022-3. Figure 2 It is also shown that a plurality of dummy cells, dummy word lines and dummy bit lines (not shown) are arranged in the dummy storage areas DMX and DMY. Figure 2 The dummy memories DMX1 - DMX2 and DMY1 - DMY2 are arranged along the side of the memory array 1022 - 1 and are used for read / write testing after the memory system is completed.

[0063] Control circuitry 1022-2 is configured to cooperate with the read / write circuitry to perform memory operations on memory array 1022-1. The control circuitry includes a state machine, an on-chip address decoder, and a power control module. The state machine is configured to provide chip-level control of memory operations; the on-chip address decoder is configured to provide an address interface between addresses used by a host or memory system controller and hardware addresses used by a row decoder and a column decoder. The power control module is configured to control the power and voltage supplied to the word lines and bit lines during each memory operation.

[0064] In some embodiments, the memory device may further include a memory array having a plurality of memory cells, a plurality of word lines, a plurality of bit lines, and a control circuit coupled to the plurality of word lines and the plurality of bit lines; wherein,

[0065] The control circuit may be configured to: in response to a first storage instruction carrying a first encrypted L2P pointer, determine a selected word line from the plurality of word lines; determine a selected bit line from the plurality of bit lines; determine a selected first memory cell based on the selected word line and the selected word line; and store the first encrypted L2P pointer in the first memory cell;

[0066] Among them, the first encrypted L2P pointer is generated by the controller of the memory system based on the first encrypted physical address and the first logical address corresponding to the first unencrypted physical address; the first encrypted physical address is generated by the controller using the first unencrypted physical address to generate a first fixed format physical address, the first fixed format physical address at least includes a first field for storing a token Token and a second field for storing the first unencrypted physical address, a cyclic redundancy check CRC is performed on the first fixed format physical address to obtain first CRC data containing the same number of bits as the Token, the first CRC data is replaced with the Token in the first field, so that the first fixed format physical address forms a second fixed format physical address, and the second fixed format physical address is encrypted.

[0067] What is described here is that, in response to a first storage instruction carrying a first encrypted L2P pointer transmitted by controller 1021 via signal line 1022-3, control circuit 1022-2 selects, via the read / write circuit, row decoder, and column decoder, a first memory cell at the intersection of a word line and a selected bit line from memory array 1022-1, i.e., the selected first memory cell. The control circuit then stores the first encrypted L2P pointer in the first memory cell, i.e., the first encrypted L2P pointer is stored in memory array 1022-1. The specific method for obtaining the first encrypted L2P pointer will be described in detail later and will not be repeated here. Furthermore, it should be understood that the term "first memory cell" may include one or more first memory cells.

[0068] In some other embodiments, the control circuit may be further controlled to: store the encrypted L2P table including the plurality of first encrypted L2P pointers in response to the second storage instruction, that is, store the encrypted L2P table in the memory array 1022-1.

[0069] In some embodiments, the control circuit can also be controlled to: in response to a read instruction or a write instruction including the first unencrypted physical address, obtain a selected second memory cell from the plurality of word lines and the plurality of bit lines, and read data from or write data to the second memory cell. This is a conventional function of a memory array, reading or writing data to or from the memory array. As described above, there can also be one or more second memory cells.

[0070] In some embodiments, the memory array may be a three-dimensional NAND memory array; and the memory system may be a three-dimensional NAND memory device.

[0071] For memory devices, in 3D architecture semiconductor memory technology, vertical structures are stacked to increase the number of layers and physical pages, thereby increasing the density of the memory system. In one embodiment, memory system 102 can be a discrete memory or memory component of the host device. In other embodiments, memory system 102 can also be part of an integrated circuit, such as a system on a chip (SOC). In this case, memory system 102 is stacked or otherwise assembled with one or more components of host device 101.

[0072] exist Figure 1 In the environment example 100, the host device 101 may include a processor 1011 and a host RAM 1012, wherein the host RAM 1012 may include DRAM, SDRAM or any other suitable volatile or non-volatile memory device. One or more communication interfaces may be provided on the memory system 102 to communicate with one or more components in the host device 101. The one or more components in the host device 101 may be a Serial Advanced Technology Attachment (SATA) interface, a Peripheral Component Interconnect Express (PCIe) interface, a Universal Serial Bus (USB) interface, a Universal Flash Storage (UFS) interface, an eMMC TM The host device 101 may also include electronic components, a memory card reader, or one or more other electronic components external to the memory system 102. In some embodiments, the host device 101 may be a reference Figure 17 In addition, Figure 16 Additional examples in host device 101 are discussed in .

[0073] Figure 1The operating principles of the environment example 100 in FIG. 1 are as follows: the controller 1021 can receive instructions from the host device 101 and communicate with the memory device 1022. For example, the controller 1021 can execute a write or erase instruction to transfer data to one or more memory cells, planes, sub-blocks, blocks, or pages in the memory device 1022; or the controller 1021 can execute a read instruction to transfer data to the host device 101. In hardware, the controller 1021 may include one or more controller units, circuits, or components configured to control access across the memory device 1022 and provide a translation layer between the host device 101 and the memory system 102. The controller 1021 may also include one or more input / output (I / O) circuits, lines, or interfaces to transfer data to or from the memory device 1022. The controller 1021 may also include a memory management unit 1021-1 and an array control unit 1021-2.

[0074] The memory management unit 1021-1 may include circuit hardware or firmware, such as multiple components or integrated circuits associated with various memory management functions. To describe the technical solutions of the present invention, NAND memory is used as an example to describe example memory operations or management functions. Those skilled in the art will appreciate that other forms of non-volatile memory may have similar memory operations or management functions. NAND memory management functions may include wear leveling, such as garbage collection or recycling, error detection or correction, block retirement, or one or more other memory management functions. The memory management unit 1021-1 may process instructions from the host device 101 into commands recognizable by the memory system 102, such as parsing or formatting instructions received from the host device 101 into commands related to the operation of the memory device 1022. Alternatively, the memory management unit 1021-1 may generate device commands for the array control unit 1021-2 or one or more other components of the memory system 102, such as commands that implement various memory management functions.

[0075] The memory management unit 1021-1 may be configured to include a set of management tables 130 for maintaining various information associated with one or more components of the memory system 102, such as various information related to a memory array or one or more memory cells coupled to the controller 1021. For example, the management tables 130 may include information such as the block age, block erase count, error history, or one or more error counts of one or more blocks of memory cells coupled to the controller 1021. Error counts may include operation error counts, read bit error counts, and the like. In some embodiments, if the detected error count is above a certain threshold, the bit error is considered uncorrectable. In some embodiments, the management tables 130 may maintain counts of correctable or uncorrectable bit errors.

[0076] The management table 130 may also include one or more L2P tables, each containing one or more L2P pointers that associate logical addresses with physical addresses in the memory array of the memory device 1022. In some embodiments, the management table 130 may include an unencrypted L2P table and / or an encrypted L2P table. An unencrypted L2P table may include an L2P pointer indicating an unencrypted logical address and an unencrypted physical address; an encrypted L2P table may include an encrypted physical address and an encrypted L2P pointer indicating an unencrypted logical address. In actual implementation, the management table 130 may be stored in the memory management unit 1021-1, meaning that the management table 130 may be stored in the RAM of the controller 1021. In other embodiments, the management table 130 may also be stored in the memory array of the memory device 1022. During use, the memory management unit 1021-1 may read part or all of the cached management table 130 from the RAM of the controller 1021, or may read the management table 130 from the memory array of the memory device 1022.

[0077] The array control unit 1021-2 may include circuit systems or components configured to control and perform the following memory operations, such as controlling the writing of data to one or more memory cells in the memory system 102 coupled to the controller 1021, reading data from the one or more memory cells, or erasing the one or more memory cells. The array control unit 1021-2 may receive commands sent by the host device 101 or host commands generated internally by the memory management unit 1021-1. The host commands may be commands associated with wear leveling, error detection or correction, etc.

[0078] The array control unit 1021-2 may also include an error correction code (ECC) component 140, which may include an ECC engine or other circuitry for detecting or correcting errors associated with writing data to or reading data from one or more memory cells in a memory system 102 coupled to the controller 1021. The controller 1021 is configured to effectively detect and recover from error events associated with various operations or data storage, such as bit errors, operational errors, etc., while maintaining the integrity of data transmitted between the host device 101 and the memory system 102, or maintaining the integrity of stored data, such as by using redundant RAID storage, etc., and removing, such as retiring, failed memory resources, such as memory cells, memory arrays, pages, blocks, etc., to prevent future errors.

[0079] exist Figure 1 In the environment example 100, the controller 1021 also includes an encryption and decryption unit 141, which is configured to perform cryptographic operations on data, such as encrypting an unencrypted physical address and decrypting an encrypted physical address as described in the present invention. In some embodiments, the encryption and decryption unit may include one or more registers and one or more math engines, wherein the registers are used to store cryptographic information for performing cryptographic operations, such as the aforementioned tokens, random numbers, etc.; the math engines are used to perform cryptographic operations using tokens and random numbers, such as generating a fixed-format physical address with a token field, performing a CRC check on the fixed-format physical address, placing the CRC data token at the fixed-format physical address, and then performing an encryption operation on the fixed-format physical address. In some embodiments, the encryption and decryption unit may be implemented in hardware, software, or a combination of hardware and software. For example, the encryption and decryption unit may include instructions executed by a processor or similar hardware component of the controller 1021. In some embodiments, the encryption and decryption unit may include repurposed hardware for performing cryptographic operations.

[0080] The memory array in the memory device 1022 may include, for example, a number of memory cells arranged in one or more devices, one or more planes, one or more sub-blocks, one or more blocks, one or more pages, and the like. As an example, a 48GB TLC NAND memory system may include 18,592 bytes (B) of data per page (16,384 + 2,208 bytes), 1,536 pages per block, 548 blocks per plane, and 4 or more planes per device. As another example, a 32GB MLC memory system (storing two bits of data per cell (i.e., 4 programmable states)) may include 18,592 bytes (B) of data per page (16,384 + 2,208 bytes), 1,024 pages per block, 548 blocks per plane, and 4 planes per device, but with half the required write time and twice the program / erase (P / E) cycles compared to a corresponding TLC memory system. Other examples may include other numbers or arrangements. In some examples, a memory system or a portion thereof can selectively operate in an SLC mode or in an MLC mode (eg, TLC, QLC, etc.) as desired.

[0081] The memory array in the memory device 1022 includes physical address locations 150A, 150B, and 150N. A physical address location is a location on the memory array in the memory device 1022 that is uniquely associated with a physical address. In operation, data is typically written to or read from the memory system 102 in units of pages and erased in units of blocks. For example, the physical address locations 150A, 150B, and 150N may correspond to pages. However, one or more memory operations (e.g., read, write, erase, etc.) may be performed on larger or smaller groups of memory cells as needed. Therefore, in some examples, the physical address locations 150A, 150B, and 150N include more or less than a page. The data transfer size of the memory system 102 is typically referred to as a page, while the data transfer size of the host is typically referred to as a sector.

[0082] Although a page of data may include several bytes of user data (e.g., a data payload comprising several data sectors) and its corresponding metadata, the size of the page generally refers only to the number of bytes used to store the user data. As an example, a data page with a page size of 4KB may include 4KB of user data (e.g., 8 sectors with a sector size of 512B) and several bytes (e.g., 32B, 54B, 224B, etc.) of metadata corresponding to the user data, such as integrity data (e.g., error detection or correction code data), address data (e.g., logical address data, etc.), or other metadata associated with the user data. The physical address locations used to store metadata, etc. may be referred to as over-provisioned physical address locations.

[0083] Different types of memory cells or the memory devices 1022 may provide different page sizes or may require different amounts of metadata associated therewith. For example, different memory system types may have different bit error rates, which may result in different amounts of metadata required to ensure the integrity of a data page (e.g., a memory system with a higher bit error rate may require more bytes of error correction code data than a memory system with a lower bit error rate). For example, a multi-level cell (MLC) NAND flash device may have a higher bit error rate than a corresponding single-level cell (SLC) NAND flash device. Thus, an MLC device may require more bytes of metadata for error data than a corresponding SLC device.

[0084] Figure 1 The environment example 100 also illustrates that the encrypted L2P pointer can be cached at the host device 101. The controller 1021 of the memory system 102 generates the encrypted L2P pointer. In some embodiments, the memory system 102 generates the encrypted L2P pointer from the L2P pointer stored at the L2P table. The L2P pointer includes an unencrypted logical address and an unencrypted physical address that references the physical address locations 150A, 150B, ... 150N. The memory system 102 uses the aforementioned encryption and decryption unit to generate an encrypted physical address from the unencrypted physical address. The encrypted physical address and the unencrypted logical address are then combined to generate an encrypted L2P pointer. The encrypted L2P pointer is sent to the host device 101, where it is cached in the RAM of the host device 101. The processor of the host device 101 sends a R / W request to the memory system 102, wherein the read / write (R / W) request includes the encrypted physical address. The controller 1021 of the memory system 102 receives the R / W request, decrypts the encrypted physical address, and finally executes the R / W request using the unencrypted physical address.

[0085] Based on the aforementioned environment example 100, Figure 4 , which is a flow chart illustrating a process flow 200 in which the controller 1021 of the memory system 102 generates an encrypted L2P pointer and caches the encrypted L2P pointer at the host device 101 .

[0086] In step 2001, the controller 1021 of the memory system 102 generates a first encrypted physical address. The controller 1021 may obtain a first unencrypted physical address from the memory device 1022 and use an encryption / decryption unit in the controller 1021 to generate a first encrypted physical address from the first unencrypted physical address.

[0087] In some embodiments, step 2001, as Figure 5 As shown, this may include:

[0088] 2001-1: Generate a first fixed-format physical address using the first unencrypted physical address; the first fixed-format physical address includes at least a first field for storing a token Token and a second field for storing the first unencrypted physical address;

[0089] 2001-2: performing a cyclic redundancy check (CRC) on the first fixed-format physical address to obtain first CRC data having the same number of bits as the Token;

[0090] 2001-3: replacing the Token in the first field with the first CRC data, so that the first fixed-format physical address becomes a second fixed-format physical address;

[0091] 2001-4: Encrypt the second fixed-format physical address to obtain a first encrypted physical address.

[0092] Here, the first fixed format physical address may refer to a physical address containing a fixed field that can be recognized by the controller 1021. For example, the first fixed format physical address may contain 64 bits, and the 64 bits may be divided into a first field and a second field containing two 32 bits. The first field may be used to place a Token; the second field may be used to place a first unencrypted physical address. It should be noted that the first field may also be divided into multiple subfields for placing different data, such as the offset and consecutive number of logical addresses. However, it must be noted that the data placed in the multiple subfields must include a Token. In some embodiments, considering the processing speed issue, the Token preferably occupies 16 bits. The other data occupies a total of 16 bits. The specific format, as an optional implementation, is as follows. Figure 6 shown.

[0093] The encryption method described here can be: first encapsulating the first unencrypted physical address to form a first fixed-format physical address in a fixed format; then, performing a CRC check on all or part of the fields of the first fixed-format physical address to obtain first CRC data that is identical to the bits occupied by the token; then, replacing the token in the first fixed-format physical address with the first CRC data to form a second fixed-format physical address; and finally, encrypting the second fixed-format physical address to obtain a first encrypted physical address. Preferably, the CRC check is performed on all fields of the first fixed-format physical address.

[0094] The encrypting the second fixed-format physical address to obtain the first encrypted physical address may include: the controller using a random number to perform an XOR encryption on the second fixed-format physical address to obtain the first encrypted physical address.

[0095] Here, the number of bits contained in the random number is not limited. In actual use, when the first fixed-format physical address and the second fixed-format physical address are 64 bits, the random number can be used to XOR-encrypt the second fixed-format physical address using an 8-byte seed. Alternatively, a random number of any number of bits can be used to XOR-encrypt the two fixed-format physical addresses, as long as the same random number is used to XOR-decrypt the physical address to be identified obtained later.

[0096] Based on the process described above, Figure 7 Shows the use of Figure 6 The encryption process of the fixed format physical address in .

[0097] It should be noted that the Token, the first CRC data and the random number used in the aforementioned encryption process of the first unencrypted physical address need to be stored by the memory system 102 for subsequent decryption.

[0098] In some embodiments, the controller 1021 is further configured to perform the following operations, including: generating an association relationship between the first logical address and the token, the first CRC data, and the random number, and storing the association relationship. The association relationship should be stored in a location in the memory system 101 that is inaccessible to the host device 101, and may be stored in a RAM or memory array of the controller in the memory system.

[0099] In some embodiments, the first unencrypted physical address can be obtained as follows: the controller 1021 reads a first L2P pointer from an L2P table stored at the memory array; the first L2P pointer indicates the first logical address and the first unencrypted physical address at the memory array associated with the first logical address.

[0100] In step 2002, the controller 1021 of the memory system 102 generates a first encrypted L2P pointer indicating the first encrypted physical address and a first logical address corresponding to the first unencrypted physical address. The controller 1021 may generate the first encrypted L2P pointer by generating a data structure including an indication of the first encrypted physical address and an indication corresponding to the first logical address. In some embodiments, the controller 1021 may also generate the first encrypted L2P pointer from an existing L2P pointer, specifically by replacing the first unencrypted physical address at the location of the existing L2P pointer with the first encrypted physical address.

[0101] In some embodiments, the memory device includes a memory array having a plurality of memory cells, a plurality of word lines, a plurality of bit lines, and a control circuit coupled to the plurality of word lines and the plurality of bit lines; wherein the control circuit can be configured to: in response to a store instruction carrying a first encrypted L2P pointer, store the first encrypted L2P pointer in a selected first memory cell. The first memory cell can be determined by a controller by sending a first store instruction to the control circuit, whereupon the control circuit, in response to the first store instruction carrying the first encrypted L2P pointer, determines a selected word line from the plurality of word lines; determines a selected bit line from the plurality of bit lines; and determines the selected bit line based on the selected word line and the selected word line.

[0102] In some other embodiments, the control circuit is further controlled to:

[0103] In response to the second storage instruction, an encrypted L2P table including a plurality of the first encrypted L2P pointers is stored.

[0104] In step 2003, the controller 1021 of the memory system 102 sends a first encrypted L2P pointer to the host device 101 for caching by the host device 101. The first encrypted L2P pointer may be sent to the host device 101 using any suitable protocol or standard and in any suitable manner. In some embodiments, the first encrypted L2P pointer may be sent to the host device 101 using a portion of the host memory buffer (HMB) feature supported by the Non-Volatile Memory Express (NVMe) standard implemented on a PCIe bus.

[0105] In other embodiments, Figure 8 , which is a flow chart illustrating a process 300 of converting an existing first L2P pointer into a first encrypted L2P pointer for caching at the host device 101 by the memory system 102. The process 300 may also be executed in the controller 1021.

[0106] In step 3001 , the controller 1021 of the memory system 102 reads a first L2P pointer from an L2P table stored in a memory array in the memory device 1022 .

[0107] In step 3002, the first L2P pointer is converted into a first encrypted L2P pointer. This may specifically include generating the first encrypted physical address using the first unencrypted physical address indicated by the first L2P pointer. The specific generation method is as described above and will not be repeated here. The controller 1021 of the memory system 102 then merges the first encrypted physical address with the first L2P pointer to generate the first encrypted L2P pointer. In this case, the first encrypted L2P pointer includes both the first unencrypted physical address and the first encrypted physical address. In other embodiments, the controller 1021 of the memory system 102 may also replace the first unencrypted physical address with the first encrypted physical address to form the first encrypted L2P pointer. In this case, the first encrypted L2P pointer does not include the first unencrypted physical address.

[0108] After obtaining the first encrypted L2P pointer, controller 1021 may perform various operations on it. For example, as described in step 3003, the first encrypted L2P pointer may be written into an L2P table to form an encrypted L2P table. In some embodiments, the encrypted L2P table may include encrypted L2P pointers and / or unencrypted L2P pointers. In actual use, the encrypted L2P table may be stored in a memory array within memory device 1022 and / or in RAM within controller 1021. In some embodiments, as described in step 3004, the encrypted L2P table may also be partially or fully cached by host device 101.

[0109] In some embodiments, the memory system 102 allows maintaining an encrypted L2P table in advance, so as to increase the speed at which the host device 101 caches the encrypted L2P pointer.

[0110] Specifically, the encrypted L2P table may be generated by the controller 1021 of the memory system 102 and include multiple first encrypted L2P pointers. The encrypted L2P table may be sent by the controller 1021 to the host device so that the host device's memory caches part or all of the encrypted L2P table.

[0111] When the encrypted L2P table already exists, the processing flow of the memory system 102 responding to the R / W request can be as follows: Figure 9 , which shows a schematic diagram of a processing flow 400 in which the memory system 102 responds to a R / W request using an encrypted L2P pointer stored at the memory system 102 .

[0112] In step 4001, the controller 1021 of the memory system 102 receives (and / or generates) a R / W request including a logical address. In step 4002, the controller 1021 of the memory system 102 uses the logical address to access or generate an encrypted L2P pointer. For example, if the R / W request is a read request, the controller 1021 of the memory system 102 uses the logical address to locate the encrypted L2P pointer at the encrypted L2P table. If the R / W request is a write request, the controller 1021 of the memory system 102 selects a physical address location for storing the data included in the write request. The controller 1021 of the memory system 102 converts the physical address of the physical address location into an encrypted physical address and generates an encrypted L2P pointer to indicate the physical address and logical address included in the write request.

[0113] In step 4003, the controller 1021 of the memory system 102 processes the R / W request using the encrypted L2P pointer. For example, if the R / W request is a read request, the memory system decrypts the encrypted physical address included in the R / W request to generate an unencrypted physical address. The controller 1021 of the memory system 102 obtains the data stored at the physical address location associated with the unencrypted physical address and returns the data to the initiator of the read request. If the R / W request is a write request, the memory system writes the data included in the R / W request to the unencrypted physical address associated with the encrypted physical address and stores the encrypted physical address in the encrypted L2P table.

[0114] In the processing flow 400 , whether reading or writing, whether the encrypted L2P read can be trusted and how to decrypt the encrypted physical address after obtaining it.

[0115] In some embodiments, as Figure 10 As shown, the controller 1021 may perform the following operations to determine whether the read encrypted L2P address can be trusted and how to decrypt the encrypted physical address:

[0116] 4003-1: Receive a read request or a write request including a to-be-identified encrypted physical address from the host device; the to-be-identified encrypted physical address is obtained by the host device accessing a first encrypted L2P pointer in part or all of the encrypted L2P table stored in the memory based on the first logical address;

[0117] 4003-2: Using the stored random number, perform XOR decryption on the encrypted physical address to be identified to obtain a third fixed-format physical address;

[0118] 4003-3: Use the stored Token to replace the data in the first field of the third fixed-format physical address, so that the third fixed-format physical address becomes a fourth fixed-format physical address;

[0119] 4003-4: Perform CRC on the fourth fixed-format physical address to obtain second CRC data having the same number of bits as the stored Token;

[0120] 4003-5: Compare the first CRC data and the second CRC data;

[0121] 4003-6: Determine whether to trust the first encrypted L2P pointer in part or all of the encrypted L2P table stored in the memory based on the comparison result.

[0122] For step 4003-6, if the first CRC data is consistent with the second CRC data, trust the first encrypted L2P pointer in part or all of the encrypted L2P table stored in the memory; generate the first unencrypted physical address based on the fourth fixed-format physical address;

[0123] When the first CRC data is inconsistent with the second CRC data, the first encrypted L2P pointer in part or all of the encrypted L2P table stored in the memory is not trusted; the first L2P pointer is re-read from the L2P table stored in the memory array based on the first logical address; and the first unencrypted physical address is obtained based on the first L2P pointer.

[0124] After obtaining the first unencrypted physical address, in some embodiments, the controller 1021 is further programmed to perform the following operations, including:

[0125] Retrieving data from the memory array based on the first unencrypted physical address; sending the data to the host device, or storing the data included in the write request in the location indicated by the first unencrypted physical address in the memory array, that is, performing a read / write operation.

[0126] The decryption process here is the inverse process of the aforementioned encryption process, specifically: first use the stored random number to perform XOR decryption on the obtained encrypted physical address to be identified to obtain a third fixed format physical address, use the stored Token to replace the data in the first field of the third fixed format physical address to obtain a fourth fixed format physical address, and then perform CRC check on the fourth fixed format physical address to obtain second CRC data, compare the stored first CRC data and the second CRC data, and trust the read encrypted L2P pointer when the first CRC data is consistent with the second CRC data; perform read and write operations based on the first unencrypted physical address in the fourth fixed format physical address; when the first CRC data is inconsistent with the second CRC data, do not trust the read encrypted L2P pointer, and re-read the unencrypted first L2P pointer from the memory array in the memory device 1022 to obtain the first unencrypted physical address, and then perform read and write operations again.

[0127] For example, in a fixed format physical address uses Figure 6 When the format is in , and the encryption is Figure 7 The decryption process can be as follows: Figure 11 shown.

[0128] In other embodiments, the encrypted L2P table may be cached at the host device 101. In this case, the processing flow of the R / W request may be as follows: Figure 12 , which is a schematic diagram showing another processing flow 500 of the memory system 102 responding to a R / W request using an encrypted L2P pointer.

[0129] exist Figure 12 In FIG. 5 , the processing flow 500 includes two columns 501 and 502 .

[0130] Column 501 includes operations performed by a host device, such as host device 101. Column 502 includes operations performed by a memory system, such as memory system 102. In process flow 500, one or more encrypted L2P pointers may be cached at host device 102. The logical addresses of the cached L2P pointers are unencrypted to the host device. The physical addresses of the cached L2P pointers are encrypted to host device 101.

[0131] In step 5011, the host device 101 generates a read request indicating a logical address. The read request may be generated by an operating system of the host device 101 and / or may be received from an application executing at the host device 101. In step 5012, the host device 101 searches one or more encrypted L2P pointers cached at the host device to determine whether any of the cached encrypted L2P pointers indicates the logical address from the read request. If none of the cached encrypted L2P pointers indicates the logical address, the host device 101 and the memory system 102 perform an uncached read request routine, for which the specific process may be referred to. Figure 11 Describes the request routine when the instance does not cache the encrypted L2P pointer.

[0132] If an encrypted L2P pointer indicating a logical address is identified at step 5012, host device 101 accesses the cached L2P pointer at step 5013. At step 5014, host device 101 sends a read request including the encrypted physical address indicated by the encrypted L2P pointer to memory system 102.

[0133] In step 5021, the memory system 102 receives a read request including an encrypted physical address. In step 5022, the memory system 102 generates an unencrypted physical address from the encrypted physical address. If the cached encrypted L2P pointer is trusted, the memory system 102 performs a read operation using the unencrypted physical address and returns the data (step 5023). If the cached encrypted L2P pointer is trusted, the memory system 102 re-reads the L2P pointer from the L2P table stored in the memory array based on the logical address. The unencrypted physical address is obtained based on the L2P pointer, and the read operation is performed using the unencrypted physical address and returns the data (step 5023). The specific decryption and judgment process has been described above and will not be repeated here.

[0134] In the above description, the host device caches the encrypted L2P pointer reading process. Figure 13 Schematic diagram of a read processing flow 600 when the encrypted L2P pointer is not cached in the host device 101 is shown.

[0135] The process 600 can be performed in the above Figure 12 Process flow 600 includes two columns 601 and 602. Column 601 includes operations performed by a memory system, such as memory system 102. Column 602 includes operations performed by a host device, such as host device 101.

[0136] In step 6021, host device 101 sends a read request to memory system 102. The read request includes a logical address. In some examples, the read request may be or be based on a read request generated by an operating system of host device 101 and / or an application executed at the host device.

[0137] In step 6011, the memory system 102 receives the aforementioned read request. In step 6012, the memory system 102 determines the unencrypted physical address associated with the logical address included in the read request. Here, the unencrypted physical address is obtained from the memory array in the memory device 1022. Next, if there is no encrypted L2P pointer corresponding to the logical address in the memory system 102, it is necessary to generate an encrypted L2P pointer corresponding to the logical address based on the obtained unencrypted physical address and the logical address. The specific generation steps are described in the aforementioned Figure 5 As described in

[15] , details will not be repeated here. If an encrypted L2P pointer corresponding to the logical address is stored in the memory system 102, it is necessary to access the encrypted L2P table stored in the RAM of the memory device 1022 and / or the controller 1021 to obtain the encrypted L2P pointer. This means that in step 6013, an encrypted logical-to-physical pointer corresponding to the logical address is generated or accessed. This means that if the encrypted L2P pointer is already stored in the memory system, the memory system reads the encrypted L2P pointer. If the encrypted L2P pointer is not yet stored in the memory system, the memory system generates the encrypted L2P pointer. As described herein, in step 6014, the memory system sends the data read based on the obtained unencrypted physical address and the obtained encrypted L2P pointer to the host device 101. In step 6022, the host device 101 caches the encrypted L2P pointer.

[0138] The above description is the processing flow of read request. Figure 14 , which shows a flow chart of an example of a process flow 700 that can be performed by a memory system and a host device to process a write request. Process flow 700 includes two columns 701 and 702. Column 701 includes operations performed by a memory system, such as memory system 102. Column 702 includes operations performed by a host device, such as host device 105.

[0139] In step 7021, the host device sends a write request to the memory system. The write request includes a logical address and data to be stored in association with the logical address. In some instances, the write request is or is based on a write request generated by an operating system of the host device and / or an application executed at the host device.

[0140] In step 7011, the memory system receives a write request and selects an unencrypted physical address to be associated with the logical address indicated by the write request. In step 7012, the memory system writes data to the unencrypted physical address location indicated by the physical address. In step 7013, the memory system generates an encrypted L2P pointer for the logical address. The memory system generates the encrypted L2P pointer as described herein. In step 7014, the memory system sends the encrypted L2P pointer to the host device. Optionally, the memory system also sends a write confirmation to the host device indicating that the requested write was successful. In step 7022, the host device caches the encrypted L2P pointer.

[0141] Figure 13 and 14 An example is shown in which a memory system provides encrypted L2P pointers for caching to a host device during transactions involving corresponding logical and physical addresses (e.g., read requests and write requests). In some examples, the host device requests a set of L2P pointers corresponding to a set of multiple logical addresses. Specifically, Figure 15 shown. Figure 15 FIG1 is a flow chart illustrating an example of a process flow 800 that may be performed by a memory system and a host device to cache a set of L2P pointers at the host device. The process flow 800 includes two columns 801 and 802. Column 801 includes operations performed by a memory system, such as memory system 102. Column 802 includes operations performed by a host device, such as host device 105.

[0142] At operation 802, the host device sends a request for a set of encrypted L2P pointers to the memory system. The request may include, for example, a set of logical addresses. In step 8011, the memory system receives the request. In step 8012, the memory system generates or accesses a set of encrypted L2P pointers corresponding to the set of physical addresses included in the request. The encrypted L2P pointers for some or all of the logical addresses included in the request may already be stored at the memory system. For example, the memory system may store an encrypted L2P table, as described herein. If there are some logical addresses in the request for which the storage system has not yet stored corresponding encrypted L2P pointers, the storage system generates L2P pointers for these logical addresses, as described herein. In step 8013, the memory system sends the encrypted L2P pointers corresponding to the logical addresses in the request to the host device. In step 8022, the host device caches the encrypted L2P pointers.

[0143] Based on the aforementioned various examples of the memory system 102 and the host device 101, Figure 16 FIG. 1 shows a schematic diagram of a structure of an application scenario of the aforementioned memory system 102 and a host device. Figure 14In the application scenario shown, the storage system 102 and host device 101 disclosed herein can be part of one or more devices 930-950. A device includes any device that can include a host device such as host device 101. Host device 101 can be any device that can execute instructions (in sequence or otherwise). For example, the device is a vehicle 930, and the memory system and the host device 101 can be part of an infotainment system, a control system, etc.; for another example, the device includes an unmanned aircraft 950, and the memory system and the host device 101 disclosed herein can be part of a control system; for another example, if the device is smart furniture or equipment 940, the memory system and the host device 101 disclosed herein can be part of a sensor system, an entertainment or infotainment system, etc. In other examples, although not shown, the device may include aviation, marine, Internet of Things (IoT), and other devices.

[0144] Figure 17 A block diagram of an example machine 1000 is shown on which any one or more techniques (e.g., methods) discussed herein may be performed. In alternative embodiments, the machine 1000 may operate as a standalone device or may be connected (e.g., networked) to other machines. In a network deployment, the machine 1000 may operate as a server machine, a client machine, or both in a server-client network environment. In an example, the machine 1000 may act as a peer machine in a peer-to-peer (P2P) (or other distributed) network environment. The machine 1000 may be a personal computer (PC), a tablet PC, a set-top box (STB), a personal digital assistant (PDA), a mobile phone, a network appliance, an IoT device, an automotive system, or any machine capable of executing instructions (in sequence or otherwise) specifying actions to be taken by the machine. Furthermore, although only a single machine is shown, the term "machine" should also be construed to include any collection of machines that, alone or in combination, execute an instruction set (or multiple instruction sets) to perform any one or more of the methods discussed herein, such as cloud computing, software as a service (SaaS), or other computer cluster configurations.

[0145] As described herein, an example may include logic, components, devices, packages, or mechanisms, or may be operated by them. A circuit system is a collection of circuits (e.g., a group of circuits) implemented in a tangible entity including hardware (e.g., simple circuits, gates, logic, etc.). The membership of a circuit system can change flexibly over time and with potential hardware variability. A circuit system includes members that can perform specific tasks individually or in combination when in operation. In an example, the hardware of the circuit system can be designed to perform specific operations (e.g., hardwired) invariably. In an example, the hardware of the circuit system may include variably connected physical components (e.g., execution units, transistors, simple circuits, etc.), which include computer-readable media that are physically modified (e.g., magnetically, electrically, movably placed particles of constant mass, etc.) to encode instructions for specific operations. When the physical components are connected, the basic electrical properties of the hardware components change, such as from an insulator to a conductor, and vice versa. The instructions enable the addition of hardware (e.g., execution units or loading mechanisms) to create members of the circuit system in hardware via variably connected components to perform a portion of a specific task when in operation. Thus, when the device is operating, the computer-readable medium is communicatively coupled to other components of the circuit system. In an example, any physical component can be used in more than one member of more than one circuit system. For example, in operation, an execution unit can be used in a first circuit of a first circuit system at one point in time and can be reused by a second circuit in the first circuit system or a third circuit in the second circuit system at a different time.

[0146] A machine (e.g., a computer system) 1000 (e.g., a host device 101, a memory system 102, etc.) may include a hardware processor 10001 (e.g., a central processing unit (CPU), a graphics processing unit (GPU), a hardware processor core, or any combination thereof, such as a memory controller 1021, etc.), a main memory 10003, and a static memory 10005, some or all of which may communicate with each other via an interconnect (e.g., a bus) 10011. The machine 1000 may also include a display unit 10012, an alphanumeric input device 10013 (e.g., a keyboard), and a user interface (UI) navigation device 10014 (e.g., a mouse). In an example, the display unit 10012, the input device 10013, and the UI navigation device 10014 may be a touch screen display. The machine 1000 may further include a storage device (e.g., a drive unit) 10018, a signal generating device 10016 (e.g., a speaker), a network interface device 10009, and one or more sensors 10015, such as a global positioning system (GPS) sensor, a compass, an accelerometer, or other sensors. The machine 1000 may include an output controller 10017, such as a serial (e.g., universal serial bus (USB), parallel or other wired or wireless (e.g., infrared (IR), near field communication (NFC)), etc.) connection, to communicate with or control one or more peripheral devices (e.g., printers, card readers, etc.).

[0147] The storage device 10018 may include a machine-readable medium 10007 on which one or more sets of data structures or instructions 10004 (e.g., software) are stored that embody or are used by any one or more techniques or functions described herein. During execution of the instructions 10004 by the machine 1000, the instructions may also reside, in whole or in part, within the main memory 10003, the static memory 10005, or the hardware processor 10001. In an example, one or any combination of the hardware processor 10001, the main memory 10003, the static memory 10005, or the storage device 10018 may constitute the machine-readable medium 10007.

[0148] Although the machine-readable medium 10007 is illustrated as a single medium, the term "machine-readable medium" may also include a single medium or multiple media (e.g., a centralized or distributed database, or associated caches and servers) configured to store one or more instructions 10004.

[0149] The term "machine-readable medium" may include any medium capable of storing, encoding, or carrying instructions to be executed by the machine 1000 and causing the machine 1000 to perform any one or more techniques of the present invention, or any medium capable of storing, encoding, or carrying data structures used by or associated with such instructions. Non-limiting examples of machine-readable media may include solid-state memory and optical and magnetic media. In an example, a mass machine-readable medium comprises a machine-readable medium having a plurality of particles having a constant (e.g., stationary) mass. Thus, a mass machine-readable medium is not a transient propagating signal. Specific examples of mass machine-readable media may include: non-volatile memory, such as semiconductor memory systems (e.g., electrically programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM)) and flash memory systems; magnetic disks, such as internal hard disks and removable disks; magneto-optical disks; and CD-ROM and DVD-ROM disks.

[0150] Instructions 10004 (e.g., software, programs, operating system (OS), etc.) or other data are stored on storage device 10006 and can be accessed by memory 1004 for use by processor 10001. Memory 1004 (e.g., DRAM) is typically fast but volatile, and therefore a different type of storage than storage device 10006 (e.g., SSD), which is suitable for long-term storage, including when in an "off" state. Instructions 10004 or data being used by a user or machine 1000 are typically loaded into memory 1004 for use by processor 10001. When memory 1004 is full, virtual space from storage device 10006 can be allocated to supplement memory 1004; however, because memory device 10006 is typically slower than memory 1004, with write speeds typically at least twice as slow as read speeds, the use of virtual memory can significantly degrade the user experience (compared to memory 1004, such as DRAM) due to memory device latency. Furthermore, using storage device 10006 for virtual memory may significantly shorten the useful life of storage device 10006 .

[0151] Compared to virtual memory, virtual memory compression (e.g., the kernel feature "ZRAM") uses a portion of memory stored as compressed blocks to avoid paging to storage device 10006. Paging occurs in compressed blocks until it is necessary to write such data to storage device 10006. Virtual memory compression increases the available size of memory 1004 while reducing wear on storage device 10006.

[0152] Memory devices optimized for mobile electronic devices or mobile storage traditionally include MMC solid-state memory devices (e.g., micro secure digital (microSDTM) cards, etc.). MMC devices include several parallel interfaces (e.g., 8-bit parallel interfaces) with host devices, and components that are usually removable and separate from the host device. In contrast, eMMCTM devices are attached to circuit boards and are considered components of host devices, with read speeds comparable to serial ATATM (serial AT (Advanced Technology) Attachment or SATA) based on SSD devices. However, the demand for mobile device performance continues to grow, such as to fully enable virtual devices or augmented reality devices, to utilize growing network speeds, etc. In response to this demand, memory devices have been converted from parallel communication interfaces to serial communication interfaces. Universal Flash Storage (UFS) devices (including controllers and firmware) communicate with host devices using a low voltage differential signaling (LVDS) serial interface with a dedicated read / write path, thereby further facilitating higher read / write speeds.

[0153] Instructions 10004 may also be transmitted or received over a communication network 10010 using a transmission medium via a network interface device 10009 using any of a number of transmission protocols (e.g., frame relay, Internet Protocol (IP), transmission control protocol (TCP), user datagram protocol (UDP), hypertext transfer protocol (HTTP), etc.). Example communication networks may include a local area network (LAN), a wide area network (WAN), a packet data network (e.g., the Internet), a mobile telephone network (e.g., a cellular network), a plain old telephone (POTS) network, and a wireless data network (e.g., the Institute of Electrical and Electronics Engineers (IEEE) 802.11 series of standards, the IEEE 802.16 series of standards), the IEEE 802.15.4 series of standards, a peer-to-peer (P2P) network, etc. In an example, the network interface device 10009 may include one or more physical jacks (e.g., Ethernet, coaxial, or telephone jacks) or one or more antennas to connect to the communication network 10010. In an example, the network interface device 10009 may include multiple antennas to enable wireless communication using at least one of single-input multiple-output (SIMO), multiple-input multiple-output (MIMO), or multiple-input single-output (MISO) technology. The term "transmission medium" should be understood to include any intangible medium capable of storing, encoding, or carrying instructions to be executed by the machine 1000, and includes digital or analog communication signals or other intangible media to facilitate communication of such software.

[0154] The above detailed description includes reference to the accompanying drawings, which form a part of the detailed description. The accompanying drawings show, by way of illustration, specific embodiments in which the present invention may be implemented. These embodiments are also referred to herein as "examples." These examples may include elements other than those shown or described. However, the present inventors also contemplate examples in which only those elements shown or described are provided. In addition, the present inventors also contemplate examples using any combination or permutation of those elements (or one or more aspects thereof) shown or described relative to the specific examples (or one or more aspects thereof) shown or described herein, or relative to other examples (or one or more aspects thereof).

[0155] In this document, as commonly used in patent documents, the terms "a" or "an" are used to include one or more than one, independent of any other instances or uses of "at least one" or "one or more." In this document, unless otherwise stated, the term "or" is used to refer to a non-exclusive or, such that "A or B" may include "A but not B," "B but not A," and "A and B." In the following claims, the terms "including" and "among which" are used as the plain English equivalents of the respective terms "comprising" and "wherein." Furthermore, in the following claims, the terms "including" and "comprising" are open-ended, that is, systems, devices, articles, or processes that include elements in addition to those listed after the term in the claim are still considered to fall within the scope of the claim. Furthermore, in the following claims, the terms "first," "second," and "third," etc., are used merely as labels and are not intended to impose numerical requirements on their objects.

[0156] In various examples, the components, controllers, processors, units, engines, or tables described herein may include physical circuitry or firmware stored on a physical device, etc. As used herein, a "processor" refers to any type of computing circuit, such as, but not limited to, a microprocessor, a microcontroller, a graphics processor, a digital signal processor (DSP), or any other type of processor or processing circuit, including a group of processors or a multi-core device.

[0157] As used in this document, the term "horizontal" is defined as a plane parallel to the conventional plane or surface of a substrate, such as the plane beneath a wafer or die, regardless of the actual orientation of the substrate at any point in time. The term "vertical" refers to a direction perpendicular to the horizontal direction defined above. Prepositions (such as "on," "over," and "under") are defined with respect to a conventional plane or surface on the top or exposed surface of a substrate, regardless of the orientation of the substrate; and "on" is intended to indicate direct contact of one structure relative to another structure (in the absence of an explicit indication to the contrary) that the structure is "above" the other structure; the terms "on" and "under" are expressly intended to identify the relative arrangement of structures (or layers, features, etc.), which explicitly includes, but is not limited to, direct contact between the identified structures, unless specifically identified as such. Similarly, the terms "on" and "under" are not limited to a horizontal orientation, as a structure may be "on" if, at a certain point in time, it is the outermost portion of the structure in question, even if such a structure extends vertically relative to a reference structure, rather than being horizontally oriented.

[0158] As used herein, the terms "wafer" and "substrate" generally refer to any structure on which an integrated circuit is formed, and also refer to these structures during the various stages of integrated circuit fabrication. The following detailed description is therefore not to be taken in a limiting sense, and the scope of the various embodiments is defined solely by the appended claims, along with the full scope of equivalents to which such claims are entitled.

[0159] Various embodiments according to the present invention and described herein include memories utilizing a vertical structure of memory cells (e.g., a NAND string of memory cells). As used herein, orientation adjectives are applied relative to the surface of the substrate on which the memory cells are formed (i.e., a vertical structure is considered to extend away from the substrate surface, a bottom end of a vertical structure is considered to be the end closest to the substrate surface, and a top end of a vertical structure is considered to be the end farthest from the substrate surface).

[0160] As used herein, orientation adjectives (such as horizontal, vertical, normal, parallel, perpendicular, etc.) may refer to relative orientations and are not intended to require strict adherence to specific geometric properties unless otherwise indicated. For example, as used herein, a vertical structure need not be strictly perpendicular to the surface of the substrate, but may be approximately perpendicular to the surface of the substrate and may form an acute angle (e.g., between 60 and 120 degrees, etc.) with the surface of the substrate.

[0161] In some embodiments described herein, different doping configurations may be applied to a source-side select gate (SGS), a control gate (CG), and a drain-side select gate (SGD), each of which in this example may be formed of or at least include polysilicon. As a result, these layers (e.g., polysilicon, etc.) may have different etch rates when exposed to an etching solution. For example, during the formation of a single pillar in a 3D semiconductor device, the SGS and CG may be recessed, while the SGD may remain less recessed or even not recessed. These doping configurations can thus enable selective etching into different layers (e.g., SGS, CG, and SGD) in a 3D semiconductor device using an etching solution (e.g., tetramethylammonium hydroxide, TMCH).

[0162] As used herein, operating a memory cell includes reading from the memory cell, writing to the memory cell, or erasing the memory cell. The operation of placing a memory cell in a given state is referred to herein as "programming" and can include both writing to the memory cell and erasing from the memory cell (i.e., a memory cell can be programmed to an erased state).

[0163] According to one or more embodiments of the present invention, a memory controller (e.g., a processor, controller, firmware, etc.) located inside or outside a memory system can determine (e.g., select, set, adjust, calculate, change, clear, communicate, adapt, derive, define, utilize, modify, apply, etc.) a certain number of wear cycles or wear states (e.g., record wear cycles, count operations occurring in the memory system, track operations initiated by the memory system, evaluate memory system characteristics corresponding to the wear states, etc.).

[0164] According to one or more embodiments of the present invention, a memory access device may be configured to provide wear cycle information to a memory system with each memory operation. Memory system control circuitry (e.g., control logic) may be programmed to compensate for changes in memory system performance corresponding to the wear cycle information. The memory system may receive the wear cycle information and determine one or more operating parameters (e.g., values, characteristics) in response to the wear cycle information.

[0165] It will be understood that when an element is referred to as being "on," "connected to," or "coupled to" another element, it can be directly on, directly connected to, or coupled to the other element, or intervening elements may be present. In contrast, when an element is referred to as being "directly on," "directly connected to," or "directly coupled to" another element, there are no intervening elements or layers present. If two elements are shown in the drawings as being connected by a line, then the two elements may be coupled or directly coupled unless otherwise specified.

[0166] The method examples described herein may be implemented at least in part by a machine or computer. Some examples may include a computer-readable medium or machine-readable medium encoded with instructions that are operable to configure an electronic device to perform the methods described in the above examples. Implementations of such methods may include code, such as microcode, assembly language code, high-level language code, or the like. Such code may include computer-readable instructions for performing various methods. The code may form part of a computer program product. In addition, the code may be tangibly stored on one or more volatile or non-volatile tangible computer-readable media, such as during execution or at other times. Examples of these tangible computer-readable media may include, but are not limited to: a hard disk, a removable magnetic disk, a removable optical disk (e.g., a compact disc and a digital video disc), a magnetic cassette, a memory card or stick, a random access memory (RAM), a read-only memory (ROM), a solid-state drive (SSD), a universal flash storage (UFS) device, an embedded MMC (eMMC) device, and the like.

[0167] Implementation:

[0168] Example 1 is a memory device comprising a memory array having a plurality of memory cells, a plurality of word lines, a plurality of bit lines, and a control circuit coupled to the plurality of word lines and the plurality of bit lines; wherein,

[0169] The control circuit is configured to: in response to a first store instruction carrying a first encrypted L2P pointer, determine a selected word line from the plurality of word lines; determine a selected bit line from the plurality of bit lines; determine a selected first memory cell based on the selected word line and the selected word line; and store the first encrypted L2P pointer in the first memory cell;

[0170] Among them, the first encrypted L2P pointer is generated by the controller of the memory system based on the first encrypted physical address and the first logical address corresponding to the first unencrypted physical address; the first encrypted physical address is generated by the controller using the first unencrypted physical address to generate a first fixed format physical address, the first fixed format physical address at least includes a first field for storing a token Token and a second field for storing the first unencrypted physical address, a cyclic redundancy check CRC is performed on the first fixed format physical address to obtain first CRC data containing the same number of bits as the Token, the first CRC data is replaced with the Token in the first field, so that the first fixed format physical address forms a second fixed format physical address, and the second fixed format physical address is encrypted.

[0171] In Example 2, the subject matter of Example 1 optionally, wherein the control circuit is further controlled to:

[0172] In response to the second storage instruction, an encrypted L2P table including a plurality of the first encrypted L2P pointers is stored.

[0173] In Example 3, the subject matter of Example 1 optionally, wherein the control circuit is further controlled to:

[0174] In response to a read command or a write command including a first unencrypted physical address, a selected second memory cell is obtained from the plurality of word lines and the plurality of bit lines, and data is read from the second memory cell or data is written to the second memory cell.

[0175] In Example 4, the subject matter of any one of Examples 1 to 3 is optionally wherein the memory array is a three-dimensional NAND memory array; the memory system is a three-dimensional NAND memory device.

[0176] Example 5 is a memory system comprising: a memory device for storing data;

[0177] and a controller coupled to the memory device, wherein the controller is programmed to perform operations including:

[0178] Generate a first fixed-format physical address using the first unencrypted physical address; the first fixed-format physical address includes at least a first field for storing a token Token and a second field for storing the first unencrypted physical address;

[0179] Performing a cyclic redundancy check (CRC) on the first fixed-format physical address to obtain first CRC data having the same number of bits as the Token;

[0180] Replacing the Token in the first field with the first CRC data so that the first fixed-format physical address forms a second fixed-format physical address;

[0181] encrypting the second fixed-format physical address to obtain a first encrypted physical address;

[0182] A first encrypted L2P pointer is generated that indicates the first encrypted physical address and a first logical address corresponding to the first unencrypted physical address.

[0183] In Example 6, the subject matter of Example 5 optionally, wherein the controller is further configured to:

[0184] The first encrypted L2P pointer is sent to a host device, so that a memory of the host device caches the first encrypted L2P pointer; the host device is a device capable of communicating with the memory system.

[0185] In Example 7, the subject matter of Example 5, optionally, wherein the controller is further programmed to perform the following operations, including:

[0186] Generate an encrypted L2P table including a plurality of the first encrypted L2P pointers; and send the encrypted L2P table to a host device so that a memory of the host device caches part or all of the encrypted L2P table.

[0187] In Example 8, the subject matter of Example 6 is optionally, wherein encrypting the second fixed-format physical address to obtain the first encrypted physical address includes: using a random number to perform XOR encryption on the second fixed-format physical address to obtain the first encrypted physical address.

[0188] In Example 9, the subject matter of Example 8 is optionally wherein the controller is further programmed to perform the following operations, including: generating an association relationship between the first logical address and the Token, the first CRC data and the random number, and storing the association relationship.

[0189] In Example 10, the subject matter of Example 5 is optionally, wherein the memory device includes a memory array having a plurality of memory cells, a plurality of word lines, a plurality of bit lines, and a control circuit coupled to the plurality of word lines and the plurality of bit lines; wherein the control circuit is configured to: in response to a store instruction carrying the first encrypted L2P pointer, store the first encrypted L2P pointer in a selected first memory cell.

[0190] In Example 11, the subject matter of Example 10 optionally, wherein the control circuit is further controlled to:

[0191] In response to the second storage instruction, an encrypted L2P table including a plurality of the first encrypted L2P pointers is stored.

[0192] In Example 12, the subject matter of Example 9, optionally, wherein the controller is further programmed to perform the following operations, including:

[0193] receiving a read request or a write request including a to-be-identified encrypted physical address from the host device; the to-be-identified encrypted physical address is obtained by the host device accessing a first encrypted L2P pointer in part or all of the encrypted L2P table stored in the memory based on the first logical address;

[0194] Using the stored random number to perform XOR decryption on the encrypted physical address to be identified to obtain a third fixed-format physical address;

[0195] Using the stored Token to replace the data in the first field of the third fixed-format physical address, so that the third fixed-format physical address forms a fourth fixed-format physical address;

[0196] Performing CRC on the fourth fixed-format physical address to obtain second CRC data having the same number of bits as the stored Token;

[0197] comparing the first CRC data and the second CRC data;

[0198] Based on the comparison result, it is determined whether to trust the first encrypted L2P pointer in part or all of the encrypted L2P table stored in the memory.

[0199] In Example 13, the subject matter of Example 12 may optionally include: determining whether to trust the first encrypted L2P pointer in part or all of the encrypted L2P table stored in the memory based on the comparison result, comprising:

[0200] trusting the first encrypted L2P pointer in part or all of the encrypted L2P table stored in the memory when the first CRC data is consistent with the second CRC data; and generating the first unencrypted physical address based on the fourth fixed-format physical address;

[0201] When the first CRC data is inconsistent with the second CRC data, the first encrypted L2P pointer in part or all of the encrypted L2P table stored in the memory is not trusted; the first L2P pointer is re-read from the L2P table stored in the memory array based on the first logical address; and the first unencrypted physical address is obtained based on the first L2P pointer.

[0202] In Example 14, the subject matter of Example 13, optionally, wherein the controller is further programmed to perform the following operations, including:

[0203] Retrieving data from the memory array based on the first unencrypted physical address; sending the data to the host device; or storing the data included in the write request in the memory array at a location indicated by the first unencrypted physical address.

[0204] In Example 15, the subject matter of Example 5 optionally, wherein the controller is further programmed to perform the following operations, including:

[0205] A first L2P pointer is read from an L2P table stored at the memory array; the first L2P pointer indicates the first logical address and the first unencrypted physical address at the memory array associated with the first logical address.

[0206] In Example 16, the subject matter of any one of Examples 5 to 15 optionally includes the memory array being a three-dimensional NAND memory array; and the memory system being a three-dimensional NAND memory system.

[0207] Example 17 is an information processing method applied to a memory system including a memory device for storing data and a controller coupled to the memory device, the method comprising:

[0208] The controller in the memory system generates a first fixed-format physical address using the first unencrypted physical address; the first fixed-format physical address includes at least a first field for storing a token Token and a second field for storing the first unencrypted physical address;

[0209] The controller performs a cyclic redundancy check (CRC) on the first fixed-format physical address to obtain first CRC data having the same number of bits as the Token;

[0210] The controller replaces the token in the first field with the first CRC data, so that the first fixed-format physical address forms a second fixed-format physical address;

[0211] The controller encrypts the second fixed-format physical address to obtain a first encrypted physical address;

[0212] A first encrypted L2P pointer is generated by the controller indicating the first encrypted physical address and a first logical address corresponding to the first unencrypted physical address.

[0213] In Example 18, the subject matter of Example 17 optionally, wherein the method further comprises:

[0214] The controller sends the first encrypted L2P pointer to a host device, so that a memory of the host device caches the first encrypted L2P pointer; the host device is a device capable of communicating with the memory system.

[0215] In Example 19, the subject matter of Example 17 optionally includes: generating, by the controller, an encrypted L2P table including a plurality of the first encrypted L2P pointers; and sending the encrypted L2P table to a host device so that a memory of the host device caches part or all of the encrypted L2P table.

[0216] In Example 20, the subject of Example 18 optionally, the encrypting the second fixed format physical address to obtain the first encrypted physical address includes: the controller using a random number to perform XOR encryption on the second fixed format physical address to obtain the first encrypted physical address.

[0217] In Example 21, the subject matter of Example 20 optionally includes: the method further comprising: generating, by the controller, an association relationship between the first logical address and the Token, the first CRC data, and the random number, and storing the association relationship.

[0218] In Example 22, the subject matter of Example 17 is optionally, wherein the memory device includes a memory array having a plurality of memory cells, a plurality of word lines, a plurality of bit lines, and a control circuit coupled to the plurality of word lines and the plurality of bit lines; and the method further comprises: because the control circuit responds to a store instruction carrying the first encrypted L2P pointer, storing the first encrypted L2P pointer in a selected first memory cell.

[0219] In Example 23, the subject matter of Example 22 optionally includes the method further comprising: storing, by the control circuit in response to a second storage instruction, an encrypted L2P table including a plurality of the first encrypted L2P pointers.

[0220] In Example 24, the subject matter of Example 21 optionally further includes: receiving, by the controller, a read request or a write request including an encrypted physical address to be identified from the host device; the encrypted physical address to be identified is obtained by the host device accessing a first encrypted L2P pointer in part or all of the encrypted L2P table stored in the memory based on the first logical address;

[0221] The controller uses the stored random number to perform XOR decryption on the encrypted physical address to be identified to obtain a third fixed-format physical address;

[0222] The controller uses the stored Token to replace data in the first field of the third fixed-format physical address, so that the third fixed-format physical address forms a fourth fixed-format physical address;

[0223] The controller performs CRC on the fourth fixed-format physical address to obtain second CRC data having the same number of bits as the stored Token;

[0224] The controller compares the first CRC data and the second CRC data; and determines whether to trust the first encrypted L2P pointer in part or all of the encrypted L2P table stored in the memory based on the comparison result.

[0225] In Example 25, the subject matter of Example 24 optionally comprises: determining whether to trust the first encrypted L2P pointer in part or all of the encrypted L2P table stored in the memory based on the comparison result, comprising: trusting, by the controller, the first encrypted L2P pointer in part or all of the encrypted L2P table stored in the memory when the first CRC data is consistent with the second CRC data; and generating the first unencrypted physical address based on the fourth fixed-format physical address;

[0226] The controller distrusts a first encrypted L2P pointer in part or all of the encrypted L2P table stored in the memory when the first CRC data is inconsistent with the second CRC data; re-reads the first L2P pointer from the L2P table stored in the memory array based on the first logical address; and obtains the first unencrypted physical address based on the first L2P pointer.

[0227] In Example 26, the subject matter of Example 25 optionally further includes: retrieving, by the controller, data from the memory array based on the first unencrypted physical address; and sending the data to the host device;

[0228] Alternatively, the data included in the write request is stored in the memory array at a location indicated by the first unencrypted physical address.

[0229] In Example 27, the subject matter of Example 17 optionally further includes: reading, by the controller, a first L2P pointer from an L2P table stored at the memory array; the first L2P pointer indicating the first logical address and the first unencrypted physical address at the memory array associated with the first logical address.

[0230] Example 28 is a computer-readable medium comprising instructions thereon, which, when executed by a processor, cause the processor to perform the following operations:

[0231] Generate a first fixed-format physical address using the first unencrypted physical address; the first fixed-format physical address includes at least a first field for storing a token Token and a second field for storing the first unencrypted physical address;

[0232] Performing a cyclic redundancy check (CRC) on the first fixed-format physical address to obtain first CRC data having the same number of bits as the Token;

[0233] Replacing the Token in the first field with the first CRC data so that the first fixed-format physical address forms a second fixed-format physical address;

[0234] encrypting the second fixed-format physical address to obtain a first encrypted physical address;

[0235] generating a first encrypted L2P pointer indicating the first encrypted physical address and a first logical address corresponding to the first unencrypted physical address;

[0236] The first encrypted L2P pointer is sent to a host device, so that a memory of the host device caches the first encrypted L2P pointer; the host device is a device capable of communicating with the memory system.

[0237] In Example 29, the subject matter of Example 28 optionally further includes instructions thereon that, when executed by a processor, cause the processor to perform the following operations, including:

[0238] Generate an encrypted L2P table including a plurality of the first encrypted L2P pointers; and send the encrypted L2P table to a host device so that a memory of the host device caches part or all of the encrypted L2P table.

[0239] In Example 30, the subject matter of Example 28 optionally further includes instructions thereon that, when executed by a processor, encrypt the second fixed-format physical address to obtain the first encrypted physical address, comprising:

[0240] The second fixed-format physical address is XOR-encrypted using a random number to obtain the first encrypted physical address.

[0241] In Example 31, the subject matter of Example 30 optionally further includes instructions thereon, which, when executed by a processor, cause the processor to perform the following operations, including:

[0242] Generate an association relationship between the first logical address and the Token, the first CRC data and the random number, and store the association relationship.

[0243] In Example 32, the subject matter of Example 31 optionally further includes instructions thereon, which, when executed by a processor, cause the processor to perform the following operations, including:

[0244] receiving a read request or a write request including a to-be-identified encrypted physical address from the host device; the to-be-identified encrypted physical address is obtained by the host device accessing a first encrypted L2P pointer in part or all of the encrypted L2P table stored in the memory based on the first logical address;

[0245] Using the stored random number to perform XOR decryption on the encrypted physical address to be identified to obtain a third fixed-format physical address;

[0246] Using the stored Token to replace the data in the first field of the third fixed-format physical address, so that the third fixed-format physical address forms a fourth fixed-format physical address;

[0247] Performing CRC on the fourth fixed-format physical address to obtain second CRC data having the same number of bits as the stored Token;

[0248] comparing the first CRC data and the second CRC data;

[0249] Based on the comparison result, it is determined whether to trust the first encrypted L2P pointer in part or all of the encrypted L2P table stored in the memory.

[0250] In Example 33, the subject matter of Example 32 optionally includes: determining whether to trust the first encrypted L2P pointer in part or all of the encrypted L2P table stored in the memory based on the comparison result, comprising:

[0251] trusting the first encrypted L2P pointer in part or all of the encrypted L2P table stored in the memory when the first CRC data is consistent with the second CRC data; and generating the first unencrypted physical address based on the fourth fixed-format physical address;

[0252] When the first CRC data is inconsistent with the second CRC data, the first encrypted L2P pointer in part or all of the encrypted L2P table stored in the memory is not trusted; the first L2P pointer is re-read from the L2P table stored in the memory array based on the first logical address; and the first unencrypted physical address is obtained based on the first L2P pointer.

[0253] In Example 34, the subject matter of Example 33 optionally further includes instructions thereon that, when executed by a processor, cause the processor to perform the following operations, including:

[0254] Retrieving data from the memory array based on the first unencrypted physical address; sending the data to the host device, or storing the data included in the write request in the memory array at a location indicated by the first unencrypted physical address.

[0255] In Example 35, the subject matter of Example 28 optionally further includes instructions thereon that, when executed by a processor, cause the processor to perform the following operations:

[0256] A first L2P pointer is read from an L2P table stored at the memory array; the first L2P pointer indicates the first logical address and the first unencrypted physical address at the memory array associated with the first logical address.

[0257] The above description is intended to be illustrative, not restrictive. For example, the above examples (or one or more aspects thereof) can be used in combination with each other. Other embodiments may be used, such as those available to a person of ordinary skill in the art upon reading the above description. It should be understood that it will not be used to interpret or limit the scope or meaning of the claims. In addition, in the above detailed description, various features may be combined together to simplify the present invention. This should not be interpreted as meaning that unclaimed disclosed features are essential to any claim. On the contrary, the disclosed subject matter may be less than all the features of a particular disclosed embodiment. Therefore, the appended claims are hereby incorporated into the detailed description, with each claim independently serving as a separate embodiment, and it is expected that these embodiments may be combined with each other in various combinations or permutations. The scope of the present invention should be determined with reference to the appended claims and the full scope of equivalents to which these claims are entitled.

Claims

1. A memory device comprising a memory array having a plurality of memory cells, a plurality of word lines, a plurality of bit lines, and a control circuit coupled to the plurality of word lines and the plurality of bit lines; wherein The control circuit is configured to: determine a selected word line from the plurality of word lines in response to a first storage instruction carrying a first encrypted L2P pointer; determining a selected bit line from the plurality of bit lines; determining a selected first memory cell based on the selected word line and the selected word line; storing the first encrypted L2P pointer in the first memory unit; The first encrypted L2P pointer is generated by a controller of the memory system based on the first encrypted physical address and a first logical address corresponding to the first unencrypted physical address; and the first encrypted physical address is obtained by the controller by performing the following operations: Generate a first fixed-format physical address using the first unencrypted physical address, where the first fixed-format physical address at least includes a first field for storing a token Token and a second field for storing the first unencrypted physical address; Performing a cyclic redundancy check (CRC) on the first fixed-format physical address to obtain first CRC data having the same number of bits as the Token, and replacing the Token in the first field with the first CRC data, so that the first fixed-format physical address forms a second fixed-format physical address; The second fixed-format physical address is encrypted to obtain the first encrypted physical address.

2. The memory device according to claim 1, wherein The control circuit is further controlled to: In response to the second storage instruction, an encrypted L2P table including a plurality of the first encrypted L2P pointers is stored.

3. The memory device according to claim 1, wherein The control circuit is further controlled to: In response to a read command or a write command including a first unencrypted physical address, a selected second memory cell is obtained from the plurality of word lines and the plurality of bit lines, and data is read from the second memory cell or data is written to the second memory cell.

4. The memory device according to any one of claims 1 to 3, wherein: The memory array is a three-dimensional NAND memory array; and the memory system is a three-dimensional NAND memory device.

5. A memory system comprising: a memory device for storing data; and a controller coupled to the memory device, wherein the controller is programmed to perform operations including: Generate a first fixed-format physical address using the first unencrypted physical address; the first fixed-format physical address includes at least a first field for storing a token Token and a second field for storing the first unencrypted physical address; Performing a cyclic redundancy check (CRC) on the first fixed-format physical address to obtain first CRC data having the same number of bits as the Token; Replacing the Token in the first field with the first CRC data so that the first fixed-format physical address forms a second fixed-format physical address; encrypting the second fixed-format physical address to obtain a first encrypted physical address; A first encrypted L2P pointer is generated that indicates the first encrypted physical address and a first logical address corresponding to the first unencrypted physical address. The memory system according to claim 5 , wherein: The controller is further configured to: The first encrypted L2P pointer is sent to a host device, so that a memory of the host device caches the first encrypted L2P pointer; the host device is a device capable of communicating with the memory system.

7. The memory system of claim 5, wherein the controller is further programmed to perform the following operations: Generate an encrypted L2P table including a plurality of the first encrypted L2P pointers; and send the encrypted L2P table to a host device so that a memory of the host device caches part or all of the encrypted L2P table.

8. The memory system according to claim 6, wherein encrypting the second fixed-format physical address to obtain the first encrypted physical address comprises: performing an XOR encryption on the second fixed-format physical address using a random number to obtain the first encrypted physical address.

9. The memory system according to claim 8, wherein the controller is further programmed to perform the following operations, including: generating an association relationship between the first logical address and the token, the first CRC data and the random number, and storing the association relationship.

10. The memory system according to claim 5, wherein: The memory device includes a memory array having a plurality of memory cells, a plurality of word lines, a plurality of bit lines, and a control circuit coupled to the plurality of word lines and the plurality of bit lines; wherein the control circuit is configured to: in response to a store instruction carrying a first encrypted L2P pointer, store the first encrypted L2P pointer in a selected first memory cell. The memory system according to claim 10 , wherein: The control circuit is further controlled to: In response to the second storage instruction, an encrypted L2P table including a plurality of the first encrypted L2P pointers is stored.

12. The memory system of claim 9, wherein the controller is further programmed to perform the following operations: receiving a read request or a write request including a to-be-identified encrypted physical address from the host device; the to-be-identified encrypted physical address is obtained by the host device accessing a first encrypted L2P pointer in part or all of the encrypted L2P table stored in the memory based on the first logical address; Using the stored random number to perform XOR decryption on the encrypted physical address to be identified to obtain a third fixed-format physical address; Using the stored Token to replace the data in the first field of the third fixed-format physical address, so that the third fixed-format physical address forms a fourth fixed-format physical address; Performing CRC on the fourth fixed-format physical address to obtain second CRC data having the same number of bits as the stored Token; comparing the first CRC data and the second CRC data; Based on the comparison result, it is determined whether to trust the first encrypted L2P pointer in part or all of the encrypted L2P table stored in the memory.

13. The memory system according to claim 12 , wherein determining whether to trust the first encrypted L2P pointer in part or all of the encrypted L2P table stored in the memory based on the comparison result comprises: trusting the first encrypted L2P pointer in part or all of the encrypted L2P table stored in the memory when the first CRC data is consistent with the second CRC data; generating the first unencrypted physical address based on the fourth fixed-format physical address; When the first CRC data is inconsistent with the second CRC data, distrusting the first encrypted L2P pointer in part or all of the encrypted L2P table stored in the memory; re-reading a first L2P pointer from the L2P table stored in the memory array based on the first logical address; The first unencrypted physical address is obtained based on the first L2P pointer.

14. The memory system of claim 13, wherein the controller is further programmed to perform the following operations: Retrieving data from the memory array based on the first unencrypted physical address; sending the data to the host device; or storing the data included in the write request in the memory array at a location indicated by the first unencrypted physical address.

15. The memory system of claim 5, wherein the controller is further programmed to perform the following operations: A first L2P pointer is read from an L2P table stored at the memory array; the first L2P pointer indicates the first logical address and the first unencrypted physical address at the memory array associated with the first logical address. 16 . The memory system according to claim 5 , wherein the memory array is a three-dimensional NAND memory array; and the memory system is a three-dimensional NAND memory system.

17. An information processing method, applied to a memory system including a memory device for storing data and a controller coupled to the memory device, the method comprising: The controller in the memory system generates a first fixed-format physical address using the first unencrypted physical address; the first fixed-format physical address includes at least a first field for storing a token Token and a second field for storing the first unencrypted physical address; The controller performs a cyclic redundancy check (CRC) on the first fixed-format physical address to obtain first CRC data having the same number of bits as the Token; The controller replaces the token in the first field with the first CRC data, so that the first fixed-format physical address forms a second fixed-format physical address; The controller encrypts the second fixed-format physical address to obtain a first encrypted physical address; A first encrypted L2P pointer is generated by the controller indicating the first encrypted physical address and a first logical address corresponding to the first unencrypted physical address.

18. The method according to claim 17, wherein The method further comprises: The controller sends the first encrypted L2P pointer to a host device, so that a memory of the host device caches the first encrypted L2P pointer; the host device is a device capable of communicating with the memory system.

19. The method according to claim 17, further comprising: generating, by the controller, an encrypted L2P table including a plurality of the first encrypted L2P pointers; The encrypted L2P table is sent to a host device, so that a memory of the host device caches part or all of the encrypted L2P table.

20. The method according to claim 18, wherein encrypting the second fixed-format physical address to obtain the first encrypted physical address comprises: The controller uses a random number to perform XOR encryption on the second fixed-format physical address to obtain the first encrypted physical address.

21. The method according to claim 20, further comprising: The controller generates an association relationship between the first logical address and the Token, the first CRC data and the random number, and stores the association relationship.

22. The method according to claim 17, wherein The memory device includes a memory array having a plurality of memory cells, a plurality of word lines, a plurality of bit lines, and a control circuit coupled to the plurality of word lines and the plurality of bit lines; the method further includes: because the control circuit responds to a store instruction carrying a first encrypted L2P pointer, storing the first encrypted L2P pointer in a selected first memory cell.

23. The method according to claim 22, wherein The method further includes storing, by the control circuit in response to a second storage instruction, an encrypted L2P table including a plurality of the first encrypted L2P pointers.

24. The method of claim 21, further comprising: receiving, by the controller, from the host device, a read request or a write request including an encrypted physical address to be identified; The encrypted physical address to be identified is obtained by the host device accessing a first encrypted L2P pointer in part or all of the encrypted L2P table stored in the memory based on the first logical address; The controller uses the stored random number to perform XOR decryption on the encrypted physical address to be identified to obtain a third fixed-format physical address; The controller uses the stored Token to replace data in the first field of the third fixed-format physical address, so that the third fixed-format physical address forms a fourth fixed-format physical address; The controller performs CRC on the fourth fixed-format physical address to obtain second CRC data having the same number of bits as the stored Token; The controller compares the first CRC data and the second CRC data; and determines whether to trust the first encrypted L2P pointer in part or all of the encrypted L2P table stored in the memory based on the comparison result.

25. The method according to claim 24, wherein determining whether to trust the first encrypted L2P pointer in part or all of the encrypted L2P table stored in the memory based on the comparison result comprises: The controller trusts, when the first CRC data and the second CRC data are consistent, a first encrypted L2P pointer in part or all of the encrypted L2P table stored in the memory; generating the first unencrypted physical address based on the fourth fixed-format physical address; When the first CRC data and the second CRC data are inconsistent, the controller distrusts the first encrypted L2P pointers in part or all of the encrypted L2P tables stored in the memory; re-reading a first L2P pointer from the L2P table stored in the memory array based on the first logical address; The first unencrypted physical address is obtained based on the first L2P pointer.

26. The method according to claim 25, further comprising: retrieving, by the controller, data from the memory array based on the first unencrypted physical address; sending the data to the host device; Alternatively, the data included in the write request is stored in the memory array at a location indicated by the first unencrypted physical address.

27. The method of claim 17, further comprising: reading, by the controller, a first L2P pointer from an L2P table stored at the memory array; The first L2P pointer indicates the first logical address and the first unencrypted physical address at the memory array associated with the first logical address.

28. A computer-readable medium comprising instructions thereon, which, when executed by a processor, cause the processor to perform the following operations: Generate a first fixed-format physical address using the first unencrypted physical address; the first fixed-format physical address includes at least a first field for storing a token Token and a second field for storing the first unencrypted physical address; Performing a cyclic redundancy check (CRC) on the first fixed-format physical address to obtain first CRC data having the same number of bits as the Token; Replacing the Token in the first field with the first CRC data so that the first fixed-format physical address forms a second fixed-format physical address; encrypting the second fixed-format physical address to obtain a first encrypted physical address; generating a first encrypted L2P pointer indicating the first encrypted physical address and a first logical address corresponding to the first unencrypted physical address; The first encrypted L2P pointer is sent to a host device, so that a memory of the host device caches the first encrypted L2P pointer; the host device is a device capable of communicating with a memory system.

29. The readable medium of claim 28, further comprising instructions thereon that, when executed by a processor, cause the processor to perform the following operations: Generate an encrypted L2P table including a plurality of the first encrypted L2P pointers; and send the encrypted L2P table to a host device so that a memory of the host device caches part or all of the encrypted L2P table.

30. The readable medium of claim 28, further comprising instructions thereon, which, when executed by a processor, encrypt the second fixed-format physical address to obtain a first encrypted physical address, comprising: The second fixed-format physical address is XOR-encrypted using a random number to obtain the first encrypted physical address.

31. The readable medium of claim 30, further comprising instructions thereon that, when executed by a processor, cause the processor to perform the following operations: Generate an association relationship between the first logical address and the Token, the first CRC data and the random number, and store the association relationship.

32. The readable medium of claim 31 , further comprising instructions thereon that, when executed by a processor, cause the processor to perform the following operations: receiving a read request or a write request including a to-be-identified encrypted physical address from the host device; the to-be-identified encrypted physical address is obtained by the host device accessing a first encrypted L2P pointer in part or all of the encrypted L2P table stored in the memory based on the first logical address; Using the stored random number to perform XOR decryption on the encrypted physical address to be identified to obtain a third fixed-format physical address; Using the stored Token to replace the data in the first field of the third fixed-format physical address, so that the third fixed-format physical address forms a fourth fixed-format physical address; Performing CRC on the fourth fixed-format physical address to obtain second CRC data having the same number of bits as the stored Token; comparing the first CRC data and the second CRC data; Based on the comparison result, it is determined whether to trust the first encrypted L2P pointer in part or all of the encrypted L2P table stored in the memory.

33. The readable medium of claim 32, wherein determining whether to trust the first encrypted L2P pointer in part or all of the encrypted L2P table stored in the memory based on the comparison result comprises: trusting the first encrypted L2P pointer in part or all of the encrypted L2P table stored in the memory when the first CRC data is consistent with the second CRC data; generating the first unencrypted physical address based on the fourth fixed-format physical address; When the first CRC data is inconsistent with the second CRC data, distrusting the first encrypted L2P pointer in part or all of the encrypted L2P table stored in the memory; re-reading a first L2P pointer from the L2P table stored in the memory array based on the first logical address; The first unencrypted physical address is obtained based on the first L2P pointer.

34. The readable medium of claim 33, further comprising instructions thereon that, when executed by a processor, cause the processor to perform the following operations: Retrieving data from the memory array based on the first unencrypted physical address; sending the data to the host device, or storing the data included in the write request in the memory array at a location indicated by the first unencrypted physical address.

35. The readable medium of claim 28, further comprising instructions thereon that, when executed by a processor, cause the processor to perform the following operations: A first L2P pointer is read from an L2P table stored at the memory array; the first L2P pointer indicates the first logical address and the first unencrypted physical address at the memory array associated with the first logical address.

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