Monocrystalline silicon wafer

Abstract

The present application relates to a single-crystalline silicon wafer comprising two major parallel surfaces, one being a front surface and the other being a back surface, a central plane between the front surface and the back surface, a circumferential edge connecting the front surface and the back surface, a front layer having a depth D measured from the front surface towards the central plane, and wherein a bulk region is between the front layer and the central plane, wherein: the bulk region contains oxygen precipitates having a density of at least about 1×10<supgt;7< / supgt> cm<supgt;‑3< / supgt> and a peak density of oxygen precipitates of at least about 1×10<supgt;9< / supgt> cm<supgt;‑3< / supgt>, wherein the peak density is between the front layer and the central plane; the front layer contains oxygen precipitates having a density less than about 1×10<supgt;7< / supgt> cm<supgt;‑3< / supgt>, wherein the depth D of the front layer is between about 1 micron and about 40 microns; and the front surface does not have a band of crystal defects associated with a gate oxide integrity pattern.

Description

[0001] This application is a divisional application of the patent application for invention titled "Method for Processing Silicon Wafers to Have Internal Defect Removal and Gate Oxide Integrity Yield" with an application date of December 13, 2017, an application number of "201780081673.6".

[0002] Cross - Reference to Related Applications

[0003] This application claims the priority of U.S. Provisional Application Serial No. 62 / 439,621, filed on December 28, 2016, the disclosure of which is hereby incorporated by reference in its entirety as if set forth in full herein. Technical Field

[0004] The field of the present invention generally relates to the preparation of silicon wafers for use in the manufacture of electronic components. More particularly, the present invention relates to an annealing method for producing silicon wafers having internal defect removal and gate oxide integrity yield. Background Art

[0005] Single-crystalline silicon, which is the starting material for most methods of manufacturing semiconductor electronic components, is typically prepared using the so-called Czochralski (Cz) method, in which a single seed crystal is immersed in molten silicon and then grown by slow extraction. During being contained in a quartz crucible, the molten silicon is contaminated with various impurities, mainly oxygen. At the temperature of the silicon melt, oxygen enters the lattice until a concentration determined by the solubility of oxygen in silicon at the temperature of the melt and the actual segregation coefficient of oxygen in solidified silicon is reached. At typical temperatures of the processes used for manufacturing electronic devices, such concentrations are greater than the solubility of oxygen in solid silicon. Thus, as the crystal grows and cools from the melt, the solubility of oxygen in it rapidly decreases, so that in the wafers sliced from the crystal, oxygen will be present at a supersaturated concentration.

[0006] Heat treatment cycles commonly used in the manufacture of electronic devices cause oxygen to precipitate in oxygen-supersaturated silicon wafers. Depending on their location in the wafer, the precipitates can be either harmful or beneficial. Oxygen precipitates located in the active device regions of the wafer can impair the operation of the device. However, oxygen precipitates located in the bulk of the wafer can trap unwanted metal impurities that may come into contact with the wafer. Using oxygen precipitates located in the bulk of the wafer to trap metals is commonly referred to as internal gettering (IG).

[0007] Heat treatment cycles suitable for achieving internal gettering in single-crystalline silicon wafers include rapid thermal annealing (e.g., by SunEdison Semiconductor, Ltd.) (MagicDenuded ) method) or annealing for a long duration in an inert gas ambient atmosphere such as argon. The short annealing duration in rapid thermal annealing is an economically efficient solution. However, the depth of the precipitate free zone (PFZ; also referred to as the clean zone) is typically too deep to effectively scavenge metallic impurities at the top 100 microns of silicon (i.e., the typical amount of silicon remaining after back grinding). In contrast, long duration annealing can achieve an excellent PFZ region (tunable within the top 20 microns) and scavenging ability. However, long duration annealing requires a certain annealing time (several hours), which affects manufacturing cost and throughput.

[0008] As an alternative to rapid thermal annealing and long duration annealing, rapid thermal annealing in a nitrogen-containing gas ambient atmosphere has been developed. Rapid thermal annealing in a nitriding ambient atmosphere, such as NH3 or N2 gas, achieves strong internal scavenging ability accompanied by a shallow PFZ (precipitate free zone or clean zone). See, for example, Journal of Applied Physics (J Appl Phys), 114, 043520 (2013). It has not been previously recognized in the art that rapid thermal annealing in a nitrogen-containing gas ambient atmosphere can reduce the gate oxide integrity (GOI) yield. SUMMARY OF THE INVENTION

[0009] Briefly, the present invention relates to a method for obtaining a suitable GOI yield in a single crystal silicon wafer that has previously undergone rapid thermal annealing in a nitrogen-containing gas ambient atmosphere.

[0010] In one aspect, the present invention relates to a method of processing a single crystal silicon wafer, the method comprising: heat treating the single crystal silicon wafer in a first ambient atmosphere comprising a nitrogen-containing gas at a temperature of at least about 1100 °C to increase the density of lattice vacancies in the bulk region of the single crystal silicon wafer, and forming a silicon nitride layer on the front surface of the single crystal silicon wafer, wherein the single crystal silicon wafer comprises two major parallel surfaces (one of which is the front surface and the other is the back surface), a center plane between the front surface and the back surface, a circumferential edge connecting the front surface and the back surface, a front layer having a depth D measured from the front surface toward the center plane, and wherein the bulk region is between the front layer and the center plane; removing the silicon nitride layer from the front surface of the single crystal silicon wafer; heat treating the single crystal silicon wafer in a second ambient atmosphere comprising oxygen at a temperature between about 900 °C and about 1100 °C for a time greater than 30 minutes to form a silicon oxide layer having a minimum thickness of at least about 50 angstroms on the front surface of the single crystal silicon wafer; and removing the silicon oxide layer from the front surface of the single crystal silicon wafer.

[0011] On the other hand, the present invention relates to a single crystal silicon wafer comprising two main parallel surfaces (one being a front surface and the other being a back surface), a central plane between the front surface and the back surface, a circumferential edge connecting the front surface and the back surface, a front layer having a depth D measured from the front surface towards the central plane, and wherein a bulk region is between the front layer and the central plane, wherein: the bulk region contains oxygen precipitates with a density of at least about 1×10 7 cm -3 and the peak density of the oxygen precipitates is at least about 1×10 9 cm -3 wherein the peak density is between the front layer and the central plane; the front layer contains oxygen precipitates with a density less than about 1×10 7 cm -3 and the depth D of the front layer is between about 1 micron and about 40 microns; and the front surface does not have a band of crystal defects associated with gate oxide integrity patterns. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 Depicts the typical depth distribution of bulk microdefect density in a wafer that has undergone rapid thermal annealing in an ammonia-containing environment and subsequently undergone NEC1 treatment (4 hours at 800 °C followed by 16 hours at 1000 °C).

[0013] Figure 2A And 2B Illustrates the GOI yield of a single crystal silicon wafer before rapid thermal annealing ( Figure 2A left wafer in Figure 2B and after rapid thermal annealing in an ammonia-containing environment (

[0014] Figures 3A to 3D right wafer in

[0015] Figure 4 Is a graph showing the calculated concentration of oxidized silicon interstitials varying with temperature.

[0016] Figure 5 Provides several images of the wafer after GOI integrity testing.

[0017] Figure 6A Depicts the BMD depth distribution of a wafer that has undergone rapid thermal annealing in an ammonia-containing environment and then rapid thermal annealing in an oxidation environment (5 seconds at 1000 °C) (after oxidation precipitation heat treatment; after NEC1 treatment at 800 °C for 4 hours followed by NEC1 treatment at 1000 °C for 16 hours). The x-axis scale is depth in microns and the y-axis scale is BMD / cm 3 .

[0018] Figure 6BDepict the BMD depth profile of wafers that have undergone rapid thermal annealing in an ammonia-containing environment, followed by rapid thermal annealing in an oxidation environment (5 seconds at 1100 °C), after an oxidation precipitation heat treatment of 4 hours at 800 °C + 16 hours at 1000 °C. The x-axis scale is depth in microns, and the y-axis scale is BMD / cm 3 。

[0019] Figure 6C Depict the BMD depth profile of wafers that have undergone a long-duration oxidation annealing of 4 hours between 900 °C and 1000 °C, after an oxidation precipitation heat treatment of 4 hours at 800 °C + 16 hours at 1000 °C. The x-axis scale is depth in microns, and the y-axis scale is BMD / cm 3 。

[0020] Figure 7 Depict the GOI integrity results of various wafers that have undergone long-duration oxidation annealing at several temperatures. The wafers depicted include as-grown wafers (leftmost wafer), wafers after rapid thermal annealing in a nitriding environment (second wafer from the left), and three wafers that have undergone 360 minutes of oxidation annealing at 900 °C, 950 °C, and 1000 °C (right side).

[0021] Figure 8 Is a contour plot of GOI improvement versus oxidation temperature and time. Detailed Description

[0022] The present invention relates to a method for restoring the gate oxide integrity (GOI) yield of single-crystalline silicon wafers, such as ideal silicon wafers, after a rapid thermal annealing treatment in a nitriding atmosphere. In some embodiments, the present invention relates to a method for restoring the gate oxide integrity (GOI) yield of single-crystalline silicon wafers, such as ideal silicon wafers, after a rapid thermal annealing treatment in a nitrogen-containing ambient atmosphere, such as NH3, nitrogen, or a combination thereof. Generally, rapid thermal annealing is performed in a nitrogen-containing ambient atmosphere, such as NH3, nitrogen, or a combination thereof, followed by an annealing sufficient to grow bulk microdefects in the wafer body to obtain a single-crystalline silicon wafer that includes a precipitate-free zone (PFZ or perfect full zone) in the surface region. However, the BMD in the wafer body may reduce the GOI yield of the silicon wafer by exposing the bulk microdefects on the wafer surface, such as oxygen precipitates, to vacancies generated by a silicon nitride film. These vacancies may cause oxygen precipitates to grow and stabilize on the wafer surface, and these defects may lead to a reduction in the gate oxide integrity yield. Since the process window for GOI from the precipitate-free zone formed by rapid thermal annealing is extremely narrow, it is necessary to find a method for restoring the complete process window of GOI after rapid thermal annealing without reducing the BMD peak density and the shallow PFZ depth.

[0023] Rapid thermal annealing in a nitrogen-containing ambient atmosphere advantageously produces a shallow precipitate-free zone. See Figure 1 , which depicts a typical depth profile of the bulk microdefect density in a wafer that has undergone rapid thermal annealing in an ammonia ambient and subsequently undergone NEC1 processing (4 hours at 800 °C followed by 16 hours at 1000 °C). The wafer has an interstitial oxygen concentration of 8.344 PPMA and 9.544 PPMA as shown in Figure 1 . Ultra-shallow PFZs can be formed on the front and back of the wafer, such as less than about 40 microns, less than about 30 microns, less than about 20 microns, or even less than about 10 microns. In addition, a peak density of BMDs is formed near the wafer surface, which is generated during a heat treatment designed to grow oxygen precipitates. Since the peak BMD density is between about 6×10 9 and 8×10 9 precipitates per cubic centimeter, this peak BMD density is within the preferred range of embodiments of the present invention regardless of key parameters such as the wafer oxygen content, the thermal annealing temperature of the MDZ, and the cooling rate. In some preferred embodiments, rapid thermal annealing in a nitrogen-containing ambient atmosphere produces a silicon wafer having a shallow PFZ depth of less than 10 microns and a high BMD peak with a depth between 20 and 30 microns or even between 10 and 20 microns. Such wafers provide much stronger defect removal capabilities compared to rapid thermal annealing in an oxygen-containing ambient atmosphere, which has a deeper PFZ depth and a peak BMD density near the center of the wafer depth.

[0024] Rapid thermal annealing in a nitrogen-containing ambient can cause a degradation of gate oxide integrity. The GOI failure pattern (see Figure 2A , 2B, 5, and 7) are related to the crystal defect bands. The defect bands include crystal originated pits (COP, i.e., a void defect), H-band, P-band, L-band, an ideal silicon interstitial-dominated band, B defect band, and A defect band. Generally, if the wafer has any COP, H-band, and P-band defects, then GOI reduction will occur. These crystal defect bands exhibit a nucleus or ring pattern, and the defect bands are observed at various radial positions in the wafer. If the GOI pattern does not exhibit a nucleus or ring pattern, then this asymmetric pattern will not be caused by crystal defects but will be caused by wafer processing or GOI test preparation. The GOI breakdown voltage (MV / cm) is also affected by the crystal defect bands and defect types. Generally, due to crystal originated pits and H-band defects, the reduction of gate oxide integrity can occur in the range between 5 MV / cm and 9 MV / cm, which affects the uniformity of the gate oxide thickness. Generally, the reduction of gate oxide integrity caused by P-band defects, microvoid defects, or oxygen precipitates can occur in the range between 10 mV / cm and 12 mV / cm. The oxygen precipitates are formed by the combination of implanted vacancies from the Si3N4 / Si interface during rapid thermal annealing and by endogenic oxygen precipitates or large-size endogenic oxygen precipitates from the crystal. Since oxidation affects the GOI in a high stress field, it is speculated that the endogenic oxygen precipitates are the main cause of GOI reduction. Examine the GOI failure pattern shape and breakdown voltage to determine whether the GOI failure is caused by the crystal defect bands. If the GOI failure pattern matches the crystal defect bands or the breakdown voltage, then it is speculated that the GOI failure pattern is related to the crystal defect bands.

[0025] Performing rapid thermal annealing in a nitrogen-containing environment does not significantly change the density of the defects. However, performing rapid thermal annealing in a nitrogen environment can decorate the defects with implanted vacancies. Therefore, small-size defects can be dissolved by the RTA effect, but other defects are decorated with vacancies, making them larger and more stable. This affects the gate oxide uniformity and reduces the GOI yield. The larger defects that can be detected can be about 20 nanometers or larger, and the density of such defects can be about 1×10 8 ea / cm 3 . Such a density is sufficient to reduce the GOI by the order of magnitude described above. If small-size but undetectable defects (<20 nm) are included, then the actual density of the defects is much higher. The large size and high density of the defects affect the uniformity of the gate oxide, and due to the stress concentration being related to the non-uniform oxide thickness, the non-uniform gate oxide has a local weakening effect on the electrical stress field. If the supply of vacancies promoted by RTA in a nitrogen environment can expand and stabilize the oxygen precipitates, then gate oxide breakdown will occur.

[0026] See Figure 2A and 2B , which illustrate a single-crystalline silicon wafer before rapid thermal annealing (Figure 2A the GOI yield of the left wafer in the [wafer] and after rapid thermal annealing in an ammonia-containing environment (in Figure 2B the right wafer in the [wafer]). Obviously, rapid thermal annealing in ammonia reduces the GOI yield in the wafer via a band of gate oxide integrity pattern-related crystal defects present at or near the circular periphery of the wafer.

[0027] The present invention thus relates to a method of preparing a single crystal silicon wafer, wherein the wafer undergoes rapid thermal annealing in a nitrogen-containing ambient atmosphere, thereby producing a wafer having a thin precipitate-free region and oxygen precipitates with a peak density or concentration near the wafer surface. After forming an oxygen precipitate nucleation template, the silicon nitride layer is stripped, and the wafer is subjected to an oxidation annealing sufficient to form a silicon oxide layer on the wafer surface. Thereafter, the silicon oxide layer of the wafer is stripped, which removes surface defects that reduce the GOI yield. The wafer prepared according to the method of the present invention has an ideal oxygen precipitate nucleation template and, additionally, does not have surface defects that reduce the GOI yield. Specifically, the wafer does not have Figure 2B a band of gate oxide integrity pattern-related crystal defects of the type exemplified in [the figure]. Thereafter, the wafer can be annealed sufficiently to grow oxygen precipitates in the bulk region of the wafer, such as NEC1. Advantageously, since the wafer has undergone RTA in a nitrogen-containing ambient atmosphere, the peak density of the oxygen precipitates in the wafer can be within about 40 microns of the wafer surface, such as within about 30 microns of the wafer surface, or between about 10 and about 20 microns from the wafer surface.

[0028] I. Substrate

[0029] Referring now to Figure 3A , which depicts silicon wafer 10 or a portion thereof. Silicon wafer 10 can include two main generally parallel surfaces, one of which is the front surface of the substrate and the other of which is the back surface of the substrate. A circular periphery connects the front and back surfaces, and a center plane is located between the front and back surfaces. Referring to Figure 3B, the silicon wafer 10 includes a front layer 40 having a depth D and a central body region or layer 50 between the front layer and the central plane. Before any operations as described herein are performed, the front and back surfaces of the silicon wafer 10 may be substantially uniform. For convenience only, the surfaces are referred to as the "front" or "back", and they are generally used to distinguish the surfaces on which the operations of the method of the present invention are performed. In some embodiments of the present invention, the operations of the present invention are performed on the front surface of the silicon wafer 10. In some embodiments of the present invention, the operations of the present invention are performed on both the front and back surfaces of the silicon wafer 10. In addition, since silicon wafers typically have a certain total thickness variation (TTV), warp, and bow, the midpoints between points on the front surface and points on the back surface may not be precisely in a plane. However, in practice, the TTV, warp, and bow are usually so small as to be very approximate, so it can be said that the midpoints are in a hypothetical central plane that is approximately equidistant from the front and back surfaces.

[0030] Generally, the diameter of the silicon wafer 10 is at least about 20 mm, more typically between about 20 mm and about 500 mm. In some embodiments, the diameter is at least about 20 mm, at least about 45 mm, at least about 90 mm, at least about 100 mm, at least about 150 mm, at least about 200 mm, at least about 250 mm, at least about 300 mm, at least about 350 mm, or even at least about 450 mm. The thickness of the silicon wafer 10 can be between about 100 microns and about 5000 microns, such as between about 100 microns and about 1500 microns, suitably in the range of about 500 microns to about 1000 microns.

[0031] In a particularly preferred embodiment, the silicon wafer 10 comprises a wafer sliced from a single crystal silicon wafer which has been sliced from a single crystal ingot grown according to the conventional Czochralski crystal growth method. Such methods as well as standard silicon slicing, grinding, etching and polishing techniques are disclosed, for example, in F. Shimura, Semiconductor Silicon Crystal Technology, Academic Press, 1989 and Silicon Chemical Etching, (ed. J. Grabmaier) Springer-Verlag, New York, N.Y., 1982 (incorporated herein by reference). Preferably, the wafer is polished and cleaned by standard methods known to those skilled in the art. See, for example, W.C. O'Mara et al., Handbook of Semiconductor Silicon Technology, Noyes Publications. If desired, the wafer can be cleaned, for example, in a standard SC1 / SC2 solution. In some embodiments, the single crystal silicon wafer of the present invention is a single crystal silicon wafer sliced from a single crystal ingot typically having a nominal diameter of at least about 150 mm, at least about 200 mm, at least about 300 mm or at least about 450 mm grown according to the conventional Czochralski ("Cz") crystal growth method. Preferably, both the single crystal silicon handling wafer and the single crystal silicon donor wafer have a mirror-polished front surface finish which is free of surface defects such as scratches, large particles, etc. The wafer thickness can vary within from about 250 microns to about 1500 microns, such as between about 300 microns and about 1000 microns, suitably in the range of about 500 microns to about 1000 microns. In some specific embodiments, the wafer thickness can be between about 725 microns and about 800 microns, such as between about 750 microns and about 800 microns. In some embodiments, the wafer thickness can be about 725 microns. In some embodiments, the wafer thickness can be about 775 microns.

[0032] In some preferred embodiments, the silicon wafer 10 is a polished silicon wafer grown by the CZ method. The silicon wafer 10 can have any crystal orientation, such as (100), (110) and (111), and the choice of crystal orientation can be determined by the end use of the structure.

[0033] Generally, the starting silicon wafer 10 can exhibit an oxygen concentration drop at any position within the range achievable by the CZ method, which is typically between about 2×10 17 and about 9×10 17atoms / cm3 or between about 4 and about 18 PPMA, as determined according to ASTM calibration; i =4.9α, where α is 1107 cm -1 In some preferred embodiments, the interstitial oxygen concentration of silicon wafer 10 is less than about 6×10 17 atoms / cm3 or about 12PPMA, such as about 2×10 17 With about 5×10 17 In addition, the starting silicon wafer 10 preferably has no stable oxygen precipitates (ie, oxygen precipitates that cannot be dissolved or annealed out of the wafer at temperatures of about 1200° C. or less) in the near-surface region of the wafer.

[0034] When present as an impurity in single crystal silicon, substitutional carbon has the ability to catalyze the formation of oxygen precipitate nucleation centers. Therefore, for this and other reasons, it is preferred that the single crystal silicon wafer 10 have a low concentration of carbon. That is, the carbon concentration of the single crystal silicon wafer 10 is preferably less than about 5×10 16 atoms / cm3, preferably less than 1×10 16 atoms / cm3 and more preferably less than 5×10 15 atoms / cubic centimeter.

[0035] The resistivity of the silicon wafer is not critical to the method of the present invention. However, the resistivity can vary depending on the end-use requirements. In view of this, the silicon wafer 10 can be heavily doped, semi-insulating, or can have an intermediate doping profile. Thus, the resistivity can vary between milliohms or less and megohms or more. In some embodiments, the silicon wafer 10 contains a p-type or n-type dopant. Suitable dopants include boron (p-type), gallium (p-type), phosphorus (n-type), antimony (n-type), and arsenic (n-type). The dopant concentration is selected based on the desired wafer resistivity. In some embodiments, the wafer type can have a certain resistivity such that it can be characterized as any one of N++, N+, N, N-, and N-- types. The typical N+ resistivity range is as low as 10 milliohm-cm for Sb doping, as low as 2 milliohm-cm for As doping N++, and as low as 1 milliohm-cm for P doping N+++. Due to segregation during crystal growth, the specified range for maximum / minimum is typically 2-3X. In some embodiments, the wafer type can have a certain resistivity such that it can be characterized as any one of P++, P+, P, P-, and P-- types. The typical P+ resistivity range is as low as 10 milliohm-cm and P++ is as low as 5 milliohm-cm. Due to segregation during crystal growth, the specified range for maximum / minimum is typically 1.5-2X. Thus, the resistivity of the wafer can vary between about 0.1 milliohm-cm and about 10 kiloohm-cm, such as between about 0.01 ohm-cm and about 10 kiloohm-cm. In some embodiments, the resistivity can be in the range of about 0.1 milliohm-cm to about 1 kiloohm-cm, such as 0.1 milliohm-cm to about 100 ohm-cm, such as 0.1 milliohm-cm to about 10 ohm-cm, or about 0.1 milliohm-cm to about 1 ohm-cm. In some embodiments, the resistivity can be in the range of about 0.01 ohm-cm to about 1 kiloohm-cm, such as 0.01 ohm-cm to about 100 ohm-cm, such as 0.01 ohm-cm to about 10 ohm-cm, or about 0.01 ohm-cm to about 1 ohm-cm. Substrates in lightly doped form can also be obtained, such as in N-type (phosphorus) and P-type (boron), rated at 1 ohm-cm or 10 ohm-cm or 100 ohm-cm. The choice of substrate resistivity depends on the application (e.g., if the substrate is used as a back gate, then a lower resistivity is preferred).

[0036] In some embodiments, the silicon wafer 10 is cleaned prior to rapid thermal annealing to remove, for example, organic matter or other impurities. A suitable cleaning solution is a piranha solution, which contains H2SO4 (concentrated) and H2O2 (30% solution), which is typically in a 3:1 ratio but other ratios such as 4:1 or 7:1 are also suitable. The cleaning duration is preferably between about 15 minutes and about 2 hours.

[0037] II. Rapid Thermal Annealing

[0038] According to the method of the present invention, rapid thermal processing is performed to form a distribution of oxygen precipitate nuclei, which establishes the distribution or template of oxygen precipitates in the wafer. In one or more embodiments, the template is a wafer that has oxygen precipitates in the wafer body but has a lower density of oxygen precipitates in the near-surface region and preferably substantially no oxygen precipitates (which is referred to herein as a precipitate-free region or "clean band"). Advantageously, a clean band of any desired depth can be obtained. In some embodiments, the clean band depth can be at least about 1 micron, at least about 3 microns, or at least about 5 microns, as measured from the front surface of the wafer towards the center plane. In some embodiments, the clean band depth can be less than about 40 microns, as measured from the front surface of the wafer towards the center plane, such as less than about 30 microns, or less than 20 microns, less than 15 microns, or even less than 10 microns, as measured from the front surface of the wafer towards the center plane. Additionally, the template enables the peak density of oxygen precipitates (produced by subsequent annealing sufficient to form oxygen precipitates) to occur within about 40 microns of the wafer surface, such as within about 30 microns of the wafer surface, or between about 10 microns and about 20 microns from the wafer surface.

[0039] In this regard, the formed oxygen precipitate nuclei typically contain lattice vacancies as part of the nuclei. The vacancies can be bound (i.e., phase-bonded and / or grouped) oxygen, such as oxygen dimers (O2); however, it should be understood that the present disclosure is not limited to any structurally and / or morphologically specific oxygen precipitate nuclei. For example, the oxygen precipitate nuclei can be individual vacancies or can be bound as VO. As used herein, "oxygen precipitate nuclei" refers to any structural unit that forms an oxygen precipitate after oxygen precipitate heat treatment or forms such a precipitate after activation, and as used herein, "oxygen precipitate nuclei" should not be understood in a restrictive sense.

[0040] A rapid thermal process is performed to form a distribution of oxygen precipitate nuclei, and the use of establishing a template for oxygen precipitation is generally described in U.S. Pat. Nos. 5,994,761, 6,191,010, and 6,180,220, each of which is incorporated herein by reference for all relevant and consistent purposes. The so-called "desirable precipitation process" generally produces a non-uniform distribution of oxygen precipitate nuclei, with a higher concentration in the wafer body than in the surface layer. After a subsequent oxygen precipitation heat treatment, the high concentration of nuclei in the wafer body forms oxygen precipitate nucleation centers, which assist in the formation and growth of oxygen precipitates, while the concentration of nuclei in the near-surface region is not sufficient to do so. Thus, a clean band is formed in the near-surface region, and oxygen precipitates, sometimes referred to as bulk microdefects, are formed in the wafer body. As described therein, the clean band depth can be less than about 40 microns, as measured from the front surface of the wafer towards the center plane, such as less than about 30 microns, or less than 20 microns, less than 15 microns, or even less than 10 microns, as measured from the front surface of the wafer towards the center plane. The clean band depth can be at least about 1 micron, at least about 3 microns, or at least about 5 microns, as measured from the front surface of the wafer towards the center plane. Additionally, the peak density of oxygen precipitates (produced by a subsequent annealing sufficient to form oxygen precipitates) can occur within about 40 microns of the wafer surface, such as within about 30 microns of the wafer surface, or between about 10 microns and about 20 microns from the wafer surface.

[0041] A method for forming a non-uniform distribution of vacancy-containing oxygen precipitate nuclei involves a heat treatment step on a silicon wafer 10, where the wafer is heated to a high temperature to form oxygen precipitate nuclei containing vacancies in the silicon wafer 10 and thus increase the number density of the oxygen precipitate nuclei. Preferably, this heat treatment step is carried out in a rapid thermal annealing device, where the wafer is rapidly heated to the target temperature and annealed at that temperature for a relatively short period of time. Temperatures of at least about 1100 °C, at least about 1175 °C, at least about 1200 °C, or at least about 1300 °C (e.g., about 1100 °C to about 1400 °C, about 1100 °C to about 1300 °C, or about 1100 °C to about 1200 °C) can be used. The silicon wafer 10 will typically be held within these temperature ranges for at least about 1 second and usually at least several seconds (e.g., at least about 3 seconds or at least about 5 seconds or more) or even tens of seconds (e.g., at least about 20 seconds, at least about 30 seconds, at least about 40 seconds, at least about 60 seconds, at least about 120 seconds or more). In some embodiments, the silicon wafer 10 is subjected to rapid thermal annealing at two different temperatures. For example, in some embodiments, the silicon wafer 10 is annealed at a temperature between about 1100 °C and about 1200 °C for a duration between about 1 second and about 60 seconds, and then annealed at a temperature between about 1200 °C and about 1300 °C for a duration between about 1 second and about 60 seconds. In some embodiments, the wafer can be annealed at a temperature of about 1100 °C for a period between 1 and 10 seconds, such as about 1 second, and then annealed at a temperature of about 1215 °C for a period between about 5 seconds and about 20 seconds, such as about 10 seconds. Depending on the desired wafer characteristics and the atmosphere in which the wafer is annealed, the time period can range up to about 60 seconds, which is close to the limit of commercially available rapid thermal annealing devices. According to the latest experimental evidence obtained, holding the silicon wafer 10 at a determined temperature for a period of time during annealing does not cause an increase in the vacancy concentration.

[0042] Reference Figure 3B and 3C, after the rapid thermal annealing step, the silicon wafer 10 has a front layer 40 and a bulk region 50. The front layer 40 includes the region of the wafer between the front surface and a distance D (measured from the front surface towards the center plane). The bulk region 50 includes the other region of the wafer between the center plane and the surface layer. Wherein the surface layer and the bulk region have a certain concentration of oxygen precipitate nuclei containing lattice vacancies. A full depletion zone is formed in the front layer 40, and during a heat treatment sufficient to precipitate oxygen precipitates, oxygen precipitation occurs in the bulk region 50 according to the template 30 formed by the rapid thermal annealing. The depth D of the front layer 40 can be less than about 40 microns, as measured from the front surface of the wafer towards the center plane, such as less than about 30 microns, or less than 20 microns, less than 15 microns, or even less than 10 microns, such as between about 5 microns and about 40 microns, or between about 5 microns and about 30 microns, or between about 5 microns and about 20 microns, or between about 5 microns and about 10 microns. The bulk region 50 can be regarded as the material between the front layer 40 of the silicon wafer 10 and the center plane. In embodiments where the back surface is exposed to a nitriding atmosphere, a similar back layer and bulk region are formed on the back surface of the wafer.

[0043] According to the method of the present invention, the rapid thermal annealing step is carried out in the presence of a nitrogen-containing gas, i.e., a nitriding atmosphere. In some embodiments, the rapid thermal annealing step is carried out in an atmosphere containing nitrogen gas (N2) or a nitrogen-containing compound gas (such as ammonia) or a combination of such gases. In some embodiments, the ambient atmosphere may additionally include an inert gas, such as argon. Generally, annealing a wafer in a nitriding atmosphere in a rapid thermal annealing apparatus will produce a non-uniform oxygen precipitate nuclei concentration (number density) distribution in the wafer, where the peak concentration appears within about 100 microns of the surface, or within about 40 microns of the surface, such as between about 10 and about 100 microns of the surface, between about 10 and about 50 microns, or between about 10 and about 40 microns, or between about 10 and about 30 microns, or between about 10 and about 20 microns, which is exposed to the nitriding gas, and a smaller and relatively uniform concentration is produced in the wafer body. If the front and back surfaces of the wafer are exposed to a nitriding atmosphere during the rapid thermal annealing step, then the resulting wafer will generally have an oxygen precipitate nuclei concentration (number density) distribution that is "M-shaped" or "U-shaped" for the cross-section of the wafer, i.e., the maximum concentration will appear within several microns of each of the front and back surfaces and will be relatively constant and a smaller concentration will appear throughout the wafer body. See Figure 3B , which depicts the oxygen precipitate nuclei concentration distribution or template 30, where the peak oxygen precipitate nuclei concentration is close to the front surface of the silicon wafer 10. Although not shown, a similar oxygen precipitate nuclei concentration template to the template 30 will also appear near the back surface of the silicon wafer 10. Therefore, the silicon wafer 10 will contain two peaks of oxygen precipitate nuclei concentration, one peak close to the front surface of the wafer 10 and one peak close to the back surface of the wafer 10.

[0044] After completion of the rapid thermal annealing step, the silicon wafer 10 is rapidly cooled through a temperature range in which oxygen precipitates with vacancies nucleate and, in particular, in which the vacancies themselves move relative to one another in the single crystal silicon. Over a commercially useful period of time down to a temperature of greater than about 700 °C, greater than about 800 °C, greater than about 900 °C or even greater than about 1000 °C, oxygen precipitates with vacancies typically nucleate in the silicon. As the temperature of the wafer is reduced through this temperature range, the vacancy-containing nuclei diffuse to the surface of the wafer and / or an oxide layer on the surface of the wafer and are eliminated, thereby causing a change in the nuclei concentration profile, the degree of change depending on the length of time the wafer is held at a temperature within this range. If the wafer is held at a temperature within this range for an infinite length of time, the nuclei concentration profile will again become uniform but the equilibrium concentration will be less than the concentration just after completion of the heat treatment step. However, as further described herein, by rapidly cooling the wafer by controlling the heat treatment and the environment in which the wafer is cooled, either alone or in combination, a non-uniform distribution of oxygen precipitate nuclei can be achieved, with a greater concentration in the bulk of the wafer than in regions closer to the surface. For example, the method conditions (such as the cooling rate) can be controlled such that the maximum nuclei concentration is within about 100 microns of the surface, or within about 40 microns of the surface, such as between about 10 and about 100 microns of the surface, between about 10 and about 50 microns, between about 10 and about 40 microns, between about 10 and about 30 microns, or between about 10 and about 20 microns of the surface.

[0045] In this regard, it should be further noted that, in general, as used herein, a "clean band" is a region that occupies an area close to the surface of the wafer and has: (i) no oxygen precipitates, defined as less than about 10 7 oxygen precipitates per cubic centimeter, less than about 10 6 oxygen precipitates per cubic centimeter or even less than about 10 5 oxygen precipitates per cubic centimeter; and (ii) a low concentration and preferably substantially no oxygen precipitate nuclei that convert to oxygen precipitates upon undergoing an oxygen precipitation heat treatment.

[0046] The cooling step may suitably be carried out in the same atmosphere as the atmosphere in which the heating step is carried out. However, it may also be carried out in a different atmosphere, which can adjust the shape of the nuclei concentration profile. Regardless of the atmosphere selected, the effect of rapidly cooling the wafer dominates the atmosphere factor and causes a significant reduction in the concentration of vacancies in the region near the surface. The rapid thermal annealing step and the cooling step can be carried out, for example, in any of a variety of commercially available rapid thermal annealing ("RTA") furnaces in which the wafers are heated independently by rows of high-power lamps. RTA furnaces are capable of rapidly heating silicon wafers in seconds, for example from room temperature to about 1200 °C.

[0047] Generally, the average cooling rate within the temperature range in which oxygen precipitate nuclei move is at least about 5 °C per second or, as in other embodiments, at least about 20 °C per second, at least about 50 °C per second, at least about 100 °C per second or even at least about 150 °C per second or greater (e.g., from about 20 °C per second to about 200 °C per second, from about 20 °C per second to about 100 °C per second or from about 100 °C per second to about 200 °C per second). Typically, current processing equipment produces cooling rates between about 30 °C per second and about 80 °C per second and more typically, between about 40 °C per second and about 50 °C per second. In this regard, it should be noted that once the wafer is cooled to a temperature outside the temperature range in which vacancy-containing oxygen precipitate nuclei move relative to each other in single-crystalline silicon, the cooling rate no longer exhibits a significant effect on the precipitation characteristics of the wafer and thus is no longer a strict limitation.

[0048] A silicon nitride layer 20 is formed on the front layer of the silicon wafer 10 by performing rapid thermal annealing in a nitrogen-containing atmosphere, see Figure 3B . Since the RTA process occurs within seconds, the silicon nitride layer is generally relatively thin, such as at least about 5 angstroms, e.g., between about 5 angstroms and about 1000 angstroms, or between about 5 angstroms and about 500 angstroms, or between about 5 angstroms and about 200 angstroms, or between about 5 angstroms and about 100 angstroms. Since the silicon nitride layer 20 interrupts the formation of the oxide layer during subsequent oxidation cycles and the barrier to vacancy implantation and its out-diffusion, the nitride layer is removed. See Figure 3C . In some embodiments, the silicon nitride layer is removed by polishing, wet chemical etching (e.g., KOH etching or phosphoric acid etching) or plasma etching. Techniques suitable for removing the silicon nitride layer are known in the art.

[0049] In some embodiments, the silicon nitride layer 20 is removed by contact polishing. Contact polishing is sufficient to remove the entire silicon nitride layer. Suitable polishing solutions for removing the silicon nitride layer are known in the art.

[0050] In some embodiments, the silicon wafer 10 is cleaned after removing the silicon nitride layer. A suitable cleaning solution is a piranha solution, which comprises H2SO4 (concentrated) and H2O2 (30% solution), which is typically in a 3:1 ratio but other ratios such as 4:1 or 7:1 are also suitable. The cleaning duration is preferably between about 15 minutes and about 2 hours.

[0051] III. Oxidation Annealing

[0052] After stripping the silicon nitride layer (see Figure 3C ), the silicon wafer 10 is subjected to oxidation annealing for a duration and at a temperature sufficient to form a silicon oxide layer 60 on the front of the silicon wafer 10. See Figure 3DThe oxidation of the silicon wafer 10 can be accomplished by thermal oxidation (wherein a portion of the deposited semiconductor material film will be consumed) or the film can be grown by CVD oxide deposition. In some embodiments, the silicon wafer 10 can be thermally oxidized in a furnace such as an ASM A400. In an oxidation environment, the temperature can be in the range of 900 °C to 1100 °C, such as between about 950 °C and about 1100 °C or between about 1000 °C and about 1100 °C. The annealing duration can be at least about 30 minutes, such as greater than about 60 minutes, greater than about 120 minutes, such as greater than about 180 minutes, or greater than about 240 minutes, greater than about 300 minutes, or greater than about 360 minutes.

[0053] In some embodiments, the single-crystalline silicon wafer is heat-treated in an oxidizing atmosphere containing an oxygen-containing gas at a temperature between about 900 °C and about 1100 °C, such as between about 900 °C and about 1000 °C, for a duration of at least about 30 minutes, such as greater than about 60 minutes, greater than about 120 minutes, such as greater than about 180 minutes, or greater than about 240 minutes, greater than about 300 minutes, or greater than about 360 minutes, such as between about 30 minutes and about 360 minutes, or between about 60 minutes and about 360 minutes, or between about 1200 minutes and about 360 minutes. In some embodiments, the single-crystalline silicon wafer is heat-treated in an oxidizing atmosphere containing an oxygen-containing gas at a temperature between about 950 °C and about 1100 °C, such as between about 950 °C and about 1050 °C, for a duration of at least about 30 minutes, such as greater than about 60 minutes, such as greater than 120 minutes, such as greater than 180 minutes, or greater than about 240 minutes, greater than 300 minutes, or greater than about 360 minutes, such as between about 30 minutes and about 360 minutes, or between about 60 minutes and about 360 minutes, or between about 1200 minutes and about 360 minutes. In some embodiments, the single-crystalline silicon wafer is heat-treated in an oxidizing atmosphere containing an oxygen-containing gas at a temperature between about 1000 °C and about 1100 °C, such as between about 1050 °C and about 1100 °C, for a duration of at least about 30 minutes, such as greater than about 60 minutes, greater than about 120 minutes, such as greater than about 180 minutes, or greater than about 240 minutes, greater than about 300 minutes, or greater than about 360 minutes, such as between about 30 minutes and about 360 minutes, or between about 60 minutes and about 360 minutes, or between about 1200 minutes and about 360 minutes. The oxidizing ambient atmosphere can be a mixture of an inert gas such as Ar or N2 and O2. The oxygen content can vary between 1 and 10 percent or higher. In some embodiments, the oxidizing ambient atmosphere can be up to 100% (“dry oxidation”). In some embodiments, the ambient atmosphere can contain a mixture of an inert gas such as Ar or N2, an oxidizing gas such as O2, and water vapor (“wet oxidation”). In an exemplary embodiment, the silicon wafer 10 can be loaded into a vertical furnace, such as an A400. The temperature is gradually raised to the oxidation temperature and an appropriate oxidizing gas such as O2 is introduced into the furnace. Various gas conditions for oxidation can be used to produce an oxide layer, such as a combination of N2 (4 slm) and O2 (20 slm). After the desired oxide thickness is obtained, the O2 is turned off, the furnace temperature is lowered, and the wafer is unloaded from the furnace. Generally, the thickness of the oxide layer is greater than about 50 angstroms, such as between about 50 angstroms and about 1000 angstroms, or between about 50 angstroms and about 500 angstroms. In some embodiments, annealing by oxidation at a temperature of about 900 °C for about 0.5 hour produces a silicon dioxide layer having a thickness of about 50 angstroms or greater. In some embodiments, annealing by oxidation at a temperature of about 900 °C for about 4 hours produces a silicon dioxide layer having a thickness of about 350 angstroms or greater.

[0054] The oxidation annealing is not for the purpose of growing oxygen precipitates in the wafer body. According to some embodiments of the present invention, the oxygen precipitate heat treatment, such as NEC1 annealing, occurs after the GOI yield test. Specifically, the oxidation annealing is sufficient to dissolve the oxygen precipitates near the wafer surface or reduce their size until they are undetectable and do not cause a reduction in GOI. The oxidation annealing supplies interstitial silicon atoms to the wafer body from the SiO2 / Si interface. For the gate oxide integrity test, the silicon oxide layer 60 is removed, which can further remove the types of defects that cause a reduction in the GOI yield. In some embodiments, the silicon oxide layer 60 is removed by polishing, chemical etching, or plasma etching. The techniques suitable for removing the silicon oxide layer are known in the art. For example, chemical etching using HF is sufficient to remove a silicon oxide layer with a thickness that may range from 0.1 micrometer to 1 micrometer, such as about 0.5 micrometer.

[0055] Wafer cleaning and polishing are optional. If needed, the wafer can be cleaned, for example, in a standard SC1 / SC2 solution. Additionally, the wafer can be subjected to chemical mechanical polishing (CMP) to reduce the surface roughness, preferably to a level where the root mean square (RMS) 2×2μm2 is less than about 5 angstroms, such as between about 1 angstrom and about 2 angstroms, where the root mean square -

[0056]

[0057] roughness distribution contains ordered equally spaced points along a trace, and y i is the vertical distance from the average line to the data point. At a surface roughness preferably less than 2 angstroms, the surface can bond.

[0058] IV. Gate Oxide Integrity Yield

[0059] According to the method of the present invention, the gate oxide integrity reduction caused by rapid thermal annealing in a nitrogen-containing ambient atmosphere is restored by oxidation annealing, which eliminates the source of GOI defects. The oxidation annealing promotes the out-diffusion of nitrogen and further changes the size of the as-grown oxygen precipitates.

[0060] Forming a silicon oxide layer on the wafer surface generates interstitial silicon and consumes vacancies. During the formation of the silicon oxide layer, the following reaction occurs:

[0061] 2Oi ＝ + Si --> SiO2 + 4e -

[0062] This reaction involves interstitial silicon and if Si I--If O decomposes before the formation of SiO2, the likelihood of generating free self-interstitials will be greatest. It is estimated that the incidence of such incomplete oxidation steps is 1 in 1000 silicon atoms. The formation rate of silicon interstitials can be calculated from the oxidation rate and the surface regeneration rate.

[0063] Figure 4 A graph showing that as the oxidation rate and surface regeneration rate increase with temperature, the concentration of silicon interstitials thus increases with increasing temperature. Therefore, if the oxidation temperature increases, the diffusion-controlled implantation of silicon interstitials on the wafer surface increases. The inward diffusion of silicon interstitials can cause interstitial supersaturation and vacancy undersaturation during high-temperature oxidation annealing. High-temperature oxidation annealing can change the equilibrium point defect concentration or inhibit the growth of as-grown oxygen precipitates during oxidation, causing the decomposition of as-grown precipitates. If sufficient interstitials are continuously implanted and the annealing time is long enough to decompose the precipitates, the size of the oxygen precipitates will decrease or completely dissolve. Thus, oxidation annealing removes the source of GOI defects caused by rapid thermal annealing in a nitriding ambient atmosphere or mitigates the effect of as-grown precipitates combined with nitrogen.

[0064] The gate oxide integrity yield can be measured by the Time Zero Dielectric Breakdown (TZDB) test method for the reliability of the gate oxide in MOS devices. This test method measures the voltage applied per oxide thickness in the gate oxide. The gate oxide (transistor structure: source-gate-drain using N-P-N or P-N-P) is an electrically insulating layer that controls the minority carrier channel below the gate oxide between the source and the drain. Whether the channel is formed is determined by the bias voltage applied to the gate. Whether there is a channel means 1 or 0, and the gate bias controls 1 or 0. If the gate oxide is not electrically insulating, the channel between the source and the drain is not controlled by the gate bias. Therefore, the oxide layer at the gate is crucial for normal transistor operation. The gate oxide integrity test is performed by changing the applied bias voltage, which enables the evaluation of the reliability of electrical insulation. TZDB is a test method for checking the breakdown of the oxide layer by increasing the bias voltage from 0V to a voltage sufficient to break down the electrical insulation. During the test, if the gate oxide breaks down at a voltage of 9 MV / cm (megavolts per centimeter) or higher, or if no breakdown occurs, the wafer surface has excellent quality conditions for the gate because the wafer surface does not have a source that causes degradation of the gate oxide.

[0065] Reference Figure 5 The effect on the GOI yield can be observed, Figure 5Depicts the GOI yield of as-grown wafers (leftmost wafer), wafers subjected to long-duration oxidation annealing (second wafer from the left), and two wafers subjected to rapid thermal annealing in an oxidizing ambient atmosphere (right). As can be seen in Figure 5, the long-duration yield in an oxidizing environment sufficiently improves the GOI yield, but rapid thermal annealing does not do so sufficiently, as evidenced by the pattern of gate oxide integrity degradation defects.

[0066] In addition, Figure 6A 、 6B and 6C show that long-duration oxidation annealing enables maintaining a high concentration of BMD throughout the bulk region of the wafer and maintaining the depth of the shallow precipitate-free region after annealing suitable for growing BMD in the wafer bulk. Rapid thermal annealing causes a decrease in BMD concentration and an increase in the depth of the precipitate-free region. Figure 6A Depicts the BMD depth profile of a wafer subjected to rapid thermal annealing in an ammonia-containing environment and then in an oxidizing environment (5 seconds at 1000 °C) (after oxidation precipitation heat treatment; 4 hours of NEC1 treatment at 800 °C followed by 16 hours of NEC1 treatment at 1000 °C). Figure 6B Depicts the BMD depth profile of a wafer subjected to rapid thermal annealing in an ammonia-containing environment followed by rapid thermal annealing in an oxidizing environment (5 seconds at 1100 °C) (after oxidation precipitation heat treatment of 4 hours at 800 °C + 16 hours at 1000 °C). Figure 6C Depicts the BMD depth profile of a wafer subjected to long-duration oxidation annealing between 900 °C and 1000 °C for 4 hours (after oxidation precipitation heat treatment of 4 hours at 800 °C + 16 hours at 1000 °C).

[0067] According to some embodiments of the present invention, defects (such as oxygen precipitates) at the wafer surface become undetectable. As Figure 6C shown, no detectable defects were observed from the surface to a depth of about 10 μm despite the application of heat treatment for the nucleation and growth of oxygen precipitates. Figure 7 Depicts the GOI integrity results of various wafers subjected to long-duration oxidation annealing at several temperatures. The wafers depicted include as-grown wafers (leftmost wafer), wafers after rapid thermal annealing in a nitriding environment (second wafer from the left), and three wafers subjected to oxidation annealing at 900 °C, 950 °C, and 1000 °C for 360 minutes (right). As Figure 7 shown, long-duration oxidation annealing effectively improves the GOI yield at several temperatures, as evidenced by the absence of the pattern of gate oxide integrity degradation defects.

[0068] The latest experimental results provide sufficient to fabricate Figure 8The data of the contour map depicted therein depict the duration and temperature sufficient to achieve an improvement in the gate oxide integrity yield of a silicon wafer after rapid thermal annealing in a nitriding ambient atmosphere. The present invention relates to a method for generating an M-shaped BMD depth profile associated with rapid thermal annealing in a nitriding ambient atmosphere. In such a profile, the peak BMD density occurs near the front layer, and the front layer includes a precipitate-free clean band having a depth generally less than about 40 microns, less than about 30 microns, or even less than about 20 microns, such as between about 10 microns and about 20 microns. Oxidative annealing restores the GOI yield of the surface of the wafer.

[0069] According to the latest current theory, the formation of the SiO2 layer at the wafer surface generates interstitial silicon by consuming vacancies, and it is expected that the implanted interstitial silicon atoms will dissolve or reduce the size of the growing oxygen precipitates by crystal growth and will consume the supersaturated vacancies generated by rapid thermal annealing in a nitriding atmosphere located at a specific depth at the wafer surface. Using ideal silicon without GOI failure as the input material, and testing various temperature and time conditions for oxidation to find the minimum oxidation details. Although the input material is favorable for GOI, the GOI yield still decreases after rapid thermal annealing in a nitriding atmosphere. According to the method of the present invention, oxidative annealing after removing the silicon nitride layer generated by rapid thermal annealing improves the reduced GOI yield at various oxidative annealing durations and temperatures. See Figure 8 Higher oxidation temperatures and longer annealing durations are suitable for removing GOI defects because the density and diffusion length of the implanted interstitials increase at the interface between the oxide and the wafer. Therefore, the test results in the present disclosure match the hypothesis well and confirm that oxidation is a practical (low-cost) method for solving the problem of GOI reduction after rapid thermal annealing without any change in the peak BMD density and the shallow PFZ.

[0070] V. Oxygen Precipitation Heat Treatment

[0071] Any heat treatment sufficient to nucleate and grow oxygen precipitates is suitable for preparing the wafers of the present invention. In some embodiments, the wafer is subjected to an oxygen precipitation heat treatment at a temperature above about 700 °C for a duration sufficient to nucleate and grow oxygen precipitates. In some embodiments, the wafer is subjected to an oxygen precipitation heat treatment comprising the NEC1 test procedure (e.g., annealing the wafer at 800 °C for 4 to 8 hours and then annealing at 1000 °C for 16 hours). In some embodiments, the oxygen precipitation heat treatment prepares a wafer comprising oxygen precipitates having an average concentration of at least about 1×10 7 precipitates / cm3 or at least about 1×10 8 precipitates / cm3 from the central axis to the circular periphery. In some embodiments, the oxygen precipitation heat treatment prepares a wafer comprising oxygen precipitates having an average concentration of at least about 5×10 8A wafer with oxygen precipitates of [number of precipitates] per cubic centimeter. In some embodiments, the oxygen precipitate heat treatment prepares a wafer containing oxygen precipitates with an average concentration of at least about 1×10 9 per cubic centimeter from the central axis to the circumferential edge. In some embodiments, the oxygen precipitate heat treatment prepares a wafer containing oxygen precipitates with an average concentration of at least about 5×10 9 per cubic centimeter from the central axis to the circumferential edge. In some embodiments, the oxygen precipitate heat treatment prepares a wafer containing oxygen precipitates with an average concentration of at least about 1×10 10 per cubic centimeter from the central axis to the circumferential edge. In the bulk region, the depth of the peak concentration of oxygen precipitates occurs within about 10 to about 100 microns from the surface, such as within about 20 to about 100 microns from the surface, such as between about 20 to about 50 microns, such as between 20 to about 30 microns, or between about 10 microns and about 20 microns from the surface.

[0072] Thus, the method of the present invention prepares a silicon wafer having a precipitate-free region in the front layer and a bulk region containing oxygen precipitates. The depth D of the front layer containing the precipitate-free region can be less than about 40 microns, less than about 30 microns, less than about 20 microns, less than about 15 microns, or even less than about 10 microns. In some embodiments, the depth D of the front layer containing the precipitate-free region can be at least about 1 micron, at least about 3 microns, or at least about 5 microns, as measured from the front of the wafer towards the central plane. A wafer substantially free of oxygen precipitate nucleation centers shall mean a wafer having less than 10 7 oxygen precipitates per cubic centimeter or less than 10 6 oxygen precipitates per cubic centimeter after annealing at a temperature of 800°C for four hours and then annealing at a temperature of 1000°C for sixteen hours. The method of the present invention is sufficient to dissolve smaller endogenous oxygen precipitates close to the wafer surface and further reduce the size of the undissolved endogenous oxygen precipitates. Accordingly, the density of both detectable and non-detectable sized oxygen precipitates is reduced. Correspondingly, in some embodiments, the front layer is substantially free of oxygen precipitates. The method of the present invention enables the preparation of a wafer having a front side that does not have a crystal defect band associated with the gate oxide integrity pattern. That is, the front side does not have defect types that reduce the GOI, as measured by standard tests.

[0073] VI. Post - Processing of the Wafer

[0074] The silicon wafers of the present invention can be used in various applications. For example, such wafers with a polished bare silicon surface (i.e., polished wafers) can be directly used in the integrated circuit manufacturing process. Alternatively, the wafers can be used as substrates for epitaxial deposition or SOI (by layer transfer or oxygen implantation).

[0075] 1. Etching

[0076] When necessary, the near-surface region of the wafer, such as typically up to about 2 micrometers, can be substantially or even completely removed by chemical etching using an etchant and techniques conventional in the art.

[0077] 2. Polishing

[0078] When necessary, before or after oxygen precipitation, the wafer can be chemically or chemically mechanically polished to a mirror finish.

[0079] 3. Epitaxial Layer

[0080] The wafer can be prepared for epitaxial layer deposition. If an epitaxial layer is to be deposited on the wafer, then the method of the present invention can be carried out before or after epitaxial deposition. If carried out before, then it may be necessary to stabilize the oxygen precipitate nucleation centers in the wafer after the method of the present invention and before epitaxial deposition. If carried out after, then it may be necessary to carry out the method of the present invention immediately after epitaxial deposition in an epitaxial reactor, provided that the cooling rate required for the method of the present invention can be achieved.

[0081] The epitaxial layer can be deposited over the entire wafer or, alternatively, only on a portion of the wafer. The epitaxial layer is preferably deposited on the front side of the wafer. More preferably, it is deposited over the entire front side of the wafer. Whether it is preferred to deposit the epitaxial layer on any other part of the wafer will depend on the intended use of the wafer. For most applications, the presence or absence of an epitaxial layer on any other part of the wafer is not critical.

[0082] The wafer surface can include an oxide or nitride layer. For example, when exposed to air at room temperature, a silicon oxide layer is formed on the silicon surface and typically has a thickness of about 10 to about Preferably, before depositing the epitaxial layer on the surface, the nitride, oxide or nitride / oxide layer is removed from the surface of the wafer.

[0083] Removal of the silicon oxide or nitride / oxide layer can be accomplished by heating the surface of the wafer in an oxidant-free atmosphere until the oxide or nitride / oxide layer is removed from the surface. For example, the surface of the wafer is preferably heated to a temperature of at least about 1100 °C and more preferably heated to a temperature of at least about 1150 °C. This heating is preferably carried out while exposing the surface of the wafer to an atmosphere containing H2 or a noble gas (such as He, Ne or Ar). More preferably, the atmosphere contains H2. Most preferably, the atmosphere consists essentially of H2 because the use of other atmospheres tends to cause the formation of etch pits on the surface of the wafer.

[0084] Typically, it is preferred to heat the wafer surface to remove the silicon oxide or nitride / oxide layer and then initiate silicon deposition less than 30 seconds (more preferably within about 10 seconds) after the oxide or nitride / oxide has been removed. Typically, this can be accomplished by heating the wafer surface to a temperature of at least about 1100 °C (more preferably at least about 1150 °C) and then initiating silicon deposition less than 30 seconds (more preferably within about 10 seconds) after the wafer surface has reached said temperature. After the silicon oxide or nitride / oxide layer has been removed, waiting up to about 10 seconds before initiating silicon deposition allows the temperature of the wafer to stabilize and become uniform.

[0085] Alternatively, the oxide or nitride / oxide layer can be chemically stripped. In embodiments where the silicon surface has a nitride / oxide layer, chemical stripping is the preferred method for removing the nitride / oxide layer. Chemical stripping can be accomplished using phosphoric acid, hydrofluoric acid, or other acids known in the art. In another alternative, the oxide or nitride / oxide layer can be etched by plasma etching, using, for example, eMAX from Applied Materials, or other methods known in the art.

[0086] In embodiments where the surface layer is primarily a silicon nitride layer, the nitride layer can be removed by polishing, chemical etching, or plasma etching (such as eMAX from Applied Materials, or other etching methods known in the art).

[0087] Epitaxial deposition is preferably carried out by chemical vapor deposition. Generally, chemical vapor deposition involves exposing the surface of the wafer to an atmosphere containing silicon in an epitaxial deposition reactor, such as a Centura reactor available from Applied Materials. Preferably, the surface of the wafer is exposed to an atmosphere containing a silicon-containing volatile gas (such as SiCl4, SiHCl3, SiH2Cl2, SiH3Cl, or SiH4). The atmosphere also preferably contains a carrier gas (preferably H2). For example, the source of silicon during epitaxial deposition can be SiH2Cl2 or SiH4. If SiH2Cl2 is used, then the reactor vacuum pressure is preferably about 500 to about 760 Torr during deposition. On the other hand, if SiH4 is used, then the reactor pressure is preferably about 100 Torr. Most preferably, during deposition, the source of silicon is SiHCl3. This tends to be much cheaper than other sources. In addition, epitaxial deposition using SiHCl3 can be carried out at atmospheric pressure. This is advantageous because no vacuum pump is required and the reactor chamber does not necessarily have to be rugged to prevent collapse. In addition, it presents fewer safety hazards and reduces the chance of air or other gases leaking into the reactor chamber.

[0088] During epitaxial deposition, the temperature of the wafer surface is preferably gradually raised to and maintained at a temperature sufficient to prevent deposition of a silicon-containing atmosphere on the surface of the polysilicon. Generally, during this period, the temperature of the surface is preferably at least about 900 °C. More preferably, the temperature of the surface is maintained in the range between about 1050 °C and about 1150 °C. Most preferably, the temperature of the surface is maintained at the silicon oxide removal temperature.

[0089] The growth rate of epitaxial deposition is preferably from about 0.5 to about 7.0 microns per minute. For example, at a temperature of about 1150 °C and an absolute pressure of up to about 1 atm, a rate of about 3.5 to about 4.0 microns per minute can be achieved by using an atmosphere consisting essentially of about 2.5 mol% SiHCl3 and about 97.5 mol% H2.

[0090] In some applications, the wafer comprises an epitaxial layer that imparts electrical properties. In some embodiments, the epitaxial layer is lightly doped with phosphorus. Accordingly, the environment for epitaxial deposition contains phosphorus in the form of a volatile compound, such as phosphine (PH3). In some embodiments, the epitaxial layer may contain boron. Such layers can be prepared, for example, by including B2H6 in the atmosphere during deposition.

[0091] Epitaxial deposition typically requires a post-epitaxial cleaning step after epitaxial deposition to remove by-products formed during epitaxial deposition. If such by-products react with air, they can cause time-dependent hazing, and this step is used to prevent time-dependent hazing. In addition, many post-epitaxial cleaning techniques tend to form a silicon oxide layer on the epitaxial surface, which tends to passivate (i.e., protect) the surface. The epitaxial wafers of the present invention can be cleaned by methods known in the art.

[0092] 4. Silicon on Insulator (SOI)

[0093] Wafers prepared according to embodiments of the present disclosure can also be incorporated into silicon-on-insulator structures. Silicon-on-insulator structures typically comprise a device layer, a handle wafer or support layer, and an insulating film or layer (usually an oxide layer) between the support layer and the device layer. Generally, the thickness of the device layer is between about 0.5 μm and about 20 μm. Silicon-on-insulator structures can be prepared using various techniques known in the art, as further described hereinbelow.

[0094] If the support layer of the SOI structure comprises or is derived from a wafer of the present disclosure, then preferably, the method (e.g., forming for oxygen precipitation and activating non-active oxygen precipitate nuclei templates) will be performed before the device layer of the SOI structure has been bonded to the disposal wafer (or in the case of an ion implantation process, before implantation is carried out). If the method of the present invention is performed before forming the SOI structure, then it may be necessary to stabilize the oxygen precipitate nucleation centers in the disposal wafer after the method is completed and before the preparation of the SOI structure begins. Additionally, if this method is employed, then in some embodiments, the oxygen precipitation heat treatment of step S2 can be achieved during the formation of the SOI structure (such as in the case of wafer bonding), provided that the processing time and temperature employed in the SOI process are sufficient to form oxygen precipitates.

[0095] However, it should be further noted that the silicon wafer method of the present invention can also be performed after the SOI structure has been prepared. Without being limited by any particular theory, it is believed that the SOI structure will behave as a typical single crystal silicon wafer, with the oxide layer serving as a free surface into which vacancies and self-interstitials can be injected and diffuse.

[0096] The SOI structure can be prepared, for example, by an ion implantation process on a wafer of the present disclosure through a SIMOX process, as noted above, which ion implantation process is a standard process in the art, as disclosed in U.S. Patent No. 5,436,175 and Plasma Immersion Ion Implantation for Semiconductor Processing, Materials Chemistry and Physics 46 (1996) 132-139, which are hereby incorporated by reference for all relevant and consistent purposes. In such processes, ions are implanted into a silicon wafer substrate, and subsequently, the silicon wafer substrate is subjected to a high-temperature annealing to form an oxide insulating buried layer. If, for example, oxygen ions are implanted, then a buried silicon dioxide (SiO2) insulating layer is formed. If nitrogen atoms are implanted, then a silicon nitride (Si3N4) buried layer is formed. In such cases, the resulting SOI structure comprises a device layer and an insulating layer, both derived from a wafer produced by the method of the present disclosure. Due to the high-temperature oxide formation annealing, typically from about 1150 °C to about 1400 °C, the oxygen solubility in the wafer exceeds the typical oxygen concentration, such that pre-existing precipitates can dissolve and become interstitial oxygen. In such cases, for some applications, a secondary annealing for oxygen reduction can be performed after the SIMOX process. Then this embodiment generally comprises the following: performing a rapid thermal annealing and cooling process on a single crystal silicon wafer having substantially any oxygen concentration obtainable using the Cz pulling technique; forming an oxide insulating layer in the wafer; and performing a secondary annealing at a temperature in the range of about 700 °C to about 1100 °C.

[0097] The SOI structure can also be prepared by bonding two wafers and removing a portion of one of the bonded wafers. For example, the SOI structure can be prepared by the BESOI process, in which the wafer of the present disclosure is bonded to another wafer, and then a substantial portion of one of the wafers is etched away using known wafer thinning techniques to obtain a device layer, as disclosed in U.S. Patent Nos. 5,024,723 and 5,189,500, which are hereby incorporated by reference for all relevant and consistent purposes. In this case, the resulting SOI structure includes: (i) a device layer, (ii) a handle wafer or support layer, and (iii) an insulating layer between the device layer and the support layer.

[0098] In an alternative wafer bonding method, hydrogen or another ion is implanted into one of the wafers and, after the two wafers are bonded, a force is applied to the bonded composite, which causes the bonded composite to split at the implantation site. For example, the SOI structure can be prepared by: (1) implanting ions (such as hydrogen, nitrogen, etc.) in the wafer of the present disclosure by bombarding to generate a layer of gaseous microbubbles while maintaining the temperature below the temperature at which the gaseous microbubbles can escape by diffusion; (2) bringing a reinforcement into contact with the wafer plane to form a bonded composite; and (3) applying heat or mechanical stress to the bonded composite, causing the wafer of the present disclosure to delaminate in the region of ion implantation. If thermal stress is used, the composite is heated to a temperature higher than the temperature at which ion implantation occurs to produce a crystallization rearrangement and pressure effect in the microbubbles, causing separation between the thin semiconductor film and most of the substrate, as disclosed in U.S. Patent No. 5,374,564, which is hereby incorporated by reference for all relevant and consistent purposes. If the SOI structure includes the wafer of the present disclosure as a reinforcement, then in one or more embodiments, the wafer is subjected to the ideal precipitation process described above before being bonded to the plane of another wafer. In other embodiments, a low-defect-density silicon wafer can first be bonded to a Czochralski-type single-crystalline silicon wafer, and then the entire SOI structure can be subjected to the ideal precipitation process and nuclear activation process described above.

[0099] In view of the above, several objects of the present invention will be found to have been achieved.

[0100] This written description uses examples to disclose the invention, including the best mode, and also enables any person skilled in the art to practice the invention, including making and using any device or system and performing any incorporated method. The patentable scope of the invention is defined by the claims and may include other examples that occur to those skilled in the art. If such other examples have elements that are not different in literal language from the claims, or if such other examples include equivalent elements that are not materially different from the literal language of the claims, then such examples are intended to be within the scope of the claims.

Claims

1. A single-crystalline silicon wafer, which comprises two main parallel surfaces, one of which is a front side and the other is a back side, a central plane between the front side and the back side, a circular peripheral edge connecting the front side and the back side, a front layer having a depth D measured from the front side towards the central plane, and a body region is between the front layer and the central plane, wherein: The single-crystalline silicon wafer has a thickness between 500 microns and 1000 microns, and wherein: The main body region contains oxygen precipitates with a density of at least 1×10 8 cm -3 and a peak density of oxygen precipitates of at least 5×10 9 cm -3 , where the peak density is between at least 10 μm and less than 20 μm from the front surface of the single-crystalline silicon wafer; The front layer contains oxygen precipitates with a density less than 1×10 7 cm -3 , wherein the depth D of the front layer is between 1 micron and 10 microns; The front side does not have a band of crystal defects related to a gate oxide integrity pattern, and wherein the single-crystalline silicon wafer is P-type and has a resistivity of less than 10 milliohm·centimeters.

2. The single-crystalline silicon wafer according to claim 1, wherein the body region contains interstitial oxygen with a concentration between 2×10 17 atoms / cm³ and 5×10 17 atoms / cm³.

3. The monocrystalline silicon wafer according to claim 1, wherein the body region comprises oxygen precipitates having an average density of at least 1×10 9 cm -3 .

4. The single-crystalline silicon wafer according to claim 1, wherein the front layer comprises oxygen precipitates having a density of less than 1×10 6 cm -3 , and the depth D of the front layer is between 5 micrometers and 10 micrometers.

5. The single-crystalline silicon wafer according to claim 1, wherein the front layer comprises oxygen precipitates having a density of less than 1×10 5 cm -3 , and the depth D of the front layer is between 5 micrometers and 10 micrometers.

6. The single-crystalline silicon wafer according to claim 1, wherein the depth D of the front layer is between 5 microns and 10 microns.

7. The single-crystalline silicon wafer according to claim 1, wherein the single-crystalline silicon wafer has a thickness between 725 microns and 800 microns.

8. The single-crystalline silicon wafer according to claim 1, wherein the single-crystalline silicon wafer has a thickness between 750 microns and 800 microns.

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