A memory cell, three-dimensional memory, and methods of operating the same

Abstract

The present disclosure provides a storage unit, comprising: a channel layer array, comprising: N channel layers, the N channel layers are vertically arranged on a substrate along a first direction, a tunneling layer and a storage layer are sequentially arranged outside the N channel layers, N is a positive integer; N heat-conducting cores, respectively located in the N channel layers and penetrating the substrate; a thermocouple array, comprising: a thermocouple word line layer grown on the substrate along a negative direction of the first direction and N thermocouple layers located on the thermocouple word line layer, the N thermocouple layers are connected in one-to-one correspondence with the N heat-conducting cores; wherein a first potential difference is applied between the thermocouple word line layer and part of the N thermocouple layers, a heat treatment is performed on the heat-conducting core connected with the part of the thermocouple layers, and the channel layer and the storage layer corresponding to the heat-conducting core maintain a first preset temperature and a second preset temperature respectively under the heat insulation effect of the tunneling layer. The present disclosure also provides a three-dimensional memory and an operating method thereof.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of three-dimensional memory, in particular to a storage unit, a three-dimensional memory and an operating method thereof. BACKGROUND

[0002] Three-dimensional NAND memory technology is a technology that is currently being developed by the state, which can be applied to multi-bit storage technology, such as 4bit / cell or 5bit / cell, and high data density three-dimensional memory is the basis for building a big data and cloud storage system. The multi-bit storage technology of three-dimensional memory requires clear read space (ESUM) between data states. Higher channel temperature during write operation is beneficial to achieve better ESUM. However, higher storage layer temperature is not conducive to data retention, which can easily cause data retention failure. SUMMARY

[0003] In view of the above problems, the present disclosure provides a storage unit, a three-dimensional memory and an operating method thereof to solve the above technical problems.

[0004] A first aspect of the present disclosure provides a storage unit, comprising: a channel layer array, comprising: N channel layers, the N channel layers are vertically arranged on a substrate along a first direction, a tunneling layer and a storage layer are sequentially arranged outside the N channel layers, and N is a positive integer; N heat conduction cores, respectively located in the N channel layers and penetrating the substrate; and a thermocouple array, comprising: a thermocouple word line layer grown on the substrate along a negative direction of the first direction and N thermocouple layers located on the thermocouple word line layer, the N thermocouple layers are connected to the N heat conduction cores one by one; wherein a first potential difference is applied between the thermocouple word line layer and part of the N thermocouple layers, a heat treatment is performed on the heat conduction cores connected to the part of the N thermocouple layers, and the channel layers and the storage layers corresponding to the heat conduction cores are maintained at a first preset temperature and a second preset temperature respectively under the heat insulation effect of the tunneling layer.

[0005] Further, the storage unit is configured to: after the temperature of part of the channel layers and the storage layers corresponding thereto in the channel layer array is maintained at the first preset temperature and the second preset temperature respectively, a write voltage is applied to a gate layer of the storage unit, the drain layer and the substrate are grounded, and the write voltage is used to drive part of the storage units in the storage unit to perform a write operation.

[0006] Further, the heating time of the first potential difference is negatively correlated with the heat conduction performance of the N heat conduction cores.

[0007] Further, the N heat conduction cores are composed of one or more of tungsten, gold, copper and silicon carbide.

[0008] Further, the storage unit further comprises: a channel insulating layer arranged between the channel layer and the heat conduction core.

[0009] Further, the channel insulation layer is used to isolate the channel layer and the heat conduction core, and is composed of silicon oxide or aluminum oxide.

[0010] Further, the tunneling layer is composed of silicon oxide or silicon nitride.

[0011] Further, the storage unit further comprises a barrier layer arranged outside the storage layer.

[0012] The second aspect of the present disclosure provides a three-dimensional memory, comprising the storage unit provided by the first aspect of the present disclosure.

[0013] The third aspect of the present disclosure provides an operation method of the three-dimensional memory provided by the second aspect of the present disclosure, comprising: enabling part of the storage units in the three-dimensional memory to respectively implement data write, read and erase operations by controlling the voltage bias of the substrate, the drain layer, the gate layer or the thermocouple layer of part of the storage units in the three-dimensional memory.

[0014] Further, the part of the storage units in the three-dimensional memory implement the data write operation, comprising: applying a first potential difference between the thermocouple word line layer and part of the thermocouple layers in the N thermocouple layers, heating the heat conduction core connected with the part of the thermocouple layers, so that the channel layer and the storage layer corresponding to the heat conduction core maintain a first preset temperature and a second preset temperature respectively under the heat insulation of the tunneling layer; grounding the substrate and the drain layer corresponding to the channel layer, and applying a write voltage to the gate layer, the write voltage being used to drive the part of the storage units in the three-dimensional memory to perform the write operation.

[0015] Further, the part of the storage units in the three-dimensional memory implement the data read operation, comprising: triggering a data read program; applying a bias voltage to the drain layer of the three-dimensional memory; grounding the substrate; applying a conduction voltage to the gate layer of the unselected storage unit, and applying a read voltage to the gate layer of the selected storage unit; sensing the voltage and / or current change between the drain layer of the selected storage unit and the substrate to read data.

[0016] Further, the part of the storage units in the three-dimensional memory implement the data erase operation, comprising: triggering a data erase program; floating or grounding the gate layer; applying an erase voltage to the drain layer, the erase voltage being sufficient to cause the tunneling effect of the three-dimensional memory, so that the stored electrons in the three-dimensional memory are attracted to the drain layer.

[0017] Compared with the prior art, the present disclosure has at least the following beneficial effects:

[0018] (1), the storage unit provided by the present disclosure, by setting heat conduction core inside the channel, each heat conduction core end connects thermocouple, thermocouple can be in string or string group as a unit to produce heat pulse to heat the heat conduction core, to form temperature gradient between the channel layer, storage layer and barrier layer. The storage unit can guarantee good writing at the same time, and achieve good data storage.

[0019] (2), by reading the ambient temperature before the operation of thermocouple, adjusting the number of pulses generated by thermocouple according to the ambient temperature, to achieve better data writing environment.

[0020] (3), the writing operation time of three-dimensional memory provided by the present disclosure is not more than 3ms. BRIEF DESCRIPTION OF DRAWINGS

[0021] In order to more completely understand the present disclosure and its advantages, the following description will be made in conjunction with the accompanying drawings, in which:

[0022] Figure 1 Part of the structure schematic diagram of the section of the storage unit according to an embodiment of the present disclosure is schematically shown;

[0023] Figure 2 The temperature gradient schematic diagram of the storage unit according to Figure 1 is schematically shown;

[0024] Figures 3A-3I The structure schematic diagram corresponding to each step of the preparation method of the storage unit according to an embodiment of the present disclosure is schematically shown;

[0025] Figure 4 The operation method flow chart of the data reading of the operation method of three-dimensional memory according to an embodiment of the present disclosure is schematically shown;

[0026] Figure 5 The operation method flow chart of the data erasing of the operation method of three-dimensional memory according to an embodiment of the present disclosure is schematically shown;

[0027] Figure 6 The operation method flow chart of the data writing of the operation method of three-dimensional memory according to an embodiment of the present disclosure is schematically shown. DETAILED DESCRIPTION

[0028] Embodiments of the present disclosure will be described below with reference to the accompanying drawings. However, it should be understood that these descriptions are merely exemplary, and are not intended to limit the scope of the present disclosure. In the following detailed description, numerous specific details are set forth in order to provide a thorough understanding of the embodiments of the present disclosure. However, it will be apparent to those skilled in the art that the embodiments can be practiced without these specific details. In addition, in the following description, descriptions of well-known structures and techniques have been omitted to avoid unnecessarily obscuring the concepts of the present disclosure.

[0029] It should be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" another element, it can be directly on the other element or intervening elements can also be present. In addition, when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element, or electrically connected or coupled through a third element.

[0030] In describing the embodiments of the present disclosure, the cross-sectional view of the device structure will be partially enlarged without the general proportion for the convenience of explanation, and the schematic view is only an example, which should not limit the scope of protection of the present disclosure herein. In addition, three-dimensional spatial dimensions of length, width and depth should be included in actual fabrication.

[0031] The embodiment of the present disclosure provides a storage unit, comprising: a channel layer array, comprising: N channel layers, the N channel layers are vertically arranged on a substrate along a first direction, a tunneling layer and a storage layer are sequentially arranged outside the N channel layers, and N is a positive integer; N heat-conducting cores, respectively located in the N channel layers and penetrating through the substrate; and a thermocouple array, comprising: a thermocouple word line layer grown on the substrate along a negative direction of the first direction and N thermocouple layers located on the thermocouple word line layer, the N thermocouple layers are connected to the N heat-conducting cores one by one; wherein a first potential difference is applied between the thermocouple word line layer and part of the N thermocouple layers, a heat treatment is performed on the heat-conducting core connected to the part of the N thermocouple layers, so that the channel layer and the storage layer corresponding to the heat-conducting core maintain a first preset temperature and a second preset temperature respectively under the heat insulation effect of the tunneling layer.

[0032] The storage unit provided by the embodiment of the present disclosure can generate a heat pulse by connecting a thermocouple to the end of each heat-conducting core, and the thermocouple can generate a heat pulse in a string or a string group to heat the heat-conducting core, so as to form a temperature gradient between the channel layer, the storage layer and the barrier layer. In the case of ensuring good writing, good data storage is also achieved.

[0033] The technical solutions of the present disclosure will be described in detail below in combination with the structure of a three-dimensional memory in a specific embodiment of the present disclosure. It should be understood that, Figure 1The material layers, shapes, and structures of the parts in the structure of the three-dimensional memory shown in the figures are only exemplary to help those skilled in the art understand the technical solutions of the present disclosure, and are not intended to limit the protection scope of the present disclosure.

[0034] In a first example embodiment of the present disclosure, a storage unit is provided.

[0035] Figure 1 A part of the structure of the cross section of the storage unit according to an embodiment of the present disclosure is schematically shown.

[0036] As shown in the figure, the structure of the storage unit of the embodiment of the present disclosure includes: Figure 1

[0037] A substrate 10.

[0038] A stack layer 20 is stacked on the substrate 10 along a first direction (z-axis positive direction).

[0039] A channel layer array includes N channel layers 30 vertically arranged on the substrate 10 along the first direction, and a tunneling layer 40 and a storage layer 50 arranged outside the N channel layers 30 in sequence, wherein N is a positive integer.

[0040] N heat-conducting cores 80 are respectively located in the N channel layers 30 and penetrate the substrate 10.

[0041] A thermocouple array includes a thermocouple word line layer 901 grown on the substrate 10 along the negative direction of the first direction (z-axis negative direction) and N thermocouple layers 902 located on the thermocouple word line layer, the N thermocouple layers 902 are connected one by one with the N heat-conducting cores 80.

[0042] Among them, a first potential difference is applied between the thermocouple word line layer 901 and part of the N thermocouple layers 902, and the heat-conducting core 80 connected with the part of the N thermocouple layers 902 is heated, so that the channel layer 30 and the storage layer 50 corresponding to the heat-conducting core 80 maintain the first preset temperature and the second preset temperature respectively under the heat insulation of the tunneling layer 40.

[0043] In the embodiment of the present disclosure, the substrate 10 can be a conductive type substrate 10, including a first conductive type substrate 101 and a second conductive type substrate 102, the materials of the first conductive type substrate 101 and the second conductive type substrate 102 are, for example, polysilicon, only the conductive types of the two are opposite.

[0044] ​Specifically, the first conductive type is p-type, the second conductive type is n-type, the first conductive type substrate 101 is a p-type substrate, and the second conductive type substrate 102 is an n-type conduction layer. The p-type substrate is used to provide holes required for an erase operation, and the holes pumped into the channel layer 30 by the first conductive type substrate 101 are used to implement the erase operation. The n-type conduction layer provides electrons required for a read operation, and the electrons pumped into the channel layer 30 by the second conductive type conduction layer 102 (n-type conduction layer) are used to implement the read operation.

[0045] According to an embodiment of the present disclosure, the stack layer 20 comprises: a plurality of stack layer pairs, each stack layer pair comprising a first stack material 201 and a second stack material 202, wherein the second stack material 202 and the first stack material 201 are sequentially stacked on the substrate 10. In an example, the second stack material 202 is an insulator layer such as OX, and the first stack material 201 is a metal dielectric layer, which is a word line layer. The word line layer closest to the substrate 10 in the stack layer 20 is a lower selection layer, and the word line layer farthest from the substrate 10 is an upper selection layer. Specifically, the channel hole array is formed on the stack layer 20 by etching.

[0046] In an embodiment of the present disclosure, the barrier layer 60, the storage layer 50, the tunneling layer 40, and the channel layer 30 are sequentially grown and formed in the etching of the stack layer 20 to form the channel hole array, and part of the barrier layer 60, the storage layer 50, and the tunneling layer 40 are removed to partially expose the channel layer 30, as shown in Figure 1 The channel insulating layer 70 is arranged between the channel layer 30 and the heat-conducting core 80.

[0047] Specifically, the tunneling layer 40 is a thermal insulation layer, which is used to prevent the temperature of the storage layer 50 from rising sharply with the temperature of the heat-conducting core 80. The material of the tunneling layer 40 can be silicon oxide or silicon nitride, etc. The channel insulating layer 70 is a thin electrical insulating layer, which is used to isolate the channel layer 30 and the heat-conducting core 80. The material of the channel insulating layer 70 can be silicon oxide or aluminum oxide, etc.

[0048] In an embodiment of the present disclosure, the thermocouple word line 901 is a small-size metal line, and the line width of the thermocouple word line 901 is smaller than the width of the channel hole. The line width of the thermocouple word line 901 is about 100 nm. As shown in Figure 1 The thermocouple word line 901 is in the same direction as the word line layer 201 in the y-axis direction, and each thermocouple word line 901 covers only one string in the x-axis direction. The word line layer 201 is a large-size metal line, which covers multiple strings in the x-axis direction, such as 9 strings, 16 strings, 19 strings, 24 strings, etc. The line width of the word line layer 201 can be 1600 nm or 3200 nm, etc. It should be noted that, in the present embodiment, as shown in Figure 1 The width of the channel hole is the distance between the two side barrier layers 60 in each channel hole.

[0049] As shown in Figure 1As shown, each channel layer 30 is provided with a heat conduction core 80, and each heat conduction core 80 penetrates the substrate 10 and the thermocouple word line layer 901 to connect with the thermocouple layer 902; wherein the thermocouple layer 902 is connected with the thermocouple bit line 903 of the storage unit one by one, or with the bit line 904 (8-bit line or 16-bit line) in the bit line group one by one. In the embodiment of the present disclosure, the heat conduction core 80 is a good conductor of temperature, and its material can be metal or semiconductor, such as tungsten, gold, copper, silicon carbide, etc.

[0050] Specifically, in order to make the temperature of the channel layer 30 and the storage layer 50 rise to the preset temperature, the heat conduction core 80 connected with the thermocouple layer 902 is heated by the thermocouple layer 902, and the heating time is negatively correlated with the heat conduction performance of the heat conduction core 80, that is, the stronger the heat conduction performance of the heat conduction core 80, the shorter the heating time. For example, if the material of the heat conduction core 80 is copper or gold with good heat conduction performance, the heating time is 1ms-5ms, and if the material of the heat conduction core 80 is a material with poor heat conduction performance, the heating time is 6-10ms. It should be noted that, in order to ensure the high-speed storage write rate, the heating time is preferably in the order of milliseconds, so that the heat conduction core 80 is quickly heated and then the write operation is performed.

[0051] According to the embodiment of the present disclosure, before the write operation is performed on the storage unit, the heat conduction core 80 connected with the partial thermocouple layer 902 in the thermocouple word line layer 901 and the N thermocouple layers is heated by applying a first potential difference between the thermocouple word line layer 901 and the partial thermocouple layer 902, so that the channel layer 30 and the storage layer 50 corresponding to the heat conduction core 80 respectively maintain the first preset temperature and the second preset temperature under the heat insulation of the tunneling layer 40.

[0052] The selection of the partial thermocouple layer 902 in the N thermocouple layers can be selected and controlled by a logic control circuit, and the bias voltage operation can be performed on the selected string or string group connected thermocouple layer, so that the temperature of the thermocouple rises to less than 450℃. The heat conduction core 80 conducts the temperature of the thermocouple to the selected string or string group, and raises the temperature of the channel layer and the storage layer to the preset temperature. According to the difference of the environmental temperature, the number of heat pulses of the bias voltage is a variable, when the environmental temperature is higher, the number of heat pulses applied is less than when the environmental temperature is lower, and after the temperature of the channel layer and the storage layer is raised to the preset temperature, the heat pulse stops.

[0053] Specifically, the first potential difference can be 8V-10V, and the heating time is 1-10ms. Under the voltage bias and heating time, the temperature of the heated heat conduction core 80 can be raised to close to the temperature of the thermocouple layer (less than 450℃), and then the temperature of the channel layer 30 is maintained at the first preset temperature t1 of 65℃-90℃, the temperature of the storage layer 50 is maintained at the second preset temperature t2 of 30℃-40℃, and the temperature of the barrier layer 60 is maintained at the natural environmental temperature t3, such as -25℃-30℃.Figure 2 The temperature gradient is formed between the channel layer 30, the storage layer 50 and the barrier layer 60, so that the storage unit can achieve good data storage while ensuring good writing, effectively avoiding the problem that the temperature of the storage layer is not conducive to data storage when writing at a high temperature.

[0054] The storage unit provided by the present disclosure heats the selected heat-conducting core through the thermocouple array, forms a temperature gradient between the channel layer, the storage layer and the barrier layer, so that the storage unit is at a constant temperature when writing, and is not disturbed by changes in the ambient temperature. In addition, the storage unit can achieve good data storage temperature while ensuring good writing temperature.

[0055] It should be noted that, Figure 1 The partial cross-sectional view of the storage unit provided by the present disclosure does not represent a limitation on the number of layers and the number of channel layer arrays of the storage unit provided by the present disclosure. The number of layers and the number of channel layer arrays of the storage unit provided by the present disclosure can be set according to actual application, and the embodiments of the present disclosure do not limit this.

[0056] In a second exemplary embodiment of the present disclosure, a preparation method of a storage unit is provided.

[0057] Figures 3A-3I The preparation method of the storage unit according to an embodiment of the present disclosure is schematically shown in the structure schematic diagram corresponding to each step of the method. The structure of the storage unit prepared by the method steps is as shown in Figure 1 .

[0058] As shown in Figures 3A-3I , the preparation method of the storage unit comprises:

[0059] Step 301, as shown in Figure 3A , N channel holes are made in the first low-concentration conductive type extension layer 12 and the stack layer 20 above the substrate 11, and the barrier layer 60, the storage layer 50, the tunneling layer 40 and the channel layer 30 are sequentially deposited inside and at the bottom of the N channel holes. Wherein, N is a positive integer.

[0060] In this embodiment, the first low-concentration conductive type extension layer 12 (p-type silicon extension layer 12) and the stack layer 20 are sequentially (along the positive direction of the z-axis) deposited on the substrate. The first low-concentration conductive type extension layer 12 is, for example, a p-type silicon substrate. In subsequent steps, wet etching of p-type silicon with high selectivity of p-type silicon can be used to stop on the p-type silicon extension layer.

[0061] Step 302, as shown in Figure 3B , the substrate 11 and the first low-concentration conductive type extension layer 12 are sequentially removed, so that part of the barrier layer 60 is exposed.

[0062] In this embodiment, the storage unit is part of a three-dimensional memory, and the front surface of the storage unit needs to be attached to the front surface of the logic control unit.

[0063] After the storage wafer / logic control unit is attached, the back surface (substrate side) of the storage unit is thinned by a chemical mechanical polishing method, and then wet etching is performed using the high selectivity of p-type silicon to p-type silicon (doping concentration difference) to stop on the p-type silicon extension layer 12. In this step S302, the wet etching operation for removing the substrate can be performed only on the substrate 11 side of the device, without placing the entire device in the etching solution.

[0064] In this embodiment, the p-type silicon extension layer 12 can be removed by wet etching using the high selectivity of silicon oxide to silicon, exposing part of the barrier layer 60.

[0065] Step 303, as shown in Figure 3C , the partial height of the barrier layer 60, the storage layer 50, the tunneling layer 40 and the stack layer 20 are removed to expose part of the channel layer 30.

[0066] Step 304, as shown in Figure 3D , the exposed upper surface (negative direction of z-axis) of the channel layer 30 is deposited with a second conductive type cover layer, and the protruding part of the channel layer 30 is removed to expose the protruding part of the channel layer 30.

[0067] In this embodiment, by depositing a second conductive type cover layer on the exposed upper surface of the channel layer 30, the second conductive type cover layer is, for example, n-type silicon, and the second conductive type cover layer is the precursor of the corresponding second conductive type substrate 102 in the subsequent device structure. After the patterning process, the second conductive type substrate 102 is obtained.

[0068] As shown in Figure 3D , the second conductive type cover layer corresponding to the protruding part of the channel layer 30 is removed to expose the protruding part of the channel layer 30, and the second conductive type cover layer is patterned to form the second conductive type substrate 102.

[0069] Step 305, as shown in Figure 3E , a first conductive type substrate 101 is deposited on the second conductive type substrate 102, wherein the formed first conductive type substrate 101 does not cover the upper side of the protruding part of the channel layer 30.

[0070] Step 306, as shown in Figure 3FAs shown, the insulator layer 202 and the thermocouple word line layer 901 are sequentially deposited on the first conductive type substrate 101, wherein the insulator layer 202 and the thermocouple word line layer 901 cover the upper part of the protruding part of the channel layer 30 and do not cover the upper part of the internal cavity of the channel layer 30.

[0071] Step 307, as shown in the figure, the channel insulating layer 70 and the heat-conducting core 80 are sequentially deposited in each channel layer 30 to be flush with the thermocouple word line layer 901 at the same horizontal plane. Figure 3G

[0072] Step 308, as shown in the figure, the thermocouple layer 902 and the thermocouple word line 903 are deposited above the channel insulating layer 70 and the heat-conducting core 80, and the insulator layer is deposited on the thermocouple layer 902. Figure 3H

[0073] Step 309, as shown in the figure, the bit line lead end is shaped, metal is deposited, and the bit line 904 is formed, completing the fabrication of the storage unit. Figure 3I

[0074] Figure 3I The schematic diagram and the structural diagram shown are upside down, in which it can be understood that the process of removing part of the structure is not limited to the wet etching and photolithography processes mentioned above, and can be a combination of the two or other dry etching or wet etching processes. Figure 1 Figure 3I It should be noted that the embodiments of the above steps are only examples, which illustrate how to fabricate the storage unit of the present disclosure on the existing conventional device structure. In the present disclosure, any fabrication process that can form the above-mentioned part of the structure and the positional relationship between them is within the protection scope of the present disclosure.

[0075] It should be noted that the embodiments of the above steps are only examples, which illustrate how to fabricate the storage unit of the present disclosure on the existing conventional device structure. In the present disclosure, any fabrication process that can form the above-mentioned part of the structure and the positional relationship between them is within the protection scope of the present disclosure.

[0076] In a third exemplary embodiment of the present disclosure, a three-dimensional memory is provided, which comprises any one of the storage units mentioned in the present disclosure.

[0077] In this embodiment, the three-dimensional memory further comprises a logic control unit, and the storage unit is opposite to the front surface of the high logic control unit. The three-dimensional memory can be a three-dimensional NAND memory.

[0078] In this embodiment, the selection of the thermocouple layer can be realized by the logic control unit, which can simultaneously select one or more thermocouple layers and heat the corresponding heat-conducting core to raise the temperature of the channel layer and the storage layer to a preset temperature, thereby realizing the process of good data writing and storage.

[0079] ​​​​In a fourth exemplary embodiment of the present disclosure, a method for operating a three-dimensional memory as described above is provided, comprising: enabling data write, read and erase operations of some memory cells in the three-dimensional memory by controlling the voltage bias of the substrate, drain layer, gate layer or thermocouple layer of the memory cells.

[0080] The method for operating comprises a method for operating data read, a method for operating data erase and a method for operating data write, and there is no fixed execution sequence between the method for operating data read, the method for operating data erase and the method for operating data write.

[0081] As shown in Figure 4 The method for operating data read comprises the following steps:

[0082] In step S401, a data read program is triggered.

[0083] In step S402, a bias voltage is applied to the drain layer, the substrate is grounded, a turn-on voltage is applied to the gate layer of unselected memory cells, and a read voltage is applied to the gate layer of selected memory cells.

[0084] In step S403, the voltage and / or current change between the drain layer and the substrate of the selected memory cells is sensed to read data.

[0085] In this embodiment, when the memory is operated for data read, a bias voltage is applied to the drain layer and the substrate is grounded, so that when the read operation is performed, the data state stored in the three-dimensional memory can be determined by sensing the current change between the drain layer and the substrate. The bias voltage ranges from 1V to 1.4V, and preferably can be 1.2V. Under the above conditions, if the channel layer is turned on, the turn-on current is inversely proportional to the threshold voltage (VT) of the memory cell. For the three-dimensional memory, the channel layer is turned on because a voltage greater than the VT of the memory cell is applied to the gate.

[0086] For unselected memory cells, a turn-on voltage is applied to the gate layer during the read operation to turn on the channel layer, and the current can flow from the drain layer to the substrate. The turn-on voltage is a voltage that can ensure that it is greater than the VT of any memory cell, but the turn-on voltage cannot be too large, otherwise the three-dimensional memory will have a tunneling effect. The turn-on voltage can range from 2V to 8V.

[0087] For selected memory cells, a read voltage is applied to the gate layer during the read operation, and if the read voltage is greater than the VT of the memory cell, the channel layer can be turned on. By trying to apply different read voltages to the gate layer, the amount of charge stored in the memory cell can be known, and thus the data stored therein can be known.

[0088] As shown in Figure 5As shown, the data erasure operation method includes the following steps:

[0089] Step S501: Trigger the data erasure procedure.

[0090] Step S502: Float or ground the gate layer; apply an erase voltage to the substrate; apply an erase voltage to the drain layer.

[0091] During data erasure operations on the three-dimensional memory, the gate layer is floating or grounded, an erase voltage is applied to the semiconductor region, and an erase voltage is applied to the drain layer. Because the drain layer is at a high potential, it can attract electrons trapped in the charge trapping layer. The erase voltage is sufficient to induce tunneling in the three-dimensional memory, allowing electrons to be successfully attracted to the drain, thereby releasing the electrons from the charge trapping layer. The semiconductor region and the drain layer maintain the same potential to prevent electrons from flowing from the drain layer to the semiconductor region. The erase voltage ranges from 14V to 20V, preferably 14V.

[0092] The above erasure method allows data to be erased using the drain layer without applying high voltage, thus improving the efficiency of erasure operations in 3D memory.

[0093] like Figure 6 As shown, the data writing operation method includes the following steps:

[0094] Step S601: Apply a first potential difference between the thermocouple line layer and a portion of the N thermocouple layers, and heat the heat-conducting core connected to the portion of the thermocouple layer, so that the channel layer and storage layer corresponding to the heat-conducting core maintain a first preset temperature and a second preset temperature respectively under the heat insulation effect of the tunneling layer.

[0095] Step S602: Trigger the data writing program.

[0096] In step S603, the substrate and the drain layer corresponding to the channel layer are grounded, and a write voltage is applied to the gate layer.

[0097] In this embodiment, before writing data to the memory, a first potential difference is first applied between the thermocouple word line layer 901 and a portion of the N thermocouple layers 902. This heats the thermally conductive core 80 connected to the portion of the thermocouple layers 902, so that the channel layer 30 and the memory layer 50 corresponding to the thermally conductive core are respectively maintained at a first preset temperature and a second preset temperature under the thermal insulation effect of the tunneling layer 40 before the data writing procedure is triggered. The first potential difference can be 8V to 10V, which can raise the temperature of the channel layer 30 and the memory layer 50 to the preset temperature in milliseconds.

[0098] In the data write operation of the three-dimensional memory, the drain layer is grounded, the substrate is grounded, and the gate layer is applied with a write voltage. Due to the high potential of the gate layer, the electrons can be attracted close to the gate layer, and the write voltage is sufficient to cause the tunneling effect of the three-dimensional memory, so that the electrons are captured by the charge trapping layer in the process of approaching the gate layer. The range of the write voltage is not higher than 25V, and different programming voltages determine the number of electrons in the write charge trapping layer, so that different programming voltages can realize different data states of the three-dimensional memory storage unit. In the above embodiment, the electrons are attracted to the gate layer, so the current flows from the gate layer to the substrate.

[0099] In the embodiment, the operation method is not limited to the steps, and other steps omitted can be adjusted according to actual conditions.

[0100] The operation method of the three-dimensional memory provided in the embodiment can clear data by using the drain layer without applying a high voltage, and facilitates data reading and data writing, thereby preventing damage to the device and improving the service life of the three-dimensional memory. In the case of ensuring good write temperature of the storage unit, good data storage temperature is also achieved.

[0101] It should be noted that the preparation process method adopted in the embodiments of the present disclosure is not limited to the above-mentioned embodiments, and can be replaced by other mature process methods in the prior art, which does not constitute a limitation of the embodiments of the present disclosure.

[0102] From the above description, it can be seen that the above-mentioned embodiments of the present disclosure at least achieve the following technical effects:

[0103] 1) The storage unit provided by the present disclosure can generate a heat pulse to heat the heat conduction core by connecting a thermocouple at the end of each heat conduction core in series or in series group, so as to form a temperature gradient between the channel layer, the storage layer and the barrier layer. The storage unit can ensure good writing while achieving good data storage.

[0104] 2) The number of pulses generated by the thermocouple is adjusted according to the ambient temperature before the operation of the thermocouple, so as to achieve a better data writing environment.

[0105] 3) The write operation time of the three-dimensional memory provided by the present disclosure is not more than 3ms. Although the present disclosure has been illustrated and described in detail in the drawings and the foregoing description, such illustration and description should be considered illustrative or exemplary rather than limiting.

[0106] Those skilled in the art can understand that the features recited in various embodiments of the present disclosure and / or claims can be combined in various ranges and / or combined, even if such combinations or combinations are not explicitly recited in the present disclosure. In particular, the features recited in various embodiments of the present disclosure and / or claims can be combined in various combinations and / or combined without departing from the spirit and teachings of the present disclosure. All such combinations and / or combinations fall within the scope of the present disclosure.

[0107] Although the present disclosure has been shown and described with respect to certain exemplary embodiments thereof, it should be understood by those skilled in the art that various changes in form and detail can be made therein without departing from the spirit and scope of the disclosure as defined by the appended claims and their equivalents. Therefore, the scope of the present disclosure should not be limited to the above-described embodiments, but should be determined by the appended claims only, and the equivalents thereof.

Claims

1. A memory cell, comprising: The application relates to a three-dimensional memory, comprising: a channel layer array, comprising: N channel layers, which are vertically arranged on a substrate along a first direction, and a tunnel layer and a storage layer arranged outside the N channel layers in sequence, N being a positive integer; N heat-conducting cores, which are respectively located in the N channel layers and penetrate through the substrate; a thermocouple array, comprising: a thermocouple word line layer grown on the substrate along a negative direction of the first direction and N thermocouple layers located on the thermocouple word line layer, the N thermocouple layers being connected with the N heat-conducting cores in one-to-one correspondence; wherein a first potential difference is applied between the thermocouple word line layer and part of the N thermocouple layers, a heating treatment is performed on the heat-conducting core connected with the part of the N thermocouple layers, and the channel layer and the storage layer corresponding to the heat-conducting core maintain a first preset temperature and a second preset temperature respectively under the heat insulation of the tunnel layer.

2. The memory cell of claim 1, wherein, The storage unit is configured to: after the temperature of part of the channel layers in the channel layer array and the corresponding storage layers maintains the first preset temperature and the second preset temperature respectively, a write voltage is applied to the gate layer of the storage unit, the drain layer and the substrate are grounded, and the write voltage is used to drive part of the storage units in the storage unit to perform a write operation.

3. The memory cell of claim 1, wherein, The heating time of the first potential difference is negatively correlated with the heat conduction performance of the N heat-conducting cores.

4. The memory cell of claim 1, wherein, The N heat-conducting cores are composed of one or more of tungsten, gold, copper and silicon carbide.

5. The memory cell of claim 1, wherein, Further comprising: a channel insulating layer arranged between the channel layer and the heat-conducting core.

6. The memory cell of claim 5, wherein, The channel insulating layer is used for isolating the channel layer and the heat-conducting core and is composed of silicon oxide or aluminum oxide.

7. The memory cell of claim 1, wherein, The tunnel layer is composed of silicon oxide or silicon nitride.

8. The memory cell of claim 1, wherein, Further comprising: a barrier layer arranged outside the storage layer.

9. A three-dimensional memory, comprising: The application further relates to a storage unit. The application further relates to a three-dimensional memory.

10. The method of operating a three-dimensional memory as claimed in claim 9, wherein, The application further relates to a three-dimensional memory. The application further relates to a three-dimensional memory.

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13. The operating method of claim 10, wherein a portion of memory cells in the three-dimensional memory implement a data erase operation, comprising: triggering a data erase procedure; floating or grounding the gate layer; applying an erase voltage to the drain layer, the erase voltage being sufficient to cause a tunneling effect in the three-dimensional memory to cause electrons stored in the three-dimensional memory to be attracted to the drain layer.

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