A three-dimensional stacked capacitor integrated structure and a manufacturing method thereof

Abstract

The present invention relates to a three-dimensional stacked capacitor integrated structure, comprising: a substrate having a front surface and a back surface opposite to the front surface; one or more capacitors, each capacitor including a plurality of capacitor plates and a capacitor dielectric sandwiched between adjacent capacitor plates, wherein the capacitor plates are flat plates penetrating through the top surface and the bottom surface of the substrate. The present invention also relates to a method for manufacturing a three-dimensional stacked capacitor integrated structure.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor packaging, and in particular to a three-dimensional stacked capacitor integrated structure and a manufacturing method thereof. Background Art

[0002] In recent years, capacitors have become indispensable components in microwave radio frequency circuits, with functions such as DC isolation, filtering, coupling, tuning, rectification, etc. As the operating frequency of integrated circuits becomes higher and the speed becomes faster, the noise problem of the circuit power supply network in electronic systems becomes more and more serious, and the demand for the decoupling function of capacitors has also increased rapidly. Especially for the currently highly regarded AI and HPC products, the increase in the operating frequency of these two types of products has also increased their demand for high-density capacitors and low-parasitic inductance capacitors.

[0003] Currently, the integration of capacitor structures mainly has the following two methods:

[0004] (1) Using integrated passive device (IPD) on-chip capacitor elements for integration. The capacitors used in this method are mostly planar capacitors in the MIM form, and a MIM capacitor structure is formed by sandwiching a capacitor dielectric layer between two planar metal electrode plates in the horizontal direction. Due to limited planar space, the capacitance value of the MIM capacitor structure generated in this integration method is limited, and the capacitance density is low.

[0005] (2) By etching deep holes in the substrate and realizing a vertical MIM capacitor structure in the hole grooves. Although this method utilizes the longitudinal space, since it is still a MIM structure, the capacitance value of the capacitor is limited, and at the same time, each capacitor unit needs to be paralleled through a redistribution layer (RDL), increasing the parasitic inductance.

[0006] In view of the above problems mentioned in the background art, a new research idea and solution method are needed. Summary of the Invention

[0007] Starting from the prior art, the task of the present invention is to provide a three-dimensional stacked capacitor integrated structure and a manufacturing method thereof. By vertically fabricating M1I1M2I2...M n capacitor structures on the substrate and stacking multiple M1I1M2I2...M n capacitors, the capacitance value and capacitance density of the capacitor can be increased, the substrate area overhead can be reduced, and the parasitic inductance can be lowered.

[0008] In the first aspect of the present invention, in view of the problems existing in the prior art, the present invention provides a three-dimensional stacked capacitor integrated structure, including:

[0009] A substrate having a front surface and a back surface opposite to the front surface;

[0010] One or more capacitors, the capacitors comprising a plurality of capacitor plates and a capacitor dielectric sandwiched between adjacent capacitor plates, wherein the capacitor plates are flat plates penetrating the top and bottom surfaces of the substrate.

[0011] In a preferred embodiment of the present invention, it is further provided that:

[0012] Through holes vertically penetrating the substrate;

[0013] Redistribution layers disposed on the front and back surfaces of the substrate, the redistribution layers being electrically connected to the capacitors and the through holes.

[0014] In another preferred embodiment of the present invention, it is specified that the redistribution layer on the front surface of the substrate is electrically connected to a Bump;

[0015] The redistribution layer on the front surface of the substrate is electrically connected to a chip through a Bump;

[0016] The redistribution layer on the back surface of the substrate is electrically connected to solder balls.

[0017] In yet another preferred embodiment of the present invention, it is specified that the capacitor is a M1I1M2I2...M n capacitor, where n≥4.

[0018] In another preferred embodiment of the present invention, it is specified that multiple of the capacitors are bonded pairwise by metal bonding.

[0019] In a second aspect of the present invention, in view of the problems existing in the prior art, the present invention provides a method for manufacturing a three-dimensional stacked capacitor integration structure, comprising:

[0020] Depositing an insulating dielectric layer on the front surface of a wafer substrate;

[0021] Fabricating a capacitor on the front surface of the wafer substrate. First, forming capacitor plates on the insulating dielectric layer on the front surface of the substrate, then depositing a capacitor dielectric on the capacitor plates, and forming capacitor plates on the capacitor dielectric;

[0022] Bonding multiple wafers;

[0023] Dicing the bonded multi-layer wafers;

[0024] Rotating the diced strip-shaped wafers by 90° and horizontally placing them on a carrier;

[0025] Recombining multiple horizontally placed strip-shaped wafers to form a flat plate structure.

[0026] In a preferred embodiment of the present invention, it is specified that the insulating dielectric layer is used for insulating the capacitor plates and the substrate.

[0027] In another preferred embodiment of the present invention, it is specified that fabricating a capacitor on the front side of the wafer substrate includes repeatedly performing the steps of forming capacitor plates and capacitor dielectrics, so as to form a capacitor on the front side of the substrate. The capacitor includes N capacitor plates and capacitor dielectrics sandwiched between adjacent capacitor plates, where N is an integer greater than or equal to 2.

[0028] In another preferred embodiment of the present invention, it is specified that via etching is performed on a substrate with a planar structure, a dielectric layer is deposited, and then a metal layer is electroplated to form a conductive via.

[0029] The material of the dielectric layer is silicon oxide.

[0030] In yet another preferred embodiment of the present invention, it is specified that it further includes fabricating multiple layers of redistribution layers on the front and back sides of the planar structure. When fabricating the redistribution layers, a photoresist is first coated, and after exposure and development, a circuit pattern is formed. A metal wiring layer is electroplated on the circuit pattern, and the operation is repeated to form multiple layers of redistribution layers.

[0031] In another preferred embodiment of the present invention, it is specified that it further includes depositing an insulating dielectric layer on the back side of the wafer substrate.

[0032] When fabricating a capacitor on the back side of the wafer substrate, first a capacitor plate is formed on the insulating dielectric layer on the back side of the substrate, then a capacitor dielectric is deposited on the capacitor plate, and a capacitor plate is formed on the capacitor dielectric.

[0033] The present invention has at least the following beneficial effects: The present invention discloses a three-dimensional stacked capacitor integrated structure and a manufacturing method thereof, which can make full use of the longitudinal space on the substrate and reduce the planar area overhead; the three-dimensional stacked capacitor integrated structure has a larger capacitance value than a general capacitor, and compared with a via trench capacitor made of the same material, the capacitance density of the three-dimensional stacked capacitor integrated structure can be increased by about 50%; the three-dimensional stacked capacitor integrated structure can be flexibly integrated with a chip; in the three-dimensional stacked capacitor integrated structure, a large number of short-distance vias are connected inside a single capacitor unit, reducing the overall parasitic inductance of the three-dimensional stacked capacitor integrated structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figure 1 A cross-sectional schematic diagram showing the structure of the integration of a three-dimensional stacked capacitor and a chip according to an embodiment of the present invention is shown.

[0035] Figure 2 A top view showing a three-dimensional stacked capacitor integrated structure according to an embodiment of the present invention is shown.

[0036] Figures 3A to 3C A flowchart showing the manufacturing method of a three-dimensional stacked capacitor integrated structure according to the present invention is shown. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0037] It should be noted that the components in the respective drawings may be exaggeratedly shown for illustrative purposes and are not necessarily to scale correctly. In the respective drawings, the same or functionally identical components are provided with the same reference numerals.

[0038] In the present invention, the respective embodiments are merely intended to illustrate the solutions of the present invention and should not be construed as restrictive.

[0039] In the present invention, unless otherwise specified, the quantifiers "a" and "one" do not exclude the scenario of multiple elements.

[0040] It should also be noted here that in the embodiments of the present invention, for the sake of clarity and simplicity, only a part of the components or elements may be shown. However, those of ordinary skill in the art can understand that, under the teachings of the present invention, the required components or elements can be added according to the specific scenario requirements.

[0041] It should also be noted here that within the scope of the present invention, the terms "identical", "equal", "equal to", etc. do not mean that the two numerical values are absolutely equal, but allow a certain reasonable error. That is to say, the said terms also cover "substantially identical", "substantially equal", "substantially equal to".

[0042] It should also be noted here that in the description of the present invention, the orientation or positional relationships indicated by the terms "center", "longitudinal", "transverse", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. are based on the orientation or positional relationships shown in the drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than explicitly or implicitly indicating that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as a limitation of the present invention. In addition, the terms "first" and "second" are only used for descriptive purposes and cannot be construed as explicitly or implicitly indicating relative importance.

[0043] In addition, the embodiments of the present invention describe the process steps in a specific order. However, this is only for the convenience of distinguishing each step and does not limit the order of the steps. In different embodiments of the present invention, the order of the steps can be adjusted according to the adjustment of the process.

[0044] Figure 1 A cross-sectional schematic view of the structure of a three-dimensional stacked capacitor integrated with a chip according to an embodiment of the present invention is shown; Figure 2 A top view of a three-dimensional stacked capacitor integrated structure according to an embodiment of the present invention is shown.

[0045] As Figure 1As shown, the three-dimensional stacked capacitor integrated with the chip structure 100 includes a first chip 101, a second chip 102, Bump (protrusion) 103, solder ball 104, and a three-dimensional stacked capacitor integrated structure 120. The three-dimensional stacked capacitor integrated structure 120 may include one or more capacitors, and each capacitor includes a plurality of capacitor plates and a capacitor dielectric sandwiched between adjacent capacitor plates. Each capacitor plate is a flat plate that penetrates the top and bottom surfaces of the substrate.

[0046] Specifically, as Figure 1 and Figure 2 shown, the three-dimensional stacked capacitor integrated structure 120 includes a substrate 121, through holes 122, one or more MIMIMIM capacitors 123, one or more MIM capacitors 124, and a redistribution layer 125. The through holes 122 vertically penetrate the substrate 121.

[0047] The substrate may include a variety of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may also be made of an electrically non-conductive material, such as glass, plastic, or a sapphire wafer.

[0048] The MIMIMIM capacitors 123 are vertically distributed in the substrate 121 and parallel to the through holes 122. The MIMIMIM capacitors can be M1I1M2I2...M n capacitors, where n≥4. The MIM capacitors 124 are vertically distributed in the substrate 121 and parallel to the through holes 122.

[0049] The redistribution layer 125 is arranged on the front (upper surface) and back (lower surface) of the substrate 121, and the redistribution layer 125 is electrically connected to the through holes 122, MIMIMIM capacitors 123, and MIM capacitors 124. The redistribution layer 125 is a multi-layer redistribution layer.

[0050] The MIMIMIM capacitor 123 includes 4 capacitor plates 1231 and 3 layers of capacitor dielectrics 1232 arranged alternately, and the two sides of the MIMIMIM capacitor are capacitor plates. The MIM capacitor 124 includes a capacitor plate 1241, a capacitor dielectric 1242, and a capacitor plate 1243. Multiple MIMIMIM capacitors 123 are bonded pairwise by metal bonding to achieve stacking. Multiple MIM capacitors 124 are bonded pairwise by metal bonding to achieve stacking. The capacitor plates 1241, capacitor dielectric 1242, and capacitor plate 1243 are all flat plates that penetrate the top and bottom surfaces of the substrate 121. The capacitor dielectric is sandwiched between adjacent capacitor plates. Those skilled in the art should be clear that, Figure 1 and Figure 2The capacitors 123 and 124 shown are merely exemplary and not restrictive. Those skilled in the art can flexibly set the number, arrangement, and ratio of capacitor plates and capacitor dielectrics according to the requirements for capacitance values in actual applications. Therefore, any number of capacitor plates and capacitor dielectrics and their arrangements and ratios fall within the protection scope of the present invention.

[0051] The redistribution layer above the three-dimensional stacked capacitor integration structure 120 is electrically connected to the Bump 103, and the Bump 103 is electrically connected to the first chip 101 and the second chip 102. The first chip 101 and the second chip 102 can be the same type of chip or different chips. The first chip 101 and the second chip 102 can be logic chips such as processors, FPGAs, MCUs, etc., or storage chips such as EPROMs, FLASHs, DRAMs, etc. The redistribution layer can be electrically connected to the capacitor plates and conductive vias according to the actual circuit design. In other embodiments of the present invention, more or fewer chips can be provided above the three-dimensional stacked capacitor integration structure 120.

[0052] The redistribution layer below the three-dimensional stacked capacitor integration structure 120 is electrically connected to the solder ball 104. The above three-dimensional stacked capacitor integration structure 120 can be integrated with chips. The redistribution layer can be electrically connected to the capacitor plates and conductive vias according to the actual circuit design.

[0053] Figures 3A to 3C Show a manufacturing method flow of a three-dimensional stacked capacitor integration structure according to the present invention.

[0054] In step 1, provide a plurality of wafers to be processed.

[0055] In step 2, as Figure 3A shown, deposit an insulating dielectric layer 301 on the front side of the wafer substrate, and the insulating dielectric layer 301 is used for insulating the capacitor plates and the substrate.

[0056] In step 3, as Figure 3A shown, fabricate the capacitor on the front side of the wafer substrate. When fabricating the capacitor on the front side of the substrate, first electroplate the first metal pattern on the insulating dielectric layer 301 on the front side of the substrate to form the first capacitor lower plate 302, then deposit the first capacitor dielectric 303 on the first capacitor lower plate 302, and electroplate the second metal pattern on the first capacitor dielectric 303 to form the first capacitor upper plate 304. In the embodiments of the present invention, the formation steps of the capacitor plates and the capacitor dielectrics can be repeated multiple times to form a capacitor on the front side of the substrate. The capacitor includes N capacitor plates and capacitor dielectrics sandwiched between adjacent capacitor plates, where N is an integer greater than or equal to 2.

[0057] Optionally, in step 4, as Figure 3AAs shown, an insulating dielectric layer is deposited on the back side of the wafer substrate, and then capacitors on the back side of the substrate are fabricated in the same way as the capacitors on the front side of the substrate.

[0058] Optionally, in step 5, the steps of forming capacitor plates and capacitor dielectrics can be repeatedly performed multiple times on the back side of the wafer substrate, so as to form capacitors on the back side of the substrate. The capacitors include N capacitor plates and capacitor dielectrics sandwiched between adjacent capacitor plates, where N is an integer greater than or equal to 2.

[0059] In step 6, as Figure 3A shown, multiple wafers are bonded. In an embodiment of the present invention, multiple wafers with capacitors are bonded to each other by metal bonding, and after multiple metal bondings, stacking of multiple capacitors is achieved. In other embodiments of the present invention, a wafer with a capacitor can be bonded to a wafer without a capacitor.

[0060] In step 7, as Figure 3B shown, the bonded multi-layer wafers are scribed.

[0061] In step 8, as Figure 3B shown, the scribed strip-shaped wafers are turned 90° and placed flat on a carrier wafer.

[0062] In step 9, multiple strip-shaped wafers are reorganized in the horizontal direction to form a flat structure (Panel).

[0063] In step 10, as Figure 3C shown, vias penetrating the substrate of the flat structure are fabricated. Via etching is performed on the substrate of the flat structure, a dielectric layer is deposited, and then a metal layer is electroplated to form conductive vias. The material of the dielectric layer is silicon oxide. The material of the metal layer can be Cu, W, etc., or other conductive materials, such as doped polycrystal or its composition, etc.

[0064] In step 11, as Figure 3C shown, redistribution layers (RDL) are fabricated on the front and back sides of the flat structure. First, the redistribution layer on the front side of the flat structure is fabricated, and then the redistribution layer on the back side of the flat structure is fabricated. When fabricating the redistribution layer, a photoresist is first coated, and after exposure and development, a circuit pattern is formed. A metal wiring layer is electroplated on the circuit pattern, and the operation is repeated to form multiple redistribution layers.

[0065] Those skilled in the art can understand that the operations shown in the above method are not exhaustive, but other operations can also be performed before, after, or between the shown operations. Additionally, some of the operations can be performed simultaneously or in an order different from that Figures 3A to 3C shown.

[0066] The present invention has at least the following beneficial effects: The present invention discloses a three-dimensional stacked capacitor integration structure and its manufacturing method, which can make full use of the longitudinal space on the substrate and reduce the planar area overhead; the three-dimensional stacked capacitor integration structure has a larger capacitance value than a general capacitor, and compared with a via trench capacitor of the same material, the capacitance density of the three-dimensional stacked capacitor integration structure can be increased by about 50%; the three-dimensional stacked capacitor integration structure can be flexibly integrated with a chip; a large number of short-distance vias are connected inside a single capacitor unit in the three-dimensional stacked capacitor integration structure, reducing the overall parasitic inductance of the three-dimensional stacked capacitor integration structure.

[0067] Although some embodiments of the present invention have been described in this application document, those skilled in the art can understand that these embodiments are merely shown as examples. Those skilled in the art can conceive numerous variant schemes, alternative schemes, and improvement schemes under the teaching of the present invention without exceeding the scope of the present invention. The appended claims are intended to define the scope of the present invention and thereby cover the methods and structures within the scope of these claims themselves and their equivalent transformations.

Claims

1. A method for manufacturing a three-dimensional stacked capacitor integrated structure, comprising: Depositing an insulating dielectric layer on the front side of the wafer substrate; A capacitor is fabricated on the front side of the wafer substrate by first forming a capacitor plate on the insulating dielectric layer on the front side of the substrate, then depositing a capacitor dielectric on the capacitor plate, and then forming a capacitor plate on the capacitor dielectric. Bond multiple wafers; Slicing the bonded multi-layer wafer; Turn the diced strip wafer 90° and place it horizontally on the carrier; Multiple horizontally placed strip wafers are reassembled to form a flat plate structure.

2. The method for manufacturing a three-dimensional stacked capacitor integrated structure according to claim 1, wherein: The insulating dielectric layer is used for insulating the capacitor plates and the substrate.

3. The method for manufacturing a three-dimensional stacked capacitor integrated structure according to claim 1, wherein: Fabricating a capacitor on the front side of a wafer substrate includes repeatedly repeating the steps of forming capacitor plates and capacitor dielectrics, thereby forming a capacitor on the front side of the substrate. The capacitor includes N capacitor plates and a capacitor dielectric sandwiched between adjacent capacitor plates, where N is an integer greater than or equal to 2.

4. The method for manufacturing a three-dimensional stacked capacitor integrated structure according to claim 1, wherein: Performing through-hole etching on a substrate of a flat structure, depositing a dielectric layer, and then electroplating a metal layer to form a conductive through-hole; The material of the dielectric layer is silicon oxide.

5. The method for manufacturing a three-dimensional stacked capacitor integrated structure according to claim 1, wherein: It also includes making multiple layers of redistribution layers on the front and back of the flat structure. When making the redistribution layers, exposure glue is first applied, and a circuit pattern is formed through exposure and development. Metal is electroplated on the circuit pattern to form a metal wiring layer. The operation is repeated to form multiple layers of redistribution layers.

6. The method for manufacturing a three-dimensional stacked capacitor integrated structure according to claim 1, wherein: The invention also includes depositing an insulating dielectric layer on the back side of the wafer substrate; Capacitors are made on the back side of the wafer substrate. First, capacitor plates are formed on the insulating dielectric layer on the back side of the substrate. Then, capacitor dielectric is deposited on the capacitor plates to form capacitor plates on the capacitor dielectric.

7. A three-dimensional stacked capacitor integrated structure formed by the method for manufacturing a three-dimensional stacked capacitor integrated structure according to any one of claims 1 to 6, comprising: a substrate having a front surface and a back surface opposite to the front surface; One or more capacitors, each capacitor comprising a plurality of capacitor plates and a capacitor dielectric sandwiched between adjacent capacitor plates, wherein the capacitor plates are flat plates penetrating the top and bottom surfaces of the substrate.

8. The three-dimensional stacked capacitor integrated structure according to claim 7, characterized in that: Also includes: a through hole vertically penetrating the substrate; A redistribution layer is arranged on the front and back sides of the substrate, and the redistribution layer is electrically connected to the capacitor and the through hole.

9. The three-dimensional stacked capacitor integrated structure according to claim 8, characterized in that: The redistribution layer on the front side of the substrate is electrically connected to the Bump; The redistribution layer on the front side of the substrate is electrically connected to the chip via a bump; The redistribution layer on the back side of the substrate is electrically connected to the solder balls.

10. The three-dimensional stacked capacitor integrated structure according to claim 7, wherein: The capacitor is M1I1M2I2...M n Capacitance, where n ≥ 4.

11. The three-dimensional stacked capacitor integrated structure according to claim 7, wherein: The plurality of capacitors are bonded in pairs by metal bonding.

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