Integrated mos transistor with selective disablement cell

Abstract

Embodiments of the present disclosure relate to integrated MOS transistors with selectively disabled cells. An integrated device includes at least one MOS transistor having a plurality of cells. A disabling structure is provided in each of one or more cells. The disabling structure is configured to be in a non-conducting condition when the MOS transistor is turned on in response to a control voltage included between a threshold voltage of the MOS transistor and an intervention voltage of the disabling structure, or in other cases to be in a conducting condition. Systems including at least one of the above integrated devices are also presented. Furthermore, corresponding processes for manufacturing the integrated devices are also presented.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the field of integrated devices. More specifically, the present disclosure relates to MOS transistors. BACKGROUND

[0002] The background of the present disclosure is introduced here by discussing the technology related to its context. However, even if this discussion refers to documents, acts, artifacts, etc., it does not imply, nor should be inferred, that they are part of the prior art or constitute common general knowledge in the field relevant to the present disclosure.

[0003] Integrated devices based on MOS transistors are commonly used for a variety of applications. In particular, MOS transistors are one of the most common components in power supply applications, where large amounts of electrical energy are handled; in such cases, MOS transistors are designed to operate at relatively high voltages and / or currents. (Power) MOS transistors typically have a honeycomb structure. In particular, throughout several cells, each MOS transistor replicates the same structure. For example, a cell comprises corresponding (basic) gate and source regions connected in parallel in the form of alternating stripes. The honeycomb structure provides a high perimeter / area ratio of the source regions. This allows obtaining a relatively wide channel in a relatively small area of the die of the integrated MOS transistor (thus reducing the size of the corresponding integrated device), thereby increasing the current that can be sustained.

[0004] The performance of MOS transistors is defined by several of their characteristics. In particular, a very important characteristic of MOS transistors is their safe operating area (SOA). The SOA of each MOS transistor is defined by the drain / source voltage Vds and the drain / source current (Ids) that the MOS transistor is expected to be able to withstand without self-damaging (where the MOS transistor should never be exposed to operating conditions outside its SOA, not even for an instant).

[0005] Several factors limit the SOA of MOS transistors. In particular, in a plot of the drain / source voltage Vds and the drain / source current Ids plotted on a logarithmic scale, the SOA is delimited by basic straight edges segments. These edge segments are defined by the drain / source on-state, or output, resistance RDSon (affecting MOS transistors operating in the linear region or ohmic region, where the drain / source voltage Vds is substantially proportional to the drain / source current Ids), the drain / source current Ids limit (decided by its maximum value), the thermal limit (decided by the maximum heat dissipation), the secondary breakdown limit (decided by the thermal runaway affecting MOS transistors when operating in linear mode, where the drain / source current Ids is proportional to small variations of its gate / source voltage Vgs), and the drain / source voltage Vds limit (decided by its maximum value) (continuously increasing the value of the drain / source voltage Vds).

[0006] The technique for enlarging the SOA of a MOS transistor (having a cellular structure) consists in removing the source region of some of the cells, such as one out of every two cells. In this way, during operation of the MOS transistor, the resulting dummy region of the die, where the source region is removed, is non-active and then does not generate heat. Moreover, the dummy region acts as a heat sink for the rest of the MOS transistor. Therefore, the heat generated by the MOS transistor (around the remaining source regions) is partially dissipated by the dummy region, limiting the heating of the MOS transistor.

[0007] However, the dummy region reduces the number of source regions of the MOS transistor, which in turn correspondingly increases its drain / source on-state resistance RDSon. In fact, the drain / source on-state resistance RDSon is given by several contributions along the path of the drain / source current Ids from the drain terminal of the MOS transistor to the source terminal of the MOS transistor; in particular, these contributions include the resistance of the source regions. Since the source regions are connected in parallel, the fewer they are, the higher their total resistance is.

[0008] The increase in the drain / source on-state resistance RDSon correspondingly increases the corresponding limit in the SOA of the MOS transistor. Therefore, this can adversely affect the performance of the MOS transistor, especially when it operates in the linear region. SUMMARY

[0009] A simplified summary of the disclosure is provided herein in order to provide a basic understanding of the disclosure; however, this summary is not an extensive overview of the disclosure and is not intended to identify key / critical elements of the disclosure or to delineate the scope of the disclosure. Its sole purpose is to present some concepts of the disclosure in a simplified form as a prelude to the more detailed description that is presented below.

[0010] Generally speaking, the disclosure is based on the idea of selectively disabling cells.

[0011] In particular, one aspect provides an integrated device comprising at least one MOS transistor having a plurality of cells. A disabling structure is provided in each of one or more cells; the disabling structure is configured to be in a non-conductive condition when the MOS transistor is switched on in response to a control voltage comprised between a threshold voltage of the MOS transistor and an intervention voltage of the disabling structure, or in other cases in a conductive condition.

[0012] Another aspect provides a system comprising at least one integrated device as described above.

[0013] Another aspect provides a corresponding process for manufacturing the integrated device. BRIEF DESCRIPTION OF DRAWINGS

[0014] The solution of the present disclosure and its further features and advantages will be best understood with reference to the following detailed description, given purely by way of non-limiting indication, and read in connection with the accompanying drawings (in which, for simplicity, corresponding elements are denoted with the same or similar references and are not repeated explained, and the name of each entity is generally used to indicate its type and properties, such as values, contents and representations). In this respect, it is expressly stated that the drawings are not necessarily drawn to scale (some details can be exaggerated and / or simplified), unless otherwise indicated, in which case they are only used to conceptually illustrate the structures and procedures described herein. In particular:

[0015] Figure 1 a partial view of a cross-section of an integrated device is shown, according to an embodiment of the present disclosure,

[0016] Figure 2 an equivalent circuit of a MOS transistor is shown, according to an embodiment of the present disclosure,

[0017] Figures 3A to 3K main steps of a manufacturing process of an integrated device are shown, according to an embodiment of the present disclosure, and

[0018] Figure 4 a schematic block diagram of a system incorporating an integrated device is shown, according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0019] With particular reference to Figure 1 a partial view is shown in a cross-section of an integrated device 100, according to an embodiment of the present disclosure.

[0020] The integrated device 100 comprises a MOS transistor 105 (or more). The MOS transistor 105 is of the double-diffused type (DMOS) and it has a vertical structure based on trench-gate (such as with U-shape, UMOS). The MOS transistor 105 implements a power component designed to handle relatively high electric power (e.g. of the order of more than 10 W), such as to operate with corresponding relatively high (e.g. of the order of more than 10 A and 10 V, respectively) electric current and / or voltage.

[0021] The MOS transistor 105 is integrated on a semiconductor block, such as a die 110 of a semiconductor material (e.g. silicon (so as to define a corresponding chip). Typically, the concentration of N-type dopants (or impurities) and P-type dopants (or impurities) of a semiconductor material are denoted by adding a symbol + or a symbol - to the letter N and P, respectively, to indicate a high or a low concentration of impurities, or by adding a symbol ++ or a symbol -- to the letter N and P, respectively, to indicate a very high or a very low concentration of impurities; the letter N and P without any addition of a symbol + or - indicates an intermediate value of concentration. The die 110 comprises a substrate 115 of N++ type (actually thicker), on which a (thin) epitaxial layer 120 of N type is arranged. A free major surface of the epitaxial layer 120 defines a front surface 125f of the die 110, while a free major surface of the substrate 115 defines a back surface 125b of the die 110 (opposite to each other).

[0022] The MOS transistor 105 comprises the following components. A drain region of N++ type is defined by the substrate 115 (extending from the back surface 125b into the die 110). A body region 130 of P type extends from the front surface 125f into the epitaxial layer 120 of the die 110, so as to remain separated from the drain region 115. The MOS transistor 105 has a cellular structure with identical structures replicated throughout a plurality of cells (such as 100-1.000). In particular, each cell comprises the following components. A source region 135 of N+ type extends from the front surface 125f into the body region 130. A gate trench 140 extends from the front surface 125f into the body region 130 and then into the epitaxial layer 120 of the die 110. The gate trench 140 is coated with a (relatively thin) gate insulating layer 145 of (electrically) insulating material (e.g. silicon oxide). The (coated) gate trench 140 is filled with a gate element 150 of (electrically) conductive material (such as N+ doped polysilicon). The MOS transistor has an interdigitated architecture; in particular, in a factory view (on the front surface 125f), the source region 135 and the gate element 150 have an elongated shape (strip-like) and are arranged in parallel (like crossed fingers) to each other, alternating. A drain contact of (electrically) conductive material (e.g. metal) contacts the drain region 115 on the back surface 125b. A passivation layer 160 of (electrically) insulating material (e.g. silicon dioxide) covers the front surface 125f (partially cut in the figure for clarity). A source contact 165 of (electrically) conductive material (e.g. metal) contacts all the source regions 135 and the body region 130 through the passivation layer 160. A gate contact 170 of (electrically) conductive material (e.g. metal) contacts all the source regions 135 through the passivation layer 160.

[0023] In general, the MOS transistor 105 can operate in three different regions of its characteristics depending on the voltage at the terminals of the MOS transistor 105 (defined by the drain contact 155, the source contact 165 and the gate contact 170). In particular, in the cut-off region or sub-threshold region, the (control) gate / source voltage Vgs is lower than the threshold voltage Vth of the MOS transistor 105 (e.g. 1-2 V); in this case, the MOS transistor 105 is turned off (no drain / source current Ids flows through the MOS transistor 105). In the linear region or ohmic region, the gate / source voltage Vgs is higher than the threshold voltage Vth and the drain / source voltage Vds is strictly lower than the overdrive voltage Vov = Vgs - Vth (Vds < Vgs - Vth); in this case, the MOS transistor 105 is turned on and the drain / source voltage Vds is substantially proportional to the drain / source current Ids. In the saturation region or active region, the gate / source voltage Vgs is again higher than the threshold voltage Vth, but the gate / source voltage Vgs is higher than the overdrive voltage (Vds > Vgs - Vth); in this case, the MOS transistor 105 is again turned on, but now the drain / source current Ids (independent of the drain / source voltage Vds) is substantially constant.

[0024] In the solution according to the embodiments of the present disclosure, as described in detail below, one or more selected cells further comprise a corresponding disabling structure able to selectively disable them. In particular, each disabling structure is interposed between a portion of the gate element 150 coupled with the gate contact 170 and another portion of the gate element 150 decoupled from the gate contact 170. The disabling structure has an intervention voltage higher than the threshold voltage Vth (e.g. equal to 1.5-3 times). The disabling structure is configured in a non-conductive condition when the MOS transistor is turned on in response to the gate / source voltage Vgs, in the other cases the disabling structure is in a conductive condition, the gate / source voltage Vgs being comprised between the threshold voltage Vth and the intervention voltage.

[0025] Therefore, when the gate / source voltage Vgs is slightly higher than the threshold voltage Vth, the disabling structure is in the non-conductive condition; in general, this occurs when the MOS transistor 105 operates in the saturation region (due to Vgs < Vth + Vds). In this case, a zero voltage is applied between the corresponding (selected) gate element 150 and the source region 135. Then, the selected cell is not active and does not generate heat, further acting as a heat sink for the rest of the MOS transistor 105. Therefore, the heat generated by the MOS transistor (around the source region 135 of the other cells) is partially dissipated by the selected cell, limiting the heating of the MOS transistor 105.

[0026] On the contrary, when the gate / source voltage Vgs is much higher than the threshold voltage Vth, the disabling structure is in a conductive condition; typically, this occurs when the MOS transistor 105 is operating in the linear region (since Vgs > Vth + Vds). In this case, the disabling structure is substantially transparent to the operation of the MOS transistor 105; in particular, all the cells are active, all the source regions 135 contribute to the drain / source on-state resistance RDSon, and therefore are not adversely affected.

[0027] Finally, when the gate / source voltage Vgs is lower than the threshold voltage Vth, the disabling structure is again in a conductive condition; this occurs when the MOS transistor 105 is operating in the cut-off region. Also in this case, the disabling structure is substantially transparent to the operation of the MOS transistor 105.

[0028] Therefore, the above-described solution allows to selectively disable the selected cells in a dynamic manner, according to the current operating conditions of the MOS transistor. In particular, when the MOS transistor is operating with a relatively high drain / source voltage Vds (as typical in the saturation region), the selected cells are not active. In this case, it is advantageous to limit the heating of the MOS transistor (since it mainly affects the corresponding portion of the SOA); in this case, the resulting increase of the drain / source on-state resistance RDSon is substantially irrelevant (since the drain / source current Ids is practically constant). On the contrary, when the MOS transistor is operating with a relatively lower drain / source voltage Vds (as typical in the linear region, down to zero in the cut-off region), all the cells are active. In this case, it is advantageous to maintain the drain / source on-state resistance RDSon low (since it mainly affects the corresponding portion of the SOA); in this case, the absence of heating limitation is substantially irrelevant (since the heat generated by the MOS transistor is relatively low).

[0029] In particular, in the specific embodiment shown in the figures, the gate element 150 of each selected cell comprises the following additional components. A P+ type (e.g., also doped polysilicon) split region 175, which extends down into the gate element 150 from the front surface 125f to reach the insulating layer 145; in the factory view (on the front surface 125f), the split region 175 (close to the gate contact 170) passes completely laterally through the gate element 150. As a result, the split region 175 divides the gate element 150 into two parts, denoted as (coupled) gate portion 150c and (uncoupled) gate portion 150u. The gate portion 150c is close to the gate contact 170, so as to remain coupled with the gate contact 170; the gate portion 150u is away from the gate contact 170, then uncoupled from the gate contact 170 (and, in particular, in the region of the die 110 that forms the channel of the MOS transistor 105 in operation). A corresponding PN junction is then created between the split region 175 and the gate portion 150c, and between the split region 175 and the gate portion 150u. A bridging contact 180 of (electrically) conductive material (e.g., metal) contacts both the split region 175 and the gate portion 150u (with the bridging contact 180 remaining floating).

[0030] Reference is now made to Figure 2 and Figure 1 , which show an equivalent circuit of the MOS transistor 105 according to embodiments of the present disclosure.

[0031] The MOS transistor 105 comprises a plurality of elementary MOS transistors M i , where i = 1...N, where N is the number of cells (four cells are shown in the figures). In particular, each elementary MOS transistor M i has a drain (formed by a corresponding portion of the drain region 115), a source (formed by a corresponding source region 135), and a gate (formed by a corresponding gate element 150), with a body (formed by a corresponding portion of the body region 130) short-circuited to the source (via the source contact 165). A gate resistor Rg i is connected to the gate of each elementary MOS transistor M i. represents the resistance of the gate element 150 between the gate contact 170 and the region of the die 110 in which the channel of the MOS transistor 105 is formed in operation.

[0032] In the solution according to embodiments of the present disclosure, in the elementary MOS transistor M s of each selected cell, in the example at issue s = 1, 3, a diode Dd s is formed by the PN junction between the split region 175 and the gate portion 150u, and a diode Dp is formed by the PN junction between the split region 175 and the gate portion 150c.s connected in anti-series to the gate resistor Rg s ; in particular, the anode of the diode Dd s is connected to the anode of the diode Dp s (the common split region 175), and the cathode of the diode Dd s is connected to the gate resistor Rg s (the gate portion 150u mainly contributes to the gate resistor Rg s ). Moreover, the anode and the cathode of the diode Dd s are shorted (via the bridging contact 180). The (reverse) breakdown voltage Vbk of the diode Dp s (which is defined by the minimum voltage at which the diode Dp s is clearly turned on when reverse-biased) is strictly higher than the threshold voltage Vth (e.g. 2-4 V), wherein the breakdown voltage Vbk defines the intervention voltage of the disable structure.

[0033] The elementary MOS transistors Mi are connected in elementary parallel (apart from the diodes Dd s , Dp s present), to form the overall MOS transistor 105. In particular, the MOS transistor 105 has a drain terminal D (formed by the drain contact 155), a source terminal S (formed by the source contact 165), and a gate terminal G (formed by the gate contact 170). The drain terminal D is connected to the drains (drain regions 115) of all elementary MOS transistors M i . The source terminal S is connected to the sources (corresponding source regions 135) of all elementary MOS transistors M i . The gate terminal G is coupled to the gates (corresponding gate elements 150) of all elementary MOS transistors M i . In particular, in the elementary MOS transistors M u of each unselected cell, the gate terminal G is connected to the gate via the gate resistor Rg u ; in contrast, in the elementary MOS transistors M s of each selected cell, the gate terminal G is connected to the cathode of the diode Dp s (the gate portion 150c, neglecting its resistance), then through the diode Dp s and the gate resistor Rg s to the gate (the diode Dd s is shorted).

[0034] When the gate / source voltage Vgs is higher than the threshold voltage Vth but lower than the breakdown voltage Vbk (as a typical saturation region), the diode Dp sare reverse-biased and then turned off. Therefore, only the basic MOS transistors M u receive the gate / source voltage Vgs and are then turned on, while the basic MOS transistors M s with the gate floating are then turned off.

[0035] Conversely, when the gate / source voltage Vgs is higher than the breakdown voltage Vbk (as in the typical linear region), the diodes Dps become (reverse) conductive due to their electrical breakdown. Therefore, all the basic MOS transistors M u , M s receive the gate / source voltage Vgs and are then turned on.

[0036] Finally, when the gate / source voltage Vgs is lower than the threshold voltage Vth (cut-off region), the diodes Dp s are forward-biased and then turned on. Therefore, all the basic MOS transistors M u , M s receive the gate / source voltage Vgs and are then turned off.

[0037] The implementation described above is very simple, but at the same time it is effective. Moreover, it allows to obtain the desired results with limited impact on the structure of the MOS transistor 105.

[0038] Reference is now made to Figures 3A to 3K , which shows the main steps of the manufacturing process of an integrated device according to an embodiment of the present disclosure.

[0039] Starting from Figure 3A , the manufacturing process is typically performed at the level of a wafer 305 of semiconductor material, on which the same structure is simultaneously integrated in a large number of identical areas thereof (for convenience, only one area is mentioned below). The wafer 305 comprises an N++-type substrate, which will form the substrate of the integrated device, then indicated with the same reference number 115. An N-type epitaxial layer, which will form the epitaxial layer of the integrated device, then indicated with the same reference number 120, is thermally grown onto the substrate 115. A mask 310 for the gate trench is formed on the free major surface of the epitaxial layer 120, which will form the front surface of the integrated device, then indicated with the same reference number 125f; for example, the mask 310 is obtained by growing a (relatively thick) layer of silicon oxide by means of a thermal oxidation step, and then etching the same by means of a photoresist layer, which is suitably patterned (and then stripped) by means of a photolithography technique. The wafer 305 is etched through the mask 310 (for example, by means of a dry etching step) to form the gate trench 140.

[0040] Moving to Figure 3B, the (oxide) mask is removed. A (relatively thin) silicon oxide layer 315 is grown onto the wafer 305, i.e. onto the front surface 125f and the exposed surfaces of the gate trenches 140, using a thermal oxidation step; in particular, the portions of the silicon oxide layer 315 coating the gate trenches 140 define their gate insulating layers 145.

[0041] Moving to Figure 3C , an N+ type doped polysilicon layer 320 is deposited onto the wafer 305, i.e. onto the silicon oxide layer 315, so as to fill the (coated) gate trenches 140 and to cover the (coated) front surface 125f.

[0042] Moving to Figure 3D , the wafer 305 is planarized (e.g. using a chemical mechanical polishing, CMP, step) to remove excess doped polysilicon from the silicon oxide layer 315 on the front surface 125f. The operation leaves the gate trenches 140 filled with (remaining) doped polysilicon (coated with the gate insulating layers 145), a corresponding (thin) silicon oxide layer 325 being formed over the gate trenches 140 so as to obtain the gate elements 150.

[0043] Moving to Figure 3E , in the solution according to embodiments of the present disclosure, a mask 330 for the separation region is formed on the wafer 305, i.e. on the silicon oxide layers 315, 325; for example, the mask 330 is obtained by depositing a layer of photoresist material and then patterning the photoresist layer using photolithography techniques. The wafer 305 is etched through the mask 330 (e.g. using a dry etching step) to form a separation trench 335 corresponding to the separation region.

[0044] Moving to Figure 3F , the (photoresist) mask is stripped. A P+ type doped polysilicon layer 340 is deposited on the wafer 305, i.e. on the silicon oxide layers 315, 325, so as to fill the separation trench 335 and to cover the (coated) front surface 125f.

[0045] Moving to Figure 3G , the wafer 305 is planarized (e.g. using a CMP step) to remove excess doped polysilicon from the silicon oxide layers 315, 325 on the front surface 125f. The operation leaves the separation trench 335 filled with (remaining) doped polysilicon, a corresponding (thin) silicon oxide layer 345 being formed over the separation trench 335 so as to obtain the separation region 175.

[0046] Moving to Figure 3HTypically, P-type body region 130 and N+ source region 135 are formed. For example, not shown, body region 130 is formed by an ion implantation step, followed by a thermal diffusion step, through a photoresist mask (then stripped); likewise, source region 135 is formed by an ion implantation step, followed by a thermal diffusion step, through another photoresist mask (then stripped).

[0047] Moving to Figure 3I A (relatively thick) silicon oxide layer 350, i.e., silicon oxide layers 315, 325 (together defining protection layer 160), is grown on wafer 305, using a thermal oxidation step. Source window 355 for a source contact, gate window 360 for a gate contact, and bridge window 365 for a bridge contact are opened in protection layer 160, by etching protection layer 160 through a photoresist mask and then stripping (not shown in the figures).

[0048] Moving to Figure 3J A metal (e.g., tungsten) layer 370 (i.e., protection layer 160) is deposited on wafer 305, so as to fill source window 355, gate window 360, and bridge window 365, and to cover (coat) front surface 125f.

[0049] Moving to Figure 3K Wafer 305 is planarized (e.g., using a CMP step) to remove excess metal from protection layer 160 on front surface 125f. This operation leaves a corresponding source plug 375 in source window 355, a corresponding gate plug 380 in gate window 360, and a corresponding bridge plug 385 in bridge window 365. At this point, not shown in the figures, a metal layer (e.g., copper) is deposited on wafer 305, i.e., protection layer 160, source plug 375, gate plug 380, and bridge plug 385. The metal layer is etched through a photoresist mask and then stripped, so as to define rods and corresponding strips in contact with source plug 375 (forming a source contact), rods and corresponding strips in contact with gate plug 380 (forming a gate contact), and corresponding pads in contact with bridge plug 385 (forming a bridge contact), thereby obtaining the structure shown in Figure 1

[0050] The implementation described above allows to obtain the desired results with a limited number of additional process steps (and then with limited additional costs).

[0051] Reference is now made to Figure 4 A schematic block diagram of a system 400 incorporating an integrated device according to embodiments of the present disclosure is shown.

[0052] ​The system 400 (e.g., a control unit for automotive applications) includes several components connected between them by a bus structure 405 (with one or more levels). In particular, one or more microprocessors (μP) 410 provide the logic capabilities of the system 400; a non-volatile memory (ROM) 415 stores the base code of the boot program for the system 400, and a volatile memory (RAM) 420 is used by the microprocessor 410 as a working memory. The system has a mass storage 425 (e.g., a flash EEPROM) for storing programs and data. Moreover, the system 400 includes a plurality of controllers of peripheral devices or input / output (I / O) units 430 (such as a Wi-Fi WNIC, a Bluetooth transceiver, a GPS receiver, an accelerometer, a gyroscope, etc.). In particular, one or more of the peripheral devices 430 each include a micro (electromechanical) structure 435 (e.g., one or more sensors / actuators) and an integrated device 100 for controlling the microstructure 435.

[0053] Clause revision

[0054] Naturally, those skilled in the art can impose numerous logical and / or physical modifications and alterations to this disclosure to meet local and specific requirements or design considerations. More specifically, while this disclosure has been described with a degree of particularity with reference to one or more embodiments thereof, it should be understood that various omissions, substitutions, and variations in form and detail, as well as in other embodiments, are possible. In particular, different embodiments of this disclosure may even be practiced without the specific details (such as numerical values) set forth in the foregoing description to provide a more thorough understanding of this disclosure; conversely, well-known features may have been omitted or simplified to avoid obscuring the description with unnecessary detail. Furthermore, as a matter of general design choice, it is explicitly intended that specific elements and / or method steps described in connection with any embodiment of this disclosure may be incorporated into any other embodiment. Moreover, items presented in the same group and different embodiments, examples, or alternatives should not be construed as being factually equivalent to each other (but they are independent and autonomous entities). In all cases, each numerical value should be modified according to the applicable tolerances; in particular, unless otherwise stated, the terms “substantially,” “approximately,” “about,” “approximately,” etc., should be understood as within 10%, preferably within 5%, and even more preferably within 1%. Furthermore, each range of numerical values ​​should be intended to explicitly specify any possible numbers along the continuum (including its endpoints) within that range. Ordinal numbers or other qualifiers are used only as markers to distinguish elements with the same name, but do not in themselves imply any priority, precedence, or order. Terms including, consisting of, having, encompassing, relating to, etc., should have an open, non-exhaustive meaning (i.e., not limited to the listed items); terms based on, depending on, according to, function of, etc., should refer to a non-exclusive relationship (i.e., possibly involving other variables); terms one, one should refer to one or more items (unless otherwise explicitly stated); and terms means (or any means plus a description of function) should refer to any structure adjusted or configured to perform the relevant function.

[0055] For example, one embodiment provides an integrated device. However, an integrated device can be of any type (e.g., raw wafer form, bare die, package, etc.).

[0056] In one embodiment, the integrated device includes at least one MOS transistor. However, the integrated device may include any number and type of MOS transistors (e.g., NMOS, PMOS, power type, signal type, mixed type, operating at any current / voltage, etc.).

[0057] In one embodiment, the MOS transistor is integrated on a die of semiconductor material. However, the die can be of any type (e.g., an epitaxial layer grown on a substrate, a single-crystal substrate, SOI, etc.) and any semiconductor material (e.g., silicon, germanium, dopants of any type and concentration, etc.).

[0058] In one embodiment, the MOS transistor includes a plurality of cells. However, the cells can be any number and any type (e.g., strip, block, interdigitated, array, etc.).

[0059] In one embodiment, each cell includes a source region of semiconductor material. However, the source region can be any shape, size, depth, and type (e.g., N, P, with any type and concentration of dopant, etc.).

[0060] In one embodiment, each cell includes a gate element of conductive material. However, the gate element can be any shape, size, and type (e.g., buried, surface, polysilicon, metal, etc. with any depth).

[0061] In one embodiment, each cell includes a gate insulating layer of electrically insulating material insulating the gate element from the semiconductor material of the die. However, the gate insulating layer can be any thickness, extent, and type (e.g., a single layer extending through all gate elements, separate portions for each gate element or group thereof, silicon oxide, silicon nitride, TEOS, etc.).

[0062] In one embodiment, the MOS transistor includes a source contact coupled with the source region. However, the source contact can be any type (e.g., metal, doped polysilicon, etc.) and can be coupled with the source region in any manner (e.g., via a corresponding buried plug, surface ground, coupled or not coupled with a possible body region, etc.).

[0063] In one embodiment, the MOS transistor includes a gate contact coupled with the gate element. However, the gate contact can be any type and can be coupled with the gate element in any manner (the same or different than the source contact).

[0064] In one embodiment, one or more selected cells are differentiated among the cells. However, the selected cells can be any number and can be arranged in any manner (e.g., alternating with other non-selected cells, one non-selected cell among two or more non-selected cells, evenly distributed, more concentrated in some areas).

[0065] In one embodiment, each selected cell includes a disabling structure interposed between a coupled gate portion of the gate element that is coupled to the gate contact and a decoupled gate portion of the gate element that is decoupled from the gate contact. However, the disabling structure can be of any type (e.g., two back-to-back diodes, a single diode, a transistor, an additional disabling contact coupled to the gate element, etc.) and can be disposed at any location between the coupled gate portion and the decoupled gate portion (e.g., in the middle, close to the gate contact, close to the source region, etc.).

[0066] In one embodiment, the disabling structure has an intervention voltage that is higher than a threshold voltage of the MOS transistor. However, the intervention voltage and the threshold voltage can have any value (whether absolute or relative); moreover, the intervention voltage can be defined in any manner (e.g., by a reverse breakdown voltage, a threshold voltage, an external bias voltage, etc.).

[0067] In one embodiment, the disabling structure is configured to be in a non-conductive condition when the MOS transistor is turned on in response to a control voltage applied between the gate contact and the source contact, the disabling structure being otherwise in a conductive condition, the control voltage being comprised between the threshold voltage and the intervention voltage. However, this result can be achieved in several manners (e.g., the diode / transistor conducts only when forward or reverse biased in electrical breakdown in response to a control voltage that is respectively lower than the threshold voltage or higher than the intervention voltage, or vice versa, the control voltage reaches the decoupled gate portion only when the control voltage overcomes a bias voltage applied to the disabling contact, and so on).

[0068] Further embodiments provide additional advantageous features, however these features can be completely omitted in the basic implementation.

[0069] In particular, in the embodiment of each of the selected cells, the disabling structure includes a diode having a reverse breakdown voltage that defines the intervention voltage. However, the diode can be of any type (e.g., avalanche diode, Zener diode, etc.).

[0070] In one embodiment, the diode is configured to be reverse biased when the MOS transistor is turned on and forward biased when the MOS transistor is turned off. However, the opposite behavior is not excluded (i.e., the diode is forward biased when the MOS transistor is turned on, conducts or not depending on the control voltage, and is reverse biased when the MOS transistor is turned off).

[0071] In one embodiment, the die has a first conductivity type and has a major surface. However, the first conductivity type can be any type (e.g., N, P, with any type and concentration of dopant, etc.).

[0072] In one embodiment, the MOS transistor includes at least one body region of a second conductivity type extending from the major surface into the die. However, the second conductivity type can be any type (e.g., P, N, with any type and concentration of dopant, etc.); moreover, the body region can be any number, shape, size, depth, and type (e.g., one cell of all cells, one cell or group of cells per cell or group thereof, etc.).

[0073] In one embodiment, each of the cells includes a source region of the first conductivity type extending from the major surface into the body region. However, the source region can extend into the body region in any manner (e.g., at any location, to any depth relative thereto, etc.).

[0074] In one embodiment, each of the cells includes a gate trench extending from the major surface into the body region and into the semiconductor material of the die. However, the gate trench can be any shape, size, and depth (e.g., having a U-shaped cross-section in a UMOS, a V-shaped cross-section in a VMOS, etc.).

[0075] In one embodiment, each of the cells includes a gate insulating layer coating the gate trench. However, the gate insulating layer can coat the gate trench in any manner (e.g., extending only in the gate trench, extending further over the front surface, etc.).

[0076] In one embodiment, each of the cells includes a gate element filling the gate trench, the gate trench being coated with the gate insulating layer. However, the possibility of a MOS transistor having a planar structure is not excluded.

[0077] In one embodiment, the die has a further major surface opposite the major surface; the MOS transistor includes a drain region of the first conductivity type extending from the further major surface into the die. However, the possibility of a MOS transistor having a planar structure is not excluded.

[0078] In one embodiment, in each of the selected cells, the gate element includes a coupled gate portion of semiconductor material of a gate conductivity type (consisting of one of the first conductivity type or the second conductivity type). However, the coupled gate portion can be any type (e.g., P, N, with any type and concentration of dopant, etc.).

[0079] In one embodiment, in each of the selected cells, the gate element includes a decoupled gate portion of the gate-conductivity-type semiconductor material. However, the decoupled gate portion can be of any type (e.g., with or without the same type and concentration of dopants as the coupled gate portion).

[0080] In one embodiment, in each of the selected cells, the disable structure includes a separation region of a separation-conductivity-type semiconductor material separating the coupled gate portion from the decoupled gate portion. However, the separation region can be of any shape, size, depth, and type (e.g., N, P, with any type and concentration of dopants, etc.).

[0081] In one embodiment, the separation region and the coupled gate portion define a diode, and the separation region and the decoupled gate portion define another diode connected in reverse series with the diode. However, the other diode can be of any type (same or different type as the diode) and the two diodes can be connected in reverse series in any manner (e.g., sharing their anodes or their cathodes).

[0082] In one embodiment, in each of the selected cells, the disable structure includes a bridging element of an electrically conductive material connected between the separation region and the decoupled gate portion, the bridging element shorting the other diode. However, the bridging element can be of any shape, size, depth, and type (e.g., metal, doped polysilicon, at any location, etc.).

[0083] In one embodiment, in each of the selected cells, the coupled gate portion, the decoupled gate portion, and the separation region fill corresponding portions of a gate trench extending from the main surface to the gate insulating layer. However, the possibility of having different arrangements (e.g., having coupled / decoupled gate portions extending to a lower depth, then filling the bottom of the gate trench by the separation region) is not excluded.

[0084] In one embodiment, in each of the selected cells, the bridging element includes a bridging trench extending from the main surface into the separation region and the decoupled gate portion. However, the bridging trench can be of any shape, size, and depth.

[0085] In one embodiment, in each of the selected cells, the bridging element includes a bridging plug of an electrically conductive material filling the bridging trench. However, the possibility of contacting the separation region and the decoupled gate portion in different manners (e.g., only on the front surface of the die, etc.) is not excluded.

[0086] One embodiment provides a system comprising at least one integrated device as described above. However, the same structures can be integrated with other circuits in the same chip; the chip can also be coupled with one or more other chips, which can be mounted in an intermediate product, or can be used in a complex apparatus. In any case, the resulting system can be of any type (e.g., for use in automotive applications, smart phones, computers, etc.) and can include any number of these integrated devices.

[0087] In general, similar considerations apply if the integrated device and system each have different structures or include equivalent components (e.g., of different materials) or have other operational characteristics. In any case, each of its components can be partitioned into more elements, or two or more components can be combined together into a single element; furthermore, each component can be replicated to support corresponding operations that are performed in parallel. Moreover, unless otherwise specified, any interaction between different components is generally not required to be continuous, and it can be a direct interaction, or an indirect interaction through one or more intermediaries.

[0088] Embodiments provide a process for manufacturing the integrated device described above. However, the integrated device can be manufactured with any technique, with different masks in number and type, or with other process steps / parameters. Moreover, the solution described above can be part of the design of the integrated device. The design can also be created in a hardware design language; moreover, if the designer does not manufacture the chip or the masks, the design can be transmitted to other people for physical realization.

[0089] In general, similar considerations apply if the same solution is implemented with equivalent methods (by using similar steps or classes of steps with the same functionality but with more steps, removing some non-essential steps or adding further optional steps). Moreover, the steps can be performed in different order, simultaneously, or in an interleaved manner (at least in part).

[0090] An integrated device (100) comprising: at least one MOS transistor (105) integrated on a die (110) of semiconductor material, wherein the MOS transistor (105) can be summarized as comprising:

[0091] a plurality of cells (135, 150), each cell comprising:

[0092] a source region (135) of semiconductor material,

[0093] a gate element (150) of conductive material, and

[0094] a gate insulating layer (145) of electrically insulating material insulating the gate element (150) from a semiconductor material of the die (110),

[0095] a source contact (165) coupled with the source region (135),

[0096] a gate contact (170) coupled with the gate element (150),

[0097] wherein the one or more selected ones of the cells (135, 150) each comprise:

[0098] a disabling structure (175, 180) interposed between a coupled gate portion (150c) of the gate element (150) coupled with the gate contact (170) and an uncoupled gate portion (150u) of the gate element (150) uncoupled from the gate contact (170), the disabling structure (175, 180) having an intervention voltage higher than a threshold voltage of the MOS transistor (105) and being configured to:

[0099] be in a non-conducting condition when the MOS transistor (105) is turned on in response to a control voltage applied between the gate contact (165) and the source contact (170), the control voltage being comprised between the threshold voltage and the intervention voltage, or

[0100] be in a conducting condition in other cases.

[0101] Each of the selected ones of the cells (135, 150) of the disabling structure (175, 180) can comprise a diode (Dpl, Dp3) having a reverse breakdown voltage defining the intervention voltage, the diode (Dpl, Dp3) being configured to be reverse-biased when the MOS transistor is turned on and to be forward-biased when the MOS transistor (105) is turned off.

[0102] The die (110) can have a first conductivity type and can have a main surface (125f), wherein the MOS transistor (105) can comprise:

[0103] at least one second conductivity type body region (130) extending into the die (110) from the main surface (125f),

[0104] Each of the cells (135, 150) comprises:

[0105] a first conductivity type source region (135) extending into the body region (130) from the main surface (125f),

[0106] a gate trench (140) in the semiconductor material extending from the main surface (125f) into the body region (130) and the die (110),

[0107] a gate insulation layer (145) coating the gate trench (140), and

[0108] a gate element (150) filling the gate trench (140) coated with the gate insulation layer (145).

[0109] The die (110) can have a further main surface (125b) opposite the main surface (125f), wherein the MOS transistor (105) can comprise:

[0110] a drain region (115) of the first conductivity type extending from the further main surface (125b) into the die (110).

[0111] In each of the selected cells (135, 150), the gate element (150) can comprise:

[0112] a coupled gate portion (150c) of the semiconductor material of the gate conductivity type consisting of one of the first conductivity type or the second conductivity type,

[0113] an uncoupled gate portion (150u) of the semiconductor material of the gate conductivity type,

[0114] and a disabling structure (175, 180) can comprise:

[0115] a separation region (175) of the semiconductor material of a separation conductivity type opposite the gate conductivity type separating the coupled gate portion (150c) from the uncoupled gate portion (150u), the separation region (175) and the coupled gate portion (150c) defining a diode (Dpl, Dp3) and the separation region (175) and the uncoupled gate portion (150u) defining a further diode (Ddl, Dd3) connected in reverse series with the diode (Dpl, Dp3), and

[0116] a bridging element (180) of an electrically conductive material connected between the separation region (175) and the uncoupled gate portion (150u), the bridging element (180) short-circuiting the further diode (Ddl, Dd3).

[0117] In each of the selected cells (135, 150), the coupled gate portion (150c), the uncoupled gate portion (150u) and the separation region (175) can fill a corresponding portion of the gate trench (140) extending from the main surface (125f) to the gate insulation layer (145).

[0118] In each selected one of the selected cells (135, 150), the bridging element (180) can comprise:

[0119] a bridging trench (365) extending from the main surface (125f) to the separation region (170) and the decoupled gate portion (150u), and

[0120] a bridging plug (385) of electrically conductive material filling the bridging trench (365).

[0121] The system (400) can be summarized as comprising at least one integrated device (100) according to the present application.

[0122] A process for manufacturing an integrated device (100) which can be summarized as comprising at least one MOS transistor (105) integrated on a die (110) of semiconductor material, wherein the process can comprise:

[0123] forming a plurality of cells (135, 150), for each one of the cells (135, 150), the process comprising:

[0124] forming a source region (135) of semiconductor material,

[0125] forming a gate cell (150) of electrically conductive material, and

[0126] forming a gate insulation layer (145) of electrically insulating material insulating the gate element (150) from the semiconductor material of the die (110),

[0127] forming a source contact (165) coupled with the source region (135),

[0128] forming a gate contact (170) coupled with the gate element (150),

[0129] wherein for each selected one of one or more selected ones of the cells (135, 150), the process can comprise:

[0130] a disable structure (175, 180) is formed interposed between a coupled gate portion (150c) of the gate element (150) coupled to the gate contact (170) and an uncoupled gate portion (150u) of the gate element (150) uncoupled to the gate contact (170), the disable structure (175, 180) having an intervention voltage higher than a threshold voltage of the MOS transistor (105), and the disable structure (175, 180) is configured to be in a non-conductive condition when the MOS transistor (105) is turned on in response to a control voltage applied between the gate contact (165) and the source contact (170), or in a conductive condition in other cases, the control voltage being comprised between the threshold voltage and the intervention voltage.

[0131] The die (110) can have a first conductivity type and have a main surface (125f), wherein the process can include:

[0132] forming a body region (130) of a second conductivity type extending into the die (110) from the main surface (125f),

[0133] For each of the cells (135, 150), the process can include:

[0134] forming a source region (135) of the first conductivity type extending into the body region (130) from the main surface (125f),

[0135] forming a gate trench (140) of a semiconductor material extending into the body region (130) and the die (110) from the main surface (125f),

[0136] forming a gate insulating layer (145) coating the gate trench (140), and

[0137] forming a gate element (150) filling the gate trench (140) coated with the gate insulating layer (145).

[0138] For each of the selected cells (135, 150), the process can include:

[0139] forming a gate element (150) of a semiconductor material of a gate conductivity type consisting of one of the first conductivity type or the second conductivity type,

[0140] forming a separation trench (365) extending from the main surface (125f) into the gate region (150), the separation trench (365) separating the gate element (150) into a coupled gate portion (150c) and an uncoupled gate portion (150u),

[0141] filling the separation trench (365) with a separation region (175) of a separation conductivity type opposite to the gate conductivity type, the separation region (175) and the coupled gate portion (150c) defining a diode (Dpl, Dp3) having a reverse breakdown voltage defining an intervention voltage, and the separation region (175) and the uncoupled gate portion (150u) defining a further diode (Ddl, Dd3) connected in reverse series with the diode (Dpl, Dp3), and

[0142] forming a bridging element (180) of an electrically conductive material connected between the separation region (175) and the uncoupled gate portion (150u), the bridging element (180) short-circuiting the further diode (Ddl, Dd3).

[0143] The various embodiments described above can be combined to provide further embodiments. These and other changes can be made to the embodiments in light of the above-detailed description. The described embodiments are to be considered in all respects only as illustrative and not restrictive in character, with the scope of the embodiments being indicated not by the foregoing description but by the appended claims, all equivalents thereof, and all of the following claims. Thus, the claims are not to be construed as being limited to the embodiments described herein.

Claims

1. A semiconductor integrated device, comprising: At least one MOS transistor is integrated on a die of semiconductor material, said MOS transistor comprising: Multiple units, each of the multiple units comprising: Source region; Gate elements made of conductive materials; and A gate insulating layer of electrically insulating material insulates the gate element from the semiconductor material of the die; Source contact element, coupled to the source region; and A gate contact, coupled to the gate element; One or more selected units among the plurality of units include: A disable structure is inserted between the coupled gate portion and the decoupled gate portion of the gate element, the coupled gate portion of the gate element being coupled to the gate contact, and the decoupled gate portion of the gate element being decoupled from the gate contact. The disable structure has an intervention voltage higher than the threshold voltage of the MOS transistor. The disabled structure is configured as follows: When the MOS transistor is turned on in response to a control voltage applied between the gate contact and the source contact, the disable structure is in a non-conductive state, and the control voltage is between the threshold voltage and the intervention voltage; or In other cases, the disabled structure is in a conductive state.

2. The semiconductor integrated device of claim 1, wherein in each of the selected units, the disable structure includes a diode having a reverse breakdown voltage defining the intervention voltage, the diode being configured to be reverse biased when the MOS transistor is turned on, and the diode being configured to be forward biased when the MOS transistor is turned off.

3. The semiconductor integrated device of claim 1, wherein the die has a first conduction type and a main surface, and the MOS transistor comprises: At least one body region having a second conduction type extends from the main surface into the die; as well as Each of the plurality of units includes: The source region, having the first conduction type, extends from the main surface to the body region; A gate trench extends from the main surface into the body region and into the semiconductor material of the die; The gate insulating layer is coated with the gate trench; and The gate element fills the gate trench coated with the gate insulating layer.

4. The semiconductor integrated device of claim 3, wherein the die has an additional main surface opposite to the main surface, and the MOS transistor comprises: The drain region, having the first conduction type, extends from the additional main surface into the die.

5. The semiconductor integrated device of claim 3, wherein in each of the selected units, the gate element comprises: The coupled gate portion of a semiconductor material of a gate conduction type composed of either the first conduction type or the second conduction type; The decoupled gate portion of the semiconductor material of the gate conduction type; as well as The disabled structures include: A separating region of semiconductor material, which is a separation type of gate conduction material, separates the coupled gate portion from the decoupled gate portion. The separating region and the coupled gate portion define a diode, and the separating region and the decoupled gate portion define another diode connected in reverse series with the diode. as well as A bridging element made of conductive material is connected between the partition region and the decoupled gate portion, and the bridging element short-circuits the additional diode.

6. The semiconductor integrated device of claim 5, wherein in each of the selected cells, the coupled gate portion, the decoupled gate portion, and the separating region fill the corresponding portion of the gate trench extending from the main surface to the gate insulating layer.

7. The semiconductor integrated device of claim 6, wherein in each of the selected cells, the bridging element comprises: A bridging trench extends from the main surface into the partition region and into the decoupled gate portion; as well as A bridging plug made of conductive material fills the bridging trench.

8. An electronic system comprising: Integrated device, the integrated device comprising: At least one MOS transistor is integrated on a die of semiconductor material, said MOS transistor comprising: Multiple units, each of the multiple units comprising: Source region; Gate elements made of conductive materials; and A gate insulating layer of electrically insulating material insulates the gate element from the semiconductor material of the die; Source contact element, coupled to the source region; and A gate contact, coupled to the gate element; One or more selected units among the plurality of units include: A disable structure is inserted between the coupled gate portion and the decoupled gate portion of the gate element, the coupled gate portion of the gate element being coupled to the gate contact, and the decoupled gate portion of the gate element being decoupled from the gate contact. The disable structure has an intervention voltage higher than the threshold voltage of the MOS transistor. The disabled structure is configured as follows: When the MOS transistor is turned on in response to a control voltage applied between the gate contact and the source contact, the disable structure is in a non-conductive state, and the control voltage is between the threshold voltage and the intervention voltage; or In other cases, the disabled structure is in a conductive state.

9. The electronic system of claim 8, wherein in each of the selected units, the disable structure includes a diode having a reverse breakdown voltage defining the intervention voltage, the diode being configured to be reverse biased when the MOS transistor is turned on, and the diode being configured to be forward biased when the MOS transistor is turned off.

10. The electronic system of claim 8, wherein the die has a first conduction type and a main surface, and the MOS transistor comprises: At least one body region having a second conduction type extends from the main surface into the die; as well as Each of the plurality of units includes: The source region, having the first conduction type, extends from the main surface to the body region; A gate trench extends from the main surface into the body region and into the semiconductor material of the die; The gate insulating layer is coated with the gate trench; and The gate element fills the gate trench coated with the gate insulating layer.

11. The electronic system of claim 10, wherein the die has an additional main surface opposite to the main surface, and the MOS transistor comprises: The drain region, having the first conduction type, extends from the additional main surface into the die.

12. The electronic system of claim 10, wherein in each of the selected units, the gate element comprises: The coupled gate portion of a semiconductor material of a gate conduction type composed of either the first conduction type or the second conduction type; The decoupled gate portion of the semiconductor material of the gate conduction type; as well as The disabled structures include: A separating region of semiconductor material, which is a separation type of gate conduction material, separates the coupled gate portion from the decoupled gate portion. The separating region and the coupled gate portion define a diode, and the separating region and the decoupled gate portion define another diode connected in reverse series with the diode. as well as A bridging element made of conductive material is connected between the partition region and the decoupled gate portion, and the bridging element short-circuits the additional diode.

13. The electronic system of claim 12, wherein in each of the selected units, the coupled gate portion, the decoupled gate portion, and the separating region fill the corresponding portion of the gate trench extending from the main surface to the gate insulating layer.

14. The electronic system of claim 13, wherein in each of the selected units, the bridging element comprises: A bridging trench extends from the main surface into the partition region and the decoupled gate portion; as well as A bridging plug made of conductive material fills the bridging trench.

15. A process for manufacturing a semiconductor integrated device, said semiconductor integrated device having at least one MOS transistor integrated on a die of semiconductor material, said process comprising: Forming multiple units, wherein forming the multiple units includes, for each of the multiple units: Formation of the source region; Gate elements forming conductive materials; and A gate insulating layer of electrically insulating material is formed, wherein the gate insulating layer of electrically insulating material insulates the gate element from the semiconductor material of the die; Forming a source contact element, the source contact element being coupled to the source region; and A gate contact is formed, and the gate contact is coupled to the gate element. For each selected unit among one or more of the plurality of units, the process includes: A disable structure is formed, which is inserted between the coupled gate portion and the decoupled gate portion of the gate element, the coupled gate portion of the gate element being coupled to the gate contact, and the decoupled gate portion of the gate element being decoupled from the gate contact. The disable structure has an intervention voltage higher than the threshold voltage of the MOS transistor. The disable structure is configured such that when the MOS transistor is turned on in response to a control voltage applied between the gate contact and the source contact, the disable structure is in a non-conductive state, the control voltage is between the threshold voltage and the intervention voltage, or the disable structure is in a conductive state under other circumstances.

16. The process of claim 15, wherein the die has a first conductive type and a main surface, the process further comprising: Forming a body region of a second conductivity type extending from the main surface into the die, and For each of the plurality of units: The source region is formed, the source region having the first conduction type, extending from the main surface to the body region; A gate trench is formed, the gate trench extending from the main surface into the semiconductor material of the body region and the die; The gate insulating layer is formed, and the gate insulating layer is coated with the gate trench; as well as The gate element is formed by filling the gate trench coated with the gate insulating layer.

17. The process of claim 16, wherein for the gate element of each of the selected cells, the process comprises: The gate element is formed from a semiconductor material of the gate conduction type, wherein the gate element of the semiconductor material of the gate conduction type is composed of one of the first conduction type or the second conduction type; A separation trench is formed, the separation trench extending from the main surface to the gate region, the separation trench separating the gate element into the coupled gate portion and the decoupled gate portion; The partition trench is filled with a partition region of a partition conduction type opposite to the gate conduction type. The partition region and the coupled gate portion define a diode having a reverse breakdown voltage that defines the intervention voltage. The partition region and the decoupled gate portion define another diode that is connected in reverse series with the diode. as well as A bridging element is formed by conductive material connecting the partition region and the decoupled gate portion, the bridging element short-circuiting the additional diode.

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