Embedded Capacitor Structure and Its Manufacturing Method

Abstract

The present invention discloses an embedded capacitor structure and a manufacturing method thereof. The capacitor structure includes a substrate having trenches with a certain depth. On the bottom of the trenches, electrode structures are sequentially provided at multiple intervals along the depth direction of the trenches. The electrode structure includes an electrode layer, an adhesive layer around the electrode layer, and a first dielectric layer. The first dielectric layer and the adhesive layer sequentially wrap the sidewalls of the electrode layer. The electrode structure is attached to the sidewalls of the trenches through the adhesive layer, and the adhesive layer also covers the bottom surfaces of the electrode layer and the first dielectric layer. A second dielectric layer is provided between two adjacent and spaced electrode structures. Two adjacent and spaced electrode structures and the second dielectric layer therebetween constitute a group of capacitor structures. The DRIE and depth endpoint detection processes are used to form trenches with vertical sidewalls. The thickness, area, and shape of the capacitor structure can be adjusted according to requirements, and variable control of the capacitance value can be achieved, ultimately achieving the goal of optimizing the performance.

Description

Technical Field

[0001] The present invention relates to the field of capacitors, and particularly to an embedded capacitor structure and a manufacturing method thereof. Background Art

[0002] With the progress and development of technology, technologies such as 5G wireless communication and GPS have emerged, and the technical requirements for high-performance radio frequency circuits, passive devices (IPD), etc. have gradually increased. As an electronic device commonly used in fields such as high-performance radio frequency circuits and passive devices, capacitors play an important role in semiconductor circuit manufacturing.

[0003] Capacitors are also a key part of the integrated filter manufacturing process. The capacitance value of the capacitor is the main factor determining the target frequency of the filter, and the size of the capacitance value is determined by the thickness and area of the dielectric layer. The current capacitor is based on forming a MIM (metal-Insulator-metal) structure on the wafer and stacking it on the wafer surface by adjusting the thickness and area of the dielectric layer.

[0004] MIM capacitors, namely metal-insulator-metal capacitors, are important components in integrated circuits and are widely used in integrated circuit modules such as sampling circuits, analog-to-digital conversion circuits, filters, and radio frequency circuits. In order to increase the capacitance of the capacitor, generally, the method of increasing the area of the capacitor's electrode plate is adopted. Therefore, the area occupied by the capacitor in the integrated circuit is increased, restricting the miniaturization of semiconductor devices. Thus, it is particularly important to reduce the area occupied by the capacitor while ensuring performance. In addition, when using large-area MIM capacitors, not only will a large area on the integrated circuit be occupied, but also relatively large parasitic capacitance will be generated. Summary of the Invention

[0005] The purpose of the present invention is to overcome the deficiencies existing in the prior art and provide an embedded capacitor structure and a manufacturing method thereof.

[0006] To achieve the above purpose, the technical solution of the present invention is as follows:

[0007] An embedded capacitor structure includes a substrate having a trench with a certain depth. On the bottom of the trench, electrode structures are sequentially provided at multiple layers spaced apart along the depth direction of the trench. The electrode structure includes an electrode layer and a first dielectric layer and an adhesive layer around the electrode layer. The first dielectric layer and the adhesive layer sequentially wrap the side walls of the electrode layer. The electrode structure is attached to the side wall of the trench through the adhesive layer, and the adhesive layer also covers the bottom surface of the electrode layer and the first dielectric layer. A second dielectric layer is provided between two adjacent and spaced electrode structures. At least one group of two adjacent and spaced electrode structures and the second dielectric layer in the middle thereof constitute at least one group of capacitor structures.

[0008] In an alternative embodiment, a third dielectric layer or an air layer is provided between two adjacent and spaced-apart capacitor structures. The material of the third dielectric layer includes SiO2, Si3N4, or polyimide, and the thickness of the third dielectric layer or the height of the air layer is 1 - 10 μm.

[0009] In an alternative embodiment, the thickness range of the first dielectric layer and the second dielectric layer is 100 nm - 2000 nm, and the materials of the first dielectric layer and the second dielectric layer include SiO2 or Si3N4.

[0010] In an alternative embodiment, the thickness of the electrode layer is 1 - 5 μm, and the material of the electrode layer includes at least one of Au, Cu, Pt, Ag, Ni, Co, or an alloy or compound containing at least one of the above metals.

[0011] In an alternative embodiment, the adhesion layer is Si or a seed layer, and the material of the seed layer includes TiW / Au or Ti / Cu.

[0012] In an alternative embodiment, the depth of the trench is 10 μm - 100 μm, and the angle between the sidewall and the bottom of the trench is 88° - 92°.

[0013] In an alternative embodiment, the projection pattern of the trench on the substrate is a single closed line of any shape, and the electrode layer extends outward from the closed line to be provided with leads connected to the outside.

[0014] A method for manufacturing an embedded capacitor structure, comprising the following steps:

[0015] 1) Etch a trench with a certain depth on a substrate by using DRIE combined with depth endpoint detection technology;

[0016] 2) Form an adhesion layer and a first dielectric layer on the sidewall and bottom of the trench by using atomic layer deposition technology;

[0017] 3) Remove the first dielectric layer at the bottom and expose the adhesion layer;

[0018] 4) Fabricate an electrode layer on the adhesion layer;

[0019] 5) Remove the adhesion layer and the first dielectric layer on the sidewall of the trench above the electrode layer to form a first electrode structure;

[0020] 6) Deposit a second dielectric layer on the first electrode structure;

[0021] 7) Repeat steps 2 - 4 on the second dielectric layer to fabricate a second electrode structure, and the first electrode structure, the second dielectric layer, and the second electrode structure form a set of capacitor structures.

[0022] 8) Remove the adhesive layer and the first dielectric layer on the sidewall of the trench above the second electrode structure, and deposit a third dielectric layer on the second electrode structure;

[0023] 9) Repeat steps 2-8 to fabricate at least one set of capacitor structures.

[0024] In an optional embodiment, the adhesive layer is Si or a seed layer. When the adhesive layer is a seed layer, the material of the seed layer includes TiW / Au or Ti / Cu, and an electroplating process is used to fabricate the electrode layer in step 4; when the adhesive layer is Si, a self-aligned silicide process is used to fabricate the electrode layer in step 4.

[0025] In an optional embodiment, the thickness of the third dielectric layer is 1-10 μm, and the material of the third dielectric layer is SiO2, Si3N4, polyimide or a sacrificial material; when the third dielectric layer is a sacrificial material, step 8 further includes: after completing the fabrication of the upper-layer electrode, forming an air layer between adjacent and spaced upper and lower layer electrode structures by opening holes and removing the sacrificial material.

[0026] Compared with the prior art, the present invention has the following beneficial effects:

[0027] (1) The embedded capacitor structure of the present invention adopts an embedded design in the wafer. Multiple sets of capacitor structures are integrated on the trench of the wafer and arranged along the depth direction of the trench, which can effectively utilize the depth of the wafer thickness. The increase in the number of sets of capacitor structures is only adjusted within the trench depth and does not affect the area of the capacitor. Applying the capacitor in the circuit can effectively reduce the area of the capacitor structure.

[0028] (2) The thickness, area and shape of the capacitor structure can be flexibly adjusted according to device requirements, achieving diversity of characteristics, realizing diversity of device design and variable control of capacitance value, and achieving the goal of performance optimization.

[0029] (3) The embedded capacitor structure of the present invention adopts the DRIE process to ensure the perpendicularity of the trench sidewall, and is combined with the depth end detection technology to measure the etching depth of the substrate, accurately controlling the depth of the trench. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 Schematic diagrams of the embedded capacitor structures of Embodiment 1 and Embodiment 2 of the present invention;

[0031] Figure 2 A three-dimensional view of the trench of the embedded capacitor structure of Embodiment 1 of the present invention on the substrate;

[0032] Figures 3a - 3gSchematic diagram of the manufacturing process of the embedded capacitor structure according to Embodiment 1 of the present invention;

[0033] Figure 4 Schematic diagrams of the embedded capacitor structures according to Embodiments 3 and 4 of the present invention. Detailed implementation manners

[0034] The present invention will be further explained below with reference to the accompanying drawings and specific embodiments. The drawings of the present invention are only for illustration to facilitate understanding of the present invention, and their specific proportions can be adjusted according to design requirements. The definitions of the up / down relationship and the front / back of the relative elements in the figures described in the text should be understood by those skilled in the art as referring to the relative positions of the components. Therefore, they can all be flipped to present the same components, and all of these should belong to the scope disclosed in this specification.

[0035] Embodiment 1

[0036] Reference Figure 1, the embedded capacitor structure proposed by the embodiments of the present application includes a substrate and at least one set of capacitor structures 2. Among them, there are trenches 11 with a certain depth on the substrate 1, and a third dielectric layer 3 can be provided between two adjacent sets of capacitor structures 2. At least two sets of capacitor structures 2 and the third dielectric layer 3 in the middle are stacked in the trenches 11 to form an embedded capacitor. Among them, the thickness of the substrate 1 is 625 - 665 μm, and the material of the substrate 1 includes Si or GaAs. The depth of the trench 11 is 10 μm - 100 μm, and the side walls of the trench 11 have a certain perpendicularity within the substrate 1. Specifically, the included angle between the side walls of the trench 11 and the bottom of the trench 11 is 88° - 92°. Multiple layers of the capacitor structures 2 are formed at intervals along the depth direction of the trench 11 from the bottom of the trench 11, and a third dielectric layer 3 is provided between two adjacent capacitor structures 2. The material of the third dielectric layer 3 includes SiO2, Si3N4 or polyimide, and the thickness is 1 - 10 μm. Looking from one set of capacitor structures, the capacitor structure 2 includes a first electrode structure, a second electrode structure, and a second dielectric layer 4 located between the first electrode structure and the second electrode structure. Among them, the thickness of the second dielectric layer 4 is 100 nm - 2000 nm, and the material of the second dielectric layer includes SiO2 or Si3N4. The first electrode structure and the second electrode structure are the same, and both include an electrode layer 21, an adhesive layer 22 and a first dielectric layer 23 around the electrode layer 21. The side walls of the electrode layer 21 are sequentially wrapped by the first dielectric layer 23 and the adhesive layer 22, and the electrode structure is attached to the side walls of the trench 11 through the adhesive layer 22. Specifically, the adhesive layer 22 is provided at the side walls of the trench 11 and the bottom of the electrode layer 21, the first dielectric layer 23 is provided between the side walls of the trench 11 and the adhesive layer 22 for isolation, the side of the electrode layer 21 is covered with the first dielectric layer 23, and the bottom surfaces of the electrode layer 21 and the first dielectric layer 23 and the side of the first dielectric layer 23 are all covered with the adhesive layer 22. In each electrode structure, the electrode layer 21, the adhesive layer 22 on the side walls of the trench, and the top of the first dielectric layer 23 are on the same plane. The thickness of the first dielectric layer 23 is 100 nm - 2000 nm, and the material of the first dielectric layer 23 includes SiO2 or Si3N4. The adhesive layer 22 is a seed layer, and the material of the seed layer includes TiW / Au or Ti / Cu, and the thickness is 100 nm - 2000 nm. The material of the electrode layer 21 can adopt at least one of Au, Cu, Pt, Ag, Ni, Co, or an alloy or compound containing at least one of the above metals. The thickness of the electrode layer 21 is 1 - 5 μm. Specifically, when the seed layer is TiW / Au, the electrode layer 21 is Au; when the seed layer is Ti / Cu, the electrode layer 21 is Cu.

[0037] Reference Figure 2, the first electrode structure and the second electrode structure form planar structures at different positions on the sidewalls of the trench along the depth of the trench. The projection pattern of the trench 11 on the substrate 1 is a single closed line of any shape, preferably square, but not limited thereto. The electrode layer 21 is provided with leads 5 connected to the outside extending outward from the closed line to facilitate charging each electrode structure. A second dielectric layer 4 is provided between the first electrode structure and the second electrode structure, thus constituting a set of capacitor structures 2.

[0038] Reference Figures 3a - 3g As shown in the flowchart, the above structure is prepared by the following method:

[0039] 1) See Figure 3a , a first photoresist is coated on the substrate 1, and a preset trench pattern is obtained through exposure and development. Then, a trench 11 with a depth of 10 μm to 100 μm is etched using DRIE combined with depth endpoint detection technology, and the photoresist is removed by using oxygen plasma (O2 plasma) and solvent cleaning. The thickness of the substrate 1 is 625 - 665 μm, and the material of the substrate 1 includes Si or GaAs. The deep reactive ion etching (DRIE) process can etch out vertical and smooth hole sidewalls, and the depth endpoint detection technology can measure the etching depth. The Bosch process of DRIE is combined with the depth endpoint detection technology to etch a trench with vertical sidewalls of a certain depth. Combining these two technologies can ensure the perpendicularity of the trench 11. Specifically, the angle between the sidewall of the trench 11 and the bottom of the trench 11 is 88° - 92°.

[0040] 2) See Figure 3b , an adhesion layer 22 with a thickness of 100 nm to 2000 nm and a first dielectric layer 23 with a thickness of 100 nm to 2000 nm are formed on the bottom and sidewalls of the trench 11 by atomic layer deposition (ALD) process. The atomic layer deposition (ALD) process belongs to an atomic-level covering method and can obtain a uniform structure surface. Among them, the material of the first dielectric layer 23 includes SiO2 or Si3N4, and the adhesion layer 22 is a seed layer, and the seed layer includes TiW / Au or Ti / Cu.

[0041] 3) See Figure 3c , ICP or RIE is used to remove the first dielectric layer 23 at the bottom and expose the adhesion layer 22. The ICP or RIE process has high directionality. When using the ICP process, the low pressure is 1 - 5 mTorr. After etching the first dielectric layer 23 at the bottom of the trench 22, the etching products are removed by solvent cleaning, so that the underlying adhesion layer 22 is exposed.

[0042] 4) See Figure 3d, apply the second photoresist, and through exposure and development, form a photoresist for the electroplating pattern. On the adhesive layer 22, fabricate an electrode layer 21 with a thickness of 1 - 5 μm by electroplating. The electrode layer 21 serves as the main body of the first electrode structure and, together with the adhesive layer 22 and the first dielectric layer 23, constitutes the first electrode structure. Specifically, when the seed layer is TiW / Au, the electrode layer 21 is Au; when the seed layer is Ti / Cu, the electrode layer 21 is Cu. After electroplating, remove the photoresist by solvent cleaning. At the same time, fabricate leads 5 extending outward from the edge of the first electrode structure for connection to the outside.

[0043] 5) See Figure 3e , use wet etching or isotropic plasma to remove the adhesive layer 22 and the first dielectric layer 23 on the sidewalls of the trench 11 above the electrode layer 21. At this time, the top of the electrode layer 21 is on the same plane as the adhesive layer 22 and the first dielectric layer 23 on the sidewalls of the trench.

[0044] 6) See Figure 3f , deposit a second dielectric layer 4 with a thickness of 100 nm - 2000 nm by plasma-enhanced chemical vapor deposition (PECVD) process. Apply the third photoresist, and through exposure and development, obtain a photoresist covering the top of the electrode layer 21 and the adhesive layer 22 and the first dielectric layer 23 on the sidewalls of the trench for the second dielectric layer 4. Etch away the excess second dielectric layer 4, and then use oxygen plasma (O2 plasma) and solvent cleaning to remove the photoresist. Finally, the second dielectric layer 4 is deposited on the surface of the top of the electrode layer 21 and the adhesive layer 22 and the first dielectric layer 23 on the sidewalls of the trench. The material of the second dielectric layer 4 is SiO2 or Si3N4.

[0045] 7) See Figure 3g , apply the fourth photoresist, and through exposure and development, form a photoresist for the electroplating pattern. On the second dielectric layer 4, fabricate an electrode layer 21 with a thickness of 1 - 5 μm by electroplating. The electrode layer 21 serves as the main body of the second electrode structure and, together with the adhesive layer 22 and the first dielectric layer 23, constitutes the second electrode structure. Specifically, when the seed layer is TiW / Au, the electrode layer 21 is Au; when the seed layer is Ti / Cu, the electrode layer 21 is Cu. After electroplating, remove the photoresist by solvent cleaning. At the same time, fabricate leads 5 extending outward from the edge of the second electrode structure for connection to the outside.

[0046] 8) The third dielectric layer 3 with a thickness of 1 - 10 μm is deposited by plasma-enhanced chemical vapor deposition (PECVD) process. The fifth photoresist is coated, and after exposure and development, the photoresist of the third dielectric layer 3 covering the top of the adhesive layer 22 and the first dielectric layer 23 on the electrode layer 21 and the sidewalls of the trenches is obtained. The excess third dielectric layer 3 is etched away, and then the removal of the photoresist is completed by using oxygen plasma (O2 plasma) and solvent cleaning. Finally, the third dielectric layer 3 is deposited on the surfaces of the adhesive layer 22 on the electrode layer 21 and the sidewalls of the trenches and the top of the first dielectric layer 23. The material of the third dielectric layer 3 is SiO2, Si3N4 or polyimide.

[0047] 9) Repeat steps 2 - 8. Finally, at least one set of capacitor structures fabricated constitutes the Figure 1 embedded capacitor structure as shown.

[0048] By using the above fabrication method, an embedded capacitor structure can be obtained, effectively utilizing the depth of the wafer thickness to obtain trenches. The number of capacitor groups can be elastically adjusted as needed within the trenches, and the thickness, area, and shape of the capacitors can also be designed and changed according to requirements. Moreover, the area of the capacitor is effectively reduced, realizing adjustable control of the capacitance value and further optimizing the performance of the product.

[0049] Example Two

[0050] Refer to Figure 1 , another embedded capacitor structure, which is different from Example One in that the adhesive layer 22 is Si, and the self-aligned silicide (Salicide) process is used to fabricate the electrode layer in step 4. Therefore, when the adhesive layer 22 is Si, the electrode layer is deposited on the surface of the Si layer and is in contact with the surface of the Si layer. Then, a thermal process treatment is carried out to form a silicided electrode layer on the surface of the contact electrode layer and the Si layer. In step 5, the first dielectric layer and the Si layer on the sidewalls of the trenches above the silicided electrode layer are removed. The electrode layer can be selected from one of the metals Ti, Co, Ni.

[0051] Example Three

[0052] Refer to Figure 4 , another embedded capacitor structure, which is different from Example One in that an air layer 5 is provided between two adjacent and spaced capacitor structures. Specifically, in step 6, a sacrificial material is filled between two adjacent and spaced capacitor structures, and the third dielectric layer 3 is set as the sacrificial layer. In the fabrication method, step 8 further includes: after completing the fabrication of the previous set of capacitor structures, an air layer 5 is formed between two adjacent and spaced sets of capacitor structures by opening holes and removing the sacrificial layer. The sacrificial material can be selected as SOG.

[0053] Example Four

[0054] Reference Figure 4 , another embedded capacitor structure, which is different from the first embodiment in that the adhesive layer 22 is Si, and an air layer 5 is provided between two adjacent and spaced capacitor structures. First, since the adhesive layer 22 is Si, the self-aligned silicide (Salicide) process is used to fabricate the electrode layer 21 in step 4. The electrode layer is deposited on the surface of the Si layer, and the electrode layer is in contact with the surface of the Si layer. Then, a thermal process is performed to form a silicided electrode layer on the surface of the contact electrode layer and the Si layer. In step 5, the first dielectric layer 23 and the Si layer on the sidewall of the trench above the silicided electrode layer are removed, and the electrode layer 21 can be selected from one of metals Ti, Co, and Ni.

[0055] In step 6, a sacrificial material is filled between two adjacent and spaced groups of the capacitor structures, and the third dielectric layer 3 is set as the sacrificial layer. In the manufacturing method, step 8 further includes: after completing the fabrication of a group of capacitor structures, an air layer 5 is formed between two adjacent and spaced groups of the capacitor structures by opening holes and removing the sacrificial layer. The sacrificial material can be selected as SOG.

[0056] The above embodiments are only used to further illustrate an embedded capacitor structure and its manufacturing method of the present invention, but the present invention is not limited to the embodiments. Any simple modification, equivalent change, and modification made to the above embodiments based on the technical essence of the present invention shall fall within the protection scope of the technical solution of the present invention.

Claims

1. An embedded capacitor structure, characterized in that, A substrate including a trench with a certain depth, on the bottom of the trench, electrode structures are sequentially provided at multiple layers spaced apart along the depth direction of the trench. The electrode structure includes an electrode layer, and a first dielectric layer and an adhesion layer around the electrode layer. The first dielectric layer and the adhesion layer sequentially wrap the side walls of the electrode layer. The electrode structure is attached to the side wall of the trench through the adhesion layer. The adhesion layer also covers the bottom surfaces of the electrode layer and the first dielectric layer. A second dielectric layer is provided between two adjacent and spaced electrode structures. At least one group of two adjacent and spaced electrode structures and the second dielectric layer in the middle thereof form at least one group of capacitive structures. A third dielectric layer or an air layer is provided between two adjacent and spaced groups of capacitive structures. At least two groups of capacitive structures and the third dielectric layer or the air layer in the middle thereof are stacked in the trench to form an embedded capacitor.

2. The embedded capacitor structure according to claim 1, characterized in that The material of the third dielectric layer includes SiO2, Si3N4 or polyimide. The thickness of the third dielectric layer or the height of the air layer is 1 - 10 μm.

3. The embedded capacitor structure according to claim 1, wherein, The thickness range of the first dielectric layer and the second dielectric layer is 100 nm - 2000 nm. The material of the first dielectric layer and the second dielectric layer includes SiO2 or Si3N4.

4. The embedded capacitor structure according to claim 1, wherein, The thickness of the electrode layer is 1 - 5 μm. The material of the electrode layer includes at least one of Au, Cu, Pt, Ag, Ni, Co, or an alloy or compound containing at least one of the above metals.

5. The embedded capacitor structure according to claim 1, wherein The adhesion layer is Si or a seed layer. The material of the seed layer includes TiW / Au or Ti / Cu.

6. The embedded capacitor structure according to claim 1, wherein, The depth of the trench is 10 μm - 100 μm. The included angle between the side wall of the trench and the bottom of the trench is 88° - 92°.

7. The embedded capacitor structure according to claim 1, wherein The projection pattern of the trench on the substrate is a single closed line of any shape. The electrode layer extends outward from the closed line and is provided with leads connected to the outside.

8. A manufacturing method of an embedded capacitor structure, characterized in that, Including the following steps: 1) Etch a trench with a certain depth on the substrate by using DRIE combined with depth endpoint detection technology; 2) Form an adhesion layer and a first dielectric layer on the side wall and the bottom of the trench by using atomic layer deposition technology; 3) Remove the first dielectric layer at the bottom and expose the adhesion layer; 4) Fabricate an electrode layer on the adhesion layer; 5) Remove the adhesion layer and the first dielectric layer on the side wall of the trench above the electrode layer to form a first electrode structure; 6) Deposit a second dielectric layer on the first electrode structure; 7) Repeat steps 2 - 4 on the second dielectric layer to fabricate a second electrode structure. The first electrode structure, the second dielectric layer and the second electrode structure form a group of capacitive structures; 8) Remove the adhesion layer and the first dielectric layer on the side wall of the trench above the second electrode structure, and deposit a third dielectric layer on the second electrode structure; 9) Repeat steps 2 - 8 to fabricate at least one group of capacitive structures.

9. The manufacturing method of the embedded capacitor structure according to claim 8, characterized in that, The adhesion layer is Si or a seed layer. When the adhesion layer is a seed layer, the material of the seed layer includes TiW / Au or Ti / Cu, and an electroplating process is used to fabricate the electrode layer in step 4; when the adhesion layer is Si, a self-aligned silicide process is used to fabricate the electrode layer in step 4.

10. The manufacturing method of the embedded capacitor structure according to claim 8, wherein, The thickness of the third dielectric layer is 1 - 10 μm, and the material of the third dielectric layer is SiO2, Si3N4, polyimide or a sacrificial material; When the third dielectric layer is a sacrificial material, step 8 further includes: after fabricating the upper-layer electrode, forming an air layer between adjacent and spaced upper- and lower-layer electrode structures by opening holes and removing the sacrificial material.

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