Control Circuit of Electronic Converter, Related Integrated Circuit, Electronic Converter and Method

Abstract

Embodiments of the present disclosure relate to control circuits for electronic converters, related integrated circuits, electronic converters, and methods. A control circuit for controlling the switching operation of a switching stage of a converter includes a phase detector circuit that generates a pulse width modulation (PWM) signal in response to a phase comparison of two clock signals. The frequency of a first clock signal is determined based on a first feedback signal proportional to the converter output voltage. A first transconductance amplifier generates a first current indicative of a difference between a reference voltage and the first feedback signal; and a second transconductance amplifier generates a second current indicative of a difference between the reference voltage and a second feedback signal proportional to the derivative of the converter output voltage. A delay line introduces a delay in the first clock signal depending on the first and second currents and a compensation current depending on a selected operating mode of the converter.

Description

[0001] Priority Claim

[0002] This application claims priority to Italian Patent Application No. 102020000013627, filed on June 8, 2020, the entire content of which is incorporated herein by reference to the maximum extent permitted by law. Technical Field

[0003] Embodiments of the present specification relate to a control device for a buck converter. Background Art

[0004] Power circuits, such as AC / DC switched-mode power supplies or DC / DC switched-mode power supplies, are well known in the art. There are many types of existing electronic converters, mainly divided into isolated converters and non-isolated converters. For example, non-isolated electronic converters are "buck" converters, "boost" converters, "buck-boost" converters, converters, "SEPIC" converters, and "ZETA" converters. On the contrary, isolated converters are, for example, "flyback" converters, "forward" converters, "half-bridge" converters, and "full-bridge" converters. For those skilled in the art, these types of converters are well known, as evidenced, for example, by the application note AN513 / 0393 "Topologies for Switched Mode Power Supplies", L. Wuidart, 1999, STMicroelectronics.

[0005] Figure 1 Schematically illustrates a DC / DC electronic converter 20. Specifically, the general electronic converter 20 includes two input terminals 200a and 200b for receiving a DC voltage V in and two output terminals 202a and 202b for supplying a DC voltage V out For example, the input voltage V in can be provided by a DC voltage source 10 such as a battery, or can be obtained from an AC voltage by means of a rectifier circuit such as a bridge rectifier and a possible filter circuit. The output voltage V out can be used to supply a load 30.

[0006] Figure 2 Schematically shows the circuit of a typical buck converter 20. Specifically, the buck converter 20 includes two input terminals 200a and 200b for receiving a DC input voltage V in and two output terminals for supplying a regulated voltage V outThe two output terminals 202a and 202b, where the output voltage is equal to or lower than the input voltage V in .

[0007] Specifically, the buck converter 20 typically includes two electronic switches Q1 and Q2 (with their current paths), which are (e.g., directly) connected in series between the input terminals 200a and 200b, where the intermediate node between the two electronic switches Q1 and Q2 represents the switching node Lx. Specifically, the electronic switch Q1 is a high-side switch (e.g., directly) connected between the (positive) terminal 200a and the switching node Lx, while the electronic switch Q2 is a low-side switch (e.g., directly) connected between the switching node Lx and the (negative) terminal 200b, and the (negative) terminal 200b typically represents the ground GND. Thus, the (high-side) switch Q1 and the (low-side) switch Q2 represent a half-bridge configured to connect the switching node Lx to the terminal 200a (voltage V in ) or the terminal 200b (ground GND).

[0008] For example, the switches Q1 and / or Q2 are typically transistors, such as field-effect transistors (FETs), such as metal-oxide semiconductor field-effect transistors (MOSFETs), e.g., n-channel FETs, such as NMOS. Typically, the second electronic switch Q2 is also implemented only using a diode, where the anode is connected to the terminal 200b and the cathode is connected to the switching node Lx.

[0009] In the example considered, an inductor such as an inductor L is (e.g., directly) connected between the switching node Lx and the (positive) output terminal 202a. Conversely, the (negative) output terminal 202b is (e.g., directly) connected to the (negative) input terminal 200b.

[0010] In the example considered, to stabilize the output voltage V out , the converter 20 typically includes a capacitor Cout, which is (e.g., directly) connected between the output terminals 202a and 202b.

[0011] In this context, Figure 3 an example waveform of the signals of such an electronic converter is shown, where

[0012] - Waveform a) shows the signal DRV1 for switching the electronic switch Q1;

[0013] - Waveform b) shows the signal DRV2 for switching the second electronic switch Q2;

[0014] - Waveform c) represents the current I flowing through the electronic switch Q1 Q1 ;

[0015] - Waveform d) shows the voltage V at the switching node Lx Lx (i.e., the voltage at the second switch Q2); and

[0016] - Waveform e) represents the current I through the inductor L L .

[0017] Specifically, when the electronic switch Q1 closes (ON state) at time t1, the current I in the inductor L L (substantially) linearly increases. At the same time, the electronic switch Q2 opens. Then, when the electronic switch Q1 opens (OFF state) at time t2 after an interval T ON1 , the electronic switch Q2 closes, and the current I L (substantially) linearly decreases. Finally, the switch Q1 closes again after an interval T OFF1 . Thus, in the example considered, when switch Q1 is open, switch Q2 (or a similar diode) is closed, and vice versa.

[0018] Therefore, the current I L can be used to charge the capacitor Cout, which supplies the voltage V at terminals 202a and 202b out .

[0019] Thus, in the example considered, the electronic converter 20 includes a control circuit 22 configured to drive the switching of switch Q1 and possibly the switching of switch Q2 to periodically repeat the intervals T ON1 and T OFF1 . For example, the buck converter 20 typically includes a feedback circuit (FBC) 24, such as a voltage divider, configured to generate a feedback signal FB that indicates the output voltage V out (preferably, proportional thereto), and the control circuit 22 is configured to generate drive signals DRV1 and optionally DRV2 by comparing the feedback signal FB with a reference signal (such as a reference voltage V REF ).

[0020] Numerous drive schemes for generating the drive signals DRV1 and optionally DRV2 are known. These solutions commonly have the possibility of regulating the output voltage V ON1 by adjusting the duration of the interval T OFF1 and / or the interval T out .

[0021] For example, in many applications, the control circuit 22 generates a pulse width modulation (PWM) signal DRV1, where the switching interval T SW = T ON1 + T OFF1has a constant duration, but the duty cycle T ON / T SW is variable. For example, a typical control scheme includes intervals T ON1 whose duration is varied via a regulator circuit having at least one integral component, such as a PI (Proportional Integral) regulator or a PID (Proportional Integral Derivative) regulator.

[0022] Specifically, it is well known that a buck converter can operate in continuous conduction mode (CCM), discontinuous conduction mode (DCM), or transition mode (TM).

[0023] As Figure 4A shown, when the control circuit 20 operates the converter in CCM mode, the current I flowing through the inductor L L at the end of the interval T OFF1 is not zero. In this case, the control circuit 20 uses two switching phases T1 and T2, where T SW = T1 + T2, where

[0024] - During phase T1 (T1 = T ON1 = T OFF2 ), switch Q1 is closed while switch / diode Q2 is open; and

[0025] - During phase T2 (T2 = T OFF1 = T ON2 ), switch Q1 is open while switch / diode Q2 is closed.

[0026] For example, in CCM, the control circuit 20 can use a switching period T SW with a fixed duration, but the on-duration T ON1 = T1 can be varied via a PID regulator, i.e., the signal DRV1 is a PWM signal with a (fixed frequency or predetermined frequency), but the on-duration / duty cycle is determined according to the output voltage (and reference signal V REF ). Conversely, the optional signal DRV2 can correspond to an inverted version of the signal DRV1.

[0027] Conversely, as Figure 4B shown, when the control circuit 20 operates the converter in DCM mode, the current I flowing through the inductor L L reaches zero during the interval T OFF1 and remains zero until the end of the interval T OFF1 . In this case, the control circuit 20 effectively uses three switching phases T1, T2, and T3, where T SW = T1 + T2 + T3, where:

[0028] - During phase T1 (T1 = T ON1 ), switch Q1 is closed while switch / diode Q2 is open;

[0029] - During phase T2 (T2 = T ON2 ), switch Q1 is open while switch / diode Q2 is closed; and

[0030] - During phase T3 (T OFF1 = T2 + T3 and T OFF2 = T3 + T1), switch Q1 is open and switch / diode Q2 is open.

[0031] For example, when using a diode as switch Q2, the diode will automatically turn on when the current I L reaches zero, thus ending interval T2. Conversely, when using a controllable electronic switch Q2, control circuit 20 typically includes (or is connected to) a demagnetization detection circuit configured to determine the moment when the current I L reaches zero (corresponding to the end of interval T2 and the start of interval T3). For example, such a demagnetization detection circuit can monitor the current I L . For example, Figure 2 shows a current sensor 24b, such as a shunt resistor, connected in series with the electronic switch Q2, which thus generates a measurement signal CS indicating the current I L flowing through the inductor L (preferably, proportional thereto) during interval T2.

[0032] Thus, in DCM, control circuit 20 can again use a switching period T SW with a fixed duration, where the on-duration T ON1 = T1 can be varied again via a PID regulator, i.e., the signal DRV1 is a PWM signal with a (fixed or predetermined frequency), and the on-duration / duty cycle is determined according to the output voltage (and the reference signal V REF ). However, when using a controllable electronic switch Q2, control circuit 20 can be configured to turn on the electronic switch Q2 when the signal CS indicates demagnetization of the inductor L.

[0033] Therefore, what the CCM mode and DCM mode of the buck converter have in common is that a PWM signal DRV1 with a fixed frequency can generally be used to drive the electronic switch Q1. Conversely, the optional drive signal DRV2 can be determined according to the drive signal DRV1 and an additional signal CS indicating demagnetization of the inductor L (when operating in DCM).

[0034] In general, a (usually fixed) dead time can also be introduced between the switching drive signals (e.g., between the falling edge of signal DRV1 and the rising edge of signal DRV2 and, similarly (in CCM mode), between the falling edge of signal DRV2 and the rising edge of signal DRV1). Since these intervals are usually short compared to the durations T ON and T OFF , these intervals are no longer considered hereinafter and are not explicitly shown in Figure 3 , Figure 4A and Figure 4B . However, in this case, the drive signal DRV2 can also be determined based on the drive signal DRV1.

[0035] Other electronic converters that often use PWM modulation are, for example, boost converters, buck-boost converters, flyback converters or forward converters, various types of half-bridge converters, etc.

[0036] For example, Figure 5 shows an example of a boost converter. Specifically, in the example considered, an inductor such as inductor L (e.g., directly) is connected between the positive input terminal 200a and the switch node Lx. The switch node Lx is (e.g., directly) connected to the negative input terminal 200b via the current path of the first electronic switch S1, and the negative input terminal 200b is usually (e.g., directly) connected to the negative output terminal 202b. The switch node Lx is also (e.g., directly) connected to the positive output terminal 202a via the current path of the second electronic switch S2. For example, the electronic switches S1 and S2 can be MOSFETs. Usually, the electronic switch S2 can also be implemented using only a diode. Usually, a capacitor such as capacitor Cout is connected between the output terminals 202a and 202b.

[0037] In addition, in this case, the electronic switch S1 can be driven via the PWM signal DRV1, where the duty cycle is determined based on the output voltage V out and the reference voltage V REF . Conversely, when using the controllable electronic switch S2, the electronic switch S2 can be driven via the signal DRV2, which signal DRV2:

[0038] - in CCM, can correspond to the inverted version of the signal DRV1; or

[0039] - in DCM, can be determined based on the signal DRV1 and the signal CS indicating the demagnetization of the inductor L (such as a current measurement signal CS proportional to the current I L flowing through the inductor L).

[0040] In this regard, Figure 6Shows a general electronic converter 20 using a PWM signal DRV with a fixed or predetermined frequency. Specifically, the electronic converter 20 includes a switching stage 26 that is connected between input terminals 200a and 200b and output terminals 202a and 202b. Such a switching stage 26 includes one or more electronic switches SW 26 and at least one inductor L 26 (such as the inductance provided by an inductor or a transformer), and optionally one or more capacitors C 26 (such as capacitors). For example, in a buck converter ( Figure 2 ), these components are switch Q1, switch or diode Q2, inductor L, and capacitor Cout. Conversely, in a boost converter ( Figure 5 ), these components are switch S1, switch or diode S2, inductor L, and capacitor Cout.

[0041] In the example considered, the control circuit 22 includes a driver circuit 222 that is configured to generate one or more drive signals for the switching stage 26 based on the following:

[0042] - The PWM signal DRV, which has a switching period T SW (with a fixed or predetermined period), where the signal DRV is set to a first logic level (e.g., high) within a first duration T ON and is set to a second logic level (e.g., low) within a second duration T OFF , where T SW = T ON + T OFF (see also Figure 7 ); and

[0043] - Optionally, a measurement signal CS, which indicates the demagnetization of the inductor L 26 .

[0044] For example, as previously mentioned, the PWM signal DRV can be used to drive the switch Q1 of Figure 2 and the switch S1 of Figure 5 . Conversely, when the electronic converter operates in the DCM mode, the measurement signal CS can be used, for example, to drive the electronic switch Q2 of Figure 2 or the switch S2 of Figure 5 .

[0045] According to Figure 2 's description, the feedback circuit 24 is typically used to generate a feedback signal FB that indicates the output voltage V out(Preferably, in proportion thereto, e.g., corresponding thereto). Next, a regulator circuit 220 such as a PID regulator can make the duration T of the PWM signal DRV REF vary according to the feedback signal FB and the reference signal V ON .

[0046] For example, as described in U.S. Patent No. 9,091,741B2, such a PID regulator is typically implemented using an error amplifier including an operational amplifier and a feedback network including one or more capacitors and resistors.

[0047] Recently, another type of regulator circuit 220 has been used, where time-based regulation is used to generate the PWM signal DRV. Because this type of control scheme has many advantages, time-based DC-DC converters are becoming increasingly popular. By virtue of the continuous-time digital nature of the time-based regulator, these time-based regulators combine the advantages of traditional analog and digital controller circuits 220. Basically, the time-based regulator operates using (e.g., CMOS-level) digital signals without adding any quantization errors typically found in digital controllers. When deploying simple circuits such as ring oscillators, delay lines, and flip-flops, the time-based regulator circuit 220 eliminates the need for broadband error amplifiers and PWM modules in analog regulator circuits or high-resolution analog-to-digital converters (ADCs) and digital PWM modules in digital voltage regulator circuits. Using time as the processing variable, this new type of control provides an attractive solution for implementing PWM-based electronic converters with wide bandwidth and high switching frequency, as it eliminates the need for broadband amplifiers and high-speed comparators with power and area requirements in traditional PID controllers.

[0048] In view of the foregoing, there is a need in the art to provide a time-based control device for PWM-driven electronic converters such as buck converters or boost converters. SUMMARY OF THE INVENTION

[0049] One or more embodiments relate to a control circuit for an electronic converter. The embodiments also relate to a related integrated circuit, electronic converter, and method.

[0050] As mentioned above, various embodiments of the present disclosure relate to a control circuit for the switching stage of an electronic converter such as a buck converter or a boost converter. In various embodiments, the electronic converter is configured to provide an output voltage via two output terminals.

[0051] In various embodiments, a control circuit includes one or more first terminals configured to provide one or more respective drive signals to one or more electronic switches of a switching stage; a second terminal configured to receive a first feedback signal proportional to an output voltage from a feedback circuit; a third terminal configured to receive a second feedback signal proportional to a derivative of the output voltage from an analog differentiator; and a fourth terminal configured to receive a control signal indicating a requested operating mode from a processing circuit.

[0052] In various embodiments, the control circuit includes a driver circuit configured to generate one or more drive signals based on a pulse width modulation (PWM) signal, wherein the driver circuit is configured to change an operating mode based on the control signal. For example, in various embodiments, the driver circuit is configured to selectively operate the switching stage in discontinuous conduction mode (DCM) or continuous conduction mode (CCM) based on the control signal.

[0053] In various embodiments, the control circuit further includes a PWM signal generator circuit configured to generate a PWM signal based on the first feedback signal, the second feedback signal, and a reference voltage.

[0054] Specifically, in various embodiments, the PWM signal generator circuit includes a first oscillator configured to generate a first clock signal; and a second oscillator configured to generate a second clock signal, wherein at least one of the first oscillator and the second oscillator generates a respective first clock signal and second clock signal having a frequency determined based on the first feedback signal. The PWM signal generator further includes a phase detector having inputs coupled to the first oscillator and the second oscillator and providing the PWM signal at an output. For example, in various embodiments, the first oscillator is a voltage controlled oscillator configured to generate a first clock signal having a frequency determined based on the first feedback signal, and the second oscillator is configured to generate a second clock signal having a frequency determined based on the reference voltage. Conversely, in various embodiments, the first oscillator is a current controlled oscillator configured to generate a first clock signal having a frequency determined based on a first current, and the second oscillator is a current controlled oscillator configured to generate a second clock signal having a frequency determined based on a second current. In this case, an operational transconductance amplifier may be configured to provide the first current and the second current, wherein a difference between the second current and the first current is proportional to a difference between the reference voltage and the first feedback signal.

[0055] Specifically, in various embodiments, the PWM signal generator circuit further includes a first operational transconductance amplifier configured to generate a first current indicative of a difference between a reference voltage and a first feedback signal; and a second operational transconductance amplifier configured to generate a second current indicative of a difference between the reference voltage and a second feedback signal. The current generator is configured to generate a compensation current based on a control signal, and one or more first current-controlled delay lines are connected between the first oscillator and the phase detector and / or one or more second current-controlled delay lines are connected between the second oscillator and the phase detector, wherein the one or more first current-controlled delay lines and / or the one or more second current-controlled delay lines are driven by the first current, the second current, and the compensation current.

[0056] For example, in various embodiments, the PWM signal generator circuit includes a first current-controlled delay line connected between the first oscillator and the phase detector, wherein the delay of the first current-controlled delay is determined based on a corresponding current; and a second current-controlled delay line connected between the second oscillator and the phase detector, wherein the delay of the second current-controlled delay is determined based on a corresponding current.

[0057] In this case, the first operational transconductance amplifier can be a differential operational transconductance amplifier configured to provide the first current and the second current, wherein a difference between the second current and the first current is proportional to the difference between the reference voltage and the first feedback signal. Similarly, the second operational transconductance amplifier can be a differential operational transconductance amplifier configured to provide the first current and the second current, wherein a difference between the second current and the first current is proportional to the difference between the reference voltage and the second feedback signal. Thus, the first summing node can provide a current to the first current-controlled delay by adding the respective first currents provided by the first operational transconductance amplifier and the second operational transconductance amplifier. Conversely, the second summing node can provide a current to the second current-controlled delay by adding the respective second currents provided by the first operational transconductance amplifier and the second operational transconductance amplifier.

[0058] For example, in this case, the compensation current can be subtracted from the first summing node or can be added to the second summing node. Generally, a portion of the compensation current can also be subtracted from the first summing node, and a portion of the compensation current can be added to the second summing node.

[0059] For example, when the control signal indicates DCM operation or CCM operation, when the control signal indicates DCM operation, the compensation current can have a first value, and when the control signal indicates CCM operation, the compensation current can have a second value, wherein the second value is greater than the first value. Description of the Drawings

[0060] Now, embodiments of the present disclosure will be described with reference to the accompanying drawings, which are provided by way of non-limiting examples only, and in which:

[0061] The features and advantages of the present invention will become apparent from the following detailed description of the actual embodiments of the present invention shown by non-limiting examples in the drawings, in which:

[0062] Figure 1 An example of an electronic converter is shown;

[0063] Figure 2 An example of a buck converter is shown;

[0064] Figure 3 Shows Figure 2 Exemplary waveforms of the buck converter of

[0065] Figure 4A Shows Figure 2 Waveforms of the buck converter of when operating in CCM mode;

[0066] Figure 4B Shows Figure 2 Waveforms of the buck converter of when operating in DCM mode;

[0067] Figure 5 An example of a boost converter is shown;

[0068] Figure 6 An example of an electronic converter using a PWM signal is shown;

[0069] Figure 7 Shows Figure 6 An example of the PWM signal of the electronic converter of

[0070] Figure 8 Shows Figure 6 The first embodiment of the control circuit of the electronic converter of

[0071] Figure 9 Shows Figure 8 Exemplary waveforms of the control circuit of

[0072] Figure 10 Waveforms when the electronic converter is operating in CCM mode are shown;

[0073] Figure 11 Shows Figure 6 The second embodiment of the control circuit of the electronic converter of

[0074] Figure 12 Shows Figure 11Exemplary waveforms of the control circuit;

[0075] Figure 13 shows Figure 6 a third embodiment of the control circuit of the electronic converter; and

[0076] Figure 14 shows Figure 6 a fourth embodiment of the control circuit of the electronic converter. Detailed Description

[0077] In the following description, various specific details are set forth in order to provide a thorough understanding of the embodiments. Embodiments may be provided without one or more of the specific details, or in combination with other methods, components, materials, etc. In other instances, well-known structures, materials, or operations are not shown or described in detail so as not to obscure aspects of the embodiments.

[0078] References to "an embodiment" or "one embodiment" in the context of this specification mean that a particular configuration, structure, or characteristic described in connection with the embodiment is included in at least one embodiment. Thus, phrases such as "in an embodiment" or "in one embodiment" that may appear in various aspects of this specification do not necessarily refer to the same embodiment. Moreover, the particular configurations, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

[0079] The references used herein are provided for convenience only and thus do not delimit the scope or boundary of the embodiments.

[0080] In the following description Figures 8 to 14 reference has been made to Figures 1 to 7 portions, elements, or components described previously in these figures are indicated by the same reference numerals as those previously used in these figures. Descriptions of these elements have been made and are not repeated herein so as not to burden this detailed description.

[0081] As previously explained, various embodiments of this specification relate to an improved time-based control circuit 22a for an electronic converter. A general description of an electronic converter using PWM signals is referenced Figures 1 to 7 to the previous description.

[0082] Figure 8 Schematically shows a time-based control circuit 22a in the form of, for example, an integrated circuit. Specifically, in this case, the control circuit 22a further includes:

[0083] - A PWM signal generator 220a configured to generate a PWM signal DRV based on a feedback signal FB that indicates an output voltage V generated by a switching stage 26 of the electronic converterout and a reference voltage V REF ; and

[0084] - a driver circuit 222 configured to drive the switch stage 26 in accordance with the PWM signal DRV.

[0085] Specifically, in the considered embodiment, the PWM signal generator 220a includes:

[0086] - a first voltage-controlled oscillator 2220 configured to generate a first clock signal CLK1 in accordance with the feedback signal FB;

[0087] - an analog differentiator 2222 configured to generate a signal indicative of the derivative of the feedback signal FB (preferably, proportional thereto), e.g., using a capacitor C D and a resistor R D connected in series between the feedback signal FB and a reference voltage (e.g., ground (which may correspond to the negative input terminal 200b or the negative output terminal 202b)), where the intermediate node between the capacitor C D and the resistor R D corresponds to the signal indicative of the derivative of the feedback signal FB;

[0088] - a first delay line 2224 delaying in accordance with the feedback signal FB and a second delay line 2226 delaying in accordance with the signal indicative of the derivative of the feedback signal FB, where the first delay line and the second delay line are cascaded and generate a delayed first clock signal CLK1';

[0089] - a second voltage-controlled oscillator 2228 configured to generate a second clock signal CLK2 in accordance with the reference voltage V REF ; and

[0090] - a phase detector circuit 2230 configured to generate the PWM signal DRV, where the duty cycle of the PWM signal DRV is determined in accordance with the phase difference Φ between the clock signal CLK2 and the delayed clock signal CLK1'.

[0091] Delay lines having programmable delays in accordance with voltage signals or current signals are well known in the art. For example, in this context, U.S. Patent Nos. 5,650,739A or 7,696,799B2 may be cited.

[0092] For example, as Figure 9 shown, the phase detector circuit 2230 may be configured to set the signal DRV high when the second clock signal CLK2 is high and the delayed first clock signal CLK1' is low. For example, the phase detector 2230 may be implemented using one or more logic gates and / or one or more latches.

[0093] Thus, in the embodiments considered, the second voltage controlled oscillator 2228 provides a clock signal CLK2 having a given (fixed or settable) frequency. Conversely, the first voltage controlled oscillator 2220 varies the frequency of the first clock signal CLK1 until the feedback signal FB corresponds to the reference voltage V REF and, in this stable condition, the frequency of the first clock signal CLK1 corresponds to the frequency of the second clock signal CLK2, but with the clock signals phase shifted by a given phase Φ REF . Thus, the first oscillator 2220 implements a regulator having an integral component with phase Φ I . Conversely, the first delay line 2224 and the second delay line 2226 introduce an additional phase Φ I proportional to the feedback signal FB and an additional phase Φ P proportional to the derivative of the feedback signal FB, i.e., the total phase shift Φ corresponds to the following: D

[0094] Φ = Φ I + Φ P + Φ D

[0095] where, as Figure 9 shown, the phase shift Φ is proportional to (preferably, corresponds to) the on-time T ON (e.g., T ON = T SW (Φ / 2π)), i.e., the signal DRV is a PWM signal where the on-time T ON / duty cycle varies according to the feedback signal FB and the reference voltage V REF via time-based control of the phase shift Φ (by PID regulation). Thus, the phase detector 2230 may also perform other operations, such as scaling operations on the frequencies of the clock signals CLK1 / CLK2, and the only thing relevant is that the phase detector 2230 is configured to generate a PWM signal DRV, where the on-time T ON of the signal DRV is determined according to the phase shift Φ.

[0096] The inventors have observed that in many applications, there is a requirement for great flexibility in electronic converters. To maximize efficiency and performance, it is typically required to operate in different modes (e.g., DCM, CCM, asynchronous mode, synchronous mode, optimized for TDMA variations, deterministic / repetitive load / line sudden changes, etc.) and maintain very high performance in different scenarios. Under such conditions, the design of DC-DC converters is quite complex.

[0097] ​As described above, a DC-DC converter is typically a closed-loop system with a certain loop bandwidth. In this regard, the inventors have observed that a feedforward action can be used as an additional "out-of-loop compensation action" that can help compensate for specific events or variabilities. These feedforwards act outside of the main loop and are designed to be very fast and quickly compensate for specific events so that the main loop does not have to be responsible for the input events, which, by definition, are slow and have a limited bandwidth.

[0098] For example, as described above, the control circuit 20a can determine to operate the converter in CCM mode or DCM mode. Thus, the control circuit 20a can use a feedforward action to compensate for the transition between these operating modes, such as from CCM switching to DCM (or vice versa) in a buck DC-DC or boost DC-DC.

[0099] Specifically, at steady state (e.g., constant input voltage Vin and load 30), the control circuit 20a operates the converter at a duty cycle given by the operating conditions. If the control circuit 20a is forced to switch from CCM mode to DCM mode, the duty cycle required to maintain regulation may be different.

[0100] For example, generally, when a smaller load 30 is connected to the output terminals 202a, 202b, the converter should operate in DCM mode. In fact, as Figure 10 shown, when the load decreases, the current I at the end of the interval T2 L may become negative in CCM mode. However, since the switch Q2 will be deactivated at the moment when the current I L becomes negative, when the control circuit is forced to switch from CCM to DCM under this condition (see also Figure 4B ), the negative current is suppressed. Thus, this (absence of negative current) results in an excessive charge transfer to the output capacitor Cout, thereby increasing the output voltage V out . Thus, in the absence of any feedforward action, this transition can be simply managed by the converter loop (feedback circuit 24, PWM signal generator 220a, and driver 222), for example, by:

[0101] 1) The converter is in steady state under CCM,

[0102] 2) Forcing DCM operation,

[0103] 3) Since in DCM, the current I L is not allowed to become negative in the inductor L (contrary to CCM), an excessive charge may be transferred at the output 202a / 202b, thereby increasing the output voltage V out ,

[0104] 4) The control loop (negative feedback) detects this deviation and generates a corrective action, and

[0105] 5) A new steady-state point is reached with the new duty cycle.

[0106] This new duty cycle in DCM is different from (usually less than) the previous duty cycle in CCM. However, as previously mentioned, during this change in the setpoint or operating mode of the converter, the output voltage V out may experience overshoot or undershoot, which are generally not desired.

[0107] Conversely, in the case of a properly designed specific feedforward compensation, when forced to transition from CCM to DCM, the feedforward compensator may turn on, and in the open loop, it may shift the control action to reduce the duty cycle and directly obtain the new duty cycle. In this way, the output voltage V out does not experience any unwanted transients, or at least reduces such transients.

[0108] Figure 11 A second embodiment of the time-based PWM signal generator 220a is shown.

[0109] Specifically, in the considered embodiment, the following modifications have been made, and these modifications can also be used separately:

[0110] - The voltage-controlled oscillator 2220 and / or the delay lines 2224 and 2226 have been replaced with current-controlled oscillators and / or delay lines;

[0111] - The delay lines 2224 and 2226 have been combined into the same delay line 2234;

[0112] - A differential approach is used, where the oscillator 2220 / 2228 and / or the delay lines 2234 / 2235 are driven with differential signals.

[0113] Specifically, in the considered embodiment, the feedback circuit 24 is again used to determine the feedback signal FB proportional to the output voltage V out For example, in various embodiments, the feedback circuit 24 is implemented using a voltage divider 24 that includes two or more resistors R FB1 and R FB2 connected in series between the terminals 202a and 202b, where the voltage V FB2 at one of the resistors (e.g., resistor R FB ) corresponds to the feedback signal FB.

[0114] In the considered embodiment, the feedback signal FB and the reference voltage V REFProvided to a first differential transconductor 2236, such as a differential operational transconductance amplifier (OTA). For example, in various embodiments, the differential transconductor 2236 provides:

[0115] - A first current i I+ = i I0 + i I / 2; and

[0116] - A second current i I- = i I0 - i I / 2.

[0117] Specifically, in the differential transconductor 2236, the difference i I+ between the currents i I- and i I = i I+ – i I- is proportional to the difference between the corresponding input voltages (i.e., the reference voltage V REF and the feedback voltage V FB ), i.e., i I = G MI (V REF - V FB ).

[0118] In the considered embodiment, the current i I+ is provided to the current-controlled oscillator 2228, and the current i I- is provided to the current-controlled oscillator 2220, such as two ring oscillators. Thus, the oscillator 2228 generates a clock signal CLK2 whose frequency is proportional to the current i I+ , and the oscillator 2220 generates a clock signal CLK1 whose frequency is proportional to the current i I- . Therefore, when the feedback voltage V FB corresponds to the reference voltage V REF , both oscillators are supplied with the current i I0 , and this current i I0 thus determines the steady-state frequencies of the clock signals CLK1 and CLK2.

[0119] Similarly, the feedback signal FB and the reference voltage V REF are provided to a second differential transconductor 2238, such as a differential operational transconductance amplifier (OTA). For example, in various embodiments, the differential transconductor 2238 provides:

[0120] - A first current i P+ = i P0 + i P / 2; and

[0121] - A second current i P- = iP0 –i P / 2。

[0122] Specifically, in differential transconductor 2238, the difference i P+ between currents i P- and i P = i P+ –i P- is proportional to the difference between the corresponding input voltages (i.e., reference voltage V REF and feedback voltage V FB ), i.e., i P = G MP (V REF - V FB ).

[0123] In the embodiment under consideration, analog differentiator 2222 is again used to generate a signal V out proportional to the derivative of output voltage V D . For example, in the embodiment under consideration, analog differentiator 2222 is implemented using a capacitor C out connected between output voltage V REF or feedback signal FB and a reference voltage (such as ground, or preferably, reference voltage V D ) and a resistor R D . For example, when resistor R D is connected to reference voltage V REF , the offset of derivative signal V D is V REF , and the derivative component of output voltage V out is added to this offset.

[0124] In the embodiment under consideration, derivative signal V D (e.g., the voltage at the intermediate node between capacitor C D and resistor R D ) and reference voltage V REF are provided to a third differential transconductor 2240, such as a differential operational transconductance amplifier (OTA). For example, in various embodiments, differential transconductor 2240 provides:

[0125] - A first current i D+ = i D0 + i D / 2; and

[0126] - A second current i D- = i D0 –i D / 2.

[0127] Specifically, in differential transconductor 2240, current i D+and i D- The difference i D = i D+ – i D- is proportional to the difference from the corresponding input voltage (i.e., the reference voltage V REF and the derivative signal V D ), i.e., i P = G MD (V REF – V D ).

[0128] Similar to the description of Figure 7 , the current i P+ and i D+ and / or the current i P- and i D- can be provided to the corresponding delay lines, such as:

[0129] - Two delay lines connected in series (substantially corresponding to delay lines 2224 and 2226) can be configured to generate a delayed version CLK1' of the clock signal CLK1 according to the currents i P- and i D- respectively; and / or

[0130] - Two delay lines connected in series can be configured to generate a delayed version CLK2' of the clock signal CLK2 according to the currents i P+ and i D+ .

[0131] Generally, the term "and / or" highlights the possibility that these delay lines can be provided for each clock signal (as shown in Figure 11 , the differential path) or only for a single clock signal (as shown in Figure 8 ).

[0132] Conversely, in the considered embodiment, the currents i P+ and i D+ are provided to the first summing node, which provides the current I R = i P+ + i D+ , and / or the currents i P- and i D- are provided to the second summing node, which provides the current I F = i P- + i D- . In the considered embodiment, the current I R is provided to the delay line 2235 and / or the current I F is provided to the delay line 2234, such as having a sequence of delay stages according to the corresponding supply current (i.e., the currents I F and I R ).

[0133] Thus, in the embodiment under consideration and as also Figure 12 shown, delay stage 2235 generates a delayed clock signal CLK2' having a delay t with respect to clock signal CLK2 and / or delay stage 2235 generates a delayed clock signal CLK1' having a delay t with respect to clock signal CLK1. d2 d1

[0134] Then, in the embodiment under consideration, the delayed clock signals CLK2' and CLK1' are provided to a phase detector configured to, for example:

[0135] - set signal DRV to a first logic level (e.g., high) at the rising edge of CLK2'; and

[0136] - set signal DRV to a second logic level (e.g., low) at the rising edge of signal CLK1'.

[0137] Thus, in the embodiment under consideration, in steady state, feedback signal V FB corresponds to reference voltage V REF , and by connecting an analog differentiator to reference voltage V REF , signal V D also corresponds to reference voltage V REF . Thus, in steady state, differential currents i D , i P and i I are zero, and (when using a differential path) the delay t d1 of delay line 2234 corresponds to the delay t d2 of delay line 2235. Moreover, oscillators 2220 and 2228 provide two clock signals CLK1 and CLK2 having the same frequency and phase shift Φ I . Due to the fact that delay lines 2234 and 2235 introduce the same delay t d1 = t d2 in the embodiment under consideration, the phase shift Φ between delayed clock signals CLK1' and CLK2' corresponds to Φ I , e.g., duration T ON corresponds to (or is proportional to) delay Φ I (e.g., T ON = T SW (Φ I / 2π)). Thus, the duty cycle D of signal DRV = T ON / T SW and thus corresponds to Φ I ​​corresponds to / 2π. For example, in a buck converter, the duty cycle can be determined (approximately) based on the input and output voltages (i.e., D = Φ I / 2π = V out / V in ).

[0138] As previously mentioned, it is also possible to use only one of the delay lines 2234 or 2235, or one of the delay lines may introduce a constant delay, i.e., a delay t d1 or t d2 wherein one of the delays can be zero or at least constant. In fact, in such a case, the oscillators 2220 and 2228 may generate clock signals with a phase shift Φ I which also compensates for the constant delay t d1 or t d2 .

[0139] Therefore, when analyzing the delay t d1 or t d2 , it can be observed that:

[0140] - When the delay t d1 increases (and the delay t d2 remains constant or decreases), the on-time T ON / duty cycle D immediately increases, and

[0141] - When the delay t d2 increases (and the delay t d1 remains constant or decreases), the on-time T ON / duty cycle D immediately decreases.

[0142] Therefore, the inventors have observed that the switching of the duty cycle of the signal DRV (e.g., due to a change in operating conditions) can be obtained by changing the delay t d1 of the delay line 2234 and / or the delay t d2 of the delay line 2235.

[0143] For example, when using the current-controlled delay lines 2234 and / or 2235, the delay t d1 and / or t d2 can be modified by changing the bias current I F and / or I R of the delay line.

[0144] For example, Figure 13 shows an embodiment in which the PWM signal generator circuit 22a includes a current source 2242 configured to provide a variable current I* (determined based on a feedforward action), the variable current I* being added to the current supplied to the delay line 2235, i.e., IR = i P+ + i D+ + I*. However, as previously mentioned, a sign opposite to that of the delay line 2234 can be provided for the current I*, i.e., I F = i P- + i D- - I*, or a given contribution (with opposite signs) can be provided to the two delay lines 2234 and 2235, e.g., I R = i P+ + i D+ + I* / 2, and I F = i P- + i D- - I* / 2.

[0145] The amount of the current I* depends on different factors starting from the gain K of the current control delay lines 2234 and / or 2235, the phenomenon / event to be compensated, and the operating conditions of the DC-DC converter.

[0146] For example, considering an example of a feedforward action for compensating the CCM / DCM transition, the feedforward current I* can be determined as follows. For example, assume regarding Figure 5 the boost converter described, where the driver circuit 26 is configured to drive the electronic switches S1 and S2 to operate the converter in CCM or DCM. For example, when the load 30 is high, CCM can be used, while when the load decreases, DCM can be used. The dynamic transition between such operating modes should be seamless at the output voltage.

[0147] For example, as previously mentioned, the drive signal DRV1 can correspond to the PWM signal DRV. Also, in CCM, the drive signal DRV2 can correspond to a complementary version (possibly with an additional dead time) of the PWM signal DRV. Conversely, in DCM, when the PWM signal DRV goes low (possibly with an additional dead time), the drive signal DRV2 can be set high, while when the signal CS indicates that the current I L reaches zero / demagnetization of the inductor L, the drive signal DRV2 can be set low.

[0148] For example, to determine whether to use CCM or DCM, the control circuit 20a can be configured to monitor, for example, the output current i out or the current I L in terms of its peak or average value. For example, assume the control circuit 20a is configured to use:

[0149] - CCM when the verification operation indicates that the output current i out is greater than a given threshold (e.g., 100 mA); and

[0150] - When the verification operation indicates that the output current i out is less than a given threshold (e.g., 100 mA) (hysteresis operation may also be used), DCM.

[0151] For example, based on the input voltage V in and the output voltage V out values and the characteristics of the converter, the frequency of the PWM signal DRV can be 1.5 MHz, and

[0152] - In CCM (100 mA), the on - duration T ON is 95 ns; and

[0153] - In DCM (100 mA), the on - time T ON is 65 ns.

[0154] Thus, when switching from CCM to DCM, the on - time T ON should be reduced by 30 ns, that is, the current generator 2242 should provide the current I*, and this current I* is, for example:

[0155] - Reduce the delay t d1 by 30 ns, that is, increase the current I F ;

[0156] - Increase the delay t d2 by 30 ns, that is, decrease the current I R ; or

[0157] - Generally, reduce the delay t d1 by the time t1 and increase the delay t d2 by the time t2, where t1 + t2 = 30 ns.

[0158] For example, assume that the gain is K = 100 ns / μA and the current - controlled delay lines 2234 and 2235 in the steady state use a current I F = I R = i D0 + i P0 bias, then the current I* can be calculated as follows:

[0159] I* = (-30 ns) / (100 ns / μA) = -0.3 μA

[0160] Generally, the current can be applied to the delay lines 2234 and 2235 in a given ratio k (where 0 ≤ k ≤ 1 (e.g., k = 0.5)), that is:

[0161] I R = i P+ + i D+ + k·I*.

[0162] I F = i P- + i D- -(1 - k)·I*.

[0163] Therefore, due to the fact that I* is negative, the current I R will decrease, thereby increasing the value t d2 , and / or the current I F will increase, thereby decreasing the value t d1 . Generally, when switching from DCM to CCM, the current I* must be removed again.

[0164] Thus, as Figure 14 shown, in various embodiments, the control circuit 20a may further include a (digital and / or analog) processing circuit 2246 configured to monitor one or more operating parameters of the switching stage 26 and determine whether to activate a given operating mode of the driver circuit 222, such as the DCM mode or the CCM mode. For example, in Figure 14 , the processing circuit 2246 monitors the measurement signal CS. Next, the processing circuit 2246 generates one or more control signals CTRL for the driver circuit 222, for example, in order to activate the DCM mode or the CCM mode. Similarly, the processing circuit 2246 provides one or more control signals CTRL (which may also correspond to the previously mentioned control signals of the driver circuit 222) in order to select a given compensation current I*. For example, when only the DCM mode and the CCM mode are supported, the control circuit 20a may be configured to provide the current I* in the DCM mode and not provide the current I* in the CCM mode, which is schematically shown by an electronic switch 2244 between the current generator 2242 and the delay line 2235, and this electronic switch 2244 closes when the DCM mode is activated and opens when the CCM mode is activated.

[0165] Therefore, the proposed solution allows for feedforward control to overcome specific phenomena / events that maintain high performance. The impact of the proposed solution on power consumption is negligible because it only includes: generating an appropriate current that powers (or draws from) the input of the delay lines 2234 and / or 2235.

[0166] In terms of system complexity and area consumption, without the proposed feedforward compensation, the differences in implementation are negligible, and the advantages overcome this minor increase in complexity. Ultimately, it only requires minimal logic to trigger the feedforward in response to the phenomenon to be compensated, and for example, a current generator 2242 implemented using a current mirror to create an appropriate feedforward current I*.

[0167] Generally speaking, the proposed feedforward implementation allows for more than one feedforward operation, independent of other feedforwards (i.e., the presence of a particular feedforward does not prevent / weaken the operation of another feedforward), for example, because multiple feedforward currents I* can be summed up.

[0168] As previously mentioned, in various embodiments, the control circuit 20a can also be integrated in an integrated circuit. In this case, the integrated circuit can include:

[0169] - Terminals for connection to the feedback circuit 24, which can also be integrated in the same integrated circuit;

[0170] - Terminals for connection to the analog differentiator 2222, which can also be integrated in the same integrated circuit;

[0171] - One or more terminals for providing one or more corresponding drive signals to the switch stage 26 of the electronic converter, where one or more of the switches in the switch stage 26 can also be integrated in the integrated circuit;

[0172] - Terminals for receiving at least one control signal CTRL from the control circuit 2246, which can also be integrated in the same integrated circuit;

[0173] - A driver circuit 222, configured to generate one or more drive signals according to the PWM signal DRV, where the driver circuit 222 is configured to change the operation mode according to the control signal CTRL; and

[0174] - A PWM signal generator circuit 220a, configured to generate the PWM signal DRV, where the PWM signal generator circuit 220a includes at least one current-controlled delay line 2234 and / or 2235 (or equally, 2224 or 2226), where the corresponding control current (I F and / or I R ) changes (substantially instantaneously) according to the control signal CTRL.

[0175] Of course, without prejudice to the principles of the present invention, according to the definitions of the following claims, the construction details and embodiments can vary widely relative to what has been described and illustrated herein only by way of example, without thereby departing from the scope of the present invention.

[0176] For example, in various embodiments, current-controlled delay lines can be used to implement the delay lines 2234 and 2235, while the oscillators 2220 and 2228 can be voltage-controlled oscillators as shown in Figure 8 or as shown in Figure 11The current-controlled oscillator shown. In fact, in both cases, at least the frequency of oscillator 2220 is determined according to the feedback signal FB. For example, a (constant) bias current i can also be supplied to oscillator 2228 I0 , and only a variable current i can be supplied to oscillator 2220 I- . Alternatively, a (constant) bias current i can also be supplied to oscillator 2220 I0 , and only a variable current i can be supplied to oscillator 2228 I+ .

[0177] Moreover, when using single-ended transconductance amplifiers 2238 and 2240, the corresponding currents i P 、i D and the compensation current I* (each with a corresponding offset bias current) can be provided to delay lines 2234 and / or 2235 in any suitable combination, which can also be implemented by a series of individual delay lines driven by the corresponding current or combination of currents, for example:

[0178] - The currents i P 、i D and I* can be provided to delay line 2234, such as a first delay line, a second delay line, and a third delay line that respectively receive the currents i P 、i D and I*, and delay line 2235 can be omitted;

[0179] - The currents i P 、i D can be provided to delay line 2234, and the compensation current I* can be provided to delay line 2236.

[0180] Thus, in various embodiments, one or more first delay lines 2234 are connected between oscillator 2220 and phase detector 2230, and / or one or more second delay lines 2235 are connected between oscillator 2228 and phase detector 2230, where one or more first delay lines 2234 and / or one or more second delay lines 2235 are driven via the currents i P 、i D and I*.

[0181] The claims form part of the technical teachings of the description provided herein.

Claims

1. A control circuit for a switching stage of an electronic converter, the electronic converter being configured to provide an output voltage, the control circuit comprising: A first terminal configured to provide a drive signal to an electronic switch of the switching stage; A second terminal configured to receive a first feedback signal proportional to the output voltage; A third terminal configured to receive a second feedback signal proportional to the derivative of the output voltage; A phase detector circuit configured to generate the drive signal in response to a phase difference between a first clock signal and a second clock signal; A first oscillator circuit configured to generate the first clock signal, the first clock signal having a frequency determined according to the first feedback signal; And A first controlled delay line connected between the first oscillator and a first input of the phase detector, the first controlled delay line being configured to apply a delay to the first clock signal in response to a combination of the first feedback signal, the second feedback signal, and a compensation signal indicating a requested operating mode of the electronic converter.

2. The control circuit according to claim 1, wherein the drive signal is pulse-width modulated PWM.

3. The control circuit according to claim 1, further comprising a second oscillator circuit configured to generate the second clock signal, the second clock signal having a frequency determined according to a reference voltage.

4. The control circuit according to claim 1, further comprising a second oscillator circuit configured to generate the second clock signal, the second clock signal having a frequency determined according to the first feedback signal.

5. The control circuit according to claim 4, further comprising a differential amplifier circuit configured to generate a differential signal in response to a comparison of the first feedback signal with a reference voltage, and wherein a first current output and a second current output of the differential signal are applied to control the frequencies of the first oscillator circuit and the second oscillator circuit, respectively.

6. The control circuit according to claim 4, further comprising a second controlled delay line connected between the second oscillator and a second input of the phase detector, the second controlled delay line being configured to apply a delay to the second clock signal in response to a combination of the first feedback signal, the second feedback signal, and the compensation signal.

7. The control circuit according to claim 6, further comprising: A first differential amplifier circuit configured to generate a first differential signal in response to a comparison of the first feedback signal with a reference voltage, and wherein a first output and a second output of the first differential signal are applied to control the delays of the first controlled delay line and the second controlled delay line, respectively.

8. The control circuit according to claim 7, further comprising: A second differential amplifier circuit, configured to generate a second differential signal in response to a comparison of the second feedback signal with a reference voltage, and wherein a first output and a second output of the second differential signal are applied to control the delays of the first controlled delay line and the second controlled delay line, respectively.

9. The control circuit according to claim 8, wherein the compensation signal includes a differential compensation signal, and wherein a first output and a second output of the differential compensation signal are applied to control the delays of the first controlled delay line and the second controlled delay line, respectively.

10. The control circuit according to claim 6, further comprising: A second differential amplifier circuit, configured to generate a second differential signal in response to a comparison of the second feedback signal with a reference voltage, and wherein a first output and a second output of the second differential signal are applied to control the delays of the first controlled delay line and the second controlled delay line, respectively.

11. The control circuit according to claim 10, wherein the compensation signal includes a differential compensation signal, and wherein a first output and a second output of the differential compensation signal are applied to control the delays of the first controlled delay line and the second controlled delay line, respectively.

12. The control circuit according to claim 1, further comprising a driver circuit configured to operate the switch stage in a continuous conduction mode (CCM) or a discontinuous conduction mode (DCM) selectively according to the requested operating mode.

13. The control circuit according to claim 12, wherein when the requested operating mode indicates DCM operation, the compensation signal has a first value, and when the requested operating mode indicates CCM operation, the compensation signal has a second value, and the second value is greater than the first value.

14. The control circuit according to claim 1, wherein the electronic converter is a buck converter or a boost converter.

15. The control circuit according to claim 1, further comprising one or more electronic switches of the switch stage.

16. The control circuit according to claim 1, further comprising a feedback circuit configured to generate the first feedback signal.

17. The control circuit according to claim 1, further comprising an analog differentiator configured to generate the second feedback signal based on the first feedback signal.

18. An integrated circuit comprising the control circuit according to claim 1.

19. An electronic converter, comprising: A switch stage, and The control circuit according to claim 1.

20. A control circuit for a switch stage of an electronic converter, the electronic converter being configured to provide an output voltage, the control circuit comprising: One or more first terminals configured to provide one or more drive signals to one or more electronic switches of the switch stage, respectively; A second terminal configured to receive a first feedback signal proportional to the output voltage from a feedback circuit; A third terminal configured to receive a second feedback signal proportional to the derivative of the output voltage from an analog differentiator; A fourth terminal configured to receive a control signal indicating a requested operating mode from a processing circuit; A driver circuit configured to generate the one or more drive signals based on a pulse width modulation (PWM) signal, wherein the driver circuit is configured to change an operating mode based on the control signal; And A PWM signal generator circuit configured to generate the PWM signal based on the first feedback signal, the second feedback signal, and a reference voltage, wherein the PWM signal generator circuit includes: A first oscillator configured to generate a first clock signal; A second oscillator configured to generate a second clock signal, wherein a frequency of at least one of the first clock signal and the second clock signal is determined based on the first feedback signal; A first operational transconductance amplifier configured to generate a first current indicative of a difference between the reference voltage and the first feedback signal; A second operational transconductance amplifier configured to generate a second current indicative of a difference between the reference voltage and the second feedback signal; A current generator configured to generate a compensation current based on the control signal; A phase detector providing the PWM signal at an output; One or more first current-controlled delay lines connected between the first oscillator and a first input of the phase detector; and One or more second current-controlled delay lines connected between the second oscillator and a second input of the phase detector; wherein a delay of the first clock signal provided by the one or more first current-controlled delay lines and a delay of the second clock signal provided by the one or more second current-controlled delay lines are controlled by the first current, the second current, and the compensation current, and wherein the phase detector generates the PWM signal based on a phase difference between the delayed first clock signal and the delayed second clock signal.

21. The control circuit according to claim 20, wherein the first oscillator is a voltage-controlled oscillator configured to generate the first clock signal having a frequency determined based on the first feedback signal, and wherein the second oscillator is configured to generate the second clock signal having a frequency determined based on a reference voltage.

22. The control circuit according to claim 20, wherein the first oscillator is a current-controlled oscillator configured to generate the first clock signal having a frequency determined based on a third current, and wherein the second oscillator is a current-controlled oscillator configured to generate the second clock signal having a frequency determined based on a fourth current, and wherein the control circuit includes: A third operational transconductance amplifier configured to provide the third current and the fourth current, wherein a difference between the third current and the fourth current is proportional to a difference between a reference voltage and the first feedback signal.

23. The control circuit according to claim 20, wherein: The one or more first current-controlled delay lines include a first current-controlled delay line having a delay determined according to a fifth current; and The one or more second current-controlled delay lines include a second current-controlled delay line having a delay determined according to a sixth current.

24. The control circuit according to claim 23, wherein the first operational transconductance amplifier is a differential operational transconductance amplifier configured to provide a seventh current and an eighth current, wherein the difference between the seventh current and the eighth current is proportional to the difference between a reference voltage and the first feedback signal; wherein the second operational transconductance amplifier is a differential operational transconductance amplifier configured to provide a ninth current and a tenth current, wherein the difference between the ninth current and the tenth current is proportional to the difference between the reference voltage and the second feedback signal; and wherein the control circuit further comprises: a first summing node that provides the fifth current by adding the seventh current and the ninth current; and a second summing node that provides the sixth current by adding the eighth current and the tenth current.

25. The control circuit according to claim 24, wherein the compensation current is subtracted from the first summing node.

26. The control circuit according to claim 24, wherein the compensation current is added to the second summing node.

27. The control circuit according to claim 24, wherein a part of the compensation current is subtracted from the first summing node and a part of the compensation current is added to the second summing node.

28. The control circuit according to claim 20, wherein the driver circuit is configured to operate the switch stage selectively in continuous conduction mode CCM or discontinuous conduction mode DCM according to the control signal.

29. The control circuit according to claim 28, wherein the compensation current has a first value when the control signal indicates DCM operation and a second value when the control signal indicates CCM operation, wherein the second value is greater than the first value.

30. The control circuit according to claim 20, wherein the electronic converter is a buck converter or a boost converter.

31. The control circuit according to claim 20, further comprising the one or more electronic switches of the switch stage.

32. The control circuit according to claim 20, further comprising the feedback circuit.

33. The control circuit according to claim 20, further comprising the analog differentiator.

34. The control circuit according to claim 20, further comprising the processing circuit.

35. An integrated circuit comprising the control circuit according to claim 20.

36. An electronic converter comprising: a switch stage, and the control circuit according to claim 20.

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