An inter-stage matching circuit with high flatness

Abstract

This invention belongs to the field of microelectronics technology, specifically a high-flatness interstage matching circuit. The interstage matching circuit of this invention includes a transformer, an output equivalent parallel RC circuit, and an input equivalent series RC circuit; wherein, the output terminal of the first stage is equivalent to a parallel RC structure, and the primary circuit is a parallel resonant network; the input terminal of the second stage is equivalent to a series RC structure, and the secondary circuit is a series resonant network; through a broadband passive interstage matching circuit, the gain of the transistor's amplitude-frequency response curve decreases with frequency, thereby achieving a broadband amplitude-frequency response curve for the entire circuit module. This invention, through asymmetric matching circuit design, compensates for the non-flat amplitude-frequency response curve of the transistor itself, achieving a high-flatness circuit design.

Description

Technical Field

[0001] This invention belongs to the field of microelectronics technology, specifically relating to high flatness interstage matching circuits. Background Technology

[0002] In recent years, the rapid development of modern wireless communication technology has greatly changed people's lives. Smartphones and laptops supporting 2G / 3G / 4G mobile communication networks (GSM / WCDMA / LTE) and Wireless Local Area Networks (WLANs) have long been standard equipment in people's daily lives. The arrival of the 5G era has made life even more convenient. To make people's lives more convenient and efficient, the Internet of Things (IoT) is also booming. The Internet of Things (IoT) refers to the use of various information sensors, radio frequency identification (RFID) technology, global positioning systems (GPS), infrared sensors, laser scanners, and other devices and technologies to collect real-time information on any object or process that needs to be monitored, connected, or interacted with. This information includes sound, light, heat, electricity, mechanics, chemistry, biology, location, and other necessary data. Through various possible network access methods, ubiquitous connections between things and between things and people are achieved, enabling intelligent perception, identification, and management of objects and processes.

[0003] The main application scenarios of the Internet of Things (IoT) include smart homes, smart public facilities, smart industry and agriculture, and smart individuals. The communication function of the IoT relies heavily on radio frequency (RF) / millimeter-wave transceivers. Located at the forefront of wireless communication terminals, the structure and performance of RF / millimeter-wave transceivers directly impact the entire communication system. To meet the broadband communication requirements of the IoT, RF / millimeter-wave transceivers also need to possess broadband transmission and reception capabilities.

[0004] Because the amplitude-frequency response curve of a transistor decreases significantly with increasing frequency, broadband implementation in RF / millimeter-wave transceivers requires special topology design to meet broadband transceiver requirements. Common broadband implementation methods have three design perspectives: one is based on the active transistor topology itself, employing a common-gate or common-source structure with gate-drain resistance negative feedback, such as... Figure 1 As shown in (a) and (b), one approach achieves broadband gain; another is a passive matching network design, which uses a broadband passive matching network compensation method to achieve broadband, as shown in (a) and (b). Figure 1 As shown in (c); another design utilizes both active and passive technologies, employing multi-level modules and multiple resonant frequency points to achieve a broadband design, such as... Figure 1 As shown in (d).

[0005] When a circuit module requires high gain or other specifications, a multi-stage cascaded design is often necessary to achieve the required performance. A common method for broadband design of multi-stage cascaded modules is to use multiple resonant points to achieve broadband gain. This involves having each matching network resonate at a different frequency, and then superimposing multiple matching networks to achieve a broadband and flat gain. However, this method requires a large number of cascaded circuits. Since the input and output matching networks need to consider input and output matching, this topology requires at least three cascaded stages to achieve broadband design. This topology is unsuitable when the circuit has only two cascaded stages and one inter-stage matching network. To address this technical problem, this invention adopts a design approach based on passive matching network design. It designs a highly flat broadband inter-stage matching network. This broadband passive inter-stage matching network compensates for the tendency of the transistor's gain to decrease with frequency in its amplitude-frequency response curve, thereby achieving a broadband amplitude-frequency response curve for the entire circuit module. Summary of the Invention

[0006] The purpose of this invention is to provide an interstage matching circuit with high flatness to solve the problem that the amplitude-frequency response curve of the transistor itself decreases with increasing frequency in the RF / millimeter-wave broadband band due to the presence of capacitance, making it impossible to achieve broadband circuitry.

[0007] The high-flatness interstage matching circuit provided by the present invention includes an output equivalent parallel RC circuit (represented by resistor R1 and capacitor C1) 110, a transformer 120, and an input equivalent series RC circuit (represented by resistor R2 and capacitor C2) 130; wherein, the output equivalent parallel RC circuit 110 is the output equivalent circuit of the previous stage, represented by a parallel RC structure; the transformer 120 is used to realize impedance transformation; and the input equivalent series RC circuit 130 is the equivalent circuit of the next stage, represented by a series RC structure.

[0008] The interstage matching circuit is implemented through an asymmetrical parallel-series transformer. That is, the output terminal of the first stage is equivalent to a parallel RC structure with a primary circuit of parallel resonant network, and the input terminal of the second stage is equivalent to a series RC structure with a secondary circuit of series resonant network.

[0009] This invention utilizes a broadband passive interstage matching circuit to compensate for the decreasing gain of the transistor's amplitude-frequency response curve with frequency, thereby achieving a broadband amplitude-frequency response curve for the entire circuit module. Specific details are as follows:

[0010] In this invention, the primary circuit (L1) and the secondary circuit (L2) are asymmetrical parallel-series circuits. The two circuits have the same resonant frequency, but their Q values ​​are different.

[0011] The inductance value of the primary circuit of transformer 120 is determined by the resistance and capacitance values ​​in the equivalent parallel RC circuit 110 of the previous stage output, and the designed bandwidth. Similarly, the coupling coefficient k of transformer 120 is obtained based on the resistance and capacitance values ​​in the equivalent parallel RC circuit 110 of the previous stage output, and the designed bandwidth. The inductance value of the secondary circuit of transformer 120 is selected based on the resonant frequency of the primary circuit and the equivalent capacitance value in the equivalent series RC circuit 130. The primary and secondary circuits resonate at the same frequency, i.e.:

[0012] L1C1=L2C2, (1)

[0013] The equivalent resistance value of the input equivalent series RC circuit 130 in the secondary circuit is determined by the ratio between the Q value of the primary circuit and the Q value of the secondary circuit, that is:

[0014]

[0015] Where Q1 and Q2 are the Q values ​​of the primary and secondary circuits, respectively. Adjusting Q... percent That is, adjusting the equivalent resistance value of the input equivalent series RC circuit 130. When Q percent When = 1, the Z21 curve of the inter-level matching network is Figure 3 As shown, the interstage matching network can achieve a wideband and flat gain curve. However, since the transistor's amplitude-frequency response curve tends to decrease with increasing frequency, Q is used... percent =1 The overall circuit designed using this approach is still non-flat and narrow-band, such as Figure 6 China Q percent The curve is shown as =1.

[0016] Q of the primary and secondary circuits percent ≠1. Adjust Q in the primary and secondary circuits. percent When Q percent From 1 to 0.25, the Z21 curve is as follows: Figure 4 As shown, with Q percent As the frequency decreases, the curve of loop Z21 changes to one that increases with increasing frequency. Therefore, a reasonable selection of Q is necessary. percent This can compensate for the decreasing amplitude-frequency response curve of the transistor as the frequency increases, thereby achieving a wide and flat gain for the overall circuit, such as... Figure 6 China Q percent The curve is shown as 0.1.

[0017] Furthermore, the interstage matching circuit can be implemented using an on-chip transformer or an off-chip transformer.

[0018] Furthermore, the highly flat interstage matching circuit design method can be applied to RF circuits, millimeter-wave circuits, transmitter PAs, receiver LNAs, and other multi-stage cascaded circuits, including but not limited to the applications listed above.

[0019] Furthermore, the highly flat interstage matching circuit design method can be implemented in CMOS, BiCMOS, GeSi, and GaAs processes, including but not limited to the listed processes; other processes are also possible.

[0020] This invention employs a highly flat interstage matching circuit design method, adopting a design approach based on passive matching network design. It designs a highly flat broadband interstage matching network and compensates for the decreasing gain of the transistor's amplitude-frequency response curve with frequency by using a transformer in the Q-asymmetric primary and secondary circuits, thereby achieving a broadband amplitude-frequency response curve for the entire circuit module.

[0021] Compared with the prior art, the significant advantages of this invention are:

[0022] Traditional broadband design of multi-stage cascaded modules commonly employs multiple resonant points to achieve broadband gain. This involves having each matching network resonate at a different frequency, with multiple matching networks superimposed to result in a broadband and flat gain. However, this method requires a large number of cascaded circuits. Due to input and output matching issues, this topology requires at least three cascaded stages to achieve broadband design. This topology is unsuitable when the circuit has only two cascaded stages and one interstage matching network. The high-flatness broadband interstage matching network used in this invention is suitable for two-stage cascaded amplifiers. Through a broadband passive interstage matching network, the gain of the transistor's amplitude-frequency response curve decreases with frequency, thereby achieving a broadband amplitude-frequency response curve for the entire circuit module. Attached Figure Description

[0023] Figure 1 Broadband circuit implementation methods.

[0024] Figure 2 : A schematic diagram of a high-flatness interstage matching circuit structure.

[0025] Figure 3 Q percent The curve of the interstage matching circuit Z21(dBohm) when = 1.

[0026] Figure 4 Different Q percent The curve of the interstage matching circuit Z21(dBohm).

[0027] Figure 5 : A schematic diagram of an implementation method of the present invention based on LNA.

[0028] Figure 6 : Overall circuit Z21(dBohm) curve. Detailed Implementation

[0029] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0030] This invention proposes a high-flatness interstage matching circuit design method. By using a transformer in the Q-asymmetric primary and secondary circuits, the gain of the transistor's amplitude-frequency response curve decreases with frequency, thereby achieving a wide amplitude-frequency response curve for the entire circuit module.

[0031] like Figure 2 As shown, a high-flatness interstage matching circuit of the present invention includes: an output equivalent parallel RC circuit 110, a transformer 120, and an input equivalent series RC circuit 130; wherein the output equivalent parallel RC circuit 110 is the output equivalent circuit of the previous stage, represented by a parallel RC structure; the transformer 120 is used to realize impedance transformation; and the input equivalent series RC circuit 130 is the equivalent circuit of the next stage, represented by a series RC structure. To compensate for the tendency of the gain of the transistor's amplitude-frequency response curve to decrease with frequency, the interstage matching network adopts a Q-asymmetric primary-secondary loop, generating an interstage matching network whose amplitude-frequency response curve increases with frequency. A reasonable selection of Q... percent This allows the entire circuit to achieve a flat gain curve across the entire bandwidth.

[0032] As can be seen from the above, the present invention designs a highly flat interstage matching circuit using a design approach based on passive matching network design. This approach creates a highly flat broadband interstage matching network and compensates for the decreasing gain of the transistor's amplitude-frequency response curve with frequency by using a transformer in the Q-asymmetric primary and secondary circuits. This results in a broadband amplitude-frequency response curve for the entire circuit module.

[0033] like Figure 5 The diagram illustrates a specific implementation example of the high flatness interstage matching circuit based on an LNA according to the present invention, which is applied to an LNA in an RF / millimeter-wave receiver. The input matching network 210 includes a first common-source NMOS transistor M1 and a first source negative feedback inductor L... s1This is a specific implementation of the output equivalent parallel RC circuit 110, wherein the gate terminal of the first common-source NMOS transistor M1 is connected to the inductor L of the input matching network. g Connected for signal input; the source terminal of the first common-source NMOS transistor M1 is connected to the first source negative feedback inductor L. s1 The circuit is connected to generate an equivalent real part of the input impedance for input matching; the drain of the first common-source NMOS transistor M1 is connected to the interstage matching transformer 220 for signal output and wideband interstage matching. In the input matching network, the parallel inductor L4 and capacitor C1 are connected in parallel, with one end connected to the signal input terminal for input matching and the other end connected to ground; the gate inductor L... g For input matching, the signal input terminal is connected in series with the gate terminal of the first common-source NMOS transistor M1 to form a signal path. The impedance from the drain terminal of the first common-source NMOS transistor M1 to the RFi terminal can be equivalent to a parallel RC circuit over a wide bandwidth, i.e., the output is equivalent to R1 and C1 in 110.

[0034] Interstage matching transformer 220 is a specific implementation of transformer 120, wherein the primary inductance L d1 One end is connected to the drain of the first common-source NMOS transistor M1 for signal transmission, and the other end is connected to the power supply VDD to transmit DC voltage to the drain of the first common-source NMOS transistor M1, providing the correct operating state for the first common-source NMOS transistor M1; the secondary inductor L g2 One end is connected to the gate terminal of the second common-source NMOS transistor M2 for signal transmission, and the other end is connected to the bias voltage V. g The primary circuit is connected to the secondary circuit, providing a DC bias voltage to the second common-source NMOS transistor M1, ensuring it operates at the correct bias point. The transformer employs a Q-asymmetric primary-secondary circuit design, with the primary circuit's resonant frequency equal to the secondary circuit's resonant frequency. The inductance of the primary circuit of the interstage matching transformer 220 is determined by the resistance and capacitance of the equivalent parallel RC circuit viewed from the drain of the first common-source NMOS transistor M1 towards the RFin terminal, and the designed bandwidth. The coupling coefficient k of the interstage matching transformer 220 is also obtained based on the resistance and capacitance of the equivalent parallel RC circuit viewed from the drain of the first common-source NMOS transistor M1 towards the RFin terminal, and the designed bandwidth. The inductance of the secondary circuit of the interstage matching transformer 220 is selected based on the primary circuit's resonant frequency and the equivalent series RLC circuit viewed from the gate of the second common-source NMOS transistor M2 towards the RFout terminal. The primary and secondary circuits resonate at the same frequency.

[0035] Output matching network 230 (second common-source NMOS transistor M2 and second source negative feedback inductor L) s2This describes the specific implementation of the second-stage input equivalent series RC circuit 130. Specifically, the gate terminal of the second common-source NMOS transistor M2 is connected to the secondary inductance L of the inter-stage matching transformer. g2 Connected to achieve signal input; the source terminal of the second common-source NMOS transistor M2 is connected to the second source negative feedback inductor L. s2 Connected to generate the real part of the second-stage input impedance, achieving wideband inter-stage matching; the drain of the second common-source NMOS transistor M2 is connected to the parallel output inductor L of the output matching network. d2 and output capacitor C out Connected to achieve signal output; the output inductance L of the output matching network. d2 The drain of the second common-source NMOS transistor M2 is connected in series with the power supply voltage VDD to provide the correct operating DC power supply for the second common-source NMOS transistor M2; the output capacitor C of the output matching network... out One end is connected to the drain of the second common-source NMOS transistor M2, and the other end is connected to the signal output terminal RFout, used to output the signal while providing DC blocking. The impedance from the gate of the second common-source NMOS transistor M2 to the RFout terminal can be equivalent to a series RLC circuit over a wide bandwidth, where C is the parasitic capacitance between the gate and source of the second common-source NMOS transistor M2. gs2 The value of R is determined by the parasitic capacitance C between the gate and source of the second common-source NMOS transistor M2. gs2 transconductance g m Second source negative feedback inductor L s2 The decision is:

[0036] C2 = C gs2

[0037] R2 = g m L s2 / C gs2

[0038] In addition, there is an equivalent inductance L. s2 Once the size and bias of the second common-source NMOS transistor M2 are fixed, adjust the second negative feedback inductor L. s2 That is, adjust the equivalent resistance R2. Figure 5 The circuit can ultimately be equivalent to Figure 2 As shown. The primary and secondary circuits resonate at the same frequency, that is:

[0039] L1C1=L2C2

[0040] The equivalent resistance value of the input equivalent series RC circuit (130) in the secondary circuit is determined by the ratio between the Q value of the primary circuit and the Q value of the secondary circuit, i.e.

[0041]

[0042] Where Q1 and Q2 are the Q values ​​of the primary and secondary circuits, respectively. Adjusting Q... percent That is, adjusting the equivalent resistance value of the input equivalent series RC circuit (130), which is also the second negative feedback inductor L of the second common-source NMOS transistor M2. s2 .

[0043] In the high-flatness interstage matching network of this invention, due to the inherent tendency of the transistor's amplitude-frequency response curve gain to decrease with frequency, even if a single interstage matching network can achieve a flat gain, i.e., Q... percent Even with a gain of 1, the overall circuit gain remains uneven and narrow-band, such as... Figure 6 China Q percent The curve is shown as 1. To achieve a flat and wide Z21 for the overall circuit, Q is adjusted. percent By selecting an appropriate value, the overall circuit gain can have a flat and wide-bandgap curve. In this specific implementation method, Q is selected. percent =0.1, Z21 of the overall circuit is as follows Figure 6 China Q percent As shown in the curve with a gain of 0.1, a flat and wide gain curve is achieved, with a gain ripple of less than 0.5dB.

[0044] The workflow of the entire LNA-based high flatness inter-stage matching circuit design method is as follows:

[0045] As shown in Figure 5, the signal is input from the RFI terminal, passes through a wideband input matching network to generate a wideband input match, and is output to the gate terminal of the first common-source NMOS transistor M1. After signal amplification, the signal outputs from the drain terminal of the first common-source NMOS transistor M1 to the interstage matching network. Since the gain of the transistor's amplitude-frequency response curve decreases with frequency, the signal's amplitude-frequency response curve decreases with increasing frequency. The signal, modulated by the input matching network and the first common-source NMOS transistor M1, passes through a Q-asymmetric interstage matching transformer. Because the amplitude-frequency response curve of the Q-asymmetric interstage matching transformer increases with increasing frequency within the frequency band, the signal, after modulation by the input matching network, the first common-source NMOS transistor M1, and the interstage matching transformer, produces an amplitude-frequency response curve that increases with increasing frequency within the frequency band. The modulated signal then passes through the secondary inductor L of the interstage matching network. g2The signal is output to the gate of the second common-source NMOS transistor M2, where it is amplified and modulated. After passing through the output matching network to the output terminal RFout, the signal exhibits a decreasing gain with frequency characteristic of the second common-source NMOS transistor M2. The modulation by M2 and the output matching network results in a wide, flat amplitude-frequency response curve. Therefore, a well-designed Q-asymmetric interstage matching transformer can achieve a highly flat interstage matching circuit, resulting in a wide and flat amplitude-frequency response curve across the entire circuit.

[0046] In summary, this invention proposes a high-flatness interstage matching circuit design method. The asymmetric parallel-series resonant interstage matching circuit design method compensates for the non-flat amplitude-frequency response curve of the transistor itself by using an asymmetric broadband passive matching circuit, thereby achieving a broadband amplitude-frequency response curve in the entire circuit module and realizing a high-flatness circuit design.

[0047] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit it. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the spirit and scope of the technical solutions of the present invention, and all such modifications or substitutions should be covered within the scope of the claims of the present invention.

Claims

1. A high-flatness interstage matching circuit, characterized in that, It includes a transformer (120), an output equivalent parallel RC circuit (110), and an input equivalent series RC circuit (130); wherein, the output equivalent parallel RC circuit (110) is the output equivalent circuit of the previous stage; the transformer (120) is used to realize impedance transformation; the input equivalent series RC circuit (130) is the equivalent circuit of the next stage; wherein: The output terminal of the first stage is equivalent to a parallel RC structure (110), and the primary circuit is a parallel resonant network. The input terminal of the second stage is equivalent to a series RC structure (130), and the secondary circuit is a series resonant network. By using a broadband passive interstage matching circuit, the gain of the transistor's amplitude-frequency response curve decreases with frequency, thereby achieving a broadband amplitude-frequency response curve for the entire circuit module. The compensation transistor itself exhibits a decreasing trend in gain with frequency in its amplitude-frequency response curve, as detailed below: The primary circuit (L1) and the secondary circuit (L2) are asymmetrical parallel and series circuits. The two circuits have the same resonant frequency, but the Q values ​​of the circuits are different. The inductance of the primary circuit of transformer (120) is determined by the resistance and capacitance values ​​in the equivalent parallel RC circuit (110) of the previous stage output and the designed bandwidth; the coupling coefficient k of transformer (120) is also obtained by the resistance and capacitance values ​​in the equivalent parallel RC circuit (110) of the previous stage output and the designed bandwidth; the inductance of the secondary circuit of transformer is selected based on the resonant frequency of the primary circuit and the equivalent capacitance value in the equivalent series RC circuit (130) of the input; the primary and secondary circuits resonate at the same frequency, that is: L1C1=L2C2, (1) The equivalent resistance value of the input equivalent series RC circuit (130) in the secondary circuit is determined by the ratio between the Q value of the primary circuit and the Q value of the secondary circuit, that is: Where Q1 and Q2 are the Q values ​​of the primary and secondary circuits, respectively; Adjusting Q in the primary and secondary circuits percent When Q percent From 1 to 0.25, as Q... percent As the frequency decreases, the curve of loop Z21 changes to a curve that increases with increasing frequency. Therefore, a reasonable selection of Q is necessary. percent This can compensate for the tendency of the transistor's amplitude-frequency response curve to decrease as the frequency increases, thereby achieving a wide and flat gain for the overall circuit. Corresponding to the RF / millimeter-wave receiver, the output equivalent parallel RC circuit (110) is the input matching network (210) on the LNA, including the first common-source NMOS transistor M1 and the first source negative feedback inductor L. s1 The gate terminal of the first common-source NMOS transistor M1 is connected to the inductor L of the input matching network. g Connected for signal input; the source terminal of the first common-source NMOS transistor M1 is connected to the first source negative feedback inductor L. s1 The two transistors are connected to form an equivalent real part of the input impedance for input matching; the drain of the first common-source NMOS transistor M1 is connected to the interstage matching transformer (220) for signal output and wideband interstage matching; in the input matching network, the parallel inductor L4 and capacitor C1 are connected in parallel, one end of which is connected to the signal input terminal for input matching, and the other end is connected to ground; the gate inductor L... g For input matching, the signal input terminal is connected in series with the gate terminal of the first common-source NMOS transistor M1 to form a signal path; the impedance from the drain terminal of the first common-source NMOS transistor M1 to the RFI terminal is equivalent to a parallel RC circuit in the broadband, that is, the output is equivalent to R1 and C1 in (110). The transformer (120) is the interstage matching transformer (220) on the LNA; wherein, the primary inductance L d1 One end is connected to the drain of the first common-source NMOS transistor M1 for signal transmission, and the other end is connected to the power supply VDD to transmit DC voltage to the drain of the first common-source NMOS transistor M1, providing the correct operating state for the first common-source NMOS transistor M1; the secondary inductor L g2 One end is connected to the gate terminal of the second common-source NMOS transistor M2 for signal transmission, and the other end is connected to the bias voltage V. G The transformer is connected to provide a DC bias voltage to the second common-source NMOS transistor M1, so that it operates at the correct bias point. The transformer adopts a Q-asymmetric primary and secondary circuit design. The resonant frequency of the primary circuit is equal to that of the secondary circuit. The inductance value of the primary circuit of the interstage matching transformer (220) is determined by the resistance and capacitance values ​​of the equivalent parallel RC circuit viewed from the drain terminal of the first common-source NMOS transistor M1 to the RFin terminal and the designed bandwidth. The coupling coefficient k of the interstage matching transformer (220) is obtained by the same method based on the resistance and capacitance values ​​of the equivalent parallel RC circuit viewed from the drain terminal of the first common-source NMOS transistor M1 to the RFin terminal and the designed bandwidth. The inductance value of the secondary circuit of the interstage matching transformer (220) is selected based on the resonant frequency of the primary circuit and the equivalent series RLC circuit viewed from the gate terminal of the second common-source NMOS transistor M2 to the RFout terminal. The primary circuit and the secondary circuit resonate at the same frequency. The input equivalent series RC circuit (130) is the output matching network (230) on the LNA, including the second common-source NMOS transistor M2 and the second source negative feedback inductor L. S2 The gate terminal of the second common-source NMOS transistor M2 is connected to the secondary inductor L of the interstage matching transformer. g2 Connected to achieve signal input; the source terminal of the second common-source NMOS transistor M2 is connected to the second source negative feedback inductor L. S2 Connected to generate the real part of the second-stage input impedance, achieving wideband inter-stage matching; the drain of the second common-source NMOS transistor M2 is connected to the parallel output inductor L of the output matching network. d2 and output capacitor C out Connected to achieve signal output; the output inductance L of the output matching network. d2 The drain of the second common-source NMOS transistor M2 is connected in series with the power supply voltage VDD to provide the correct operating DC power supply for the second common-source NMOS transistor M2; the output capacitor C of the output matching network... out One end is connected to the drain of the second common-source NMOS transistor M2, and the other end is connected to the signal output terminal RFout, which is used to output the signal while providing DC blocking. The impedance from the gate of the second common-source NMOS transistor M2 to the RFout terminal can be equivalent to a series RLC circuit over a wide bandwidth, where C is the parasitic capacitance between the gate and source of the second common-source NMOS transistor M2. gs2 The value of R is determined by the parasitic capacitance C between the gate and source of the second common-source NMOS transistor M2. gS2 transconductance g m Second source negative feedback inductor L s2 The decision is: C2=C gs2 R2=g m L s2 / C gs2 In addition, there is an equivalent inductance L. s2 Once the size and bias of the second common-source NMOS transistor M2 are fixed, adjust the second negative feedback inductor L. s2 That is, adjust the equivalent resistance R2; the primary and secondary circuits resonate at the same frequency, i.e.: L1C1=L2C2 The equivalent resistance value of the input equivalent series RC circuit (130) in the secondary circuit is determined by the ratio between the Q value of the primary circuit and the Q value of the secondary circuit, i.e. Where Q1 and Q2 are the Q values ​​of the primary and secondary circuits, respectively; adjusting Q... percent That is, adjusting the equivalent resistance value of the input equivalent series RC circuit (130), which is also the second negative feedback inductor L of the second common-source NMOS transistor M2. s2 .

2. The high flatness interstage matching circuit according to claim 1, characterized in that, The interstage matching circuit can be implemented using an on-chip transformer or an off-chip transformer.

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