A New Broadband Filter Power Amplifier

Abstract

The present invention discloses a novel broadband filter power amplifier, wherein a gate DC bias network is used to provide a gate bias voltage required for the operation of a power amplifier transistor; a drain DC bias network is used to provide a drain bias voltage required for the operation of a power amplifier transistor; an input impedance matching network includes a microstrip line, a DC blocking capacitor, and an RC parallel circuit; an output impedance matching network includes a T-type tuning network and a bandpass filter, wherein the bandpass filter includes a parallel coupled microstrip line with a length of λ / 4 and different loads are loaded on four ports of the parallel coupled microstrip line. Compared with the existing method of directly cascading a filter with a power amplifier, the present invention integrates a bandpass filter into an output matching network, thereby achieving miniaturization of the overall circuit while ensuring broadband and high efficiency.

Description

Technical Field

[0001] The invention belongs to the technical field of power semiconductor devices, and in particular relates to a novel broadband filtering power amplifier. Background Art

[0002] With the rapid development and progress of communication technology, wireless communication system standards have put forward higher and higher requirements on the performance of RF transmitters. As a key component of the RF front end, the power amplifier has a great impact on the performance of the transmitter, especially with the advent of the 5G era, which requires the RF module to be able to support multiple frequency bands at the same time or cover as wide a frequency band as possible in the working frequency band, and the smaller the overall circuit size, the better. The traditional design method is generally to directly cascade the power amplifier and the filter, but this will also increase additional insertion loss and increase the size of the circuit.

[0003] Therefore, some design ideas of integrating filters into the input and output networks of amplifier circuits have been proposed, but the working bandwidth of the power amplifier circuits usually designed is not sufficient to cover the 5G commercial frequency band or the efficiency is not high enough.

[0004] Therefore, in view of the defects in the current technology, it is necessary to conduct research to provide a broadband filtering power amplifier that is small in size and sufficient to cover the 5G commercial frequency band while ensuring high efficiency. Summary of the invention

[0005] In order to overcome the problems existing in the above-mentioned technologies, the present invention provides a novel broadband filter power amplifier. The joint design theory and harmonic suppression theory are considered at the same time, thereby effectively improving the working bandwidth and efficiency of the filter power amplifier. The working bandwidth of 2.9-3.7GHz covers the 5G commercial frequency band of 3.3-3.6GHz, and the streamlined circuit structure is also beneficial to the miniaturization of the overall circuit size.

[0006] To achieve the above object, the present invention provides a novel broadband filter power amplifier, comprising a gate DC bias network, a drain DC bias network, an input impedance matching network, a power amplifier transistor and an output impedance matching network, wherein:

[0007] The gate DC bias network is used to provide the gate bias voltage required for the power amplifier transistor to work;

[0008] The drain DC bias network is used to provide the drain bias voltage required for the power amplifier transistor to work;

[0009] The input impedance matching network includes a microstrip line, a DC blocking capacitor and an RC parallel circuit;

[0010] The output impedance matching network includes a T-type tuning network and a bandpass filter, wherein the bandpass filter includes a parallel coupled microstrip line with a length of λ / 4 and four ports of the parallel coupled microstrip line are respectively loaded with different loads.

[0011] Preferably, the gate DC bias network and the drain DC bias network both include microstrip lines and a plurality of filter capacitors.

[0012] Preferably, the input signal enters the gate of the power amplifier transistor through the input impedance matching network, and the input impedance of 50 ohms is matched to the optimal source impedance of the gate of the power amplifier transistor through the input impedance matching network, thereby improving the efficiency of the overall circuit during operation; the input impedance matching network includes microstrip lines TL8, TL9, TL11, TL12, TL13, a DC blocking capacitor C1 and an RC parallel circuit, one end of the microstrip line TL8 serves as the input port of the signal, the other end of the microstrip line TL8 is connected to one end of the DC blocking capacitor C1, the other end of the DC blocking capacitor C1 is connected to one end of the microstrip line TL9, the other end of the microstrip line TL9 is connected to one end of the microstrip lines TL11 and TL12, the other end of the microstrip line TL11 remains open, the other end of the microstrip line TL12 is connected to one end of the RC parallel circuit, the other end of the RC parallel circuit is connected to one end of the microstrip line TL13, and the other end of the microstrip line TL12 is connected to the gate of the power amplifier transistor.

[0013] Preferably, the output impedance matching network is composed of a "T" type tuning network and a bandpass filter. The "T" type tuning network is composed of microstrip lines TL5, TL6 and TL7, one end of the three microstrip lines are connected together, wherein the other end of TL5 is connected to the drain of the power amplifier transistor as the input end of the output matching circuit; the other end of TL6 is connected to the input port of the bandpass filter, and the other end of TL7 remains open. The bandpass filter is composed of microstrip lines TL1, TL2, TL3, TL4 and a parallel coupled microstrip line CLin with a length of λ / 4, one end of the microstrip line TL1 with a length of λ / 4 is connected to one end of the microstrip line TL2 with a length of λ / 4 to form a stepped impedance resonator, the other end of the microstrip line TL2 is connected to port 1 of the parallel coupled microstrip line CLin, one end of the short-circuited microstrip line TL3 with a length of λ / 4 is connected to port 2 of the parallel coupled microstrip line CLin, and one end of the short-circuited microstrip line TL4 with a length of λ / 4 is connected to port 3 of the parallel coupled microstrip line CLin.

[0014] Preferably, the power amplifier transistor is a GaN HEMT CGH40010F transistor.

[0015] The beneficial effects of the present invention include at least: the gate DC bias network and the drain DC bias network include a microstrip line and a plurality of filter capacitors; the input impedance matching network includes a microstrip line, a DC blocking capacitor and an RC parallel circuit; the output impedance matching network includes a "T" type tuning network and a bandpass filter, wherein the bandpass filter is composed of a parallel coupled microstrip line with a length of λ / 4 and four ports are loaded with different loads. Compared with the existing method of directly cascading filters with power amplifiers, the present invention integrates the bandpass filter into the output matching network, thereby achieving miniaturization of the overall circuit while ensuring broadband and high efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to make the purpose, technical solution and beneficial effects of the present invention clearer, the present invention provides the following drawings for illustration:

[0017] Figure 1 It is a structural schematic diagram of a novel broadband filter power amplifier according to an embodiment of the present invention;

[0018] Figure 2 A topological structure diagram of a gate DC bias network and an input impedance matching network of a novel broadband filter power amplifier according to an embodiment of the present invention;

[0019] Figure 3 This is a topological diagram of an output impedance matching network of a novel broadband filter power amplifier according to an embodiment of the present invention;

[0020] Figure 4 It is a schematic diagram of S-parameter simulation results of an output impedance matching network of a novel broadband filter power amplifier according to an embodiment of the present invention;

[0021] Figure 5 This is a diagram of simulation results of output power, drain efficiency and gain obtained through simulation and measurement of the novel broadband filter power amplifier according to an embodiment of the present invention. DETAILED DESCRIPTION

[0022] The preferred embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0023] See also Figure 1 , which is a schematic diagram of the structure of a broadband power amplifier of the present invention, includes a gate DC bias network 10, a drain DC bias network 20, an input impedance matching network 30, a power amplifier transistor 40 and an output impedance matching network 50; the gate DC bias network 10 is used to provide a gate bias voltage required for the power amplifier transistor 40 to work; the drain DC bias network 20 is used to provide a drain bias voltage required for the power amplifier transistor 40 to work;

[0024] See also Figure 2, which is a topological structure diagram of the input impedance matching network in the present invention, one end of the microstrip line TL8 is used as the input port of the signal, the other end of the microstrip line TL8 is connected to one end of the DC blocking capacitor C1, the other end of the DC blocking capacitor C1 is connected to one end of the microstrip line TL9, the other end of the microstrip line TL9 is connected to one end of the microstrip lines TL11 and TL12, the other end of the microstrip line TL11 is kept open, the other end of the microstrip line TL12 is connected to one end of the RC parallel circuit, the other end of the RC parallel circuit is connected to one end of the microstrip line TL13, and the other end of the microstrip line TL12 is connected to the gate of the power amplifier transistor 40. The input signal enters the gate of the power amplifier transistor 40 through the input impedance matching network 30, and the 50 ohm input impedance is matched to the optimal source impedance of the power amplifier gate through the input impedance matching network 30, thereby improving the efficiency of the overall circuit when working.

[0025] See also Figure 3 , which is a topological structure diagram of the output impedance matching network 50 in the present invention. The output impedance matching network 50 is composed of a T-type tuning network and a bandpass filter. The T-type tuning network is composed of microstrip lines TL5, TL6 and TL7. One end of the three microstrip lines are connected together, wherein the other end of TL5 is connected to the drain of the power amplifier transistor 40 as the input end of the output matching circuit; the other end of TL6 is connected to the input port of the bandpass filter, and the other end of TL7 remains open. The input impedance Z of the T-type tuning network is i The calculation formula of " is:

[0026]

[0027] Where Z T is the characteristic impedance of microstrip lines TL5 and TL6, Z7 is the characteristic impedance of microstrip line TL7, θ5, θ6 and θ7 are the electrical lengths of microstrip lines TL5, TL6 and TL7 respectively, and Z N is the input impedance of the left port of microstrip line TL6, Z BPFis the input impedance of the bandpass filter. The bandpass filter is composed of microstrip lines TL1, TL2, TL3, TL4 and a parallel coupled microstrip line CLin with a length of λ / 4. One end of the microstrip line TL1 with a length of λ / 4 is connected to one end of the microstrip line TL2 with a length of λ / 4 to form a step impedance resonator. The other end of the microstrip line TL2 is connected to port 1 of the parallel coupled microstrip line CLin. One end of the short-circuited microstrip line TL3 with a length of λ / 4 is connected to port 2 of the parallel coupled microstrip line CLin. One end of the short-circuited microstrip line TL4 with a length of λ / 4 is connected to port 3 of the parallel coupled microstrip line CLin. When the signal amplified by the power amplifier transistor 40 passes through the output impedance matching network 50, the second harmonic component is suppressed, and the load impedance of 50 ohms is matched to the optimal load impedance of the drain of the power amplifier tube through the output impedance matching network 50, thereby improving the efficiency of the overall circuit when working.

[0028] See also Figure 4 , which is a schematic diagram of the S parameter simulation results of the output impedance matching network 50. From the S parameter simulation results, it can be seen that the output impedance matching network 50 will generate four zero points f TZ1 、f TZ2 、f TZ 3. f TZ4 and three poles f TP1 ,f TP2 ,f TP 3. The values ​​of the four zero points are determined by the following formula:

[0029]

[0030] Where R is the ratio of the characteristic impedance Z1 of TL1 to the characteristic impedance Z2 of TL2. Obviously, when the center frequency is determined, f TZ1 and f TZ4 The value of is unchanged, and f TZ3 and f TZ4 The value of will change with the change of R, so by adjusting the characteristic impedance ratio R of TL1 and TL2, the passband selectivity and suppression performance of the matching network in the stopband can be adjusted to meet the designer's design goals. In this embodiment, by optimizing the value of R, the matching network suppresses the second harmonic component 5.8-7.4GHz by at least 49dB. Due to the presence of three poles, the output impedance matching network 50 achieves very low return loss in a wider passband, wherein the return loss in the operating frequency band of 2.9-3.7GHz is less than 22dB. From the results, it can be seen that the output impedance matching network 50 exhibits excellent bandpass filtering characteristics.

[0031] See also Figure 5, which shows the simulation results of output power, drain efficiency and gain obtained by simulating and measuring a broadband power amplifier of the present invention. From the results, it can be seen that the designed power amplifier operates in the 2.9-3.7GHz frequency band, the drain efficiency is between 60%-68%, the saturated output power is between 40-41dBm, and the gain is between 10-11.2dB, showing good performance indicators.

[0032] Finally, it should be noted that the above preferred embodiments are only used to illustrate the technical solutions of the present invention rather than to limit it. Although the present invention has been described in detail through the above preferred embodiments, those skilled in the art should understand that various changes can be made in form and details without departing from the scope defined by the claims of the present invention.

Claims

1. A novel broadband filter power amplifier, characterized in that: It includes a gate DC bias network, a drain DC bias network, an input impedance matching network, a power amplifier transistor and an output impedance matching network, wherein: The gate DC bias network is used to provide the gate bias voltage required for the power amplifier transistor to work; The drain DC bias network is used to provide the drain bias voltage required for the power amplifier transistor to work; The input impedance matching network includes a microstrip line, a DC blocking capacitor and an RC parallel circuit; The output impedance matching network includes a T-type tuning network and a bandpass filter, wherein the bandpass filter includes a parallel coupled microstrip line with a length of λ / 4 and different loads are loaded on four ports of the parallel coupled microstrip line; The gate DC bias network and the drain DC bias network both include microstrip lines and a number of filter capacitors; The input signal enters the gate of the power amplifier transistor through the input impedance matching network, and the 50 ohm input impedance is matched to the optimal source impedance of the gate of the power amplifier transistor through the input impedance matching network, thereby improving the efficiency of the overall circuit during operation; the input impedance matching network includes microstrip lines TL8, TL9, TL11, TL12, TL13, a DC blocking capacitor C1 and an RC parallel circuit, one end of the microstrip line TL8 serves as the input port of the signal, the other end of the microstrip line TL8 is connected to one end of the DC blocking capacitor C1, the other end of the DC blocking capacitor C1 is connected to one end of the microstrip line TL9, the other end of the microstrip line TL9 is connected to one end of the microstrip lines TL11 and TL12, the other end of the microstrip line TL11 remains open, the other end of the microstrip line TL12 is connected to one end of the RC parallel circuit, the other end of the RC parallel circuit is connected to one end of the microstrip line TL13, and the other end of the microstrip line TL12 is connected to the gate of the power amplifier transistor.

2. The novel broadband filter power amplifier according to claim 1 is characterized in that: The output impedance matching network is composed of a "T"-type tuning network and a bandpass filter. The "T"-type tuning network is composed of microstrip lines TL5, TL6 and TL7. One ends of the three microstrip lines are connected together, wherein the other end of TL5 is connected to the drain of the power amplifier transistor as the input end of the output matching circuit; the other end of TL6 is connected to the input port of the bandpass filter, and the other end of TL7 remains open. The bandpass filter is composed of microstrip lines TL1, TL2, TL3, TL4 and a parallel coupled microstrip line CLin with a length of λ / 4. One end of the microstrip line TL1 with a length of λ / 4 is connected to one end of the microstrip line TL2 with a length of λ / 4 to form a stepped impedance resonator, the other end of the microstrip line TL2 is connected to port 1 of the parallel coupled microstrip line CLin, one end of the short-circuited microstrip line TL3 with a length of λ / 4 is connected to port 2 of the parallel coupled microstrip line CLin, and one end of the short-circuited microstrip line TL4 with a length of λ / 4 is connected to port 3 of the parallel coupled microstrip line CLin.

3. The novel broadband filter power amplifier according to claim 1, characterized in that: The power amplifier transistor adopts a GaN HEMT CGH40010F transistor.

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