A fully differential sigma-delta ADC with chord noise cancellation

Abstract

The present invention discloses a fully differential sigma-delta ADC with string-tone elimination, comprising a plurality of modulation units cascaded in sequence and a quantizer unit, and also comprising a pseudo-random signal generator; the modulation units of each order respectively comprise an adder and an integrator connected in sequence; the quantizer unit comprises an adder and a quantizer connected in sequence; the output of the quantizer is respectively fed back and connected to the adder input of each modulation unit; the output of the pseudo-random signal generator is respectively connected to the adder input of the last modulation unit and the adder input of the quantizer unit. The present invention adds a dither circuit to the input stage of the last modulation unit and the quantizer of the sigma-delta ADC; the dither circuit input amplitude is adjustable, disrupting the periodicity of the output signal of the sigma-delta ADC when a DC signal or a low-frequency sinusoidal signal is input, thereby achieving the effect of suppressing the generation of string-tone.

Description

Technical Field

[0001] The present invention relates to analog-to-digital conversion technology, and in particular to a fully differential sigma-delta ADC with string tone elimination. Background Art

[0002] Sigma-delta ADCs utilize oversampling technology, offering advantages such as high precision and excellent linearity. These ADCs are widely used in fields such as audio and video processing, automated control, image processing for medical equipment, electronic measurement, and electronic monitoring. These applications are particularly evident in radar, sonar, high-resolution video and image displays, military and medical imaging, high-performance controllers and actuators, and modern digital communications systems, including wireless phones and base station receivers.

[0003] However, Sigma-delta ADC has a natural disadvantage - string sound. For low-order Sigma-delta modulator system, when the input amplitude is DC signal, AC signal with very slow change or AC signal with very small amplitude, the system output is a periodic sequence. At this time, at the output of Sigma-delta ADC, at f S Idle tones, or string tones, appear at / N and its integer multiples, where N is the period of the sequence. When N is small, these idle tones occur at a high frequency and can be filtered out by the subsequent digital low-pass filter. However, when N is large, these idle tones occur at a low frequency, and some frequencies cannot be filtered out by the subsequent digital low-pass filter. Therefore, the sigma-delta modulator needs to process these string tones.

[0004] There are many string noise elimination technologies. The main string noise elimination technologies are as follows:

[0005] 1. Dithering technology

[0006] Currently, the most widely used compression technique is dithering. Dithering involves adding an uncorrelated signal to the input of a data converter, decoupling the input signal from the quantization noise. As the dither signal increases, the modulator's quantization noise increases. Therefore, stability must be considered when designing high-order modulators. This can be achieved by adding a dither signal to the quantizer and shaping it using an NTF. However, the introduction of a dither signal makes the modulator less stable, increases the energy of the baseband noise, and reduces the signal-to-noise ratio (SNR).

[0007] In most practical designs, jitter is generated by digital circuits, so a quantized signal is required, and a pseudo-random sequence generator is needed to generate pseudo-random noise.

[0008] 2. Chaotic Sigma-Delta Modulator Technology

[0009] A chaotic modulator can be obtained by using a non-chaotic modulator with at least one zero in the noise transfer function outside the unit circle. The overall feedback system remains stable, but the ring filter is dynamically unstable, disrupting the periodic sequence. Therefore, a chaotic sigma-delta modulator is toneless. Moving the zero outside the unit circle degrades the modulator's signal-to-noise ratio (SNR). Chaotic sigma-delta modulators are typically obtained by expanding the noise transfer function of a non-chaotic modulator.

[0010] 3. Dynamic AC dithering technology

[0011] The generation of a chord depends on the input signal: a quiet input signal produces a chord, while a busy input signal does not. Therefore, it is advantageous to monitor the input signal and determine the energy of the dither signal fed into the modulator based on the input signal's magnitude. If the input signal is small, a large dither can be added without overloading the modulator. If the input signal is large, no dither is required. Alternatively, the output of the decimation filter can be monitored to approximate the analog input signal.

[0012] 4. Dynamic DC dithering technology

[0013] Figure 1 This is a block diagram of a CRFF Sigma-Delta ADC using dynamic DC dithering technology. Compared to a traditional Sigma-Delta ADC, this one adds a dynamic DC dithering control circuit and a dynamic DC dithering DAC. The Sigma-Delta modulator consists of an analog input signal and a dynamic DC dithering input, whose value is determined by the output of a digital filter. This technology uses a dynamic DC dithering circuit to reduce the Sigma-Delta ADC's stringing noise. By adding a small amount of circuitry, the stringing noise is moved out of the audio band. This method eliminates the need for a random sequence generator and minimizes degradation in DR and SNR. The dithering circuit generates different DC dithering voltages based on the digital control code output by the dynamic dithering control circuit. The DC dithering voltage has a polarity opposite to the overall bias voltage. Because the dithered signal is DC, it can be filtered out by a high-pass filter, thus having no effect on the digital output.

[0014] Figure 2 This is an analog-to-digital converter with a dither circuit proposed in US Pat. No. 7,696,910B2. In this circuit, a dither generation circuit is generated by a pseudo-random signal, which is input into the integrator of a Sigma-Delta ADC through a dither input circuit.

[0015] By connecting capacitors in parallel and summing currents, the modulator output can be prevented from being static and the digital output signal from having a constant value, thus eliminating circuit hum. However, this method adds a dither signal to the first stage of the sigma-delta ADC, which can easily cause modulator overload when a high-frequency signal is input. Summary of the Invention

[0016] The purpose of the present invention is: sigma-delta ADC is one of the most popular high-precision ADCs currently. The largest application areas of this type of ADC are the audio field and the digital telephone field. Currently, digital audio technology is developing very rapidly, and various digital audio products have been widely used, and 24-bit high-resolution analog-to-digital converters are used in large quantities. Due to its own technical characteristics, Sigma-delta ADC has high precision but is very prone to produce string sound, especially when the input signal is DC or a relatively low-frequency sinusoidal signal. Even at a very low level, the human ear can capture it, which seriously affects the user experience. Therefore, the present invention provides a fully differential sigma-delta ADC with string sound elimination.

[0017] The technical solution of the present invention is:

[0018] A fully differential sigma-delta ADC with string tone elimination includes a plurality of cascaded modulation units and a quantizer unit, and also includes a pseudo-random signal generator; each modulation unit includes an adder and an integrator connected in sequence; the quantizer unit includes an adder and a quantizer connected in sequence;

[0019] The output terminals of the quantizers are respectively fed back to the input terminals of the adders of the modulation units of each order;

[0020] The output end of the pseudo-random signal generator is connected to the adder input end of the last order modulation unit and the adder input end of the quantizer unit respectively.

[0021] Preferably, the output end of the quantizer and the input end of the adder of each order modulation unit are connected via an amplifier with a certain feedback gain coefficient.

[0022] Preferably, the output end of the pseudo-random signal generator is connected to the adder input end of the last-order modulation unit and the adder input end of the quantizer unit respectively through amplifiers with certain gain coefficients.

[0023] Preferably, the pseudo-random signal generator uses a fully differential dither generation circuit to output a signal to the quantizer unit; the fully differential dither generation circuit includes pseudo-random signal control switches K1, K2 and double-pole clock switches clk1, clk2 and single-pole clock switch clk3; the complementary bias voltage V C1 and V C2 Through the pseudo-random signal control switch K1, K2 and the double-pole clock switch clk1 connected to the two input terminals of the quantizer, the pseudo-random signal generator generates a pseudo-random signal to control K1, K2; at the same time, the input signal V in1 and V in2 The double-pole clock switch clk2 is connected to the two input terminals of the quantizer; the two ends of the single-pole clock switch clk3 are respectively connected to the two input terminals of the quantizer.

[0024] Preferably, the quantizer includes a comparator and capacitors C1 and C2, and the capacitors C1 and C2 are respectively connected in series to two input terminals of the comparator.

[0025] Preferably, the double-pole clock switches clk1 and clk2 are two non-overlapping clocks.

[0026] Preferably, the complementary bias voltage V C1 and V C2 Generated by a controllable bias voltage generator; the controllable bias voltage generator includes a selection switch K n , operational amplifiers amp1, amp2, switch tubes M1, M2 and adjustable resistors R1, R2, R3, R4; the switch tube M1, adjustable resistors R1, R2, R3, R4 and switch tube M2 are sequentially connected in series between the positive and negative poles of the power supply, and the switch K is selected n Select input voltage V1, V2...V n The output terminal M is connected to the inverting input terminal of the operational amplifier amp1, the non-inverting input terminal of the operational amplifier amp1 is connected to the common node N of the switch tube M1 and the adjustable resistor R1, and the output terminal of the operational amplifier amp1 is connected to the gate of the switch tube M1; the inverting input terminal of the operational amplifier amp2 is connected to the input voltage V cm The positive input terminal is connected to the common node O of the adjustable resistors R2 and R3, and the output terminal is connected to the gate of the switch tube M2; the adjustment terminals of the adjustable resistors R2 and R3 are respectively used as complementary bias voltages V C1 and V C2 output terminal.

[0027] Preferably, the selection switch K n Output terminal M voltage V M 、N point voltage V N , O point voltage V O , under the clamping action of op amp1 and amp2, V M =V N , Vcm =V O ,

[0028] The adjustable resistors R1, R2, R3, and R4 are controlled by a logic circuit so that the circuit satisfies:

[0029]

[0030]

[0031] Where ΔV is the voltage V M With V cm The difference between , n is an integer not less than 2.

[0032] The advantages of the present invention are:

[0033] 1. The fully differential sigma-delta ADC with string noise cancellation of the present invention adds a dither circuit to the input stage of the last-order modulation unit and quantizer of the sigma-delta ADC. The dither circuit has an adjustable input amplitude, which disrupts the periodicity of the output signal of the sigma-delta ADC when a DC signal or a low-frequency sinusoidal signal is input, thereby achieving the effect of suppressing the generation of string noise.

[0034] 2. The bias voltage generator of the present invention generates a complementary adjustable voltage signal, which is input into the ADC after pseudo-random signal conditioning. The dither signal size can be adjusted according to actual conditions, reducing the impact of the dither circuit on the ADC signal-to-noise ratio. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] The present invention will be further described below with reference to the accompanying drawings and embodiments:

[0036] Figure 1 A block diagram of a Sigma-delta ADC using dynamic DC dithering technology in the prior art is provided;

[0037] Figure 2 This is a block diagram of an analog-to-digital converter with a dither circuit in the prior art;

[0038] Figure 3 This is a fully differential second-order sigma-delta ADC with chord noise cancellation in the embodiment;

[0039] Figure 4 This is the schematic diagram of the fully differential dither generation circuit;

[0040] Figure 5 A controllable dither voltage generating circuit;

[0041] Figure 6This is the simulink simulation result of the existing second-order sigma-delta ADC;

[0042] Figure 7 This is the Simulink simulation result of a second-order sigma-delta ADC with dither. DETAILED DESCRIPTION

[0043] like Figure 3 As shown, the present invention uses a second-order sigma-delta ADC as an example to disclose a fully differential sigma-delta ADC with chord noise cancellation. The figure includes a cascaded second-order modulation unit and a quantizer unit, as well as a pseudo-random signal generator. The first-order modulation unit includes gain amplifiers a1, b1, and c1, an adder ∑1, and an integrator A. The second-order modulation unit includes gain amplifiers a2, c2, and d1, an adder ∑2, and an integrator B. The quantizer unit includes an adder ∑3 and a quantizer connected in sequence. The pseudo-random signal generator generates a pseudo-random signal, which is applied to the second-order modulation unit via gain amplifier d1. Simultaneously, the pseudo-random signal is applied to the input of the quantizer unit via gain amplifier d2.

[0044] For more convenient and intuitive expression, the gain coefficients of the gain amplifiers a1, b1, c1, a2, c2, d1, and d2 in this embodiment are a1, b1, c1, a2, c2, d1, and d2, respectively, that is, a1 and a2 are the feedback coefficients of the quantizer to the first-order modulation unit and the second-order modulation unit, b1 is the gain coefficient from the input end to the second-order modulation unit, c1 and c2 are the gain coefficients of the first-order modulation unit and the second-order modulation unit, respectively, and d1 and d2 are the gain coefficients from the random signal generator to the second-order modulation unit and the quantizer input stage, respectively.

[0045] The present invention achieves the effect of suppressing the generation of string sound by applying a pseudo-random signal with a certain amplitude to the second-stage input end of the second-order sigma-delta ADC and the front end of the quantizer, disrupting the periodicity of the output signal of the sigma-delta ADC when a DC signal or a low-frequency sinusoidal signal is input.

[0046] Figure 4 The fully differential dither generation circuit of the present invention uses a fully differential dither generation circuit to output a signal to the quantizer unit; the fully differential dither generation circuit includes pseudo random signal control switches K1, K2 and double-pole clock switches clk1, clk2 and single-pole clock switch clk3; complementary bias voltage V C1 and V C2Through the pseudo-random signal control switch K1, K2 and the double-pole clock switch clk1 connected to the two input terminals of the quantizer, the pseudo-random signal generator generates a pseudo-random signal to control K1, K2; at the same time, the input signal V in1 and V in2 A double-pole clock switch, clk2, is connected to the two input terminals of the quantizer. The double-pole clock switches, clk1 and clk2, are two non-overlapping clocks. The two ends of the single-pole clock switch, clk3, are connected to the two input terminals of the quantizer. The quantizer includes a comparator and capacitors C1 and C2, which are connected in series to the two input terminals of the comparator.

[0047] V of the present invention C1 and V C2 To have complementary output and adjustable amplitude bias voltage, the dither generator generates pseudo-random signals to control switches K1 and K2, V dither1 and V dither2 The two voltage signals are input to the quantizer under the control of the double-pole clock switch clk1. At the same time, the input signal V in1 and V in2 It is also input into the quantizer under the control of the double-pole clock switch clk2, and the single-pole clock switch clk3 controls the switch tube to reset it in the non-comparison stage.

[0048] like Figure 5 The figure shows the controllable dither generation circuit of the present invention. The disadvantage of using a dither circuit to suppress string sound is that it increases circuit noise and reduces the circuit's SNR. If the dither signal is too large, the circuit's SNR will drop too seriously, affecting circuit performance. If the dither signal is too small, the dither circuit will not be able to disrupt the periodicity of the output, thus failing to eliminate the string sound. Therefore, the present invention generates an adjustable complementary voltage V for a fully differential sigma-delta ADC. C1 and V C2 .

[0049] Figure 5 , the complementary bias voltage V C1 and V C2 Generated by a controllable bias voltage generator; the controllable bias voltage generator includes a selection switch K n , operational amplifiers amp1, amp2, switch tubes M1, M2 and adjustable resistors R1, R2, R3, R4; the switch tube M1, adjustable resistors R1, R2, R3, R4 and switch tube M2 are sequentially connected in series between the positive and negative poles of the power supply, and the switch K is selected n Select input voltage V1, V2...V nThe output terminal M is connected to the inverting input terminal of the operational amplifier amp1, the non-inverting input terminal of the operational amplifier amp1 is connected to the common node N of the switch tube M1 and the adjustable resistor R1, and the output terminal of the operational amplifier amp1 is connected to the gate of the switch tube M1; the inverting input terminal of the operational amplifier amp2 is connected to the input voltage V cm The positive input terminal is connected to the common node O of the adjustable resistors R2 and R3, and the output terminal is connected to the gate of the switch tube M2; the adjustment terminals of the adjustable resistors R2 and R3 are respectively used as complementary bias voltages V C1 and V C2 output terminal.

[0050] The selection switch K n Output terminal M voltage V M 、N point voltage V N , O point voltage V O , under the clamping action of op amp1 and amp2, V M =V N , V cm =V O ,

[0051] The adjustable resistors R1, R2, R3, and R4 are controlled by a logic circuit so that the circuit satisfies:

[0052]

[0053]

[0054] Where ΔV is the voltage V M With V cm The difference between n and 2 is an integer not less than 2. This method can effectively control the voltage V C1 and V C2 The size of V C1 and V C2 Both complementary and adjustable in size.

[0055] Figure 6 The following is the Simulink simulation result of the existing second-order sigma-delta ADC. From the simulation results, we can see that at this time, the spectrum has many string tones at low frequencies, which greatly affects the circuit performance.

[0056] Figure 7 Figure 3 is the Simulink simulation result of the second-order sigma-delta ADC with dither of the present invention. From the simulation results, it can be seen that the idle tone of the circuit is effectively suppressed by the present invention.

[0057] The above embodiments are intended only to illustrate the technical concepts and features of the present invention. Their purpose is to enable those skilled in the art to understand the contents of the present invention and implement them accordingly. They are not intended to limit the scope of protection of the present invention. Any modifications made based on the spirit of the main technical solution of the present invention shall be included in the scope of protection of the present invention.

Claims

1. A fully differential sigma-delta ADC with chord noise cancellation, characterized in that: The invention comprises a multi-order modulation unit and a quantizer unit connected in series, and also comprises a pseudo-random signal generator; the modulation unit of each order comprises an adder and an integrator connected in series; the quantizer unit comprises an adder and a quantizer connected in series; The output terminals of the quantizers are respectively fed back to the input terminals of the adders of the modulation units of each order; The output end of the pseudo-random signal generator is connected to the adder input end of the last order modulation unit and the adder input end of the quantizer unit respectively; The pseudo-random signal generator uses a fully differential dither generation circuit to output signals to the quantizer unit; the fully differential dither generation circuit includes pseudo-random signal control switches K1, K2 and double-pole clock switches clk1, clk2 and single-pole clock switch clk3; complementary bias voltage V C1 and V C2 Through the pseudo-random signal control switch K1, K2 and the double-pole clock switch clk1 connected to the two input terminals of the quantizer, the pseudo-random signal generator generates a pseudo-random signal to control K1, K2; at the same time, the input signal V in1 and V in2 The double-pole clock switch clk2 is connected to the two input terminals of the quantizer; the two ends of the single-pole clock switch clk3 are respectively connected to the two input terminals of the quantizer.

2. The fully differential sigma-delta ADC with chord noise cancellation according to claim 1, wherein: The output end of the quantizer is connected to the input end of the adder of each order modulation unit through an amplifier with a certain feedback gain coefficient.

3. The fully differential sigma-delta ADC with chord noise cancellation according to claim 2, wherein: The output end of the pseudo-random signal generator is connected to the adder input end of the last-order modulation unit and the adder input end of the quantizer unit respectively through amplifiers with a certain gain coefficient.

4. The fully differential sigma-delta ADC with chord noise cancellation according to claim 3, wherein: The quantizer includes a comparator and capacitors C1 and C2. The capacitors C1 and C2 are connected in series to two input terminals of the comparator respectively.

5. The fully differential sigma-delta ADC with chord noise cancellation according to claim 3, wherein: The double-pole clock switches clk1 and clk2 are two non-overlapping clocks.

6. The fully differential sigma-delta ADC with chord noise cancellation according to claim 5, wherein: The complementary bias voltage V C1 and V C2 Generated by a controllable bias voltage generator; the controllable bias voltage generator includes a selection switch K n , operational amplifiers amp1, amp2, switch tubes M1, M2 and adjustable resistors R1, R2, R3, R4; the switch tube M1, adjustable resistors R1, R2, R3, R4 and switch tube M2 are sequentially connected in series between the positive and negative poles of the power supply, and the switch K is selected n Select input voltage V1, V2...V n The output terminal M is connected to the inverting input terminal of the operational amplifier amp1, the non-inverting input terminal of the operational amplifier amp1 is connected to the common node N of the switch tube M1 and the adjustable resistor R1, and the output terminal of the operational amplifier amp1 is connected to the gate of the switch tube M1; the inverting input terminal of the operational amplifier amp2 is connected to the input voltage V cm The positive input terminal is connected to the common node O of the adjustable resistors R2 and R3, and the output terminal is connected to the gate of the switch tube M2; the adjustment terminals of the adjustable resistors R2 and R3 are respectively used as complementary bias voltages V C1 and V C2 output terminal.

7. The fully differential sigma-delta ADC with string noise cancellation according to claim 6, wherein: The selection switch K n Output terminal M voltage V M 、N point voltage V N , O point voltage V O , under the clamping action of op amp1 and amp2, V M =V N , V cm =V O , The adjustable resistors R1, R2, R3, and R4 are controlled by a logic circuit so that the circuit satisfies: ， Where ΔV is the voltage V M With V cm The difference between , n is an integer not less than 2.

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