Semiconductor packaging device and method for manufacturing the same

Abstract

The present disclosure relates to a semiconductor packaging device and a manufacturing method thereof. The semiconductor packaging device includes: a substrate having a first cavity and two first openings, wherein the first openings penetrate through a first end of the substrate and communicate with the first cavity; and a first semiconductor element disposed on the substrate and covering one of the first openings. The semiconductor packaging device can prevent the electrical connection of the semiconductor packaging device from being affected by the residual molding compound, and avoid the difficulties in controlling the height of the adhesive and the overflow of the adhesive caused by the excessive surface roughness of the molding compound, which is beneficial to improving the product yield.

Description

Technical Field

[0001] The present disclosure relates to the technical field of semiconductor packaging, and particularly to a semiconductor packaging device and a manufacturing method thereof. Background Art

[0002] A differential pressure gauge is a pressure measuring instrument for measuring the pressure difference between two different points. Existing differential pressure gauges are usually formed by a double-sided plastic quad flat package (QFP) method.

[0003] Figure 1A is a schematic diagram of a semiconductor packaging device used as a differential pressure gauge. As Figure 1A shown, the semiconductor packaging device includes an upper molding compound 12, a lower molding compound 11, and pins 13. The pins 13 are located between the upper molding compound 12 and the lower molding compound 11. A cover 14 is provided on the upper side of the upper molding compound 12, and a seal 15 is provided on the lower side of the lower molding compound 11. A microelectromechanical system chip 16 and an application-specific integrated circuit chip 17 are provided on the lower surface of the upper molding compound 12. The microelectromechanical system chip 16 and the application-specific integrated circuit chip 17 are electrically connected to the pins 13 through connection lines 18 respectively. When there is a pressure difference between the upper cavity 21 and the lower cavity 22, the sensing membrane ( Figure 1A (not shown in the figure)) of the microelectromechanical system chip 16 will deform, thereby causing a change in the resistance value of the surface coil, and based on this, the pressure difference on both sides of the microelectromechanical system chip 16 can be calculated.

[0004] Figure 1A The semiconductor packaging device shown has at least the following deficiencies: (1) Since the pins 13 are located between the upper molding compound 12 and the lower molding compound 11, the ends of the pins 13 may be covered by the residual molding compound, affecting the electrical connection between the pins 13 and the connection lines 18; (2) Figure 1B is Figure 1A a partial enlarged view of the semiconductor packaging device in Figure 1B As shown, the microelectromechanical system chip 16 needs to be connected to the upper molding compound 12 through an adhesive 19. Since the surface roughness of the upper molding compound 12 is relatively large, it will affect the height control of the adhesive 19, thereby affecting the positioning of the microelectromechanical system chip 16 and the subsequent wire bonding process. In addition, the relatively large roughness of the upper molding compound 12 will also cause the adhesive 19 to overflow, increasing the process difficulty.

[0005] Therefore, it is necessary to propose a new technical solution to solve the above at least one technical problem. Summary of the Invention

[0006] The present disclosure provides a semiconductor packaging device and a manufacturing method thereof.

[0007] In a first aspect, the present disclosure provides a semiconductor packaging device, including:

[0008] A substrate having a first cavity and two first openings, wherein the first openings penetrate a first end of the substrate and communicate with the first cavity;

[0009] A first semiconductor element disposed on the substrate and covering one of the first openings.

[0010] In some alternative embodiments, a second semiconductor element is further disposed on the substrate, the second semiconductor element being located near the first semiconductor element and electrically connected to the first semiconductor element.

[0011] In some alternative embodiments, the second semiconductor element and the first semiconductor element are electrically connected through the substrate.

[0012] In some alternative embodiments, the first semiconductor element is located on an outer surface or an inner surface of the substrate.

[0013] In some alternative embodiments, the substrate is a three-layer board structure.

[0014] In some alternative embodiments, a first cover is further disposed at the first end of the substrate, a first partition portion is disposed inside the first cover, and the first cover, the first partition portion and the substrate enclose two adjacent second cavities, and each of the second cavities communicates with the first cavity through a corresponding first opening;

[0015] The first cover further has two second openings, and each of the second openings penetrates the first cover and communicates with a corresponding second cavity.

[0016] In some alternative embodiments, a second semiconductor element is further disposed on the substrate, the second semiconductor element being located near the first semiconductor element and electrically connected to the first semiconductor element, and the second semiconductor element and the first semiconductor element are respectively located in different second cavities.

[0017] In some alternative embodiments, two first protrusion portions are disposed on a surface of the first cover, and each of the second openings penetrates a corresponding first protrusion portion.

[0018] In some alternative embodiments, a second cover is further disposed on the first cover, a second partition portion is disposed inside the second cover, and the second cover, the second partition portion and the first cover enclose two adjacent third cavities, and each of the third cavities communicates with a corresponding second cavity through a corresponding second opening;

[0019] The second cover further has two third openings, each of the third openings respectively penetrating through the second cover and communicating with the corresponding third cavity, and two second protrusion parts are arranged on the surface of the second cover, and each of the second openings respectively penetrates through the corresponding second protrusion part.

[0020] In some alternative embodiments, the first semiconductor element has a sensing film, a first surface of the sensing film is in direct contact with the first cavity, and a second surface of the sensing film is in direct contact with the second cavity.

[0021] In a second aspect, the present disclosure further provides a semiconductor packaging device, including:

[0022] A substrate having a first cavity and two first openings, wherein the first openings penetrate through a first end of the substrate and communicate with the first cavity;

[0023] A first semiconductor element disposed on the substrate and covering one of the first openings;

[0024] A first cover disposed at the first end of the substrate, a first partition part is disposed in the first cover, the first cover, the first partition part and the substrate enclose two adjacent second cavities, and each of the second cavities respectively communicates with the first cavity through the corresponding first opening;

[0025] The first cover further has two second openings, each of the second openings respectively penetrating through the first cover and communicating with the corresponding second cavity.

[0026] In a third aspect, the present disclosure provides a manufacturing method of a semiconductor packaging device, including:

[0027] Providing a substrate, wherein the substrate has a first cavity and two first openings, and the first openings penetrate through a first end of the substrate and communicate with the first cavity;

[0028] Disposing a first semiconductor element and a second semiconductor element on the corresponding substrate to obtain a semiconductor packaging device, wherein the first semiconductor element covers one of the first openings, and the second semiconductor element is located near the first semiconductor element and is electrically connected to the first semiconductor element.

[0029] In some alternative embodiments, the providing the substrate includes:

[0030] Performing a singulation process on a substrate panel to obtain at least two substrates.

[0031] In some alternative embodiments, after the disposing the first semiconductor element and the second semiconductor element on the corresponding substrate, the method further includes:

[0032] A corresponding first cover is provided on the substrate. Wherein, a first partition portion is provided inside the first cover, and the first cover, the first partition portion and the substrate enclose two adjacent second cavities. Each of the second cavities is communicated with the first cavity through a corresponding first opening. The first cover further has two second openings, and each of the second openings penetrates through the first cover and is communicated with a corresponding second cavity.

[0033] In a fourth aspect, the present disclosure provides a manufacturing method of a semiconductor packaging device, including:

[0034] A corresponding first semiconductor element and a second semiconductor element are provided on each substrate in a substrate panel. Wherein, the substrate has a first cavity and two first openings. The first openings penetrate through a first end portion of the substrate and are communicated with the first cavity. The first semiconductor element covers one of the first openings, and the second semiconductor element is located near the first semiconductor element and is electrically connected to the first semiconductor element;

[0035] A first cover panel is disposed on the substrate panel. Wherein, the first cover panel includes at least two first covers. A first partition portion is provided inside the first cover. The first cover, the first partition portion and the substrate enclose two adjacent second cavities. Each of the second cavities is communicated with the first cavity through a corresponding first opening. The first cover further has two second openings, and each of the second openings penetrates through the first cover and is communicated with a corresponding second cavity;

[0036] The substrate panel and the first cover panel are singulated to obtain at least two packaging units;

[0037] A corresponding second cover is provided on each of the packaging units to obtain a semiconductor packaging device. Wherein, a second partition portion is provided inside the second cover. The second cover, the second partition portion and the first cover enclose two adjacent third cavities. Each of the third cavities is communicated with a corresponding second cavity through a corresponding second opening. The second cover further has two third openings, and each of the third openings penetrates through the second cover and is communicated with a corresponding third cavity. Two second protrusion portions are provided on the surface of the second cover, and each of the second openings penetrates through a corresponding second protrusion portion.

[0038] In the semiconductor packaging device and its manufacturing method provided by the present disclosure, a differential pressure gauge is formed using a substrate having a first cavity and two first openings, without involving the molding process in double-sided QFP. This can prevent the electrical connection of the semiconductor packaging device from being affected by the residual molding material, and avoid the difficulties in controlling the height of the adhesive and the overflow of the adhesive caused by the excessive surface roughness of the molding material, which is beneficial to improving the product yield. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] Other features, objects, and advantages of the present disclosure will become more apparent by reading the detailed description of the non-limiting embodiments with reference to the following drawings:

[0040] Figure 1A and Figure 1B are schematic diagrams of semiconductor packaging devices in the prior art;

[0041] Figures 2 - 6 are the first to fifth schematic diagrams of the semiconductor packaging device according to the embodiment of the present invention.

[0042] SYMBOL DESCRIPTION:

[0043] 11, lower molding material; 12, upper molding material; 13, pins; 14, cover; 15, capping; 16, microelectromechanical system chip; 17, application-specific integrated circuit chip; 18, connecting wires; 19, adhesive; 21, upper cavity; 22, lower cavity; 100, substrate; 110, first cavity; 120, first opening; 200, first cover; 210, second cavity; 220, second opening; 230, first protrusion; 240, first partition; 300, second cover; 310, third cavity; 320, third opening; 330, second protrusion; 340, second partition; 400, first semiconductor element; 500, second semiconductor element; 600, solder; 700, electrical connector; 800, connecting wire. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0044] The following will describe the specific embodiments of the present disclosure in conjunction with the drawings and embodiments. Those skilled in the art can easily understand the technical problems solved by the present disclosure and the technical effects generated through the content recorded in this specification. It can be understood that the specific embodiments described herein are only used to explain the relevant invention and are not intended to limit the invention. In addition, for the sake of convenience of description, only the parts related to the relevant invention are shown in the drawings.

[0045] It should be noted that the structures, ratios, sizes, etc. shown in the accompanying drawings of the specification are only used to cooperate with the content recorded in the specification for the understanding and reading of those skilled in the art, and are not used to limit the conditions for the implementation of the present disclosure. Therefore, they do not have substantial technical significance. Any modification of the structure, change of the proportional relationship, or adjustment of the size, without affecting the efficacy that the present disclosure can produce and the purpose that can be achieved, should still fall within the scope that can be covered by the technical content disclosed in the present disclosure. At the same time, terms such as "upper", "first", "second", and "one" cited in this specification are only for the convenience of clear narration, rather than used to limit the scope of implementation of the present disclosure. The change or adjustment of their relative relationships, without substantial change in the technical content, should also be regarded as the scope that the present disclosure can implement.

[0046] It should also be noted that the longitudinal section corresponding to the embodiment of the present disclosure can be the section corresponding to the front view direction, the transverse section can be the section corresponding to the right view direction, and the horizontal section can be the section corresponding to the top view direction.

[0047] It should be easily understood that the meanings of "on...", "above...", and "over..." in the present disclosure should be interpreted in the broadest sense, such that "on..." not only means "directly on something", but also means "on something" including intermediate components or layers between the two.

[0048] In addition, for the convenience of description, the present disclosure may use spatial relative terms such as "under...", "below...", "lower part", "above...", "upper part", etc. to describe the relationship between one element or component and another element or component shown in the accompanying drawings. In addition to the orientations described in the figures, the spatial relative terms are also intended to cover different orientations during the use or operation of the device. The device can be oriented in other ways (rotated 90° or in other orientations), and the spatial relative descriptive terms used in the present disclosure can be correspondingly interpreted in the same way.

[0049] In addition, without conflict, the embodiments in the present disclosure and the features in the embodiments can be combined with each other. The present disclosure will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0050] The embodiments of the present disclosure provide a semiconductor packaging device. Figures 2 - 6 are the first to fifth schematic diagrams of the semiconductor packaging device according to the embodiments of the present invention.

[0051] Figure 2 shows the longitudinal section of the semiconductor packaging device. As Figure 2As shown, the semiconductor packaging device includes a substrate 100 and a first semiconductor element 400. The substrate 100 has a first cavity 110 and two first openings 120. The first openings 120 penetrate through the first end portion of the substrate 100 (i.e., Figure 2 the upper end portion in

[0052] ), and are in communication with the first cavity 110. The first semiconductor element 400 is disposed on the outer surface of the substrate 100 and covers the first opening 120 on the left side. An electrical connector 700 is also disposed on the substrate 100 for realizing the external connection of the substrate 100. Figure 2 In this embodiment, the substrate 100 is a three-layer board structure. Three substrate 100 units can be stacked and joined (wherein, the middle-layer substrate 100 unit and the uppermost-layer substrate 100 unit have openings) to obtain

[0053] the substrate 100 in Figure 2 As shown, a second semiconductor element 500 is also disposed on the substrate 100. The second semiconductor element 500 is located near the first semiconductor element 400. The second semiconductor element 500 and the first semiconductor element 400 are electrically connected through the substrate 100.

[0054] In this embodiment, the first semiconductor element 400 is, for example, a Micro-Electro-Mechanical System (MEMS) chip, and the second semiconductor element 500 is, for example, an Application-Specific Integrated Circuit (ASIC) chip.

[0055] As Figure 2 shown, a first cover 200 is further disposed at the first end portion of the substrate 100. The substrate 100 and the first cover 200 are connected by solder 600. A first partition portion 240 is disposed in the first cover 200. The first cover 200 (as shown), the first partition portion 240, and the substrate 100 enclose two adjacent second cavities 210. Each second cavity 210 is respectively in communication with the first cavity 110 through a corresponding first opening 120. The first cover 200 also has two second openings 220. Each second opening 220 penetrates through the first cover 200 and is in communication with a corresponding second cavity 210. The second semiconductor element 500 and the first semiconductor element 400 are respectively located in different second cavities 210.

[0056] As Figure 2 shown, two first protrusion portions 230 are disposed on the surface of the first cover 200, and each second opening 220 penetrates through a corresponding first protrusion portion 230. As Figure 2As shown by the dashed line with an arrow, the gas in the external environment can enter the semiconductor packaging device through the second opening 220 on the first protrusion 230.

[0057] In this embodiment, the first semiconductor element 400 has a sensing film ( Figure 2 not shown in the figure). The first surface of the sensing film is in direct contact with the first cavity 110, and the second surface of the sensing film is in direct contact with the second cavity 210. Among them, the first cavity 110 communicates with the first pressure environment through the first opening 120 on the right, the second cavity 210 on the right, and the second opening 220 on the right. The second cavity 210 on the left communicates with the second pressure environment through the second opening 220 on the left. When there is a pressure difference between the first pressure environment and the second pressure environment, this pressure difference will cause the sensing film to deform, and then change the resistance value of the coil on the surface of the sensing film. According to the change value of the above resistance value, the pressure difference between the first pressure environment and the second pressure environment can be calculated.

[0058] Figure 3 shows Figure 2 the three-dimensional structure of the semiconductor packaging device in the figure. As Figure 3 shown, two first openings 120 are provided on the substrate 100. The first semiconductor element 400 covers the first opening 120 on the left. The second semiconductor element 500 is arranged on one side of the first opening 120 on the right. The first cover 200 covers the substrate 100 from above and forms two second cavities 210. The first semiconductor element 400 and the second semiconductor element 500 are respectively located in the two second cavities 210.

[0059] Figure 4 shows Figure 2 a deformation of the semiconductor packaging device in the figure. In Figure 2 this figure, the second semiconductor element 500 and the first semiconductor element 400 are respectively directly electrically connected to the substrate 100. While in Figure 4 this figure, the second semiconductor element 500 and the first semiconductor element 400 are respectively electrically connected to the substrate 100 through connecting wires 800.

[0060] Figure 5 shows Figure 4 a deformation of the semiconductor packaging device in the figure. In Figure 4 this figure, both the second semiconductor element 500 and the first semiconductor element 400 are located on the outer surface of the substrate 100. While in Figure 5 this figure, both the second semiconductor element 500 and the first semiconductor element 400 are located on the inner surface of the substrate 100.

[0061] Figure 6 shows Figure 4 a deformation of the semiconductor packaging device in the figure. In Figure 4In [reference], a single-layer cover is provided on the substrate 100. And in Figure 6 In [reference], a multi-layer cover is provided on the substrate 100. As Figure 6 shown, a first cover 200 is provided on the substrate 100. A second cover 300 is further provided on the first cover 200. A second partition 340 is provided inside the second cover 300. The second cover 300, the second partition 340 and the first cover 200 enclose two adjacent third cavities 310, and each third cavity 310 is respectively communicated with a corresponding second cavity 210 through a corresponding second opening 220. The second cover 300 further has two third openings 320. Each third opening 320 penetrates through the second cover 300 and is communicated with a corresponding third cavity 310. Two second protrusions 330 are provided on the surface of the second cover 300. Each second opening 220 penetrates through a corresponding second protrusion 330.

[0062] In Figure 6 [reference], the first cavity 110 can be communicated with the first pressure environment through the first opening 120 on the right side, the second cavity 210 on the right side, the second opening 220 on the right side, the third cavity 310 on the right side and the third opening 320 on the right side, and the second cavity 210 on the left side can be communicated with the second pressure environment through the second opening 220 on the left side, the third cavity 310 on the left side and the third opening 320 on the left side.

[0063] For Figure 6 the semiconductor packaging device in [reference], its manufacturing process can be based on the panel form for batch operation, so as to improve production efficiency. For details, please refer to the following description.

[0064] In the semiconductor packaging device of this embodiment, a differential pressure gauge is formed by using the substrate 100 having the first cavity 110 and two first openings 120. It does not involve the molding process in the double-sided QFP, which can prevent the influence of the residual molding material on the electrical connection of the semiconductor packaging device, and avoid the difficulties in controlling the height of the adhesive and the overflow of the adhesive caused by the too large surface roughness of the molding material, which is beneficial to improving the product yield.

[0065] The present disclosure embodiment also provides a manufacturing method of a semiconductor packaging device, and this manufacturing method can be used to manufacture the semiconductor packaging device as Figure 2 shown. Referring to Figure 2 , this method includes the following steps:

[0066] The first step is to provide a substrate 100, wherein the substrate 100 has a first cavity 110 and two first openings 120, and the first opening 120 penetrates through the first end of the substrate 100 and is communicated with the first cavity 110.

[0067] Second step, dispose the first semiconductor element 400 and the second semiconductor element 500 on corresponding substrates 100 to obtain a semiconductor packaging device, wherein the first semiconductor element 400 covers a first opening 120, and the second semiconductor element 500 is located near the first semiconductor element 400 and is electrically connected to the first semiconductor element 400.

[0068] In some alternative embodiments, the first step further includes: performing a singulation process on the substrate panel to obtain at least two substrates 100.

[0069] In some alternative embodiments, after the second step, the method may further include the following steps: dispose a corresponding first cover 200 on the substrate 100, wherein a first partition 240 is disposed in the first cover 200, and the first cover 200, the first partition 240 and the substrate 100 enclose two adjacent second cavities 210. Each second cavity 210 communicates with the first cavity 110 through a corresponding first opening 120. The first cover 200 further has two second openings 220, and each second opening 220 penetrates through the first cover 200 and communicates with a corresponding second cavity 210.

[0070] The manufacturing method of the semiconductor packaging device provided by the embodiments of the present disclosure can achieve similar technical effects to those of the semiconductor packaging device described above, which will not be elaborated here.

[0071] The embodiments of the present disclosure also provide another manufacturing method of a semiconductor packaging device. This manufacturing method can be used to manufacture a semiconductor packaging device as Figure 6 shown. Referring to Figure 6 , the method includes the following steps:

[0072] First step, dispose a corresponding first semiconductor element 400 and a second semiconductor element 500 on each substrate 100 in the substrate panel, wherein the substrate 100 has a first cavity 110 and two first openings 120. The first openings 120 penetrate through the first end of the substrate 100 and communicate with the first cavity 110. The first semiconductor element 400 covers one of the first openings 120, and the second semiconductor element 500 is located near the first semiconductor element 400 and is electrically connected to the first semiconductor element 400.

[0073] In the second step, the first cover panel is disposed on the substrate panel. The first cover panel includes at least two first covers 200. A first partition portion 240 is disposed inside the first cover 200. The first cover 200, the first partition portion 240, and the substrate 100 enclose two adjacent second cavities 210. Each second cavity 210 is respectively communicated with the first cavity 110 through a corresponding first opening 120. The first cover 200 further has two second openings 220. Each second opening 220 penetrates through the first cover 200 and is communicated with a corresponding second cavity 210.

[0074] In the third step, the substrate panel and the first cover panel are singulated to obtain at least two packaging units.

[0075] In the fourth step, corresponding second covers 300 are disposed on each packaging unit to obtain a semiconductor packaging device. A second partition portion 340 is disposed inside the second cover 300. The second cover 300, the second partition portion 340, and the first cover 200 enclose two adjacent third cavities 310. Each third cavity 310 is respectively communicated with a corresponding second cavity 210 through a corresponding second opening 220. The second cover 300 further has two third openings 320. Each third opening 320 penetrates through the second cover 300 and is communicated with a corresponding third cavity 310. Two second protrusion portions 330 are disposed on the surface of the second cover 300. Each second opening 220 penetrates through a corresponding second protrusion portion 330.

[0076] The manufacturing method of the semiconductor packaging device provided by the embodiments of the present disclosure can achieve similar technical effects as those of the semiconductor packaging device described above, which will not be elaborated here.

[0077] In addition, Figure 4 The shown semiconductor packaging device adopts a single-layer cover. Since there is a first protrusion portion 230 above the first cover 200, it cannot be placed flat for singulation, so it cannot be formed in batches. For the structures other than the first cover 200, since the chip and the connection line 800 are exposed, they are easily contaminated during singulation, so they cannot be formed in batches either. And Figure 6 The shown semiconductor packaging device adopts a multi-layer cover. On the one hand, the first cover 200 can protect the chip and the connection line 800 from contamination during the singulation step. On the other hand, the upper surface of the first cover 200 is a flat surface and can be placed flat for singulation. Therefore, for Figure 6 the semiconductor packaging device in, the steps before disposing the second cover 300 can all be carried out in batch in the form of a panel, which is beneficial to improving production efficiency.

[0078] Although the present disclosure has been described and illustrated with reference to specific embodiments thereof, such description and illustration do not limit the present disclosure. Those skilled in the art will clearly understand that various changes can be made, and equivalent elements can be substituted within the embodiments without departing from the true spirit and scope of the present disclosure as defined by the appended claims. The drawings may not necessarily be drawn to scale. There may be differences between the technical reproductions and the actual devices in the present disclosure due to variables in the manufacturing process and so on. There may be other embodiments of the present disclosure that are not specifically described. The specification and the drawings should be regarded as illustrative rather than restrictive. Modifications can be made to adapt a particular situation, material, composition of matter, method, or process to the objectives, spirit, and scope of the present disclosure. All such modifications fall within the scope of the appended claims herein. Although the methods disclosed in the present disclosure have been described with reference to specific operations performed in a particular order, it should be understood that these operations can be combined, subdivided, or reordered without departing from the teachings of the present disclosure to form equivalent methods. Therefore, unless specifically indicated in the present disclosure, the order and grouping of the operations do not limit the present disclosure.

Claims

1. A semiconductor packaging device, comprising: A substrate having a first cavity and two first openings, wherein the first openings penetrate through a first end of the substrate and communicate with the first cavity; A first semiconductor element disposed on the substrate and covering one of the first openings; A first cover is further disposed at the first end of the substrate. A first partition is disposed inside the first cover. The first cover, the first partition and the substrate enclose two adjacent second cavities, and each of the second cavities communicates with the first cavity through a corresponding first opening; The first cover further has two second openings, and each of the second openings penetrates through the first cover and communicates with a corresponding second cavity; A second cover is further disposed on the first cover. A second partition is disposed inside the second cover. The second cover, the second partition and the first cover enclose two adjacent third cavities, and each of the third cavities communicates with a corresponding second cavity through a corresponding second opening; The second cover further has two third openings, and each of the third openings penetrates through the second cover and communicates with a corresponding third cavity. Two second protrusions are disposed on the surface of the second cover, and each of the second openings penetrates through a corresponding second protrusion.

2. The semiconductor packaging device according to claim 1, wherein, A second semiconductor element is further disposed on the substrate. The second semiconductor element is located near the first semiconductor element and is electrically connected to the first semiconductor element.

3. The semiconductor packaging device according to claim 2, wherein, The second semiconductor element and the first semiconductor element are electrically connected through the substrate.

4. The semiconductor packaging device according to claim 1, wherein, The first semiconductor element is located on the outer surface or the inner surface of the substrate.

5. The semiconductor package device according to claim 1, wherein, The substrate has a three-layer board structure.

6. The semiconductor package device according to claim 1, wherein, A second semiconductor element is further disposed on the substrate. The second semiconductor element is located near the first semiconductor element and is electrically connected to the first semiconductor element. The second semiconductor element and the first semiconductor element are respectively located in different second cavities.

7. The semiconductor packaging device according to claim 1, wherein Two first protrusions are disposed on the surface of the first cover, and each of the second openings penetrates through a corresponding first protrusion.

8. The semiconductor packaging device according to claim 1, wherein, The first semiconductor element has a sensing film. A first surface of the sensing film is in direct contact with the first cavity, and a second surface of the sensing film is in direct contact with the second cavity.

9. A semiconductor packaging device, comprising: A substrate having a first cavity and two first openings, wherein the first openings penetrate through a first end of the substrate and communicate with the first cavity; A first semiconductor element disposed on the substrate and covering one of the first openings; A first cover disposed at the first end of the substrate. A first partition is disposed inside the first cover. The first cover, the first partition and the substrate enclose two adjacent second cavities, and each of the second cavities communicates with the first cavity through a corresponding first opening; The first cover further has two second openings, and each of the second openings penetrates through the first cover and communicates with a corresponding second cavity; A second cover is provided on the first cover. A second partition portion is provided inside the second cover. The second cover, the second partition portion and the first cover enclose two adjacent third cavities. Each of the third cavities is communicated with a corresponding second cavity through a corresponding second opening. The second cover further has two third openings. Each of the third openings penetrates through the second cover and is communicated with a corresponding third cavity. Two second protrusion portions are provided on the surface of the second cover. Each of the second openings penetrates through a corresponding second protrusion portion.

10. A manufacturing method of a semiconductor packaging device, comprising: Providing a substrate, the substrate having a first cavity and two first openings, the first openings penetrating through a first end portion of the substrate and being communicated with the first cavity; Arranging a first semiconductor element and a second semiconductor element on the corresponding substrate to obtain a semiconductor packaging device, wherein the first semiconductor element covers one of the first openings, and the second semiconductor element is located near the first semiconductor element and is electrically connected to the first semiconductor element; After arranging the first semiconductor element and the second semiconductor element on the corresponding substrate, the method further comprises: Arranging a corresponding first cover on the substrate, wherein a first partition portion is provided inside the first cover, the first cover, the first partition portion and the substrate enclose two adjacent second cavities, each of the second cavities is communicated with the first cavity through a corresponding first opening, and the first cover further has two second openings, each of the second openings penetrating through the first cover and being communicated with a corresponding second cavity; Performing a singulation process on the substrate panel to obtain at least two packaging units; Arranging a corresponding second cover on each of the packaging units to obtain a semiconductor packaging device, wherein a second partition portion is provided inside the second cover, the second cover, the second partition portion and the first cover enclose two adjacent third cavities, each of the third cavities is communicated with a corresponding second cavity through a corresponding second opening; the second cover further has two third openings, each of the third openings penetrating through the second cover and being communicated with a corresponding third cavity, and two second protrusion portions are provided on the surface of the second cover, and each of the second openings penetrates through a corresponding second protrusion portion.

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