Programmable logic device and its memory management system

Abstract

The application discloses a programmable logic device and a memory management system thereof, and belongs to the field of integrated circuit design. The programmable logic device comprises a wiring resource management module, a user information management module, a temporary container management module and a parameter management module. The wiring resource management module is used for inputting wiring resource information of a chip into a preset wiring resource graph, and performing read-write access control on the wiring resource in the wiring resource graph through a preset wiring resource manager. The user information management module is used for storing connection information of a user-designed circuit to be wired. The temporary container management module is used for temporarily constructing at least one memory pool when the programmable logic device executes a wiring algorithm process, and the memory pool stores a plurality of temporary wiring containers. The parameter management module is used for managing wiring parameters required by the programmable logic device when executing the wiring algorithm process. The application can support multiple CPU cores to execute a parallel wiring algorithm process, reduce the occurrence of access conflicts of excessive critical resources, improve the development efficiency of the wiring algorithm, and thus speed up the overall wiring process.

Description

Technical Field

[0001] The present invention belongs to the field of integrated circuit design, and relates to field programmable logic device (PLD) integrated circuit software tool design technology, and in particular to a PLD and its memory management system. Background Art

[0002] When a programmable logic device executes a routing algorithm process (including a serial routing algorithm process and a parallel routing algorithm process), it will call the routing data in the programmable logic device memory (storage). If the routing data in the programmable logic device memory can be managed efficiently, the development efficiency of the routing algorithm can be greatly improved, thereby speeding up the overall routing process.

[0003] Most existing programmable logic devices use a serial process for integrated circuit design. In order to adapt to the serial wiring algorithm process when managing memory, the programmable logic device cannot implement memory management by having multiple CPU cores execute parallel wiring algorithm processes in actual operation. This is prone to access conflicts caused by excessive critical resources. This will reduce the efficiency of wiring algorithm development in the integrated circuit design process and slow down the overall wiring process.

[0004] Some existing programmable logic devices (PLDs) use a parallel process for integrated circuit design. These PLDs do not uniformly organize or partition the routing data within the memory when managing memory. Instead, they allow the routers corresponding to each parallel thread to independently access the routing data within the memory as needed while completing their respective routing algorithm tasks. This results in a complex memory management approach and is prone to access conflicts caused by excessive critical resources. This also reduces the efficiency of routing algorithm development during the IC design process, slowing the overall routing process. Summary of the Invention

[0005] The embodiment of the present invention provides a programmable logic device and its memory management system, which can support multiple CPU cores to execute parallel routing algorithm processes, reduce the occurrence of access conflicts caused by excessive critical resources, improve the development efficiency of routing algorithms, and thus speed up the overall routing process.

[0006] The technical solution of the present invention is as follows: providing a memory management system for a programmable logic device, the memory management system comprising:

[0007] A wiring resource management module, configured to input the wiring resource information of the chip into a preset wiring resource map, and perform read and write access control on the wiring resources in the wiring resource map through a preset wiring resource manager;

[0008] User information management module, used to store the connection information of each user-designed circuit to be routed;

[0009] a temporary container management module, configured to temporarily construct at least one memory pool when the programmable logic device executes a routing algorithm process, wherein the memory pool stores a plurality of temporary routing containers, and wherein the temporary routing containers are configured to store temporary data generated when the programmable logic device executes the routing algorithm process;

[0010] The parameter management module is used to manage the wiring parameters required by the programmable logic device when executing the wiring algorithm process.

[0011] Preferably, the wiring resource management module includes:

[0012] A resource map entry unit is used to classify the wiring resources in the chip and enter the classified wiring resources into the wiring resource map according to the preset operation logic of the programmable logic device;

[0013] The resource manager unit is used to determine whether a routing module of a programmable logic device needs to be locked by the routing resource manager when accessing the routing resource map.

[0014] Preferably, the resource manager module is further configured to provide an access interface for each agent in the routing algorithm process, and to declare all writing methods of the routing resource graph to be privately owned by the routing resource manager.

[0015] Preferably, the temporary container management module includes:

[0016] A temporary array management unit, configured to manage a temporary array, wherein the temporary array is used to store temporary data;

[0017] The temporary linked list management unit is used to manage a temporary linked list, where the temporary linked list is used to temporarily store a table required by the programmable logic device when executing a routing algorithm process.

[0018] Preferably, the temporary array management unit is further configured to determine whether the language executing the routing algorithm process in the programmable logic device is a computer language capable of self-managing memory; if so, clearing the memory data index of the computer language when executing the routing algorithm process to allow the computer language to self-manage its own memory data; if not, destroying the memory data of the computer language of the routing algorithm process at the end of the routing algorithm process;

[0019] The temporary linked list management unit is further configured to apply for corresponding memory for different temporary linked lists through a preset block allocator, and at least one temporary linked list is correspondingly provided in the memory.

[0020] Preferably, the parameter management module includes:

[0021] A hyperparameter management unit, configured to manage a hyperparameter, wherein the hyperparameter is a first routing parameter that does not change when the programmable logic device executes a routing algorithm process;

[0022] The adaptive parameter management unit is used to manage the adaptive parameter, where the adaptive parameter is a second wiring parameter that the programmable logic device will adaptively adjust when executing the wiring algorithm process.

[0023] Preferably, the hyperparameter management unit is further configured to set a plurality of hyperparameters according to the circuit connection information designed by the user, obtain a set of hyperparameters that can optimize the user's design timing from the plurality of hyperparameters, and send the obtained hyperparameters to the routing module of the programmable logic device;

[0024] The adaptive parameter management unit is further configured to adjust the adaptive parameters when the routing algorithm flow of the programmable logic device changes, and send the adjusted adaptive parameters to the routing module of the programmable logic device.

[0025] Preferably, the hyperparameter management unit is further configured to obtain read-only parameters uniformly read into the programmable logic device before executing the routing algorithm process, and send the obtained read-only parameters to the routing module of the programmable logic device.

[0026] Another technical solution of the present invention is to provide a programmable logic device, including a memory management system of the programmable logic device.

[0027] The programmable logic device executes a multi-threaded parallel routing process. When executing the routing process, at least one router is arranged in each thread, and each thread executes the routing algorithm process of its own thread through its own router.

[0028] When executing the routing algorithm for each thread, the router calls upon routing resources within the chip's memory. Routing resources can be called through the routing resource manager or directly. However, write-only resources within the routing resource graph must be called through the routing resource manager. In this case, the inventors have allocated a separate memory area (resource graph management module) to house and manage the routing resource graph and routing resource manager.

[0029] When executing the routing algorithm process of each thread, the router directly calls the user design information. That is, when the router is running, it directly reads the connection information of each user-designed circuit to be routed. At this time, the inventors have allocated a separate memory area (user information management module) to store and manage this user design information.

[0030] When the router executes the routing algorithm process of each thread, some data will be created when the routing algorithm starts and destroyed when the routing algorithm ends. The containers (temporary arrays and temporary tables) that store this temporary data are also temporary routing containers. The inventors have allocated a separate memory area (temporary container management module) to manage these temporary routing containers.

[0031] When executing the routing algorithm flow of each thread, the router will call some routing parameters. In order to speed up the routing, the inventors have allocated a separate memory interval (parameter management module) to manage these routing parameters, which include hyperparameters and adaptive parameters.

[0032] Compared with the prior art, the present invention has the following beneficial effects:

[0033] 1. The present invention not only enables the wiring unit of a programmable logic device to more conveniently and quickly call the wiring data (memory data) in the memory, but also minimizes access conflicts caused by excessive critical resources, thereby improving the development efficiency of the wiring algorithm and speeding up the overall wiring process;

[0034] 2. The present invention is not only applicable to the memory management of serial and parallel routing algorithm flows, but is also particularly applicable to the memory management of ultra-large-scale programmable logic devices that execute multi-threaded parallel routing algorithm flows. When the ultra-large-scale programmable logic device executes the routing algorithm flow using multi-threaded parallel routing, if the memory management system described in the present invention is used to manage the memory of the programmable logic device, the parallel routing algorithm speed and the development efficiency of the parallel routing algorithm can be significantly improved.

[0035] 3. When a very large-scale programmable logic device employs the memory management system described in the present invention, the programmable logic device can perform wiring operations independently using only one PC, eliminating the need for multiple PCs to perform distributed collaborative operations. Thus, the present invention can significantly improve the efficiency of developing wiring algorithms, thereby accelerating the overall wiring process.

[0036] 4. The memory in the present invention mainly refers to the memory used to store the internal data of the programmable logic device. Managing the memory means dividing the memory into multiple different storage areas (i.e., different management and control modules) and adopting different operation modes to ensure that the wiring module of the programmable logic device can access the memory more conveniently and quickly.

[0037] 5. The present invention mainly adopts different management control modules to perform memory management for different types of internal module objects inside the programmable logic device, so that the existing programmable logic device can effectively respond to the control needs of critical resource access when executing the wiring algorithm process (especially the multi-threaded parallel wiring algorithm process), thereby improving the wiring rate of the programmable logic device. Among them, the programmable logic device of the present invention can be an ultra-large-scale programmable logic device (such as an FPGA chip), and the internal module includes a wiring resource map, wiring parameters, temporary wiring containers, etc. The management control module includes a resource map management module, a temporary container management module and a parameter management module, etc. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments of the present invention. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0039] Figure 1 It is a structural diagram of the memory management system of the programmable logic device described in the present invention.

[0040] Figure 2 This is a schematic diagram of the layout resource graph access read and write control of the present invention;

[0041] Figure 3 This is a schematic diagram of how to access a multi-threaded memory pool in a very large-scale programmable device. DETAILED DESCRIPTION

[0042] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. All other embodiments obtained by ordinary technicians in this field based on the embodiments of the present invention without making any creative efforts shall fall within the scope of protection of the present invention.

[0043] The terms "first", "second", and "third" in the present invention are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, a feature defined as "first", "second", and "third" may explicitly or implicitly include at least one of the features. In the description of the present invention, "multiple" means at least two, for example, two, three, etc., unless otherwise clearly and specifically defined. All directional indications in the embodiments of the present invention (such as up, down, left, right, front, back, etc.) are only used to explain the relative positional relationship, movement, etc. between the components under a specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indication will also change accordingly. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product, or device that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units that are not listed, or may optionally include other steps or units that are inherent to these processes, methods, products, or devices.

[0044] Reference herein to an "embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment may be included in at least one embodiment of the present invention. The appearance of this phrase in various places in the specification does not necessarily refer to the same embodiment, nor does it constitute a separate or alternative embodiment that is mutually exclusive of other embodiments. It is understood, both explicitly and implicitly, by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0045] Existing routing algorithms for programmable logic devices (PLDs), such as FPGAs, are mostly executed serially. During routing algorithm execution, memory management methods are primarily tailored to the needs of serial routing algorithms. Therefore, most existing PLD memory management methods are unsuitable for multi-threaded parallel routing algorithms. For multi-threaded parallel routing, PLD memory management needs to be redesigned to address the need to control access to critical resources, thereby improving overall routing speed.

[0046] At the same time, for ultra-large-scale programmable logic devices (such as FPGA chips), parallel wiring algorithms can further improve the compilation rate of user designs. Currently, the use of parallel wiring has become a trend.

[0047] like Figure 1 As shown, the present invention provides a memory management method (particularly suitable for multi-threaded parallel routing algorithms) in field programmable logic device (referred to as programmable device, such as FPGA chip) integrated circuit software tools, which can effectively improve the efficiency of parallel routing algorithm development, accelerate the overall routing process, and enhance the user experience of EDA tools.

[0048] Figure 1 It is a structural diagram of a memory management system of a programmable logic device according to a first embodiment of the present invention. The memory management system is applied to a wiring algorithm process of a programmable logic device, and is particularly suitable for a multi-threaded parallel wiring process.

[0049] like Figure 1 As shown, the present invention mainly divides the memory data of the programmable logic device into multiple different types of internal modules, and adopts different management control modules to manage different types of internal module objects.

[0050] The internal module 91 includes a wiring resource map 11, a wiring resource manager 12, user design information 2, a temporary wiring container 3 and wiring parameters 4, wherein the temporary wiring container 3 includes a temporary array 31 and a temporary linked list 32, and the wiring parameters 4 include hyperparameters 41 and adaptive parameters 42.

[0051] The management control module 92 includes: a wiring resource management module 5, a user information storage module 6, a temporary container management module 7 and a parameter management module 8, wherein the wiring resource management module 5 includes a resource map entry unit 51 and a resource manager unit 52, the temporary container management module 7 includes a temporary array management unit 71 and a temporary linked list management unit 72, and the parameter management module 8 includes a hyperparameter management unit 81 and an adaptive parameter management unit 82.

[0052] The wiring resource management module 5 is used to enter the wiring resource information of the chip into a preset wiring resource map 11 , and perform read and write access control on the wiring resources in the wiring resource map through a preset wiring resource manager 12 .

[0053] In this embodiment, the wiring resource map 11 primarily records chip structural information (wiring resource information) to facilitate subsequent wiring operations, while the wiring resource manager 12 primarily controls read and write access. During wiring (particularly during multi-threaded parallel wiring), the corresponding wiring nodes within the programmable logic device (PLD) contain additional wiring information. This requires the routing module within the PLD to read and write access to the wiring resource map 11. In this case, the present invention utilizes the wiring resource manager 12 to perform read and write access control, further improving the efficiency of the routing algorithm.

[0054] The resource map entry module is used to classify the wiring resources in the chip and enter the classified wiring resources into the wiring resource map according to the preset operating logic of the programmable logic device, so that the router (wiring unit) can perform read and write operations on the wiring resources.

[0055] The resource manager module is used to determine whether the wiring module of the programmable logic device needs to be locked through the wiring resource manager when accessing the wiring resource map based on the actual usage of the wiring resources (or based on the work experience of the on-site staff).

[0056] In actual work, Figure 2 As shown in the schematic diagram of read and write control of access to the layout resource graph, when the router performs read and write operations on the wiring resource graph, different wiring resources require read and write access control according to different situations for the wiring resource graph. For example, in order to prevent external objects from arbitrarily writing to corresponding resource objects, the present invention can add access control for writes through the wiring resource manager. All write operations are proxied through the wiring resource manager, and no access control is required for reads.

[0057] Furthermore, in order to more strictly perform read and write access control on the wiring resource graph, the present invention can also allow the router to perform read and write operations on the wiring resource graph only through the wiring resource manager.

[0058] Furthermore, in order to more strictly implement read and write access control on the wiring resource graph, the resource manager module is also used to provide an access interface for each agent in the wiring algorithm process, and declare all writing methods of the wiring resource graph as private to the wiring resource manager.

[0059] In practice, the wiring resource graph of the present invention is an abstraction of chip wiring resources (chip structure information). It exists throughout the entire programmable logic device routing algorithm process. Write access control effectively prevents multiple threads from modifying data simultaneously, thus preventing unexpected errors during the execution of multi-threaded parallel routing algorithms. The wiring resource manager of the present invention primarily provides access interfaces for various agents, enabling read and write operations on the resource graph.

[0060] To prevent other external modules from writing resource objects (such as new wiring nodes, new wiring resources, etc.) that cannot be entered into the wiring resource map, the present invention can declare all write methods of the wiring resource map as private. Only the wiring resource manager is a friend of the wiring resource map, so that external objects can only write to corresponding resource objects (wiring resources) through the wiring resource manager. In actual operation, whether locking is required when writing wiring resources into the wiring resource map depends on the specific usage of the corresponding wiring resources (here the staff can handle it based on their own experience and historical records), which will not be elaborated here.

[0061] The user information storage module 6 is used to store user design information 2. The user design information 2 refers to the connection information of each user design circuit to be routed obtained after the user's design is synthesized and laid out.

[0062] In the embodiment, the user design information 2 is generally not written again after being read for the parallel routing algorithm process. Meanwhile, the connection relationship between the user circuit design units (i.e. user design circuit connection information) is determined after the user's RTL is loaded and the layout is completed, and the timing information can be calculated in advance, so the user design information 2 is a read-only resource in the whole routing process.

[0063] The temporary container placement module 7 is used to temporarily construct at least one memory pool when the programmable logic device executes the routing algorithm process, and the memory pool stores a plurality of temporary routing containers, which are used to store temporary data generated by the programmable logic device when executing the routing algorithm process. The temporary container placement module includes a temporary array management unit for managing temporary arrays and a temporary linked list management unit for managing temporary linked lists.

[0064] In actual work, when the super large programmable logic device adopts the multi-thread parallel routing algorithm process, for example, Figure 3 As shown in the multi-thread memory pool access schematic diagram, because the programmable logic device has a global memory lock, the programmable logic device may encounter a parallel bottleneck in memory management, and the routing temporary container disclosed in the present application can solve the above problem. At this time, the present application can select a plurality of multi-thread memory pools (i.e. arranging a plurality of routing temporary containers in each thread) or a custom block memory pool (i.e. customizing a routing temporary container with a larger volume).

[0065] In the present application, the routing temporary container refers to a hash table, a priority queue, a stack, an array, a linked list, a path tree and other temporary linked lists or temporary arrays used in the execution process of the routing algorithm. The temporary linked lists or temporary arrays can realize a specific memory allocation function (can be used as a memory allocator) when the programmable logic device executes the routing algorithm process (especially the multi-thread parallel routing algorithm process), thereby improving the running efficiency of the routing algorithm (especially the multi-thread parallel routing algorithm process).

[0066] In the embodiment, the temporary routing container includes a temporary array and a temporary linked list, and the temporary array is used to store temporary data. The temporary data refers to memory data created with the start of the routing algorithm process and destroyed with the end of the routing algorithm process. The temporary linked list is a table needed in the routing algorithm process.

[0067] The temporary array management unit is also used to determine whether the language executing the wiring algorithm process in the programmable logic device is a computer language that can manage its own memory; if so, the memory data index of the computer language is cleared when the wiring algorithm process is executed to allow the computer language to manage its own memory data; if not, the memory data of the computer language of the wiring algorithm process is destroyed at the end of the wiring algorithm process.

[0068] In actual operation, the temporary array of the present invention is a continuous storage space of the array type, such as a hash table, priority queue, stack, etc. These temporary arrays should be created when the routing algorithm process starts and destroyed when the routing algorithm process ends in the thread running the routing algorithm. Temporary arrays can avoid frequent memory requests. When cleaning, if using a language that manages its own memory, such as C / C++, there is no need to clean up the specific content. Only the corresponding index needs to be cleared, which can improve the algorithm iteration rate.

[0069] The temporary linked list management unit is further used to apply for different memories through a preset block allocator according to different wiring resources, and each page of memory is correspondingly provided with at least one temporary linked list.

[0070] In actual operation, the temporary linked list of the present invention is a container data structure of the linked list type, such as a multi-branch tree, a bidirectional linked list, etc. These temporary linked lists can realize specific memory allocation functions. The temporary linked list can use a block allocator to apply for dedicated memory one by one. The block allocator is a tool built into the programmable logic device. The main function of the block allocator is to allocate pages of memory in advance. Each page of memory is a storage space of several corresponding volumes (for placing temporary linked lists). The temporary linked lists of the present invention are taken out one at a time and returned when they are used. Because in the wiring process, the memory data is cleaned up uniformly after the iteration is completed, and because the objects inside the temporary linked list are either pointers or some objects that do not need to delete additional data, the present invention can implement a corresponding method of quickly cleaning the index to clear the temporary linked list without cleaning the contents inside the temporary linked list, thereby improving the wiring speed of the programmable logic device.

[0071] The parameter management module is used to manage the wiring parameters required by the programmable logic device when executing the wiring algorithm process. Some of the above wiring parameters are user-configured, and some can adaptively adjust some behaviors of the wiring algorithm. In the wiring algorithm process (especially the multi-threaded parallel wiring algorithm process), these wiring parameters need to be stored and processed separately. If certain wiring parameters are illegally modified, inconsistencies may occur between the wiring instances of different wiring algorithm processes. The wiring module in the programmable logic device of the present invention must ensure that when all kinds of setting parameters are the same, the results of each compilation of the user design are the same.

[0072] The parameter management module comprises a hyperparameter management unit for managing hyperparameters and an adaptive parameter management unit for managing adaptive parameters. The hyperparameters in the application are first routing parameters that do not change when the programmable logic device executes the routing algorithm process, and the adaptive parameters are second routing parameters that are adaptively adjusted when the programmable logic device executes the routing algorithm process.

[0073] The hyperparameter management unit is further configured to set a plurality of hyperparameters according to circuit connection information designed by a user, obtain a set of hyperparameters that can optimize the timing of the user's design from the plurality of hyperparameters, and send the obtained hyperparameters to a routing module of the programmable logic device. In this way, the routing module can more conveniently and quickly call the hyperparameters according to its own needs, thereby improving the routing speed of the programmable logic device.

[0074] Further, the hyperparameter management unit is further configured to obtain read-only parameters that are uniformly read by the programmable logic device before executing the routing algorithm process, to prevent external modules from re-writing or modifying the read-only parameters, and to send the obtained read-only parameters to the routing module of the programmable logic device. The read-only parameters can be hyperparameters. Furthermore, the hyperparameter management unit can package the hyperparameters together and then send them to the routing module of the programmable logic device, to further improve the routing speed of the programmable logic device.

[0075] In the embodiment, the hyperparameters do not change during the entire routing process, so the hyperparameters can be uniformly placed and set as read-only, and are uniformly read before executing the routing. The hyperparameters of the application sometimes also involve training issues, such as for a certain type of user-designed test set, batch automatic hyperparameter setting can be performed to search for an optimal set of hyperparameter settings, so that the timing of the user's design in a specific test set is best after the routing ends.

[0076] The adaptive parameter management unit is further configured to adjust the adaptive parameters when the routing algorithm process of the programmable logic device changes, and to send the adjusted adaptive parameters to the routing module of the programmable logic device. Preferably, the adaptive parameter management unit can also package the adaptive parameters together and then send them to the routing module of the programmable logic device, to further improve the routing speed of the programmable logic device.

[0077] In this embodiment, when a large-scale programmable logic device executes a multi-threaded parallel routing algorithm process, each parallel thread of the programmable logic device needs to have its own copy of the above-mentioned adaptive parameters, so that each parallel thread does not affect each other when executing the routing algorithm process of its own thread through its own router. When a parallel thread of the programmable logic device adjusts its own routing process (such as the read-write control behavior of the router), the parallel thread can perform adaptive adjustments through its own built-in adaptive parameters, so that the parallel thread does not affect the routing algorithm process of other parallel threads. Furthermore, in some special parallel threads, when certain adaptive parameters undergo adaptive changes, they will also affect other parallel threads. At this time, the programmable logic device only needs to preset the corresponding algorithm.

[0078] The present invention also provides a programmable logic device, including a memory management system for the programmable logic device. The programmable logic device of the present invention further includes a parallel routing module. When executing a routing algorithm, the parallel routing module accesses memory within the programmable logic device through the memory management system. The parallel routing module is configured to deploy at least one router within each thread, with the routers within each thread executing the routing algorithm within their respective threads, thereby executing a multi-threaded parallel routing process.

[0079] The present invention takes the multi-threaded parallel routing algorithm process as an example and combines the memory management system described in the present invention to illustrate the implementation scheme of the programmable logic device, as follows:

[0080] The programmable logic device executes a multi-threaded parallel routing process, and when executing the parallel routing process, each thread executes its own routing algorithm process through its own router;

[0081] When executing the routing algorithm flow of each thread, the router will call the routing resources within the chip memory. This can be done through the routing resource manager or directly. However, write-only resources within the routing resource graph must be called through the routing resource manager. In this case, the present invention allocates a separate memory area (resource graph management module) to store and manage the routing resource graph and routing resource manager.

[0082] When executing the routing algorithm process of each thread, the router will directly call the user design information. That is, the router will directly read the connection information of each user-designed circuit to be routed during operation. At this time, the present invention allocates a separate memory area (user information management module) to store and manage this user design information.

[0083] When the router executes the routing algorithm process of each thread, some data will be created when the routing algorithm starts and destroyed when the routing algorithm ends. The containers (temporary arrays and temporary tables) that store this temporary data are also called temporary routing containers. The present invention allocates a separate memory area (temporary container management module) to manage these temporary routing containers.

[0084] When executing the routing algorithm flow of each thread, the router will call some routing parameters. In order to speed up the routing, the present invention allocates a separate memory area (parameter management module) to manage these routing parameters, which include hyperparameters and adaptive parameters.

[0085] The above description is only an embodiment of the present invention. It should be pointed out that those skilled in the art can make improvements without departing from the creative concept of the present invention, but these improvements all fall within the scope of protection of the present invention.

Claims

1. A memory management system for a programmable logic device, characterized in that: The memory management system includes: A wiring resource management module, configured to input the wiring resource information of the chip into a preset wiring resource map, and perform read and write access control on the wiring resources in the wiring resource map through a preset wiring resource manager; User information management module, used to store the connection information of each user-designed circuit to be routed; a temporary container management module, configured to temporarily construct at least one memory pool when the programmable logic device executes a routing algorithm process, wherein the memory pool stores a plurality of temporary routing containers, and wherein the temporary routing containers are configured to store temporary data generated when the programmable logic device executes the routing algorithm process; A parameter management module, used to manage the wiring parameters required by the programmable logic device when executing the wiring algorithm process; The parameter management module includes: A hyperparameter management unit, configured to manage a hyperparameter, wherein the hyperparameter is a first routing parameter that does not change when the programmable logic device executes a routing algorithm process; An adaptive parameter management unit, configured to manage an adaptive parameter, wherein the adaptive parameter is a second routing parameter that is adaptively adjusted by the programmable logic device when executing a routing algorithm process; The hyperparameter management unit is further configured to set multiple hyperparameters based on the circuit connection information designed by the user, obtain a set of hyperparameters that can optimize the user's design timing from the multiple hyperparameters, and send the obtained hyperparameters to the routing module of the programmable logic device; The adaptive parameter management unit is further configured to adjust the adaptive parameters when the routing algorithm flow of the programmable logic device changes, and send the adjusted adaptive parameters to the routing module of the programmable logic device.

2. The memory management system of a programmable logic device according to claim 1, wherein: The wiring resource management module includes: A resource map entry unit is used to classify the wiring resources in the chip and enter the classified wiring resources into the wiring resource map according to the preset operation logic of the programmable logic device; The resource manager unit is used to determine whether a routing module of a programmable logic device needs to be locked by the routing resource manager when accessing the routing resource map.

3. The memory management system of a programmable logic device according to claim 2, wherein: The resource manager unit is further configured to provide an access interface for each agent in the routing algorithm process, and to declare all writing methods of the routing resource graph to be privately owned by the routing resource manager.

4. The memory management system of a programmable logic device according to claim 1, 2 or 3, characterized in that: The temporary container management module includes: A temporary array management unit, configured to manage a temporary array, wherein the temporary array is used to store temporary data; The temporary linked list management unit is used to manage a temporary linked list, where the temporary linked list is used to temporarily store a table required by the programmable logic device when executing a routing algorithm process.

5. The memory management system of a programmable logic device according to claim 4, characterized in that: The temporary array management unit is further configured to determine whether the language executing the routing algorithm process in the programmable logic device is a computer language capable of self-managing memory; if so, clearing the memory data index of the computer language when executing the routing algorithm process to allow the computer language to self-manage its own memory data; if not, destroying the memory data of the computer language of the routing algorithm process at the end of the routing algorithm process; The temporary linked list management unit is further configured to apply for corresponding memory for different temporary linked lists through a preset block allocator, and at least one temporary linked list is correspondingly provided in the memory.

6. The memory management system of a programmable logic device according to claim 1, wherein: The hyperparameter management unit is further configured to obtain read-only parameters uniformly read into the programmable logic device before executing the routing algorithm process, and send the obtained read-only parameters to the routing module of the programmable logic device.

7. A programmable logic device, characterized in that: A memory management system comprising the programmable logic device according to any one of claims 1 to 6.

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