Resource-configurable storage controller

Abstract

This application provides a resource-configurable storage controller, including a direct memory access unit. The direct memory access unit includes at least two physical channels and multiple logical channels, each of the multiple logical channels being coupled to each of the at least two physical channels; each physical channel is used to couple one of the PCIe ports.

Description

Technical Field

[0001] This application relates to storage technology, and in particular to a resource-configurable storage controller, and a direct memory access unit, control unit, and data transmission method therein. Background Technology

[0002] See Figure 1 The diagram illustrates a block diagram of a storage device. Storage device 102 is coupled to a host computer to provide storage capabilities. The host computer and solid-state storage device 102 can be coupled in various ways, including but not limited to connections via SATA (Serial Advanced Technology Attachment), SCSI (Small Computer System Interface), SAS (Serial Attached SCSI), IDE (Integrated Drive Electronics), USB (Universal Serial Bus), PCIe (Peripheral Component Interconnect Express), NVMe (NVM Express), Ethernet, Fibre Channel, and wireless communication networks. The host computer can be an information processing device capable of communicating with the storage device via the aforementioned methods, such as a personal computer, tablet computer, server, laptop computer, network switch, router, cellular phone, or personal digital assistant. Storage device 102 includes interface 103, control unit 104, one or more NVM (Non-Volatile Memory) chips 105, and DRAM (Dynamic Random Access Memory) 110.

[0003] NAND flash memory, phase change memory, FeRAM (Ferroelectric RAM), MRAM (Magnetic Random Access Memory), RRAM (Resistive Random Access Memory), XPoint memory, etc. are common NVMs.

[0004] Interface 103 is compatible with exchanging data with the host via methods such as SATA, IDE, USB, PCIe, NVMe, SAS, Ethernet, and Fibre Channel.

[0005] The control unit 104 is used to control data transfer between the interface 103, the NVM chip 105, and the firmware memory 110. It is also used for memory management, host logical address to flash physical address mapping, erase leveling, bad block management, etc. The control unit 104 can be implemented through software, hardware, firmware, or a combination thereof. The control unit 104 can be in the form of an FPGA (Field-programmable gate array), an ASIC (Application Specific Integrated Circuit), or a combination thereof. The control unit 104 may also include a processor or controller, in which software executes to manipulate the hardware of the control unit 104 to process I / O (Input / Output) commands. The control unit 104 can also be coupled to the DRAM 110 and can access the data in the DRAM 110. FTL tables and / or cached I / O command data can be stored in the DRAM.

[0006] Optionally, the storage device also includes firmware memory. The control unit 104 loads firmware from the firmware memory during operation. The firmware memory is, for example, NOR flash memory, ROM, EEPROM, or may be part of the NVM chip 105.

[0007] The control unit 104 includes a flash interface controller (or media interface controller, flash channel controller), which is coupled to the NVM chip 105 and issues commands to the NVM chip 105 in accordance with the interface protocol of the NVM chip 105 to operate the NVM chip 105, and receives the command execution results output from the NVM chip 105.

[0008] Known NVM chip interface protocols include "Toggle" and "ONFI".

[0009] A memory target is one or more logic units within a NAND flash memory package that share a chip enable (CE) signal. Each logic unit has a logic unit number (LUN). A NAND flash memory package may include one or more dies. Typically, a logic unit corresponds to a single die. A logic unit may include multiple planes. Multiple planes within a logic unit can be accessed in parallel, while multiple logic units within a NAND flash memory chip can execute commands and report status independently of each other. The meanings of target, logic unit, LUN, and plane are provided in the "Open NAND Flash Interface Specification (Revision 3.0)" available at http: / / www.micron.com / ~ / media / Documents / Products / Other%20Documents / ON FI3_0Gold.ashx, which is part of the prior art.

[0010] Figure 2 A detailed block diagram of the control components of the storage device is shown.

[0011] The host accesses the storage device using I / O commands that conform to the storage protocol. The control unit generates one or more media interface commands based on the I / O commands from the host and provides them to the media interface controller. The media interface controller generates storage media access commands (e.g., programming commands, read commands, erase commands) that conform to the NVM chip's interface protocol based on the media interface commands. The control unit also tracks the completion of all media interface commands generated from a single I / O command and indicates the processing results of the I / O commands to the host.

[0012] See Figure 2 The control components include, for example, a host interface, a host command processing unit, a storage command processing unit, a media interface controller, and a storage media management unit. The host interface receives I / O commands from the host and generates storage commands, which are then provided to the storage command processing unit. A storage command may access a storage space of the same size, such as 4KB. The data unit recorded in the NVM chip corresponding to the data accessed by a storage command is called a data frame. A physical page records one or more data frames. For example, if the size of a physical page is 17664 bytes and the size of a data frame is 4KB, then one physical page can store four data frames.

[0013] The storage media management unit (SMMU) maintains a logical address to physical address translation for each storage command. For example, the SMMU includes an FTL table. For a read command, the SMMU outputs the physical address corresponding to the logical address accessed by the storage command; for a write command, the SMMU allocates an available physical address and records the mapping between the accessed logical address and the allocated physical address. The SMMU also maintains functions required for managing the NVM chip, such as garbage collection and wear leveling.

[0014] The storage command processing unit, based on the physical address provided by the storage media management unit, operates the media interface controller to issue storage media access commands to the NVM chip. For clarity, commands sent from the host to the storage device are called I / O commands, commands sent from the host command processing unit to the storage command processing unit are called storage commands, commands sent from the storage command processing unit to the media interface controller are called media interface commands, and commands sent from the media interface controller to the NVM chip are called storage media access commands. Storage media access commands conform to the NVM chip's interface protocol.

[0015] The PCIe protocol defines dual-port and single-port modes. To ensure compatibility with both single-port and dual-port operating modes, the control unit provides, for example, two PCIe x3 port circuits. In dual-port mode, the two port circuits operate independently. In single-port mode, the two port circuits are combined to provide a PCIe x8 port; or one of the two PCIe x3 port circuits provides a PCIe x4 port.

[0016] In existing dual-port PCIe solid-state drives, to achieve multiplexing between single-port and dual-port modes, the dual-port mode consists of two sets of devices that implement single-port mode. When the load on the two ports in dual-port mode is unbalanced, technical problems arise such as large differences in device utilization across different ports and low utilization of some devices. Summary of the Invention

[0017] A PCIe Gen3 x8 port can provide approximately 8GB / s of bandwidth, while each PCIe Gen3 x4 provides approximately 4GB / s of bandwidth. However, when the control unit operates in dual-port mode, if the load on the two ports is unbalanced—for example, port 1 requires 4GB / s of data traffic while port 2 requires 1GB / s—existing solutions require both ports to provide full hardware resources to achieve the 4GB / s bandwidth. When the actual bandwidth of port 2 is less than 4GB / s, some hardware resources are wasted as they are not used.

[0018] Furthermore, a transmission bandwidth of, for example, 4 GB / s might serve a variable number of concurrent data transmission commands. For instance, a command transmitting 4 KB of data would require processing 1 million data transmission commands per second to fully utilize the bandwidth; while a command transmitting 1 MB of data would require processing 4,000 data transmission commands per second. Therefore, in addition to data transmission, identifying and processing these data transmission commands also consumes resources from the control unit. Providing an appropriate amount of resources for identifying and processing data transmission commands on each port becomes a challenge when the load on the two ports is unbalanced or the size of the data transmission commands varies.

[0019] According to embodiments of this application, an attempt is made to solve the technical problem in the prior art where, in a dual-port mode, the traffic demand of different ports is uneven, resulting in the PCIe ports not being fully utilized and leading to low utilization of some devices. According to a first aspect of this application, a first direct memory access unit is provided, comprising at least two physical channels and multiple logical channels, each of the multiple logical channels being coupled to each of the at least two physical channels; each physical channel is used to couple one of the PCIe ports.

[0020] According to the first direct memory access unit of the first aspect of this application, a second direct memory access unit according to the first aspect of this application is provided, the direct memory access unit including single-channel mode and multi-channel mode.

[0021] According to the second direct memory access unit of the first aspect of this application, a third direct memory access unit according to the first aspect of this application is provided. In the multi-channel mode, a first logical channel receives a first command, the first command instructing the direct memory access unit to perform data transmission through a first PCIe port, the first PCIe port being any one of at least two PCIe ports; the first logical channel determines a first physical channel according to the first command; the first logical channel generates and sends first control information to the first physical channel according to the first command; in response to receiving the first control information, the first physical channel performs data transmission through the first PCIe port.

[0022] According to the third direct memory access unit of the first aspect of this application, a fourth direct memory access unit according to the first aspect of this application is provided, wherein the first control information includes a source address and a destination address, and the first physical channel moves the first data from the source address to the destination address; wherein, when the source address points to a device coupled to the first PCIe port, the destination address points to a cache; when the source address points to a cache, the destination address points to a device coupled to the first PCIe port.

[0023] According to one of the second to fourth direct memory access units of the first aspect of this application, a fifth direct memory access unit according to the first aspect of this application is provided. In the single-channel mode, only the second physical channel among the at least two physical channels is coupled to a PCIe port, and the other physical channels among the at least two physical channels do not perform data transmission with any PCIe port. In the single-channel mode, a first logical channel receives a second command, the second command instructing the direct memory access unit to perform data transmission through a second PCIe port, the second PCIe port being the PCIe port among the at least two PCIe ports coupled to the second physical channel. In response to receiving the second command, the logical channel generates and sends second control information to the second physical channel according to the second command. In response to receiving the second control information, the second physical channel performs data transmission through the second PCIe port.

[0024] According to one of the second to fifth direct memory access units of the first aspect of this application, a sixth direct memory access unit according to the first aspect of this application is provided. In the multi-channel mode, the plurality of logical channels include dedicated logical channels, each corresponding one-to-one with a physical channel, and the first logical channel is any one of the plurality of logical channels other than the dedicated logical channels; or, the plurality of logical channels do not include dedicated logical channels, and the first logical channel is any one of the plurality of logical channels.

[0025] According to the third, fourth, or sixth direct memory access unit of the first aspect of this application, a seventh direct memory access unit according to the first aspect of this application is provided. The first logical channel receives a third command, the third command instructing the direct memory access unit to perform data transmission through a second PCIe port. The third command is a command received after receiving the first command, and the second PCIe port is different from the first PCIe port. The first logical channel determines a second physical channel according to the third command. The first logical channel generates and sends third control information to the second physical channel according to the third command. In response to receiving the third control information, the second physical channel performs data transmission through the second PCIe port.

[0026] According to one of the third to seventh direct memory access units of the first aspect of this application, an eighth direct memory access unit according to the first aspect of this application is provided, wherein after the first logical channel determines the first physical channel according to the first command, the first logical channel selects the first physical channel.

[0027] According to the seventh or eighth direct memory access unit of the first aspect of this application, a ninth direct memory access unit according to the first aspect of this application is provided, which stops selecting the first physical channel and selects the second physical channel after the first logical channel determines the second physical channel according to the third command.

[0028] According to one of the seventh to ninth direct memory access units of the first aspect of this application, a tenth direct memory access unit according to the first aspect of this application is provided, wherein the first physical channel responds to completing data transmission through the first PCIe port as indicated by the first control information, and the first physical channel feeds back first completion information to the first logical channel that generated the first control information.

[0029] According to the tenth direct memory access unit of the first aspect of this application, an eleventh direct memory access unit according to the first aspect of this application is provided, wherein in response to receiving the first completion information, the first logical channel stops selecting the first physical channel; after the first logical channel determines the second physical channel, it selects the second physical channel.

[0030] According to a second aspect of this application, a first data transmission method according to the second aspect of this application is provided, comprising: receiving a first command, the first command instructing a first physical channel to perform data transmission with a first PCIe device; determining the first physical channel according to the first command; generating and sending first control information to the first physical channel according to the first command, so that the first physical channel performs data transmission through a first PCIe port according to the first control information.

[0031] According to the first data transmission method of the second aspect of this application, a second data transmission method according to the second aspect of this application is provided, wherein after determining the first physical channel, the method further includes: activating the first physical channel.

[0032] According to the second data transmission method of the second aspect of this application, a third data transmission method according to the second aspect of this application is provided, the method further comprising: receiving first completion information fed back by the first physical channel.

[0033] According to one of the first to third data transmission methods of the second aspect of this application, a fourth data transmission method according to the second aspect of this application is provided, wherein after receiving the first command, the method further includes: receiving a second command, the second command instructing a second physical channel to perform data transmission with a second PCIe port, the second physical channel being different from the first physical channel; determining the second physical channel according to the second command; generating and sending second control information to the second physical channel according to the second command, so that the second physical channel performs data transmission through the second PCIe port according to the second control information.

[0034] According to the fourth data transmission method of the second aspect of this application, a fifth data transmission method according to the second aspect of this application is provided, wherein in response to receiving the first completion information, the selection of the first physical channel is stopped; after determining the second physical channel, the second physical channel is selected; or, after determining the second physical channel, the selection of the first physical channel is stopped and the second physical channel is selected.

[0035] According to a third aspect of this application, a first control component according to the third aspect of this application is provided, comprising a command processing unit and a direct memory access unit as described in any one of the first aspects; the command processing unit sends a first command to the direct memory access unit, the first command instructing the direct memory access unit to perform data transmission through a first PCIe port; in response to the first command, the direct memory access unit performs data transmission through the first PCIe port.

[0036] According to the first control component of the third aspect of this application, a second control component according to the third aspect of this application is provided, the command processing unit including at least one processing module and at least one acceleration module, each of the at least one processing module being coupled to the direct memory storage unit, each of the at least one acceleration module being coupled to the direct memory storage unit, and each processing module also being coupled to each acceleration module.

[0037] According to the second control component of the third aspect of this application, a third control component according to the third aspect of this application is provided, wherein each processing module is coupled to one or more logical channels in the direct memory access unit; and each hardware acceleration module is coupled to one or more logical channels in the direct memory access unit.

[0038] According to the second or third control component of the third aspect of this application, a fourth control component according to the third aspect of this application is provided, wherein the processing module or acceleration module sends a first command to the first logical channel, the first command instructing the first physical channel to perform data transmission with the first PCIe port; in response to receiving the first command, the first logical channel determines the first physical channel according to the first command; the first logical channel generates and sends first control information to the first physical channel according to the first command; in response to receiving the first control information, the first physical channel performs data transmission through the first PCIe port according to the first control information.

[0039] According to the fourth control component of the third aspect of this application, a fifth control component according to the third aspect of this application is provided, wherein after the first physical channel is determined, the first logical channel selects the first physical channel.

[0040] According to the fifth control component of the third aspect of this application, a sixth control component according to the third aspect of this application is provided, wherein in response to the completion of data transmission with the first PCIe port, the first physical channel feeds back first completion information to the first logical channel.

[0041] According to the fifth or sixth control component of the third aspect of this application, a seventh control component according to the third aspect of this application is provided. After receiving the first command, the first logical channel further receives a second command, the second command instructing a second physical channel to perform data transmission with a second PCIe port, the second physical channel being different from the first physical channel; the first logical channel determines the second physical channel according to the second command; the first logical channel generates and sends second control information to the second physical channel according to the second command; the second physical channel performs data transmission with the second PCIe port according to the second control information.

[0042] According to the seventh control component of the third aspect of this application, an eighth control component according to the third aspect of this application is provided, wherein, in response to receiving the first completion information, the first logical channel stops selecting the first physical channel; after determining the second physical channel, the first logical channel selects the second physical channel; or, after determining the second physical channel, the first logical channel stops selecting the first physical channel and selects the second physical channel.

[0043] According to the third control component of the third aspect of this application, a ninth control component according to the third aspect of this application is provided, wherein in response to the control component coupling multiple PCIe ports, the direct memory access unit is configured in multi-channel mode; and in response to the control component coupling only a single second PCIe port, the direct memory access unit is configured in single-channel mode.

[0044] According to the ninth control component of the third aspect of this application, a tenth control component according to the third aspect of this application is provided, which couples a first number of logical channels to a first physical channel and couples a second channel's logical channel to a second physical channel according to the load or configuration of the PCIe port.

[0045] According to the first to ninth control components of the third aspect of this application, an eighth control component according to the third aspect of this application is provided, wherein the command processing unit allocates one or more logical channels to process commands for accessing a first namespace; allocates one or more logical channels to process commands for accessing a second namespace; the namespace is also associated with one or more PCIe ports; in order to generate a command to be sent to the logical channel, the command processing unit obtains the physical channel coupled to the PCIe port associated with the namespace; and indicates the physical channel associated with the namespace accessed by the command in the generated command. Attached Figure Description

[0046] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in this application. For those skilled in the art, other drawings can be obtained based on these drawings.

[0047] Figure 1 A block diagram of a storage device in the prior art;

[0048] Figure 2 A block diagram of a control component in the prior art;

[0049] Figure 3A This is a schematic diagram of a direct memory access unit in the prior art;

[0050] Figure 3B A schematic diagram of a direct memory access unit provided in an embodiment of this application;

[0051] Figure 4 A flowchart illustrating the data transmission method provided in this application embodiment;

[0052] Figure 5 A schematic diagram of the control component provided in the embodiments of this application;

[0053] Figure 6 A schematic diagram illustrating the coupling relationship between the command processing unit and the direct memory access unit provided in an embodiment of this application;

[0054] Figure 7 A schematic diagram of a single-port storage device provided in an embodiment of this application;

[0055] Figure 8A A schematic diagram of a dual-port storage device provided in an embodiment of this application;

[0056] Figure 8B This is a schematic diagram of another dual-port storage device provided in an embodiment of this application. Detailed Implementation

[0057] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0058] Figure 3A This is a schematic diagram of a Direct Memory Access (DMA) unit 300 supporting dual-port mode in the prior art. The DMA unit 300 includes physical channel 1 and physical channel 2. Physical channel 1 is coupled to PCIe port 1, and physical channel 2 is coupled to PCIe port 2. Logical channels 11, 12, and 13 are coupled to physical channel 1. Logical units 21, 22, and 23 are coupled to physical channel 2. The two physical channels of the DMA unit 300 independently possess the same number of logical channels, so in dual-port mode, each physical channel is responsible for the operation of one PCIe port. In single-port mode, for example, one PCIe port in the DMA unit 300 is not used. For instance, in single-port mode, PCIe port 1 of the DMA unit 300 is working normally, while PCIe port 2 is not working, thus physical channel 2 and logical units 21, 22, and 23 are all inactive. Alternatively, in single-port mode, PCIe port 1 and PCIe port 2 work together to provide twice the data transfer bandwidth.

[0059] Figure 3B This embodiment provides a direct memory access unit 310 that supports both dual-port and single-port modes. For example... Figure 3BAs shown, the Direct Memory Access Unit 310 includes physical channel 1, physical channel 2, logical channel 11, logical channel 12, logical channel 13, logical channel 21, logical channel 22, and logical channel 23. Physical channel 1 is coupled to PCIe port 1, and physical channel 2 is coupled to PCIe port 2. Each logical channel among logical channels 11, 12, 13, 21, 22, and 23 is coupled to physical channel 1, and each of these logical channels is also coupled to physical channel 2. In this embodiment, the number of physical channels in the Direct Memory Access Unit 310 includes, but is not limited to, 2, and the number of logical channels coupled to each physical channel is greater than or equal to 2. For example, physical channel 1 is coupled with 16 logical channels. It should be noted that physical channel 1 being coupled with 16 logical channels indicates that all 16 logical channels can transmit data with physical channel 1, but it does not mean that physical channel 1 transmits data with 16 logical channels simultaneously. At any given time, the actual number of logical channels transmitting data through physical channel 1 can be much less than 16 or even 0.

[0060] Understandably, in this embodiment, physical channel 1 is also coupled to PCIe port 2, and physical channel 2 is coupled to PCIe port 2. The PCIe port conforms to the PCIe standard and is used to couple PCIe devices. The PCIe devices in this application include, but are not limited to, solid-state drives (SSDs) and hosts according to the NVMe protocol. For example, PCIe port 1 couples to one PCIeGen 3×4 SSD, and PCIe port 2 also couples to one PCIeGen 3×4 SSD. Another example is that PCIe port 1 couples to one PCIeGen 3×8 SSD, and PCIe port 2 is not connected to an SSD. Yet another example is that PCIe port 1 and PCIe port 2 are combined into a single PCIe port coupled to one PCIeGen 3×8 SSD.

[0061] Optionally, the direct memory access unit 310 is integrated into the control unit of a storage device such as a solid-state drive (SSD). Thus, PCIe port 1 and / or PCIe port 2 are used to couple a host's PCIe port or a PCIe switch. When the SSD operates in dual-port mode, PCIe port 1 and PCIe port 2 are each independently coupled to a host or PCIe switch's PCIe port. When the SSD operates in single-port mode, PCIe port 1 and PCIe port 2 are jointly coupled to a single PCIe port of the host or PCIe switch.

[0062] Optionally, the direct memory access unit 310 provides single-channel mode and multi-channel mode.

[0063] According to an embodiment of this application, in multi-channel mode, a first logical channel receives a first command. The first command instructs the direct memory access unit 310 to perform data transmission through a first PCIe port, where the first PCIe port is any one of at least two PCIe ports. The first logical channel determines a first physical channel based on the first command. In this embodiment, the first logical channel is any one of the logical channels in the direct memory access unit 310, or the logical channel in the memory access unit 310 that receives the first command is the first logical channel. Any physical channel in the memory access unit 310 may become the first physical channel.

[0064] For example, logical channel 13 receives a first command indicating the identifier of PCIe port 2 and the identifier of physical channel 1. After receiving the first command, logical channel 13 determines that the first physical channel is physical channel 1 based on the identifier of physical channel 1. As another example, logical channel 21 receives a first command indicating the identifier of physical channel 2, as well as the source and destination addresses. If either the source or destination address points to PCIe port 2, logical channel 21 determines that data transmission is performed through physical channel 2 via PCIe port 2. Yet another example: logical channel 13 receives a first command indicating the identifier of PCIe port 2 but not the identifier of the physical channel. Logical channel 13 checks the binding relationship between physical channel 1 and physical channel 2, determines that a binding relationship exists between physical channel 2 and PCIe port 2, and therefore determines that data transmission is performed through physical channel 2 and PCIe port 2.

[0065] After determining the first physical channel, the first logical channel generates and sends first control information to the first physical channel according to the first command. In response to receiving the first control information, the first physical channel performs data transmission through the first PCIe port. For example, logical channel 13 generates and sends first control information to physical channel 1 according to the first command, and the first control information instructs physical channel 1 to perform data transmission through PCIe port 1.

[0066] Optionally, the first control information may also include a source address and a destination address. For example, in response to receiving the first control information, physical channel 1 moves the data indicated by the first command from the source address to the destination address. For example, if the source address points to the cache and the destination address points to the host, then physical channel 1 moves the data from the cache to the host.

[0067] In some embodiments, in single-channel mode, only the second physical channel out of at least two physical channels is coupled to a PCIe port, and the other physical channels do not transmit data to any PCIe port. The second physical channel is the physical channel that operates normally in single-channel mode. For example, physical channel 1 is the second physical channel, and physical channel 1 is coupled to PCIe port 1, which is connected to a PCIe device, while PCIe port 2 is not connected to a PCIe device, so physical channel 2 cannot transmit data through PCIe port 2.

[0068] Furthermore, in single-channel mode, the first logical channel receives a second command, which instructs the direct memory access unit to perform data transmission through a second PCIe port. The second PCIe port is one of at least two PCIe ports coupled to the second physical channel. In this embodiment, the first logical channel is any one of the direct memory access units 310, or the logical channel in the direct memory access unit 310 that receives the second command is the first logical channel. For example, logical channel 22 receives a second command, which instructs data transmission through PCIe port 2, and the second physical channel is physical channel 2.

[0069] In response to receiving the second command, the first logical channel generates and sends second control information to the second physical channel according to the second command; in response to receiving the second control information, the second physical channel performs data transmission through the second PCIe port. Following the previous example, after receiving the second command, logical channel 22 generates second control information and sends it to physical channel 2; physical channel 2 performs data transmission through PCIe port 2.

[0070] According to embodiments of this application, multiple logical channels present a user of the direct memory access unit 310 with multiple (greater than the number of physical channels) channels capable of concurrently processing commands to perform PCIe data transfer according to each command. Thus, the user can select any idle logical channel (not currently used for PCIe data transfer) and send commands to it. Therefore, in multi-channel mode, the number of concurrently processed commands on each physical channel is determined by allocating some logical channels to one physical channel and others to another, with the number of logical channels allocated to each physical channel. Thus, when the load on the PCIe ports provided by each physical channel changes or becomes unbalanced, the ability to provide adjustable concurrent processing commands to each physical channel is achieved by adjusting the number of logical channels coupled to each physical channel.

[0071] Understandably, in dynamically adjusting the coupling relationship between logical channels and physical channels, at certain times, a physical channel may not be coupled to any logical channel, resulting in no data transmission on that physical channel and causing a very poor user experience for devices connected to the PCIe ports coupled to that physical channel. Therefore, in some embodiments, in multi-channel mode, to reserve basic bandwidth or data transmission capacity for some physical channels, some logical channels are set as dedicated logical channels. For example, a one-to-one correspondence may exist between dedicated logical channels and physical channels, while the first logical channel may be any one of the multiple logical channels other than the dedicated logical channels. For example, if the dedicated logical channel corresponding to physical channel 1 is logical channel 11, and the dedicated logical channel corresponding to physical channel 2 is logical channel 21, then the first logical channel may be any one of logical channels 12, 13, 22, and 23. Optionally, the multiple logical channels may not include dedicated logical channels, and the first logical channel may be any one of the multiple logical channels.

[0072] In some embodiments, the first logical channel receives a third command, which instructs the direct memory access unit to perform data transmission through the second PCIe port. The third command is a command received after receiving the first command, and the second PCIe port is different from the first PCIe port. The first logical channel determines the second physical channel according to the third command. The first logical channel generates and sends third control information to the second physical channel according to the third command. In response to receiving the third control information, the second physical channel performs data transmission through the second PCIe port.

[0073] Taking logical channel 12 as the first logical channel, a first command instructing data transmission through PCIe port 1, and a third command instructing data transmission through PCIe port 2 as an example: After receiving the first command, logical channel 12 determines that the first physical channel is physical channel 1. Logical channel 12 generates first control information based on the first command and sends the first control information to physical channel 1. Physical channel 1 then transmits data with PCIe port 1 based on the first control information. After receiving the third command following the first command, logical channel 12 determines that the second physical channel is physical channel 2. Logical channel 12 generates third control information based on the third command and sends the third control information to physical channel 2. Physical channel 2 then transmits data with PCIe port 2 based on the third control information.

[0074] In this embodiment, after the first logical channel determines the first physical channel according to the first command, the first logical channel selects the first physical channel. For example, if logical channel 22 is coupled to both physical channel 1 and physical channel 2, after receiving the first command, logical channel 22 determines the first physical channel to be physical channel 2 according to the first command. Then, logical channel 22 selects physical channel 2, so that physical channel 2 can perform subsequent data transmission, while physical channel 1, which is not selected, cannot perform data transmission.

[0075] Optionally, after the first logical channel determines the second physical channel according to the third command, it stops selecting the first physical channel and selects the second physical channel. For example, after receiving the first command, logical channel 22 selects physical channel 2. After physical channel 2 completes the data transmission indicated by the first command, logical channel 22 receives the third command, determines physical channel 1 as the second physical channel, and thus logical channel 22 stops selecting physical channel 2 and selects physical channel 1.

[0076] In this embodiment, in response to completing data transmission through the first PCIe port as instructed by the first control information, the first physical channel sends first completion information back to the first logical channel that generated the first control information. For example, after physical channel 1 completes data transmission with PCIe port 1, it sends first completion information to logical channel 23, indicating that the data transmission instructed by the first command has been completed. Exemplarily, after receiving the first completion information, logical channel 23 can stop selecting physical channel 1 and, after determining that the second physical channel is physical channel 2, select physical channel 2. In other possible embodiments, after receiving the third command, the current physical channel 1 is still in the selected state. After determining that the second physical channel is physical channel 2 according to the third command, logical channel 23 stops selecting physical channel 1 and selects physical channel 2.

[0077] For example, after receiving the first command, logical channel 11 selects physical channel 1. After physical channel 1 completes data transmission, logical channel 11 stops selecting physical channel 1. When logical channel 11 receives a fourth command, it determines that the physical channel to be selected is physical channel 1, and then logical channel 11 selects physical channel 1 again.

[0078] For example, after receiving the first command, the logical channel 11 selects the physical channel 1. After the physical channel 1 completes the data transmission, the logical channel 11 receives the fourth command. According to the fourth command, the logical channel 11 determines that the physical channel to be selected is still the physical channel 1. Therefore, the logical channel 11 maintains the state of selecting the physical channel 1 between the completion of data transmission on the physical channel and the determination of the physical channel 1 according to the fourth command.

[0079] Figure 4 This is a flowchart illustrating the data transmission method provided in this embodiment. The method provided in this embodiment can be executed by the direct memory access unit 310, and can also be executed by a processor or other devices; no limitation is made here. The following describes the direct memory access unit 310 and... Figure 4 Describe it.

[0080] like Figure 4 As shown, the method includes:

[0081] Step 401: Receive a first command, which instructs the first physical channel to transmit data with the first PCIe device.

[0082] For example, logical channel 21 receives a first command that instructs physical channel 1 to transmit data with PCIe port 1. The first command is generated by the processor or hardware and sent to the logical channel.

[0083] Step 402: Determine the first physical channel according to the first command.

[0084] For example, the first command carries the identifier of physical channel 1, and logical channel 21 determines physical channel 1 as the first physical channel based on the identifier. Alternatively, if the first command does not carry the identifier of physical channel, logical channel 21 determines that physical channel 1 is bound to PCIe port 1 based on the binding relationship between physical channel and PCIe port, thereby determining physical channel 1 as the first physical channel.

[0085] Optionally, after determining that the first physical channel is physical channel 1, logic channel 21 selects physical channel 1.

[0086] Step 403: Generate and send first control information to the first physical channel according to the first command, so that the first physical channel can transmit data through the first PCIe port according to the first control information.

[0087] For example, logical channel 21 generates first control information according to a first command, and sends the first control information to physical channel 1. After receiving the first control information, physical channel 1 performs data transmission with PCIe port 1. It should be noted that, in this embodiment, the data transmission between physical channel 1 and PCIe port 1 can refer to the prior art DMA data transmission method, and this application does not limit it.

[0088] Step 404: Receive the first completion information fed back from the first physical channel.

[0089] Specifically, for example, after physical channel 1 transmits data with PCIe port 1, physical channel 1 generates a first completion message, indicating that the data transmission is complete. Upon receiving the first completion message, logical channel 21 stops selecting physical channel 1. After receiving the first completion message, logical channel 21 continues to process other received commands.

[0090] Step 405: Receive a second command. The second command instructs the second physical channel to transmit data with the second PCIe port. The second physical channel is different from the first physical channel.

[0091] For example, after receiving the second command, logical channel 21 determines that physical channel 2 needs to transmit data with PCIe port 2 based on the second command.

[0092] Step 406: Determine the second physical channel according to the second command. In this embodiment, the method for determining the second physical channel is the same as that for determining the first physical channel, and will not be repeated here. Optionally, after determining the second physical channel, the second physical channel is activated; or, after determining the second physical channel, the activation of the first physical channel is stopped, and the second physical channel is activated. For example, after receiving the first completion information, logic channel 21 stops activating physical channel 1, and after determining that the second physical channel is physical channel 2, activates physical channel 2. As another example, after determining that the second physical channel is physical channel 2, logic channel 21 stops activating physical channel 1 and activates physical channel 2.

[0093] Step 407: Generate and send second control information to the second physical channel according to the second command, so that the second physical channel can transmit data through the second PCIe port according to the second control information. The execution method of step 407 can refer to the execution method of step 403, and will not be described again here.

[0094] Figure 5 The control component 500 provided in this application embodiment includes a command processing unit 501 and a direct memory access unit 310 in the above embodiment.

[0095] Specifically, the command processing unit 501 sends a first command to the direct memory access unit 310, instructing the direct memory access unit 310 to perform data transmission through PCIe port 1. In response to the first command, the direct memory access unit 310 performs data transmission through PCIe port 1.

[0096] In this embodiment, the method for data transmission between the direct memory access unit 310 and the PCIe port 1 can be the data transmission method described in the above embodiment, or it can be a method in the prior art.

[0097] See also Figure 5 Optionally, the command processing unit 501 includes at least one processing module 502 and at least one acceleration module 503. Each processing module in the at least one processing module 502 is coupled to the direct memory storage unit 310, and each acceleration module in the at least one acceleration module 503 is coupled to the direct memory storage unit 310. Each processing module is also coupled to each acceleration module. For example, the at least one processing module 502 includes three processing modules, and the at least one acceleration module 503 includes three acceleration modules. Optionally, the at least one processing module 502 includes one, two, four, or more processing modules. The at least one acceleration module 503 includes one, two, four, or more acceleration modules.

[0098] Optionally, each processing module in at least one processing module 502 is coupled to one or more logical channels in direct memory access unit 310. Each hardware acceleration module in at least one acceleration module is coupled to one or more logical channels in direct memory access unit 310.

[0099] Taking a storage device conforming to the NVMe protocol as an example, the command processing unit 501 processes NVMe commands. Each of the processing modules 502 is responsible for parsing the NVMe command and generating a data transfer command for the direct memory access unit 310 based on the NVMe command, instructing the direct memory access unit 310 to perform data transfer between the control unit 500 and a remote device coupled through PCIe port 1 and / or PCIe port 2. Optionally, acceleration modules 503 assist the processing modules 502 in processing NVMe commands. For example, one or more acceleration modules 503 are responsible for retrieving NVMe commands from the command submission queue and providing them to the processing module 502; one or more acceleration modules 503 are responsible for retrieving the PRP list or SGL list indicated by the NVMe command based on the NVMe command; one or more acceleration modules 503 are responsible for generating a completion message and filling the completion queue based on the NVMe command processing result. One or more acceleration modules 503 are responsible for detecting whether there are errors in the various fields of the NVMe command and whether the protocol requirements are met.

[0100] Each processing module 502 can be assigned one or more acceleration modules to assist it in processing NVMe commands. Optionally, the processing module 502 can acquire idle acceleration modules to assist it in processing NVMe commands based on the working status of the acceleration modules.

[0101] Processing module 502 transmits data via PCIe port 1 and / or PCIe port 2 by sending data transmission commands to one of the logical units of memory direct access unit 310. Optionally, processing module 502 acquires an idle logical channel based on the operating status of the logical channel to assist in processing NVMe commands.

[0102] It also maintains the binding relationship between logical channels and PCIe ports. For example, three logical channels are bound to PCIe port 1, and another three logical channels are bound to PCIe port 2. The processing module 502 is aware of the host coupled to the PCIe port. For example, host 1 is coupled to control unit 500 through PCIe port 1, and host 2 is coupled to control unit 500 through PCIe port 2; or in dual-port operating mode, host 1 is coupled to control unit 500 through PCIe port 1 and PCIe port 2. Based on the destination host to which data is to be transferred, the processing module 502 provides the generated data transfer command to one or more logical channels bound to the PCIe port coupled to that host, and obtains an indication from that logical channel that the data transfer command processing is complete. Thus, the logical channels provide the processing module 502 with the ability for the memory direct access unit 310 to concurrently process data transfer commands, and also provide the processing module 502 with the ability for each PCIe port to concurrently process data transfer commands.

[0103] Furthermore, according to embodiments of this application, the binding relationship between logical channels and PCIe ports is variable, thus the ability of each PCIe port to concurrently process data transmission commands is variable. For example, in response to identifying that the current load of PCIe port 1 is low, while the current load of PCIe port 2 is high, the ability of PCIe port 1 to concurrently process data transmission commands can be improved by changing one or more logical channels originally bound to PCIe port 2 to be bound to PCIe port 1, without providing additional control component resources.

[0104] Similarly, the acceleration module transmits data via PCIe port 1 and / or PCIe port 2 by sending a data transmission command to one of the logic units of the direct memory access unit 310.

[0105] For example, Figure 6 A schematic diagram illustrating the coupling relationship between the acceleration module and processing module in the command processing unit 501 and the logic channel in the direct memory access unit 310 is provided. As an example, Figure 6 Only the coupling relationships between acceleration module 3, processing module 3, and the logic channels are shown. Acceleration module 3 is coupled to all six logic channels, and processing module 3 is also coupled to all six logic channels. The remaining acceleration modules in at least one acceleration module 503 are not described in the text. Figure 6 The diagram illustrates the coupling relationships with the logic units; it can be understood that each acceleration module is coupled to at least one logic channel. Similarly, each processing module is coupled to at least one logic channel.

[0106] The control unit 500 can execute the data transmission method in the above embodiments. The following description uses logical channel 13 as an example of the first logical channel. The processing module 3 in the command processing unit 501 sends a first command to logical channel 13, instructing data transmission between physical channel 1 and PCIe port 1. In response to receiving the first command, logical channel 13 determines the first physical channel as physical channel 1 based on the first command. Logical channel 13 generates and sends first control information to physical channel 1 based on the first command. In response to receiving the first control information, physical channel 1 performs data transmission through PCIe port 1 based on the first control information.

[0107] Optionally, after determining that the first physical channel is physical channel 1, logic channel 13 selects physical channel 1.

[0108] Furthermore, in response to the completion of data transmission with PCIe port 2, physical channel 1 sends a first completion message back to logical channel 13.

[0109] After receiving the first command, logical channel 13 also receives a second command, which instructs physical channel 2 to transmit data with PCIe port 2. Based on the second command, logical channel 13 determines the second physical channel to be physical channel 2. Logical channel 13 then generates and sends second control information to physical channel 2 according to the second command. Physical channel 2 then transmits data with PCIe port 2 based on the second control information.

[0110] Further optionally, in response to receiving the first completion information, logical channel 13 stops selecting physical channel 1. After determining that the second physical channel is physical channel 2, logical channel 13 selects physical channel 2. Alternatively, after determining that the second physical channel is physical channel 2, logical channel 13 stops selecting physical channel 1 and selects physical channel 2.

[0111] In this embodiment, the control unit 500 also has two working modes, including single-channel mode and multi-channel mode.

[0112] Furthermore, in this embodiment, a first number of logical channels are coupled to a first physical channel based on the load or configuration of the PCIe port; and the logical channels of a second channel are coupled to a second physical channel. For example, the direct memory access unit 310 has 6 logical channels and physical channels 1 and 2. Physical channel 1 is coupled to PCIe port 1, and physical channel 2 is coupled to PCIe port 2. If the loads of PCIe port 1 and PCIe port 2 are detected to be the same or similar, then 3 logical channels are coupled to physical channel 1, and the other 3 logical channels are coupled to physical channel 2; if the load of PCIe port 1 is detected to be twice the load of PCIe port 2, then 4 logical channels are coupled to physical channel 1, and the other 2 logical channels are coupled to physical channel 2; or, depending on the configuration, 1 logical channel is coupled to physical channel 1, and 5 logical channels are coupled to physical channel 2. Optionally, the different logical channels in this application have the same working capability, and the different physical channels also have the same working capability. In this embodiment, the number of logical channels coupled to different physical channels is dynamically adjusted according to the load and configuration of the PCIe port. This ensures that there are enough logical channels to handle the load when it is heavy, while the remaining logical channels can handle the heavy load of the PCIe port when the load is light. This not only improves work efficiency but also effectively increases the utilization rate of logical channels and / or physical channels.

[0113] In some embodiments, the command processing unit 501 assigns one or more logical channels to process commands accessing a first namespace. It also assigns one or more logical channels to process commands accessing a second namespace. The namespaces are also associated with one or more PCIe ports. For example, PCIe port 1 is associated with command space 1, and PCIe port 2 is associated with namespaces 2 and 3. Thus, logical channels 12 and 13 are responsible for processing commands accessing namespace 1, while logical channels 11, 21, 22, and 23 are responsible for processing commands accessing namespaces 2 and 3. This provides different levels (e.g., bandwidth) of service for namespace 1 and namespaces 2 / 3.

[0114] To generate a command to be sent to the logical channel, the command processing unit 501 obtains the physical channel coupled to the PCIe port associated with the namespace. For example, when generating a first command, which is a command to access namespace 1, the command processing unit 501 obtains that PCIe port 2 is associated with namespace 1, and the physical channel bound to PCIe port 2 is physical channel 2. Therefore, based on the instruction in the first command to namespace 1, the command processing unit 501 determines that the physical channel to be used is physical channel 2.

[0115] Figure 7 This is a schematic diagram of a single-port storage device provided according to an embodiment of this application.

[0116] like Figure 7 As shown, the single-port storage device presents, for example, two namespaces (namespace 1 and namespace 2) to the host. The storage device operates in single-port mode and is coupled to the host via port 1 (port 1 is a PCIe port). The direct memory access unit 310 includes multiple logical channels (not shown), each coupled to a physical port bound to port 1. Thus, these logical channels all serve port 1.

[0117] Each namespace provided by the single-port storage device to the host promises its own performance; for example, namespace 1 promises a bandwidth of 1GB / s, while namespace 2 promises a bandwidth of 2GB / s. To this end, logical channels are further bound to namespaces. For example, two logical channels in direct memory access unit 310 are bound to namespace 1, while four logical channels in direct memory access unit 310 are bound to namespace 2. For example, processing module 502 (not in...) Figure 7 (As shown in the diagram) When a direct memory access unit 310 is accessed according to an NVMe command accessing namespace 1, the data transfer command is sent to one of the two logical channels bound to namespace 1. Therefore, even if a large number of NVMe commands access namespace 1 at a given time, four logical channels are still reserved to handle NVMe commands accessing namespace 2, thus ensuring that the physical bandwidth of port 1 is not saturated by NVMe commands accessing namespace 1 when NVMe commands accessing namespace 2 are present. This also ensures that the concurrent number of data transfer commands for namespace 1 is less than the concurrent number of data transfer commands for namespace 2.

[0118] Optionally, each logical channel serves all namespaces.

[0119] Figure 8A This is a schematic diagram of a dual-port storage device provided in an embodiment of this application.

[0120] like Figure 8A As shown, the storage device used as an example is a dual-port storage device, which includes, for example, three namespaces. Host 1 is coupled to the dual-port storage device through port 1, and host 2 is coupled to the dual-port storage device through port 2. Both ports 1 and 2 are PCIe ports. Host 1 accesses namespaces 1 and 2 of the storage device through port 1. Host 2 accesses namespaces 2 and 3 of the storage device through port 2. Thus, host 1 and host 2 share namespace 2, while each has exclusive access to namespaces 1 and 3.

[0121] As an example again, physical channel 1 in direct memory access unit 310 is coupled to port 1, and physical channel 2 is coupled to port 2.

[0122] According to embodiments of this application, in order to reserve performance for each namespace, allocate resources among namespaces, and reserve command processing capabilities such as bandwidth for each namespace, a variable binding relationship is established between logical channels and namespaces. A variable binding relationship is also established between logical channels and ports (through physical channels coupled to ports).

[0123] Direct memory storage unit 310 includes 6 logical channels (see also...) Figure 6 For example, logical channels 11 and 12 are bound to namespace 1, logical channels 13 and 21 are bound to namespace 2, and logical channels 22 and 23 are bound to namespace 3. Thus, logical channels 11 and 12 are responsible for data transmission in namespace 1, logical channels 13 and 21 are responsible for data transmission in namespace 2, and logical channels 22 and 23 are responsible for data transmission in namespace 3. This process determines which logical channel to initiate data transmission based on the namespace accessed by the command, and determines which port and physical channel to use for data transmission based on the host issuing the command to access the namespace.

[0124] According to embodiments of this application, the number of logical channels bound to each namespace is adjusted based on the load and / or performance requirements of namespace 1 and / or namespace 2. This is achieved by increasing the number of logical channels bound to a namespace to provide higher command processing capabilities for that namespace, and by binding, for example, at least one logical channel to a namespace to guarantee basic command processing capabilities. Furthermore, in response to changes in the load and / or performance requirements of namespace 1 and / or namespace 2, the number of logical channels bound to one or more namespaces is changed to meet the changed load and / or performance requirements. Further, the number of logical channels serving each physical channel is changed to adapt to changes in the load of each physical channel.

[0125] Figure 8B This is a schematic diagram of another dual-port storage device provided in an embodiment of this application. Figure 8B Dual-port storage devices and Figure 8A The similarities will not be repeated here; the difference lies in... Figure 8B Both port 1 and port 2 are coupled to the same host 1. Host 1 can access the three namespaces provided by the storage device through either port 1 or port 2.

[0126] According to the embodiments of this application, there is an adjustable binding relationship between logical channels and namespaces, and the number of logical channels providing services to physical channels is also adjustable. Its operation method can be found in [reference needed]. Figure 8A The description of the dual-port storage device is omitted here.

[0127] Although the examples referenced in this application are described for illustrative purposes only and not for limiting the scope of this application, changes, additions and / or deletions to the implementation may be made without departing from the scope of this application.

[0128] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A direct memory access unit, characterized in that, It includes at least two physical channels and multiple logical channels, each of the multiple logical channels being coupled to each of the at least two physical channels; Each physical channel is used to couple one of the PCIe ports; wherein, a logical channel receives a data transmission command, determines a physical channel from its coupled physical channels based on the data transmission command, generates and sends control information to the determined physical channel; the determined physical channel performs data transfer in response to receiving the control information; the data transmission command indicates the physical channel for data transmission; wherein... The data transmission command is provided to the direct memory access unit by the command processing unit; the command processing unit dynamically adjusts the binding relationship between the logical channel and the PCIe port according to the load of the PCIe port, so as to dynamically adjust the number of logical channels allocated to different physical channels. The command processing unit instructs the physical channel for data transmission by sending a data transmission command to the logical channel of the direct memory access unit, thereby adjusting the binding relationship between the logical channel and the PCIe port. In the direct memory access unit, the logical channel selects the corresponding physical channel according to the physical channel for data transmission indicated by the received data transmission command.

2. The direct memory access unit as described in claim 1, characterized in that, In multi-channel mode, the first logical channel receives a first command, which instructs the direct memory access unit to perform data transmission through the first PCIe port, where the first PCIe port is any one of at least two PCIe ports. The first logical channel determines the first physical channel according to the first command; The first logical channel generates and sends first control information to the first physical channel according to the first command; In response to receiving the first control information, the first physical channel transmits data through the first PCIe port.

3. The direct memory access unit as described in claim 1 or 2, characterized in that, In single-channel mode, only the second physical channel among the at least two physical channels is coupled to the PCIe port, and the other physical channels among the at least two physical channels do not transmit data with any PCIe port; in single-channel mode, the first logical channel receives a second command, the second command instructing the direct memory access unit to transmit data through the second PCIe port, the second PCIe port being the PCIe port among the at least two PCIe ports coupled to the second physical channel; In response to receiving the second command, the logical channel generates and sends second control information to the second physical channel according to the second command; In response to receiving the second control information, the second physical channel transmits data through the second PCIe port.

4. The direct memory access unit as described in claim 1 or 2, characterized in that, In multi-channel mode, the plurality of logical channels include dedicated logical channels, each corresponding one-to-one with a physical channel, and the first logical channel is any one of the plurality of logical channels other than the dedicated logical channels; or, the plurality of logical channels do not include dedicated logical channels, and the first logical channel is any one of the plurality of logical channels.

5. The direct memory access unit as described in claim 2, characterized in that, After the first logical channel determines the first physical channel according to the first command, the first logical channel selects the first physical channel.

6. A data transmission method, characterized in that, include The logical channel of the direct memory access unit receives a first command, which instructs the first physical channel to perform data transmission with the first PCIe device; The logical channel determines the first physical channel according to the first command; The logical channel generates and sends first control information to the first physical channel according to a first command, so that the first physical channel performs data transmission through the first PCIe port according to the first control information; wherein... The first command is provided to the direct memory access unit by the command processing unit; the command processing unit dynamically adjusts the binding relationship between the logical channel and the PCIe port according to the load of the PCIe port, so as to dynamically adjust the number of logical channels allocated to different physical channels. The command processing unit instructs the first physical channel for data transmission by sending a first command to the logical channel of the direct memory access unit, thereby adjusting the binding relationship between the logical channel and the PCIe port. The logical channel in the direct memory access unit selects the first physical channel according to the first physical channel indicated by the received first command.

7. The method as described in claim 6, characterized in that, After determining the first physical channel, the method further includes: Select the first physical channel.

8. The method as described in claim 6 or 7, characterized in that, After receiving the first command, the method further includes: Receive a second command, which instructs a second physical channel to transmit data with a second PCIe port, the second physical channel being different from the first physical channel; The second physical channel is determined according to the second command; The second control information is generated according to the second command and sent to the second physical channel so that the second physical channel can transmit data through the second PCIe port according to the second control information.

9. The method as described in claim 8, characterized in that, In response to receiving the first completion message, stop selecting the first physical channel; after determining the second physical channel, select the second physical channel; or, After determining the second physical channel, stop selecting the first physical channel and select the second physical channel.

10. A control component, characterized in that, Includes a command processing unit and a direct memory access unit as described in any one of claims 1-5; The command processing unit sends a first command to the direct memory access unit, the first command instructing the direct memory access unit to perform data transmission through the first PCIe port; In response to the first command, the direct memory access unit performs data transmission through the first PCIe port; wherein, The command processing unit dynamically adjusts the binding relationship between the logical channel and the PCIe port according to the load of the PCIe port, so as to dynamically adjust the number of logical channels allocated to different physical channels. The command processing unit instructs the physical channel for data transmission by sending a first command to the logical channel of the direct memory access unit, thereby adjusting the binding relationship between the logical channel and the PCIe port. The logical channel in the direct memory access unit selects the corresponding physical channel according to the physical channel for data transmission indicated by the received first command. The selected physical channel transmits data through the first PCIe port of the first P.

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