Sense amplifier and operation method for nonvolatile memory

Abstract

A sense amplifier includes a voltage comparator with offset compensation, a first clamping device, and a second clamping device. The voltage comparator is coupled to a bit line and a reference bit line, respectively, and is configured to compare a first input voltage and a second input voltage to output a sense signal. The first clamping circuit and the second clamping circuit respectively fine-tune the voltage corresponding to the bit line and the voltage corresponding to the reference bit line to match the voltage corresponding to the bit line. Embodiments of the present invention also relate to a method for operating a non-volatile memory.

Description

Technical Field

[0001] Embodiments of the present invention relate to a sense amplifier and an operating method of a nonvolatile memory. Background Art

[0002] As semiconductor process nodes shrink, the integration density of electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) in integrated circuits (ICs) has increased, resulting in a decrease in the operating voltage and current consumption of electronic circuits developed in the semiconductor process nodes. Consequently, it is expected that the access speed of memory integrated circuits will become faster. For example, some memories have very small read windows, which require low-offset sense amplifiers to successfully perform read operations.

[0003] Due to unavoidable process variations, mismatches or offsets often exist between components in sense amplifier circuits. According to existing approaches, the sense amplifier undergoes an offset sampling or cancellation phase before the actual read operation to eliminate mismatches in the sense amplifier circuit. Furthermore, offset-compensated sense amplifiers cannot eliminate variations in reference cells, which are often used in read path designs and are subject to process variations. Summary of the Invention

[0004] According to one aspect of an embodiment of the present invention, a readout amplifier is provided, comprising: a voltage comparator with offset compensation, coupled to a bit line and a reference bit line via a first I / O node and a second I / O node of the readout amplifier, respectively, and configured to compare a first input voltage and a second input voltage to output a readout signal; a first clamping circuit coupled between the first I / O node and the bit line; and a second clamping circuit coupled between the second I / O node and the reference bit line, wherein the first clamping circuit and the second clamping circuit respectively fine-tune a voltage corresponding to the bit line and a voltage corresponding to the reference bit line so that the voltage corresponding to the reference bit line matches the voltage corresponding to the bit line.

[0005] According to another aspect of an embodiment of the present invention, a readout amplifier is provided, comprising: a voltage comparator coupled to a bit line and a reference bit line, and configured to compare a first input voltage and a second input voltage to output a readout signal; and a clamping circuit coupled between the voltage comparator, the bit line, and the reference bit line, wherein one of the voltage comparator and the clamping circuit has offset compensation, and wherein the voltage comparator is further configured to fine-tune a first voltage corresponding to the bit line and a second voltage corresponding to the reference bit line to match a voltage corresponding to the reference bit line with a voltage corresponding to the bit line.

[0006] According to another aspect of an embodiment of the present invention, there is provided an operating method for a non-volatile memory, the non-volatile memory including a memory array and a read amplifier, wherein the read amplifier includes a voltage comparator with offset compensation, a first clamping circuit, and a second clamping circuit, the first clamping circuit being coupled between a first I / O node of the read amplifier and a bit line, and the second clamping circuit being coupled between a second I / O node of the read amplifier and a reference bit line, wherein the operating method includes: the voltage comparator comparing a first input voltage and a second input voltage via the first I / O node and the second I / O node of the read amplifier, respectively, to output a read signal; and the first clamping circuit and the second clamping circuit respectively fine-tuning a voltage corresponding to the bit line and a voltage corresponding to the reference bit line to match the voltage corresponding to the bit line.

[0007] According to another aspect of an embodiment of the present invention, a method for operating a non-volatile memory is provided, wherein the non-volatile memory includes a memory array and a read amplifier, wherein the read amplifier includes a voltage comparator and a clamping circuit, the clamping circuit is coupled to a first I / O node, a bit line, a second I / O node and a reference bit line of the read amplifier, and one of the voltage comparator and the clamping circuit has offset compensation, wherein the operating method includes: the voltage comparator compares a first input voltage and a second input voltage via the first I / O node and the second I / O node of the read amplifier respectively to output a read signal; and the voltage comparator fine-tunes a voltage corresponding to the bit line and a voltage corresponding to the reference bit line respectively to match the voltage corresponding to the bit line. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] When with Figure 1 The embodiments of the present disclosure are best understood from the following detailed description when read together. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, the dimensions of the various components may be arbitrarily increased or decreased for clarity of discussion.

[0009] Figure 1 A schematic diagram of a nonvolatile memory with a sense amplifier according to some embodiments of the present disclosure is shown.

[0010] Figure 2 A schematic block diagram of a sense amplifier according to some embodiments of the present disclosure is shown.

[0011] Figure 3A A schematic diagram of a sense amplifier according to some embodiments of the present disclosure is shown.

[0012] Figure 3B A circuit of a voltage comparator of a sense amplifier according to one embodiment is shown.

[0013] Figure 3C An exemplary circuit of a voltage comparator of a sense amplifier according to some embodiments of the present disclosure is shown.

[0014] Figure 3D An exemplary circuit of a voltage comparator of a sense amplifier according to some embodiments of the present disclosure is shown.

[0015] Figure 3E An exemplary circuit of a voltage comparator of a sense amplifier according to some embodiments of the present disclosure is shown.

[0016] Figure 4A A schematic diagram of a first adjustable clamping circuit according to some embodiments of the present disclosure is shown.

[0017] Figure 4B A schematic diagram of a fine-tunable second clamping circuit according to some embodiments of the present disclosure is shown.

[0018] Figure 5 A schematic block diagram of a sense amplifier according to some embodiments of the present disclosure is shown.

[0019] Figure 6 A schematic diagram of a sense amplifier according to some embodiments of the present disclosure is shown.

[0020] Figure 7A An exemplary circuit of a trimmable voltage comparator according to some embodiments of the present disclosure is shown.

[0021] Figure 7B An exemplary circuit of a trimmable voltage comparator according to some embodiments of the present disclosure is shown.

[0022] Figure 8A A schematic diagram of an offset compensation clamp device according to some embodiments of the present disclosure is shown.

[0023] Figure 8B According to some embodiments of the present disclosure, Figure 8A Flowchart showing how the offset compensation clamp device in FIG. 1 charges the clamp voltage.

[0024] Figure 8C According to some embodiments of the present disclosure, Figure 8A Flowchart showing how the offset compensation clamp device in FIG. 1 discharges the clamp voltage.

[0025] Figure 9 A schematic diagram illustrating adjusting the size of a clamping device by fine-tuning a branch according to some embodiments of the present disclosure is shown.

[0026] Figure 10A schematic block diagram of a sense amplifier with offset compensation and a trimmable voltage comparator according to some embodiments of the present disclosure is shown.

[0027] Figure 11 A schematic block diagram of a sense amplifier with offset compensation and a trimmable clamping device according to some embodiments of the present disclosure is shown. DETAILED DESCRIPTION

[0028] The following disclosure provides many different embodiments or examples of different components for implementing the provided subject matter. Specific examples of elements and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to limit the present disclosure. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly in contact with each other, and may also include an embodiment in which additional components may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the present disclosure may repeat reference numerals and / or characters in various examples. This repetition is for the purpose of simplicity and clarity and does not, by itself, indicate the relationship between the various embodiments and / or configurations discussed.

[0029] Additionally, for ease of description, spatially relative terms such as "under," "beneath," "lower," "over," and "upper" may be used herein to describe the relationship of one element or component to another element or component as illustrated in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientations depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used therein interpreted accordingly. Terms such as "attached," "bonded," "connected," and "interconnected" refer to a relationship whereby structures are affixed or attached, directly or indirectly, to one another through intermediate structures, and both removable and rigid attachments or relationships, unless expressly stated otherwise.

[0030] refer to Figure 1 , non-volatile memory 100 includes a memory array 110 and a sense amplifier 120. Memory array 110 includes a plurality of memory cells located in the intersection region between word lines and bit lines. Memory array 110 may also include at least one reference memory cell. The memory cells of memory array 110 include a memory cell 112 coupled to a bit line BL and a word line WL, and a reference memory cell 114 coupled to a reference word line RWL and a reference bit line RBL. Sense amplifier 120 is coupled to memory cell 112 and reference memory cell 114 via bit line BL and reference bit line RBL, respectively.

[0031] The sense amplifier 120 is configured to perform a read operation or a sense operation to sense the value of the data stored in the memory cell 112. For example, the sense amplifier 120 may compare the data stored in the memory cell 112 with a reference value (e.g., reference data of the reference memory cell 114) to output a sense signal indicating the value of the data stored in the memory cell 112.

[0032] refer to Figure 2 , the sense amplifier 120 includes a voltage comparator 121 (offset compensation voltage comparator), a first clamp circuit 122, and a second clamp circuit 123. Theoretically, since the first clamp circuit 122 and the second clamp circuit 123 have the same circuit structure, the two clamp circuits 122 and 123 have the same threshold voltage Vth. And, theoretically, if the resistor R BL and the resistor R on the reference bit line RBL RBL The same, and the current I BL and I RBL Same (ie, the voltage V BL and the voltage V of the reference bit line RBL RBL The voltage comparator 121 can detect that the voltage provided by the first clamping circuit 122 is the same as the voltage provided by the second clamping circuit 123. However, depending on the semiconductor manufacturing process used to manufacture the transistors, the physical characteristics of each transistor may be slightly different, and thus a mismatch may occur between the threshold voltage Vth of the transistor (i.e., metal oxide semiconductor field effect transistor, MOS) in the first clamping circuit 122 and the threshold voltage Vth of the MOS in the first clamping circuit 123.

[0033] In order to compensate for the mismatch between the threshold voltage Vth of the MOS in the first clamping circuit 122 and the threshold voltage Vth of the MOS in the second clamping circuit 123, at least one of the first clamping circuit 122 and the second clamping circuit 123 has a fine-tuning correction function (e.g., fine-tunable) for matching the threshold voltage Vth of the MOS in the first clamping circuit 122 with the threshold voltage Vth of the MOS. Therefore, in the embodiment of the present disclosure, at least one of the first clamping circuit 122 and the second clamping circuit 123 having the fine-tuning correction function matches the voltage Vth of the bit line BL provided by the fine-tuning circuits 122 and 123. BL and the voltage V of the reference bit line RBL RBLThe one or more fine-tuning correction functions of at least one of the first clamping circuit 122 and the second clamping circuit 123 may be controlled by the controller 140. At least one of the first clamping circuit 122 and the second clamping circuit 123 having one or more fine-tuning correction functions means that the first clamping circuit 122, the second clamping circuit 123, or both the first clamping circuit 122 and the second clamping circuit 123 have a fine-tuning correction function.

[0034] For example, when the memory cell is in the reset state (ie, the current I BL is low), the voltage corresponding to the bit line BL (eg, V BL ) and a voltage corresponding to the reference bit line RBL (eg, V RBL ) are fine-tuned to the same voltage level. In detail, the first clamp circuit 122 and the second clamp circuit 123 (e.g., the fine-tunable clamp circuit 122 and / or 123) having one or more fine-tuning correction functions have a main branch circuit and a plurality of fine-tuning branch circuits. Each fine-tuning branch circuit has a current path and a switch, and the switch is used to conduct or not conduct the current path and is controlled by the controller 140. The controller 140 controls the plurality of switches in the fine-tuning branch circuit and reads the voltage V corresponding to the bit line BL. BL and V corresponding to the reference bit line RBL RBL same or different so that the voltage V BL and V BL The voltage comparator 120 can display the voltage corresponding to V BL The bit line current I BL and corresponding to V RBL The reference bit line current I RBL The voltage comparator can output the bit line current I BL and the reference bit line current I RBL The difference between the bit line BL and the reference bit line RBL can be considered as the comparator 120, which can also be used to measure the voltage difference between the bit line BL and the reference bit line RBL, rather than the current difference. The sense amplifier 120 also includes a controller 140. The controller 140 can be coupled to the voltage comparator 121, the first clamping circuit 122, and the second clamping circuit 123 to control switching to the voltage comparator 121, the first clamping circuit 122, and the second clamping circuit 123, so as to implement the functions of the voltage comparator 121, the first clamping circuit 122, and the second clamping circuit 123.

[0035] refer to Figure 2 and Figure 3A The sense amplifier 220 includes a voltage comparator 221, a first clamping circuit 222, and a second clamping circuit 223. The voltage comparator 221 is an embodiment of the present disclosure. Figure 2An example of the voltage comparator 121 in FIG. 1 , the first clamping circuit 222 is an embodiment of the present disclosure. Figure 2 The first clamp circuit 122 is an example of the embodiment of the present disclosure, and the second clamp circuit 223 is an example of the embodiment of the present disclosure. Figure 2 1 and 2. The voltage comparator 221 is coupled to the bit line BL and the reference bit line RBL via the first and second I / O nodes ION1 and ION2 of the sense amplifier 220. The sense amplifier is configured to compare a first input voltage and a second input voltage (input via the first and second I / O nodes ION1 and ION2) to output a read signal (output from the first and second I / O nodes ION1 and ION2).

[0036] The first clamp circuit 222 is coupled between the first I / O node ION1 and the bit line BL. The first clamp circuit 222 is configured to fine-tune the voltage (V BL The second clamp circuit 223 is coupled between the second I / O node ION2 and the reference bit line RBL. The second clamp circuit 223 is configured to fine-tune the voltage corresponding to the reference bit line (V RBL ). In detail, the first clamp circuit 222 and the second clamp circuit 223 (e.g., the fine-tunable clamp circuit 222 and / or 223) with one or more fine-tuning correction functions include a main branch circuit and a plurality of fine-tuning branch circuits. Each fine-tuning branch circuit has a current path and a switch, each switch being used to conduct or not conduct. Figure 1 The current path in and is controlled by the controller 140. Figure 1 The controller 140 in the embodiment controls the switches in the fine-tuning branch circuit and reads the voltage V corresponding to the bit line BL. BL and V corresponding to the reference bit line RBL RBL Same or different, in order to fine-tune the voltage V BL and V RBL to the same voltage level.

[0037] In an embodiment of the present disclosure, the difference between the first output voltage and the second output voltage corresponding to the read signal is greater than the difference between the first input voltage and the second input voltage. In addition, the first input voltage is input to the voltage comparator via the first I / O node ION1, the second input voltage is input to the voltage comparator via the second I / O node ION2, the first output voltage is output from the voltage comparator via the first I / O node ION1, and the second output voltage is output from the voltage comparator via the second I / O node ION2.

[0038] In an embodiment of the present disclosure, the voltage comparator 221 includes a first circuit 310 and a second circuit 320 , wherein the first circuit and the second circuit are coupled to a first I / O node ION1 and a second I / O node ION2 .

[0039] The first circuit 310 includes a first transistor M1, a second transistor M2, and a third transistor M3, wherein a first terminal of the first transistor M1 and a first terminal of the second transistor M2 are coupled to a first reference voltage level (eg, V DD ), a control terminal of the first transistor M1, a control terminal of the second transistor M2, and a control terminal of the third transistor M3 are coupled to receive a precharge signal PREB, a second terminal of the first transistor M1 and a second terminal of the third transistor M3 are coupled to the first I / O node ION1 and a connection node between the first transistor M1 and the third transistor M3, and a second terminal of the second transistor M2 and a first terminal of the third transistor M3 are coupled to the second I / O node ION2 and another connection node between the second transistor M2 and the third transistor M3.

[0040] Second circuit 320 includes a fourth transistor M4, a fifth transistor M5, a first pair of p-type transistors PM1 and PM2, a first pair of n-type transistors NM1 and NM2, a second pair of p-type transistors PM3 and PM4, and a second pair of n-type transistors NM3 and NM4. The first pair of p-type transistors PM1 and PM2 and the first pair of n-type transistors NM1 and NM2 form a third circuit 321. The second pair of p-type transistors PM3 and PM4 and the second pair of n-type transistors NM3 and NM4 form a fourth circuit 322. Third circuit 321 is cross-coupled to fourth circuit 322, and the outputs of third circuit 321 and fourth circuit 322 are coupled to a first I / O node ION1 and a second I / O node ION2, respectively.

[0041] In more detail, the fourth transistor M4 is coupled to the third circuit 321 and the fourth circuit 322, wherein a first terminal of the fourth transistor M4 is coupled to a first reference voltage level (eg, V DD ), a second terminal of the fourth transistor M4 is coupled to a connection node between the fourth transistor M4, the third circuit 321 and the fourth circuit 322, and a control terminal of the fourth transistor M4 is coupled to receive a first enable signal EN1.

[0042] Furthermore, the fifth transistor M5 is coupled to the third circuit 321 and the fourth circuit 322, wherein a first terminal of the fifth transistor M5 is coupled to a connection node between the fifth transistor M5, the third circuit 321, and the fourth circuit 322. A second terminal of the fifth transistor M5 is coupled to a second reference voltage level (e.g., ground), and a control terminal of the fifth transistor M5 is coupled to receive a second enable signal EN2.

[0043] Moreover, in the embodiments of the present disclosure, Figure 3A As shown, switches SW1 to SW3 are coupled between the third circuit 321 and the first I / O node ION1, and switches SW4 to SW6 are coupled between the fourth circuit 322 and the second I / O node ION2. The switches SW1 to SW6 can be closed (turned on) / opened by a control signal SWEN, and can be closed (turned on) to electrically couple the second circuit 320 to the bit line BL and the reference bit line RBL.

[0044] exist Figure 3A In the embodiments of the present disclosure, the second circuit 320 is referred to as a voltage comparator with an offset compensation function, wherein the offset required to obtain the same voltage difference corresponding to the read signal is reduced. For example, when switches SW1 to SW6 are closed to connect their two terminals, transistors PM1 to PM4 and NM1 to NM4 connected to switches SW1 to SW6 receive a first input voltage input via the first I / O node ION1 and a second input voltage input via the second I / O node ION2. Furthermore, when switches SW1 to SW6 are opened to disconnect their two terminals, third circuit 321 and fourth circuit 322 double the difference between the first output voltage output via the first I / O node ION1 and the second output voltage output via the second I / O node ION2 by using first circuit 310 and transistors M4 and M5 with enable signals PREB, EN1, and EN2. Therefore, when the voltage difference between the first input voltage (input via the first I / O node ION1 and the second I / O node ION2) and the second input voltage is 5 mV, the difference between the first output voltage and the second output voltage (output via the first I / O node ION1 and the second I / O node ION2) obtained will be 10 mV, and the circuit structure of the second circuit of the voltage comparator having the same input voltage difference ( Figure 3B The voltage difference at the output is 5mV.

[0045] Figure 3B The circuit structure in is a voltage comparator. Specifically, in the first period, enable signals EN1 and EN2 are enabled to connect the source terminals of transistors PM1, PM2, NM1, and NM2 to VDD / VSS through transistors M4 and M5. In the second period, switches SW1 and SW2 are closed (i.e., switches SW1 and SW2 are connected to their two terminals), and the input voltage difference between the first input voltage via the first I / O node ION1 and the second input voltage via the second I / O node ION2 is input to transistors PM1, PM2, NM1, and NM2 to generate output voltages of the first I / O node ION1 and the second I / O node ION2. That is, Figure 3BThe offset compensation function of the circuit structure can be less than Figure 3A and Figure 3C The offset compensation function of the voltage comparator 320 in FIG. Due to the better offset compensation function of the voltage comparator 320, it is easier to determine the voltage difference between the voltage provided by the first clamp circuit 122 / 222 and the voltage provided by the second clamp circuit 123 / 223. Therefore, because the voltage difference between the voltages provided by the first clamp circuit and the second clamp circuit is easily determined, the risk of read disturb occurring is reduced. Furthermore, because the voltage comparator 121 / 221 is sensitive to determining the voltage difference between the voltages provided by the first clamp circuit and the second clamp circuit, the first clamp circuit 122 / 222 and the second clamp circuit 123 / 223 do not need to have a large number of fine-tuning branches, and thus the fine-tuning range and area overhead of the fine-tuning circuits (i.e., the first clamp circuit 122 / 222 and the second clamp circuit 123 / 223) are correspondingly reduced.

[0046] In another embodiment, Figure 3B The circuit structure of the voltage comparator in includes a first pair of p-type transistors PM1 and PM2, a first pair of n-type transistors NM1 and NM2, a fourth transistor M4, a fifth transistor M5, and switches SW1 to SW2. For example, after the voltage difference (e.g., ΔV) between the first input voltage and the second input voltage is input via the first I / O node ION1 and the second I / O node ION2, and the first enable signal EN1 and the second enable signal EN2 are input to close the fourth transistor M4 and the fifth transistor M5, the fourth transistor M4 pulls up the source terminals of the p-type transistors PM1 and PM2, and the fifth transistor M5 pulls down the source terminals of the n-type transistors NM1 and NM2. In addition, after the first enable signal / second enable signal EN1 / EN2 is triggered, positive feedback from the transistors PM1, PM2, NM1, and NM2 is activated. Therefore, Figure 3B The offset of the voltage comparator in will be 4.6mV. That is, Figure 3B The offset compensation function of the circuit structure can be less than Figure 3A and Figure 3C The offset compensation function of the voltage comparator 320 in FIG.

[0047] In another embodiment, the transistor can be replaced with a capacitor to improve the Figure 3A The second circuit 320. Specifically, refer to Figure 3C The second circuit 320 includes a fourth transistor M4, a fifth transistor M5, p-type transistors PM1 to PM5, n-type transistors NM1 to NM5, and capacitors C1 to C4, wherein the capacitors C1 and C3, for example, replace Figure 3AThe p-type transistors PM1 and PM3, and capacitors C2 and C4 in the second circuit 320, for example, replace Figure 3A n-type transistors NM2 and NM4 form second circuit 320 in FIG. P-type transistor PM1 and n-type transistor NM1 form a third circuit. P-type transistor PM2 and n-type transistor NM2 form a fourth circuit. The third circuit is cross-coupled to the fourth circuit, and the outputs of the third and fourth circuits are coupled to first I / O node ION1 and second I / O node ION2, respectively. P-type transistors PM3 to PM5 form a fifth circuit, and n-type transistors NM3 to NM5 form a sixth circuit.

[0048] In more detail, in the fifth circuit, the first terminal of the p-type transistor PM3 and the first terminal of the p-type transistor PM5 are coupled to a first reference voltage level (eg, V DD ), control terminals of the p-type transistors PM3 to PM5 are coupled to receive a first predetermined signal, a second terminal of the p-type transistor PM3 and a second terminal of the p-type transistor PM4 are coupled to a first I / O node ION1, a connection node between the capacitor C1 and the first terminal of the p-type transistor PM1, and a second terminal of the p-type transistor PM5 and a first terminal of the p-type transistor PM4 are coupled to another connection node between the second I / O node ION2, the capacitor C3 and the p-type transistor PM2.

[0049] The fourth transistor M4 is coupled to the third circuit, the fourth circuit, and the fifth circuit, wherein a first terminal of the fourth transistor M4 is coupled to a first reference voltage level (eg, V DD ), a second terminal of the fourth transistor M4 is coupled to a connection node between the capacitor C1 and the capacitor C3, and a control terminal of the fourth transistor M4 is coupled to receive a first enable signal EN1.

[0050] Furthermore, a fifth transistor M5 is coupled to the third circuit, the fourth circuit, and the sixth circuit, wherein a first terminal of the fifth transistor M5 is coupled to a connection node between the capacitor C2 and the capacitor C4. A second terminal of the fifth transistor M5 is coupled to a second reference voltage level (e.g., ground), and a control terminal of the fifth transistor M5 is coupled to receive a second enable signal EN2.

[0051] Moreover, in the sixth circuit, the second terminal of the n-type transistor NM3 and the second terminal of the n-type transistor NM5 are coupled to a second reference voltage level (e.g., ground), the control terminals of the n-type transistors NM3 to NM5 are coupled to receive a second predetermined signal, the first terminal of the n-type transistor NM3 and the second terminal of the n-type transistor NM4 are coupled to a connection node between the first I / O node ION1, the capacitor C2, and the second terminal of the n-type transistor NM1, and the first terminal of the n-type transistor NM5 and the first terminal of the n-type transistor NM4 are coupled to another connection node between the second I / O node ION2, the capacitor C4, and the n-type transistor NM2.

[0052] In addition, if Figure 3C As shown, switches SW1 to SW3 are coupled between the third circuit and the first I / O node ION1, and switches SW4 to SW5 are coupled between the fourth circuit and the second I / O node ION2. The switches SW1 to SW6 can be closed (turned on) / opened by a control signal SWEN, and can be closed (turned on) to electrically couple the second circuit 320 to the bit line BL and the reference bit line RBL.

[0053] In an embodiment of the present disclosure, the second circuit 320 may be referred to as an offset compensation circuit, wherein the offset required to generate the same voltage difference corresponding to the read signal is also reduced. For example, after a voltage difference (e.g., ΔV) between a first input voltage and a second input voltage is input via the first I / O node ION1 and the second I / O node ION2, and after the first enable signal EN1 and the second enable signal EN2 are input to close the fourth transistor M4 and the fifth transistor M5, the fourth transistor M4 pulls up the source terminals of the p-type transistors PM1 and PM2 via the capacitors C1 and C3, and the fifth transistor M5 pulls down the source terminals of the n-type transistors NM1 and NM2 via the capacitors C2 and C4. Furthermore, after the first enable signal EN1 / the second enable signal EN2 is triggered, positive feedback from the transistors PM1, PM2, NM1, and NM2 is activated to amplify the input voltage difference (e.g., ΔV), thereby outputting a larger voltage difference via the first I / O node ION1 and the second I / O node ION2. Also, a first enable delay signal EN1D and a second enable delay signal EN2D are provided to provide VDD / VSS to the source terminals of the transistors PM1 , PM2 , NM1 , and NM2 to make the output voltage difference rail-to-rail.

[0054] The following describes the embodiments of the present disclosure Figure 3CThe operation of the voltage comparator 320 is shown in FIG. During a first period, enable signals EN1 and EN2 are enabled to connect the source terminals of transistors PM1, PM2, NM1, and NM2 to VDD / VSS via transistors M4 and M5 and capacitors C1 to C4. During the first period, switches SW1 to SW6 are opened (i.e., switches SW1 and SW2 are disconnected from their two terminals), and enable signals EN1D and EN2D are disabled. During a second period, switches SW1 to SW6 are closed (i.e., switches SW1 and SW2 are connected to their two terminals), enable signals EN1, EN2, EN1D, and EN2D are disabled, and an input voltage difference between a first input voltage via the first I / O node ION1 and a second input voltage via the second I / O node ION2 is input to transistors PM1, PM2, NM1, and NM2. In the third period, the first enable delay signal EN1D and the second enable delay signal EN2D are enabled, the switches SW1 to SW6 are closed (i.e., the switches SW1 and SW2 are connected to their two terminals), and the enable signals EN1 and EN2 are disabled, and the capacitors C1 to C4 and the transistors PM1 to PM5 and NM1 to NM5 generate the output voltages of the first I / O node ION1 and the second I / O node ION2. In other words, the circuit structure of the capacitors C1 to C4 and the transistors PM1 to PM5 and NM1 to NM5 forms a structure that functions as a charge pump, and the output voltage difference between the first output voltage output via the first I / O node ION1 and the second output voltage output via the second I / O node ION2 doubles from the first period to the third period. In an embodiment, the expected offset will also be reduced by 8% (e.g., from 3.8 mV / σ to 3.5 mV / σ). That is, Figure 3B The offset compensation function of the circuit structure in the Figure 3C The offset compensation function of the mid-voltage comparator 320 is shown.

[0055] In some embodiments of the present disclosure, one or more capacitors are used to store a charge corresponding to an input voltage difference, and the charge stored in the one or more capacitors is discharged to eliminate the mismatch of the device during the readout phase. In detail, although the first enable signal / second enable signal EN1 / EN2 is not triggered (i.e., the first enable signal / second enable signal EN1 / EN2 is disabled), in order to maintain the voltage of the two terminals of the capacitors C1 to C4, the capacitors C1 to C4 store a charge corresponding to the input voltage difference. Furthermore, although the first enable signal / second enable signal EN1 / EN2 is triggered (i.e., the first enable signal / second enable signal EN1 / EN2 is enabled), the charge stored in the capacitors C1 to C4 is discharged to eliminate the mismatch of the device during the readout phase.

[0056] refer to Figure 3DIn an embodiment, second circuit 320 includes a fourth transistor M4, a fifth transistor M5, p-type transistors PM1 and PM2, n-type transistors NM1 and NM2, capacitors C1 and C2, and switches SW1 through SW8. Capacitor C1, p-type transistor PM1, and n-type transistor NM1 form a third circuit 321. Capacitor C2, p-type transistor PM2, and n-type transistor NM2 form a fourth circuit 322. The third circuit is cross-coupled to the fourth circuit via switches SW7 and SW8, and the outputs of the third and fourth circuits are coupled to a first I / O node ION1 and a second I / O node ION2, respectively.

[0057] In more detail, the fourth transistor M4 is coupled to the third circuit 321 and the fourth circuit 322, wherein a first terminal of the fourth transistor M4 is coupled to a first reference voltage level (eg, V DD ), a second terminal of the fourth transistor M4 is coupled to a connection node between the fourth transistor M4, the third circuit 321, and the fourth circuit 322, and a control terminal of the fourth transistor M4 is coupled to receive the first enable signal EN1. Furthermore, a fifth transistor M5 is coupled to the third circuit 321 and the fourth circuit 322, wherein a first terminal of the fifth transistor M5 is coupled to a connection node between the fifth transistor M5, the third circuit 321, and the fourth circuit 322. A second terminal of the fifth transistor M5 is coupled to a second reference voltage level (e.g., ground), and a control terminal of the fifth transistor M5 is coupled to receive the second enable signal EN2.

[0058] A first terminal of capacitor C1 is coupled to a first connection node between p-type transistor PM2 and n-type transistor NM2 via switch SW8, and a second terminal of capacitor C1 is coupled to a second connection node between p-type transistor PM1 and n-type transistor NM1 via switch SW2, and is coupled to the control terminal of n-type transistor NM1. A first terminal of capacitor C2 is coupled to a second connection node between p-type transistor PM1 and n-type transistor NM1 via switch SW7, and a second terminal of capacitor C2 is coupled to a first connection node between p-type transistor PM2 and n-type transistor NM2 via switch SW5, and is coupled to the control terminal of n-type transistor NM2.

[0059] The switch SW1 is coupled between the first I / O node ION1 and the second connection node, and the switch SW4 is coupled between the second I / O node ION2 and the first connection node. In addition, the switch SW3 is coupled between the second reference voltage level (e.g., ground) and the first terminal of the capacitor C1, and the switch SW6 is coupled between the second reference voltage level (e.g., ground) and the first terminal of the capacitor C2.

[0060] The following describes Figure 3DOperation of the circuit structure in FIG. During a first period, enable signals EN1 and EN2 are enabled to connect the source terminals of transistors PM1, PM2, NM1, and NM2 to VDD / VSS via transistors M4 and M5, and switches SW2 to SW3 and SW5 to SW8 are closed. During a second period, switches SW1 and SW4 are closed (i.e., switches SW1 and SW2 are connected to their two terminals), and an input voltage difference between a first input voltage via the first I / O node ION1 and a second input voltage via the second I / O node ION2 is input to transistors PM1, PM2, NM1, and NM2 to generate output voltages of the first and second I / O nodes ION1 and ION2. During a second period, switches SW2 to SW3 and SW5 to SW8 are closed. During the third period, switches SW2 to SW3 and SW5 to SW8 are opened, switches SW1 and SW4 are closed, enable signals EN1 and EN2 are disabled, and output voltages are generated by capacitors C1 to C4 and transistors PM1 to PM5 and NM1 to NM5 to the first I / O node ION1 and the second I / O node ION2. In other words, the circuit structure of capacitors C1 to C2 and transistors PM1 to PM2 and NM1 to NM2 forms a structure that functions as a charge pump, and the output voltage difference between the first output voltage output via the first I / O node ION1 and the second output voltage output via the second I / O node ION2 doubles from the first period to the third period.

[0061] refer to Figure 3E In another embodiment, second circuit 320 includes p-type transistors PM1 and PM2, n-type transistors NM1 and NM2, capacitor C1, and switches SW1 through SW10. Capacitor C1, p-type transistor PM1, and n-type transistor NM1 form third circuit 321. P-type transistor PM2 and n-type transistor NM2 form fourth circuit 322. The third circuit is cross-coupled to the fourth circuit via switches SW7 and SW8, and outputs of the third and fourth circuits are coupled to first and second I / O nodes ION1 and ION2, respectively.

[0062] In more detail, the switch SW1 is coupled to the third circuit 321 and the fourth circuit 322, wherein a first terminal of the switch SW1 is coupled to a first reference voltage level (eg, V DD), a second terminal of switch SW1 is coupled to a connection node between third circuit 321 (p-type transistor PM1) and fourth circuit 322 (p-type transistor PM2). Furthermore, switch SW2 is coupled to third circuit 321 and fourth circuit 322, wherein a second terminal of switch SW2 is coupled to a second reference voltage level (e.g., ground), and a first terminal of switch SW2 is coupled to a connection node between third circuit 321 (n-type transistor NM1) and fourth circuit 322 (n-type transistor NM2).

[0063] A first terminal of the capacitor C1 is coupled to a first connection node between the p-type transistor PM2 and the n-type transistor NM2 via the switch SW7, and a second terminal of the capacitor C1 is coupled to a connection node between the p-type transistor PM1, the n-type transistor NM1, and the switch SW9.

[0064] The switch SW3 is coupled between the first I / O node ION1 and the second connection node, and the switch SW4 is coupled between the second I / O node ION2 and the first connection node. In addition, the switch SW5 is coupled between the second reference voltage level (e.g., ground) and the second connection node, and the switch SW6 is coupled between the second reference voltage level (e.g., ground) and the first connection node.

[0065] In addition, switch SW10 is coupled between the first connection node and the connection node between the control terminal of p-type transistor PM2 and the control terminal of n-type transistor NM2; and switch SW9 is coupled between the second connection node and the connection node between the control terminal of p-type transistor PM1 and the control terminal of n-type transistor NM1.

[0066] exist Figure 3E The second circuit 320 further includes p-type transistors PM3 and PM4, n-type transistors NM3 to NM5, a reference current generator, a resistor R AP1 、R AP2 and R P The output node of the reference current generator is coupled to the control terminals of the p-type transistors PM3 and PM4. The p-type transistors PM3 and PM4 are respectively biased according to the bias voltage V generated by the output node of the reference current generator. 偏置_R Produce I 读 and 2I 读 The first I / O node ION1 is coupled to one node of the third switch SW3 and the bit line BL, and the second I / O node ION2 is coupled to one node of the fourth switch SW4 and the reference bit line RBL. The control terminals of the n-type transistors NM3 to NM5 are coupled to the word line WL. The drain terminal of the n-type transistor NM3 is connected to the word line WL via the resistor R AP1The source terminal of the n-type transistor NM3 is coupled to the bit line BL, and the drain terminal of the n-type transistor NM4 is coupled to the ground terminal through the eleventh switch SW11. AP2 The source terminal of the n-type transistor NM4 is coupled to the reference bit line RBL, and the drain terminal of the n-type transistor NM5 is coupled to the ground terminal. P is coupled to the reference bit line RBL, and a source terminal of the n-type transistor NM5 is coupled to the ground terminal.

[0067] The following describes the embodiments of the present disclosure. Figure 3E In the first period, the switches SW1 to SW2 and SW5 to SW6 are closed to connect the source terminals of the transistors PM1, PM2, NM1 and NM2 to VDD / VSS. In the first period, the switches SW3 to SW4 and SW7 to SW10 are closed. In the second period, I 参考 The generator generates a bias voltage V 偏置_R , according to the bias voltage V 偏置_R The current I 读 and 2I 读 , to generate the first and second input voltages input via the first and second I / O nodes ION1 and ION2. During the second period, switches SW7 to SW10 remain closed. During the third period, switches SW7 to SW10 are open, and switches SW3 to SW4 are closed. During the third period, because a voltage difference exists between the two terminals of capacitor C1, the difference between the first output voltage via I / O node ION1 and the second output voltage via I / O node ION2 is offset by the voltage difference across capacitor C1, making it easier to determine the voltage difference between bit line BL and reference bit line RBL.

[0068] like Figure 3A As shown, each of the trimmable clamp circuits may have a main branch circuit and a plurality of trimmable branch circuits. Each trimmable branch circuit has a current path and a switch, each switch being used to conduct or not conduct. Figure 1 The current path in and is controlled by the controller 140. Figure 1 The controller 140 in the embodiment controls the switches in the fine-tuning branch circuit and reads the voltage V corresponding to the bit line BL. BL and V corresponding to the reference bit line RBL RBL same or different so that the voltage V BL and V RBL Trim to the same voltage level.

[0069] For example, reference Figure 4AThe first clamp circuit 222 includes a first main branch circuit MB1 and a plurality of first fine-tuning branch circuits TB1(1)-TB1(N). The first main branch circuit MB1 includes a first main transistor MT1 having a first terminal, a second terminal, and a control terminal, and a first main switch MS1. The first terminal of the first main transistor MT1 is coupled to a first connection node N1 between the first I / O node ION1 and the first clamp circuit 222, and the control terminal of the first main transistor MT1 is coupled to receive a clamp voltage (V 钳位 The first main switch MS1 is coupled between the second terminal of the first main transistor MT1 and the bit line BL, wherein the first main switch MS1 is turned on to electrically couple the bit line BL to the first main transistor MT1, and the first main switch MS1 is turned off to electrically isolate the bit line BL from the first main transistor MT1.

[0070] Each of the first trimming sub-circuits TB1(1)-TB1(N) includes a first trimming transistor TT1 having a first terminal, a second terminal, and a control terminal, and a first trimming switch TS1. The first terminal of the first trimming transistor TT1 is coupled to the first connection node N1, and the control terminal of the first trimming transistor TT1 is coupled to receive a clamping voltage (V 钳位 The first fine tuning switch TS1 is coupled between the second terminal of the first fine tuning transistor TT1 and a second connection node N2 between the first main switch MS1 and the bit line BL, wherein the first fine tuning switch TS1 is turned on to electrically couple the bit line BL to the first fine tuning transistor TT1, and the first fine tuning switch TS1 is turned off to electrically isolate the bit line BL from the first fine tuning transistor TT1.

[0071] Similarly, reference Figure 4B The second clamping circuit 223 includes a second main branch circuit MB2 and a plurality of second fine-tuning branch circuits TB2(1)-TB2(N). The second main branch circuit MB2 includes a second main transistor MT2 having a first terminal, a second terminal, and a control terminal, and a second main switch MS2. The first terminal of the second main transistor MT2 is coupled to a first connection node N1 between the second I / O node ION2 and the second clamping circuit 223, and the control terminal of the second main transistor MT2 is coupled to receive a clamping voltage (V 钳位 The second main switch MS2 is coupled between the second terminal of the second main transistor MT2 and the reference bit line RBL, wherein the second main switch MS2 is turned on to electrically couple the reference bit line RBL to the second main transistor MT2, and the second main switch MS2 is turned off to electrically isolate the bit line BL from the second main transistor MT2.

[0072] Each of the second trimming sub-circuits TB2(1)-TB2(N) includes a second trimming transistor TT2 having a first terminal, a second terminal, and a control terminal, and a second trimming switch TS2. The first terminal of the second trimming transistor TT2 is coupled to the first connection node N1, and the control terminal of the second trimming transistor TT2 is coupled to receive a clamping voltage (V 钳位 The second fine tuning switch TS2 is coupled between the second terminal of the second fine tuning transistor TT2 and a second connection node N2 between the second main switch MS2 and the reference bit line RBL, wherein the second fine tuning switch TS2 is turned on to electrically connect the reference bit line RBL to the second fine tuning transistor TT2, and the second fine tuning switch TS2 is turned off to electrically isolate the reference bit line RBL from the second fine tuning transistor TT2.

[0073] It should be mentioned that in the embodiments of the present disclosure, N represents the total number of fine-tuning branch circuits, and P is a default value representing the predetermined number of closed fine-tuning branch circuits. In one embodiment of the present disclosure, P can be set to '8' and N can be set to '16'. In other words, the number of first fine-tuning branch circuits initially closed in the first clamp circuit 222 is 8, that is, the first fine-tuning branch circuits TB1 (1)-TB1 (8) are closed; the number of second fine-tuning branch circuits initially closed in the second clamp circuit 222 is 8, that is, the second fine-tuning branch circuits TB2 (1)-TB2 (8) are closed. Those who implement the embodiments of the present disclosure can set P and N to other numbers. For example, P can be set to one of the numbers '1' to '16' and N can be set to '16'. In other embodiments, P can be set to one of the numbers '1' to '32' and N can be set to '32'.

[0074] In an embodiment, the first main branch MB1 may not include the first main switch MS1 and the second main branch MB2 may not include the second main switch MS2. In other words, in this embodiment, the second terminals of the first / second main transistors MT1 / MT2 are coupled to the second connection node N2.

[0075] In the embodiment, by closing or opening the first fine-tuning switch TS11-TS1 N One or more of the bit lines BL can be used to fine-tune the voltage corresponding to the bit line BL (eg, V BL ), and the voltage corresponding to the fine adjustment of the bit line BL is proportional to the total number of the first fine adjustment switches currently closed in the first clamp circuit 222. In addition, by closing or opening the second fine adjustment switches TS21-TS2 N One or more of the voltages corresponding to the reference bit line RBL (eg, V RBL), and the voltage corresponding to the fine adjustment of the reference bit line RBL is proportional to the total number of the second fine adjustment switches currently closed in the second clamp circuit 223. In an embodiment, Figure 2 The controller 120 in the embodiment can read the readout signal outputted from the first I / O node ION1 and the second I / O node ION2 to control Figure 4A and Figure 4B The first fine-tuning switch TS11-TS1 N and the second fine-tuning switch TS21-TS2 N , for adjusting / fine-tuning the voltages on the first I / O node ION1 and the second I / O node ION2 according to the readout signal. In an embodiment, Figure 2 The controller 120 may use a stepwise fine-tuning scheme or a binary approximation fine-tuning scheme to determine the second fine-tuning switches TS21-TS2. N Is it closed or open, in other words, the second fine-tuning switch TS21-TS2 used to determine the closed N The number and disconnection of the other second fine-tuning switch TS21-TS2 N .

[0076] Reference again Figure 3A , the sense amplifier 220 further includes a first resistor R BL and the second resistor R RBL The first resistor RBL is coupled between the first clamp circuit 222 and the bit line BL, and the second resistor RRBL is coupled between the second clamp circuit 223 and the reference bit line RBL. BL Can be Figure 1 The equivalent resistance of the memory cell 112, and the second resistor R BL Can be Figure 1 The equivalent resistance of the reference cell 114 in FIG.

[0077] refer to Figure 5 and Figure 6In an embodiment of the present disclosure, the sense amplifier 120 includes a voltage comparator 124 having a fine-tuning correction function (e.g., a fine-tunable voltage comparator) and a clamp device 125 having a reduced offset function (e.g., an offset compensation clamp device). More specifically, the sense amplifier 120 includes a voltage comparator 124 and a clamp device 125. The voltage comparator 124 is coupled to the bit line BL and the reference bit line RBL, and is configured to compare a first input voltage and a second input voltage to output a read signal. The clamp device 125 is coupled between the voltage comparator 124, the bit line BL, and the reference bit line RBL. The sense amplifier 120 also includes a controller 140. The controller 140 can be coupled to the voltage comparator 124 and the clamp device 125 for controlling switching to the voltage comparator 124 and the clamp device 125 so as to implement the functions of the voltage comparator 124 and the clamp device 125. In detail, an example of the voltage comparator 124 is Figure 6 The voltage comparator 524 is provided in the first fine-tuning sub-circuit and the second fine-tuning sub-circuit has a plurality of switches. Figure 2 The controller 120 in may use a stepwise trimming scheme or a binary approximation trimming scheme to determine whether each of the first trimming branch circuits and each of the second trimming branch circuits are closed or open.

[0078] In addition, reference Figure 5 The voltage comparator 124 is further configured to fine-tune the first voltage V1 corresponding to the bit line BL and fine-tune the second voltage V2 corresponding to the reference bit line RBL, and the clamp device 125 is configured to adjust the bias voltage V 偏置 Provides a first clamping voltage and a second clamping voltage. In detail, the clamping device 125 requires a reference voltage to adjust the voltage according to the bias voltage V 偏置 The presence or absence of an offset voltage difference between the voltages on the bit line BL and the reference bit line RBL is known to implement an offset compensation function. A first input voltage and a second input voltage are input to a first I / O node and a second I / O node, respectively, and a first output voltage and a second output voltage corresponding to a read signal are output from the first I / O node and the second I / O node of the sense amplifier 120, respectively.

[0079] In an embodiment of the present disclosure, the voltage comparator 524 includes a first circuit 610, a second circuit 620, and a third circuit 630. The second circuit 620 is cross-coupled to the third circuit 630 via the first I / O node ION1, the second I / O node ION2, the first connection node CN1, and the second connection node CN2.

[0080] The first circuit includes a first transistor M1, a second transistor M2, and a third transistor M3. A first terminal of the first transistor M1 and a first terminal of the second transistor M2 are coupled to a first reference voltage level (eg, VDD ), a control terminal of the first transistor M1, a control terminal of the second transistor M2, and a control terminal of the third transistor M3 are coupled to receive a precharge signal PREB, a second terminal of the first transistor M1 and a second terminal of the third transistor M3 are coupled to a first node N1 and a connection node between the first transistor M1 and the third transistor M3, and a second terminal of the second transistor M2 and a first terminal of the third transistor M3 are coupled to a second node N2 and another connection node between the second transistor M2 and the third transistor M3.

[0081] The second circuit 620 includes a fourth transistor M4, a first main branch circuit (such as Figure 6 The embodiment of the present invention further comprises an n-type transistor (as shown); and a plurality of first fine-tuning sub-circuits. A first terminal of a fourth transistor M4 is coupled to a first reference voltage level, a control terminal of the fourth transistor M4 is coupled to a first node N1, and a second terminal of the fourth transistor M4 is coupled to the first main sub-circuit via a first I / O node ION1. A second terminal of the first fine-tuning sub-circuit is coupled to a second terminal of the first main sub-circuit via a third node N3, and a control terminal of the first fine-tuning sub-circuit is coupled to a control terminal of the n-type transistor of the first main sub-circuit.

[0082] The third circuit 630 includes a fifth transistor M5, a second main branch circuit (such as Figure 6 The embodiment of the present invention also includes an n-type transistor in the third circuit 630 (shown as an n-type transistor in the third circuit 630); and a plurality of second fine-tuning sub-circuits. A first terminal of a fifth transistor M5 is coupled to a first reference voltage level, a control terminal of the fifth transistor M5 is coupled to a second node N2, and a second terminal of the fifth transistor M5 is coupled to the second main sub-circuit via a second I / O node ION2. A second terminal of the second fine-tuning sub-circuit is coupled to a second terminal of the second main sub-circuit via a fourth node N4, and a control terminal of the second fine-tuning sub-circuit is coupled to a control terminal of an n-type transistor of the second main sub-circuit.

[0083] It should be noted that both the third circuit 620 and the fourth circuit 630 of the voltage comparator 524 have a fine-tuning circuit (e.g., a first fine-tuning branch circuit and a second fine-tuning branch circuit), but the present disclosure is not limited thereto. For example, in another embodiment, only the third circuit 620 or the fourth circuit 630 may have a fine-tuning circuit. In other words, in another embodiment, the voltage comparator 524 may provide a fine-tuning correction function only through the third circuit 620 or the fourth circuit 630 having the fine-tuning circuit. Figure 7A and Figure 7B Describe the details of the fine-tuning circuit.

[0084] refer to Figure 7AThe first main branch circuit MT1 of the third circuit 620 includes a first main transistor MT1, wherein a first terminal of the first main transistor MT1 is coupled to the first I / O node ION1, a control terminal of the first main transistor MT1 is coupled to a first connection node CN1 between the first node N1 and the second I / O node ION2, and a second terminal of the first main transistor MT1 is coupled to a third node N3.

[0085] Each of the first fine-tuning branch circuits TB1(1)-TB1(M) includes a first fine-tuning switch TS1 and a first fine-tuning transistor TT1, wherein a first terminal of the first fine-tuning transistor TT1 is coupled to the first fine-tuning switch TS1, a control terminal of the first fine-tuning transistor TT1 is coupled to the first connection node CN1, and a second terminal of the first fine-tuning transistor TT1 is coupled to the third node N3.

[0086] The first fine-tuning switch TS1 is coupled to the first terminal of the first fine-tuning transistor TT1 and a first reference voltage level (eg, V DD ), wherein the first fine-tuning switch TS1 is turned on to electrically couple the first reference voltage level to the first fine-tuning transistor TT1, and the first fine-tuning switch TS1 is turned off to electrically isolate the first reference voltage level from the first fine-tuning transistor TT1. The voltage corresponding to the third node N3 is fine-tuned by closing or opening one or more of the first fine-tuning switches TS1, and the fine-tuned voltage corresponding to the third node N3 is proportional to the total number of the first fine-tuning switches TS1 currently closed in the third circuit 620.

[0087] Similarly, reference Figure 7B The second main branch circuit MT2 of the fourth circuit 630 includes a second main transistor MT2, wherein a first terminal of the second main transistor MT2 is coupled to the second I / O node ION2, a control terminal of the second main transistor MT2 is coupled to a second connection node CN2 between the second node N2 and the first I / O node ION1, and a second terminal of the second main transistor MT2 is coupled to a fourth node N4.

[0088] Each of the second fine-tuning branch circuits TB2(1)-TB2(M) includes a second fine-tuning switch TS2 and a second fine-tuning transistor TT2, wherein a first terminal of the second fine-tuning transistor TT2 is coupled to the second fine-tuning switch TS2, a control terminal of the second fine-tuning transistor TT2 is coupled to the second connection node CN2, and a second terminal of the second fine-tuning transistor TT2 is coupled to the fourth node N4.

[0089] The second fine-tuning switch TS2 is coupled to the first terminal of the second fine-tuning transistor TT2 and the first reference voltage level (eg, V DD), wherein the second fine-tuning switch TS2 is turned on to electrically couple the first reference voltage level to the second fine-tuning transistor TT2, and the second fine-tuning switch TS2 is turned off to electrically isolate the first reference voltage level from the second fine-tuning transistor TT2. The voltage corresponding to the fourth node N4 is fine-tuned by closing or opening one or more of the second fine-tuning switches TS2, and the fine-tuned voltage corresponding to the fourth node N4 is proportional to the total number of the second fine-tuning switches TS2 currently closed in the fourth circuit 630.

[0090] It should be mentioned that in the embodiments of the present disclosure, M represents the total amount of fine-tuning branch circuits, and Q is a default value representing the predetermined amount of closed fine-tuning branch circuits. In one embodiment, Q can be set to '4', and M can be set to '8'. In other words, the number of first fine-tuning branch circuits initially closed in the third circuit 620 is 4, that is, the first fine-tuning branch circuits TB1 (1)-TB1 (4) are closed; the number of second fine-tuning branch circuits initially closed in the fourth circuit 630 is 4, that is, the second fine-tuning branch circuits TB2 (1)-TB2 (4) are closed. Those who implement the embodiments of the present disclosure can set Q and M to other numbers. For example, Q can be set to one of the numbers '1' to '8', and M can be set to '8'. In other embodiments, Q can be set to one of the numbers '1' to '16', and M can be set to '16'.

[0091] In the embodiment, by closing or opening the first fine-tuning switch TS11-TS1 N The voltage corresponding to the bit line BL (for example, the voltage corresponding to the third node N3) is fine-tuned by one or more of the first fine-tuning switches TS21-TS2, and the fine-tuned voltage corresponding to the bit line BL is proportional to the total number of the first fine-tuning switches currently closed in the first fine-tuning branch circuits TB1(1)-TB1(M) of the third circuit 620. In addition, by closing or opening the second fine-tuning switches TS21-TS2 N One or more of the fourth circuit 630 are used to fine-tune the voltage corresponding to the reference bit line RBL (for example, the voltage corresponding to the fourth node N4), and the fine-tuned voltage corresponding to the reference bit line RBL is proportional to the total number of currently closed second fine-tuning switches of the second fine-tuning branch circuits TB2(1)-TB2(M) of the fourth circuit 630.

[0092] It should be noted that in the case of the stepwise fine adjustment scheme or the binary approximation fine adjustment scheme, since the clamp device 525 provides a reduced offset function to compensate for the Figure 5 The mismatch between transistor NM1 and transistor NM2 controlled by controller 140 can reduce the required fine-tuning steps / range. Figure 6 The total number of trimming subcircuits (ie, M) in the trimmable voltage comparator is set to be less than Figure 3A The total number of trimming subcircuits (ie, N) in the trimmable clamping circuit can be adjusted; and Figure 6 The amount of the initially closed trimming branch circuit (ie, Q) in the trimmable voltage comparator is set to be less than Figure 3A The value of the amount of initial closed trim branch circuit (ie, P) in the trimmable clamp circuit.

[0093] refer to Figure 6 and Figure 8A The clamping device 525 includes a first clamping circuit 640, a second clamping circuit 650, and an operational amplifier OP. The first clamping circuit 640 is coupled between the voltage comparator 524 and the bit line BL. The second clamping circuit 650 is coupled between the voltage comparator 524 and the reference bit line RBL.

[0094] The operational amplifier OP has an output terminal, a first input terminal, and a second input terminal, wherein the output terminal is coupled to a connection node between the first clamp circuit 640 and the second clamp circuit 650, and the first input terminal is coupled to receive a bias voltage (e.g., V 偏置 ), and the second input terminal is coupled to an additional connection node between the first clamping circuit 640 and the second clamping circuit 650.

[0095] The first clamp circuit 640 includes a first transistor NM1, a first switch SW1, a second switch SW2, and a first capacitor C1. A first terminal of the first transistor NM1 is coupled to the third node N3 of the second circuit 620, and a control terminal of the first transistor NM1 is coupled to a first connection node between the first switch SW1 and the first terminal of the first capacitor C1, wherein the second terminal of the first capacitor C1 is coupled to a second reference voltage level (e.g., ground). The first switch SW1 is coupled between a first connection node CN1 and a connection node between the first clamp circuit 640 and the second clamp circuit 650. Turning on the first switch SW1 electrically couples the connection node to the first transistor NM1 and the first capacitor C1, and turning off the first switch SW1 electrically isolates the connection node from the first transistor NM1 and the first capacitor C1.

[0096] The second switch SW2 is coupled between the second terminal of the first transistor NM1 and an additional connection node between the first clamp circuit 640 and the second clamp circuit 650, wherein turning on the second switch SW2 electrically couples the additional connection node to the first transistor NM1, and turning off the second switch SW2 electrically isolates the additional connection node from the first transistor. The first capacitor C1 is configured to store charge corresponding to a voltage at the control terminal of the first transistor NM1.

[0097] The second clamp circuit 650 includes a second transistor NM2, a third switch SW3, a fourth switch SW4, and a second capacitor C2. A first terminal of the second transistor NM2 is coupled to the fourth node N4 of the third circuit 630, a control terminal of the second transistor NM2 is coupled to a second connection node CN2 between the third switch SW3 and the first terminal of the second capacitor C2, and a second terminal of the second capacitor C2 is coupled to a second reference voltage level (e.g., ground). The third switch SW3 is coupled between the second connection node CN2 and a connection node between the first clamp circuit 640 and the second clamp circuit 650. Turning on the third switch SW3 electrically couples the connection node to the second transistor NM2 and the second capacitor C2, and turning off the third switch SW3 electrically isolates the connection node from the second transistor NM2 and the second capacitor C2.

[0098] The fourth switch SW4 is coupled between the second terminal of the second transistor NM2 and the other connection node between the first clamp circuit 640 and the second clamp circuit 650, wherein the fourth switch SW4 is turned on to electrically couple the other connection node to the second transistor NM2, and the fourth switch SW4 is turned off to electrically isolate the other connection node from the second transistor NM2. The second capacitor C2 is configured to store a charge corresponding to the voltage of the control terminal of the second transistor C2. Figure 8B Steps S810 to S850 in the embodiment of the present disclosure are described. Figure 8A Operation of the voltage comparator.

[0099] The following describes the embodiments of the present disclosure. Figure 7A and 7B The operation of the voltage comparator. Figure 7A For example, Figure 7A The second circuit 620 includes a main branch circuit having transistors M4 and MT1 and a plurality of first fine-tuning branch circuits. Each first fine-tuning branch circuit has a first fine-tuning transistor TT11 to TT1 through each first fine-tuning transistor TT11 to TT1 M and the first fine-tuning switch TS11 to TS1 M Each first fine-tuning switch TS11 to TS1 M used for conducting or non-conducting current paths and consists of Figure 5 The controller 140 controls the operation of the controller. Figure 5 The controller 140 in the embodiment controls the switches in the fine-tuning branch circuit and reads the voltage V corresponding to the bit line BL. BL and V corresponding to the reference bit line RBL RBL same or different so that the voltage V BL and V RBL Trim to the same voltage level. Figure 5The controller 140 may use a stepwise fine-tuning scheme or a binary approximation fine-tuning scheme to determine the disconnected first fine-tuning switches TS11 to TS12 corresponding to the bit line BL and corresponding to the reference bit line RBL. M The number and closing of the other first fine-tuning switch TS11 to TS1 M The number of is the same or different. And, Figure 7B The third circuit 630 includes a main branch circuit having transistors M5 and MT2 and a plurality of second fine-tuning branch circuits. Each second fine-tuning branch circuit has a plurality of second fine-tuning transistors TT21 to TT21. M and the second fine-tuning switch TS21 to TS2 M Each second trimming switch TS21 to TS2 M Used to conduct or not conduct the current path and is Figure 5 The controller 140 controls the operation of the controller. Figure 7B The operation of the third circuit 630 can be compared with Figure 7A The operation of the second circuit 620 is the same.

[0100] Figure 8B According to some embodiments of the present disclosure, Figure 8A Flowchart showing how the offset compensation clamp device in FIG. 1 charges the clamp voltage. Figure 8B The steps of the flowchart can be represented by Figure 5 The controller 140 in FIG. 1 is implemented while performing the offset compensation function of the clamp device 525 to Figure 8A V in BL and V RBL The clamping voltage is charged. This can be implemented by a processor, integrated circuit, microcontroller (MCU) or other types of control circuit modules. Figure 5 Controller 140 in. Reference Figure 8A and Figure 8B In step S810, the first switch SW1 and the second switch SW2 of the first clamping circuit 640 of the clamping device 525 are closed by the control signal SE1 (for example, at a high level), and the third switch SW3 and the fourth switch SW4 of the second clamping circuit 650 of the clamping device 525 are opened by the control signal SE2 (for example, at a low level), so as to charge the first capacitor C1 of the first clamping circuit 640. When the operational amplifier OP enters the steady state, the first capacitor C1 is charged to the first clamping voltage V 钳位1 That is, the voltage on the bit line BL is greater than the bias voltage V BL At the same time, the operational amplifier OP enters a steady state.

[0101] In step S820, in response to determining that the operational amplifier OP enters a steady state, it is determined that the charging of the first capacitor C1 is completed, wherein the bias voltage V 偏置 = equal to the voltage of the second terminal of the first transistor NM1 of the first clamp circuit 640 when the operational amplifier OP enters the steady state (eg, V BL In other words, in response to the operational amplifier OP entering the steady state after both the first switch SW1 and the second switch SW2 are closed and both the third switch SW3 and the fourth switch SW4 are opened, Figure 6 The first resistor R BL The voltage obtained at the third node CN3 is equal to the bias voltage V 偏置 , and the voltage corresponding to the control terminal of the first transistor NM1 (eg, V 钳位1 ) is stored in the first capacitor C1.

[0102] In step S830, the first switch SW1 and the second switch SW2 of the first clamp circuit 640 are opened by the control signal SE1 (e.g., at a low level), and the third switch SW3 and the fourth switch SW4 of the second clamp circuit 650 are closed by the control signal SE2 (e.g., at a high level), so as to charge the second capacitor C2 of the second clamp circuit 650. When the operational amplifier OP enters another steady state, the capacitor C2 is charged to the second clamp voltage V 钳位2 That is, the voltage on the reference bit line RBL is greater than the bias voltage V BL At the same time, the operational amplifier OP enters another stable state.

[0103] In step S840, in response to determining that the operational amplifier OP enters another steady state, it is determined that the charging of the second capacitor is completed, wherein the bias voltage V 偏置 is equal to the voltage (eg, V RBL ). In other words, in response to the operational amplifier OP entering another stable state after both the first switch SW1 and the second switch SW2 are opened and the third switch SW3 and the fourth switch SW4 are closed, Figure 6 The second resistor R RBL The voltage obtained at the fourth node CN4 is equal to the bias voltage V 偏置 , and the voltage corresponding to the control terminal of the second transistor NM2 (eg, V 钳位2 ) is stored in the second capacitor C2.

[0104] In other words, after steps S810-S840, the first clamping voltage V is provided to the control terminals of the n-type transistors NM1 and NM2. 钳位1 and the second clamping voltage V 钳位2 At the same time, the first clamping voltage V is obtained through capacitors C1 and C2 钳位1 and the second clamping voltage V 钳位2 , and the voltages corresponding to the second terminals of the n-type transistors NM1 and NM2 (ie, the third node CN3 and the fourth node CN4) will be the same (eg, V 偏置 ) in order to eliminate the influence of mismatch between the n-type transistors NM1 and NM2 caused by inevitable process variations.

[0105] It should be noted that the bias voltage V 偏置 The value of is predetermined according to the type of memory cell. For example, for MRAM (magnetoresistive random access memory), the bias voltage V 偏置 Set to about 200mV; for RRAM (resistive random access memory), the bias voltage V 偏置 Set to about 300mV. If the bias voltage V 偏置 If the value of is set to a value much higher than the appropriate level (e.g., 400mV for MRAM and 600mV for RRAM), the possibility of read disturb phenomenon will be greatly increased.

[0106] Figure 8C According to some embodiments of the present disclosure, Figure 8A Flowchart showing how the offset compensation clamp device in FIG. 1 discharges the clamp voltage. Figure 8C The steps of the flowchart can be represented by Figure 5 The controller 140 in FIG. 1 is implemented while performing the offset compensation function of the clamp device 525 to Figure 8A V in BL and V RBL Discharge the clamp voltage. Figure 8A and Figure 8C In step S850, the first switch, the second switch, the third switch and the fourth switch are turned off by controlling signals SE1 and SE2.

[0107] Next, in step S860, the first capacitor C1 provides a first clamping voltage V to the control terminal of the first transistor NM1 of the first clamping circuit 640 by discharging the first capacitor C1 of the first clamping circuit 640. 钳位1 In step S870, the second clamping voltage V is provided to the control terminal of the second transistor NM2 of the second clamping circuit 650 by discharging the second capacitor C2 of the second clamping circuit 650. 钳位2 .

[0108] Next, in step S880, the same bit line voltage V corresponding to the bit line BL and the reference bit line RBL is obtained. BL and the reference bit line voltage V RBL , so as to reduce the influence of the mismatch between the first clamp circuit 640 (eg, the first transistor NM1) and the second clamp circuit 650 (eg, the second transistor NM2). Specifically, since the control terminals of the first transistor NM1 and the second transistor NM2 receive the first clamp voltage V 钳位1 and the second clamping voltage V 钳位2 , so the first transistor NM1 and the second transistor NM2 are maintained, and the voltages at the second terminals of the first transistor NM1 and the second transistor NM2 (eg, V BL and V RBL ) will be the same (for example, with the bias voltage V 偏置 same).

[0109] Figure 9 FIG2 shows a schematic diagram of adjusting the size of a clamping device by fine-tuning a branch according to some embodiments of the present disclosure. Figure 9 and Figure 4A (or Figure 4B ), the proposed curve represents the relationship between the provided trimming steps / range and the size of the clamping device. The intermediate clamp size "100%" is the default size of the clamping device (e.g., the first clamping circuit / the second clamping circuit) corresponding to a "100%" trimming step (e.g., 8 trimming branches closed). The clamping device size represents the total ratio of the width to length of the transistors of the first clamping circuit / the second clamping circuit. The device size of all transistors in the trimming branch circuit is predetermined and different.

[0110] In addition, if Figure 9 As shown by the arrows in , closing more trimming branches will increase the clamp device size, while closing fewer trimming branches will reduce the clamp device size. Each trimming step may affect the default bit line voltage or the default reference bit line voltage by 1.3%.

[0111] For example, if it is necessary to reduce the reference bit line voltage V RBL To compensate for the mismatch of the first clamp circuit 222, the number of closed second fine-tuning switches is adjusted from 8 (the default number of closed second fine-tuning switches) to 7 (for example, the second fine-tuning switches TS11-TS17 are currently closed after the second fine-tuning switch TS18 is opened), and the reference bit line voltage V RBL Decreases to the reference bit line voltage V RBL98.7% of the initial 100%. At the same time, the size of the clamping device of the second clamping circuit is reduced to about 92% of the initial clamping device size (100%). In an embodiment of the present disclosure, the formula of the proposed curve is:

[0112] y=55.258x 3 -140.46x 2 +121.81x-35.609

[0113] y represents the clamp device size, and x represents the initial 100% voltage of the bit line corresponding to the reference bit line (e.g., V BL or V RBL ). For example, assuming x equals 1.013 (the total number of closed trimming subcircuits is adjusted from 8 to 9, the expected trimming voltage is 101.3% of the 100% voltage (100% + 1.3%)). Based on the above formula, the clamp device size (y) is adjusted to 109% of the original 100% clamp device size.

[0114] It should be noted that in the embodiment of the present disclosure, the interval between each of the fine-tuning steps is 1.3% of the initial voltage, but the present invention is not limited to this. For example, in another embodiment, the interval between each of the fine-tuning steps can be set to other values ​​based on the formula of the proposed curve. In addition, the total number of fine-tuning branches of a fine-tunable clamp circuit can be increased to a value greater than 16 (for example, as shown by the dashed line).

[0115] Reference again Figure 6 , the sense amplifier 520 further includes a first resistor R BL and the second resistor R RBL The first resistor R BL The second resistor R is coupled between the bit line BL and a third connection node CN3 between the second switch SW2 and the second terminal of the first transistor NM1. RBL A first resistor R is coupled between the reference bit line RBL and a fourth connection node CN4 between the fourth switch SW4 and the second terminal of the second transistor NM2. In addition, after both the first switch SW1 and the second switch SW2 are closed and both the third switch SW3 and the fourth switch SW4 are opened, a first resistor R corresponding to the bit line BL is obtained. BL The voltage (for example, V BL ), and after closing both the third switch SW3 and the fourth switch SW4 and opening both the first switch SW1 and the second switch SW2, a second resistor R corresponding to the reference bit line RBL is obtained. RBL The voltage (for example, V RBL ). Moreover, when the switches SW1-SW4 are turned off, a bias voltage V 偏置 The voltage VBL and voltage V RBL .

[0116] refer to Figure 10 In an embodiment of the present disclosure, the sense amplifier 120 includes an offset-compensated and trimmable voltage comparator 126 (e.g., a voltage comparator having an offset-compensation function and a trimming correction function), a first clamping circuit 127, and a second clamping circuit 128. The first clamping circuit 127 and the second clamping circuit 128 may be, for example, Figure 3A The clamp circuit has a main branch circuit, and the first clamp circuit 127 and the second clamp circuit 128 do not have Figure 3A The sense amplifier 120 further includes a controller 140. The controller 140 may be coupled to the offset compensation and trimmable voltage comparator 126 to control switching to the offset compensation and trimmable voltage comparator 126 so as to implement the functions of the offset compensation and trimmable voltage comparator 126.

[0117] refer to Figure 11 In an embodiment of the present disclosure, the sense amplifier 120 includes a conventional voltage comparator 129 and an offset compensation and trimmable clamp device 130 (e.g., the clamp device has both an offset compensation function and a trim correction function). The sense amplifier 120 also includes a controller 140. The controller 140 can be coupled to the offset compensation and trimmable clamp device 130 to control switching to the offset compensation and trimmable clamp device 130 so as to implement the functions of the offset compensation and trimmable clamp device 130.

[0118] Based on the aforementioned embodiments, the provided sense amplifier with offset compensation and trim correction functions, and the nonvolatile memory device using the same, can reduce the required adjustment offset to compensate for the mismatch between transistors corresponding to a bit line and a reference bit line, and fine-tune the voltages corresponding to the bit line and the reference bit line to compensate for the mismatch between the transistors corresponding to the bit line and the reference bit line. Furthermore, due to the provided offset compensation clamp device, the total number of trimming steps / ranges corresponding to the trimmable voltage comparator can be reduced. Consequently, the provided sense amplifier improves the efficiency and accuracy of read operations performed on memory cells.

[0119] In some embodiments of the present disclosure, a sense amplifier is provided. The sense amplifier includes a voltage comparator with offset compensation, a first clamping circuit, and a second clamping circuit. The voltage comparator with offset compensation is coupled to a bit line and a reference bit line via a first I / O node and a second I / O node of the sense amplifier, respectively, and is configured to compare a first input voltage and a second input voltage to output a sense signal. The first clamping circuit is coupled between the first I / O node and the bit line. The second clamping circuit is coupled between the second I / O node and the reference bit line. The first clamping circuit and the second clamping circuit respectively fine-tune a voltage corresponding to the bit line and a voltage corresponding to the reference bit line to match the voltage corresponding to the bit line.

[0120] In the above-mentioned sense amplifier, the first clamping circuit includes a first main branch circuit and a plurality of first fine-tuning branch circuits, wherein the first main branch circuit includes: a first main transistor having a first terminal, a second terminal, and a control terminal, wherein the first terminal of the first main transistor is coupled to a first connection node between a first I / O node and the first clamping circuit, and a terminal of the first main transistor is coupled to receive a clamping voltage; and a first main switch coupled between the second terminal of the first main transistor and a bit line, wherein turning on the first main switch electrically couples the bit line to the first main transistor, and turning off the first main switch electrically couples the bit line to the first main transistor. The bit line is electrically isolated from the first main transistor, and each of the first fine-tuning branch circuits includes: a first fine-tuning transistor having a first terminal, a second terminal, and a control terminal, wherein the first terminal of the first fine-tuning transistor is coupled to the first connection node and the control terminal of the first fine-tuning transistor is coupled to receive the clamping voltage; and a first fine-tuning switch coupled between the second terminal of the first fine-tuning transistor and a second connection node between the first main switch and the bit line, wherein turning on the first fine-tuning switch electrically couples the bit line to the first fine-tuning transistor, and turning off the first fine-tuning switch electrically isolates the bit line from the first fine-tuning transistor.

[0121] In the above-mentioned sense amplifier, the second clamping circuit includes a second main branch circuit and a plurality of second fine-tuning branch circuits, wherein the second main branch circuit includes: a second main transistor having a first terminal, a second terminal, and a control terminal, wherein the first terminal of the second main transistor is coupled to a first connection node between the second I / O node and the second clamping circuit, and the control terminal of the second main transistor is coupled to receive a clamping voltage; and a second main switch coupled between the second terminal of the second main transistor and a reference bit line, wherein turning on the second main switch electrically couples the reference bit line to the second main transistor, and turning off the second main switch electrically couples the reference bit line to the second main transistor. The bit line is electrically isolated from the second main transistor, and each of the second fine-tuning branch circuits includes: a second fine-tuning transistor having a first terminal, a second terminal, and a control terminal, wherein the first terminal of the second fine-tuning transistor is coupled to the first connection node and the control terminal of the second fine-tuning transistor is coupled to receive the clamping voltage; and a second fine-tuning switch coupled between the second terminal of the second fine-tuning transistor and a second connection node between the second main switch and the reference bit line, wherein turning on the second fine-tuning switch electrically couples the reference bit line to the second fine-tuning transistor, and turning off the second fine-tuning switch electrically isolates the reference bit line from the second fine-tuning transistor.

[0122] In the above-mentioned readout amplifier, the voltage corresponding to the bit line is fine-tuned by closing or opening one or more of the first fine-tuning switches, and the fine-tuned voltage corresponding to the bit line is proportional to the total number of the currently closed first fine-tuning switches of the first clamping circuit, and the voltage corresponding to the reference bit line is fine-tuned by closing or opening one or more of the second fine-tuning switches, and the fine-tuned voltage corresponding to the reference bit line is proportional to the total number of the currently closed second fine-tuning switches of the second clamping circuit.

[0123] In the above-mentioned readout amplifier, the voltage comparator includes: a first circuit; and a second circuit, wherein the first circuit and the second circuit are coupled to a first I / O node and a second I / O node, wherein the first circuit includes: a first transistor, a second transistor, and a third transistor, wherein a first terminal of the first transistor and a first terminal of the second transistor are coupled to a first reference voltage level, a control terminal of the first transistor, a control terminal of the second transistor, and a control terminal of the third transistor are coupled to receive a precharge signal, a second terminal of the first transistor and a second terminal of the third transistor are coupled to the first I / O node and a connection node between the first transistor and the third transistor, and a second terminal of the second transistor and a first terminal of the third transistor are coupled to a second I / O node and another connection node between the second transistor and the third transistor.

[0124] In the above-mentioned sense amplifier, the second circuit of the voltage comparator includes: a fourth transistor, a fifth transistor, a first p-type transistor pair, a first n-type transistor pair, a second p-type transistor pair, and a second n-type transistor pair, wherein the first p-type transistor pair and the first n-type transistor pair form a third circuit, the second p-type transistor pair and the second n-type transistor pair form a fourth circuit, the third circuit is cross-coupled to the fourth circuit, and outputs of the third circuit and the fourth circuit are coupled to a first I / O node and a second I / O node, wherein the fourth transistor is coupled to the third circuit and the fourth circuit, wherein a first terminal of the fourth transistor is coupled to a first reference voltage level, a second terminal of the fourth transistor is coupled to a connection node between the fourth transistor, the third circuit, and the fourth circuit, and a control terminal of the fourth transistor is coupled to receive a first enable signal, wherein the fifth transistor is coupled to the third circuit and the fourth circuit, wherein a first terminal of the fifth transistor is coupled to a connection node between the fifth transistor, the third circuit, and the fourth circuit, a second terminal of the fifth transistor is coupled to a second reference voltage level, and a control terminal of the fifth transistor is coupled to receive a second enable signal.

[0125] In the above-mentioned readout amplifier, the difference between the first output voltage and the second output voltage corresponding to the readout signal is greater than the difference between the first input voltage and the second input voltage, wherein the first input voltage is input to the voltage comparator via the first I / O node, the second input voltage is input to the voltage comparator via the second I / O node, the first output voltage is output from the voltage comparator via the first I / O node, and the second output voltage is output from the voltage comparator via the second I / O node, and the readout amplifier further includes: a first resistor coupled between the first clamp circuit and the bit line; and a second resistor coupled between the second clamp circuit and the reference bit line.

[0126] In some embodiments of the present disclosure, a sense amplifier is provided. Another sense amplifier includes a voltage comparator and a clamping circuit. The voltage comparator is coupled to a bit line and a reference bit line and is configured to compare a first input voltage and a second input voltage to output a sense signal. The clamping circuit is coupled between the voltage comparator, the bit line, and the reference bit line. One of the voltage comparator and the clamping circuit has offset compensation. The voltage comparator is further configured to fine-tune a first voltage corresponding to the bit line and a second voltage corresponding to the reference bit line to match a voltage corresponding to the reference bit line with a voltage corresponding to the bit line.

[0127] In the above-mentioned readout amplifier, the voltage comparator includes: a first circuit; a second circuit; and a third circuit, wherein the second circuit is cross-coupled to the third circuit via a first I / O node and a second I / O node, wherein the first circuit includes: a first transistor, a second transistor, and a third transistor, wherein the first terminal of the first transistor and the first terminal of the second transistor are coupled to a first reference voltage level, the control terminal of the first transistor, the control terminal of the second transistor, and the control terminal of the third transistor are coupled to receive a precharge signal, the second terminal of the first transistor and the second terminal of the third transistor are coupled to a first node and a connection node between the first transistor and the third transistor, and the second terminal of the second transistor and the first terminal of the third transistor are coupled to a second node and another connection node between the second transistor and the third transistor.

[0128] In the above-mentioned readout amplifier, the second circuit includes: a fourth transistor; a first main branch circuit; and a plurality of first fine-tuning branch circuits, wherein a first terminal of the fourth transistor is coupled to a first reference voltage level, a control terminal of the fourth transistor is coupled to a first node, and a second terminal of the fourth transistor is coupled to the first main branch circuit via a first I / O node, wherein the first fine-tuning branch circuit is coupled to the first main branch circuit via a third node.

[0129] In the above-mentioned sense amplifier, the first main branch circuit includes: a first main transistor, wherein a first terminal of the first main transistor is coupled to a first I / O node, a control terminal of the first main transistor is coupled to a first connection node between the first node and a second I / O node, and a second terminal of the first main transistor is coupled to a third node, and each of the first fine-tuning branch circuits includes: a first fine-tuning switch; and a first fine-tuning transistor, wherein a first terminal of the first fine-tuning transistor is coupled to the first fine-tuning switch, a control terminal of the first fine-tuning transistor is coupled to the first connection node, and a second terminal of the first fine-tuning transistor is coupled to the third node, wherein the first fine-tuning switch is coupled between the first terminal of the first fine-tuning transistor and a first reference voltage level, wherein turning on the first fine-tuning switch electrically couples the first reference voltage level to the first fine-tuning transistor, and turning off the first fine-tuning switch electrically isolates the first reference voltage level from the first fine-tuning transistor, wherein a voltage corresponding to the third node is fine-tuned by closing or opening one or more of the first fine-tuning switches, and the fine-tuned voltage corresponding to the third node is proportional to the total number of first fine-tuning switches currently closed in the third circuit.

[0130] In the above-mentioned readout amplifier, the third circuit includes: a fifth transistor; a second main branch circuit; and a plurality of second fine-tuning branch circuits, wherein a first terminal of the fifth transistor is coupled to a first reference voltage level, a control terminal of the fifth transistor is coupled to a second node, and a second terminal of the fifth transistor is coupled to the second main branch circuit via a second I / O node, wherein the second fine-tuning branch circuit is coupled to the second main branch circuit via a fourth node.

[0131] In the above-mentioned sense amplifier, the second main branch circuit includes: a second main transistor, wherein a first terminal of the second main transistor is coupled to the second I / O node, a control terminal of the second main transistor is coupled to a second connection node between the second node and the first I / O node, and a second terminal of the second main transistor is coupled to a fourth node, and each of the second fine-tuning branch circuits includes: a second fine-tuning switch; and a second fine-tuning transistor, wherein a first terminal of the second fine-tuning transistor is coupled to the second fine-tuning switch, a control terminal of the second fine-tuning transistor is coupled to the second connection node, and a second terminal of the second fine-tuning transistor is coupled to the fourth node, wherein the second fine-tuning switch is coupled between the first terminal of the second fine-tuning transistor and a first reference voltage level, wherein turning on the second fine-tuning switch electrically couples the first reference voltage level to the second fine-tuning transistor, and turning off the second fine-tuning switch electrically isolates the first reference voltage level from the second fine-tuning transistor, wherein a voltage corresponding to the fourth node is fine-tuned by closing or opening one or more of the second fine-tuning switches, and the fine-tuned voltage corresponding to the fourth node is proportional to the total number of second fine-tuning switches currently closed in the third circuit.

[0132] In the above-mentioned readout amplifier, the clamping circuit includes: a first clamping circuit coupled between the voltage comparator and the bit line; a second clamping circuit coupled between the voltage comparator and the reference bit line; and an operational amplifier having an output terminal, a first input terminal, and a second input terminal, wherein the output terminal is coupled to a connection node between the first clamping circuit and the second clamping circuit, the first input terminal is coupled to receive a bias voltage, and the second input terminal is coupled to another connection node between the first clamping circuit and the second clamping circuit.

[0133] In the above-mentioned sense amplifier, the first clamping circuit includes a first transistor, a first switch, a second switch, and a first capacitor, wherein a first terminal of the first transistor is coupled to a third node of the second circuit, a control terminal of the first transistor is coupled to a first connection node between the first switch and a first terminal of the first capacitor, a second terminal of the first capacitor is coupled to a second reference voltage level, the first switch is coupled between the first connection node and a connection node between the first clamping circuit and the second clamping circuit, wherein turning on the first switch electrically couples the connection node to the first transistor and the first capacitor, and turning off the first switch electrically isolates the connection node from the first transistor and the first capacitor, the second switch is coupled between the second terminal of the first transistor and another connection node between the first clamping circuit and the second clamping circuit, wherein turning on the second switch electrically couples the other connection node to the first transistor, and turning off the second switch electrically isolates the other connection node from the first transistor, and the first capacitor is configured to store a charge corresponding to a voltage of the control terminal of the first transistor.

[0134] In the above-mentioned sense amplifier, the second clamping circuit includes a second transistor, a third switch, a fourth switch, and a second capacitor, wherein a first terminal of the second transistor is coupled to a fourth node of the third circuit, a control terminal of the second transistor is coupled to a second connection node between the third switch and the first terminal of the second capacitor, a second terminal of the second capacitor is coupled to a second reference voltage level, the third switch is coupled between the second connection node and a connection node between the first clamping circuit and the second clamping circuit, wherein turning on the third switch electrically couples the connection node to the second transistor and the second capacitor, and turning off the third switch electrically isolates the connection node from the second transistor and the second capacitor, the fourth switch is coupled between the second terminal of the second transistor and another connection node between the first clamping circuit and the second clamping circuit, wherein turning on the fourth switch electrically couples the other connection node to the second transistor, and turning off the fourth switch electrically isolates the other connection node from the second transistor, and the second capacitor is configured to store a charge corresponding to a voltage of the control terminal of the second transistor.

[0135] In the above-mentioned read-out amplifier, it also includes: a first resistor, coupled between the bit line and a third connection node between the second switch and the second terminal of the first transistor; and a second resistor, coupled between the reference bit line and a fourth connection node between the fourth switch and the second terminal of the second transistor, wherein after closing both the first switch and the second switch and opening both the third switch and the fourth switch, a voltage corresponding to the bit line is obtained for the first resistor, and wherein, after closing both the third switch and the fourth switch and opening both the first switch and the second switch, a voltage corresponding to the second resistor is obtained.

[0136] In the sense amplifier described above, in response to the operational amplifier entering a steady state after both the first and second switches are closed and the third and fourth switches are opened, a voltage across the first resistor equals the bias voltage, and a charge corresponding to the voltage of the control terminal of the first transistor is stored in the first capacitor. In response to the operational amplifier entering another steady state after both the first and second switches are opened and the third and fourth switches are closed, a voltage across the second resistor equals the bias voltage, and a charge corresponding to the voltage of the control terminal of the second transistor is stored in the second capacitor. Furthermore, after the first, second, third, and fourth switches are opened together, the first capacitor discharges the stored charge to the control terminal of the first transistor to provide a first clamping voltage to the control terminal of the first transistor, and the second capacitor discharges the stored charge to the control terminal of the second transistor to provide a second clamping voltage to the control terminal of the second transistor, so that the voltages across the first and second resistors are equal to the bias voltage. In some embodiments of the present disclosure, a method for operating a nonvolatile memory is provided. The nonvolatile memory includes a memory array and a sense amplifier, wherein the sense amplifier includes a voltage comparator with offset compensation, a first clamping circuit coupled between a first I / O node of the sense amplifier and a bit line, and a second clamping circuit coupled between a second I / O node of the sense amplifier and a reference bit line. The operating method includes the following steps: the voltage comparator compares a first input voltage and a second input voltage via the first I / O node and the second I / O node of the sense amplifier, respectively, to output a read signal; the first clamping circuit and the second clamping circuit respectively adjust a voltage corresponding to the bit line and a voltage corresponding to the reference bit line to match the voltage corresponding to the bit line.

[0137] In some embodiments of the present disclosure, a method for operating a non-volatile memory is provided. The non-volatile memory includes a memory array and a sense amplifier. The sense amplifier includes a voltage comparator and a clamp circuit, the clamp circuit being coupled to a first I / O node of the sense amplifier, a bit line, a second I / O node of the sense amplifier, and a reference bit line, and one of the voltage comparator and the clamp circuit has offset compensation. The operating method includes the following steps: the voltage comparator compares a first input voltage and a second input voltage via the first I / O node and the second I / O node of the sense amplifier, respectively, to output a read signal; and the voltage comparator fine-tunes a voltage corresponding to the bit line and a voltage corresponding to the reference bit line, respectively, to match the voltage corresponding to the reference bit line with the voltage corresponding to the bit line.

[0138] The features of several embodiments have been summarized above so that those skilled in the art can better understand aspects of the present disclosure. It will be understood by those skilled in the art that they can easily use the present disclosure as a design or modification for performing other processes and structures that have the same purpose and / or achieve the same advantages as the embodiments described herein. It will also be appreciated by those skilled in the art that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that various changes, substitutions, and modifications may be made without departing from the spirit and scope of the present disclosure.

Claims

1. A sense amplifier comprising: a voltage comparator having offset compensation, coupled to the bit line and the reference bit line via the first I / O node and the second I / O node of the sense amplifier, respectively, and configured to compare a first input voltage and a second input voltage to output a read signal; a first clamp circuit coupled between the first I / O node and the bit line; as well as a second clamping circuit coupled between the second I / O node and the reference bit line, The first clamping circuit and the second clamping circuit respectively fine-tune the voltage corresponding to the bit line and the voltage corresponding to the reference bit line so that the voltage corresponding to the reference bit line matches the voltage corresponding to the bit line.

2. The sense amplifier according to claim 1, wherein The first clamping circuit includes a first main branch circuit and a plurality of first fine-tuning branch circuits. Wherein, the first main branch circuit includes: a first master transistor having a first terminal, a second terminal, and a control terminal, wherein the first terminal of the first master transistor is coupled to a first connection node between the first I / O node and the first clamp circuit, and the terminals of the first master transistor are coupled to receive a clamp voltage; and a first main switch coupled between the second terminal of the first main transistor and the bit line, wherein turning on the first main switch electrically couples the bit line to the first main transistor, and turning off the first main switch electrically isolates the bit line from the first main transistor, and each of the first fine-tuning sub-circuits comprises: a first trimming transistor having a first terminal, a second terminal, and a control terminal, wherein the first terminal of the first trimming transistor is coupled to the first connection node and the control terminal of the first trimming transistor is coupled to receive the clamping voltage; and a first fine-tuning switch coupled between the second terminal of the first fine-tuning transistor and a second connection node between the first main switch and the bit line, wherein turning on the first fine-tuning switch electrically couples the bit line to the first fine-tuning transistor, and turning off the first fine-tuning switch electrically isolates the bit line from the first fine-tuning transistor.

3. The sense amplifier according to claim 2, wherein: The second clamping circuit includes a second main branch circuit and a plurality of second fine-tuning branch circuits. Wherein, the second main branch circuit includes: a second master transistor having a first terminal, a second terminal, and a control terminal, wherein the first terminal of the second master transistor is coupled to a first connection node between the second I / O node and the second clamp circuit, and the control terminal of the second master transistor is coupled to receive a clamp voltage; and a second main switch coupled between the second terminal of the second main transistor and the reference bit line, wherein turning on the second main switch electrically couples the reference bit line to the second main transistor, and turning off the second main switch electrically isolates the reference bit line from the second main transistor, and Each of the second trimming sub-circuits comprises: a second trimming transistor having a first terminal, a second terminal, and a control terminal, wherein the first terminal of the second trimming transistor is coupled to the first connection node and the control terminal of the second trimming transistor is coupled to receive the clamping voltage; and a second fine-tuning switch coupled between the second terminal of the second fine-tuning transistor and a second connection node between the second main switch and the reference bit line, wherein turning on the second fine-tuning switch electrically couples the reference bit line to the second fine-tuning transistor, and turning off the second fine-tuning switch electrically isolates the reference bit line from the second fine-tuning transistor.

4. The sense amplifier according to claim 3, wherein: The voltage corresponding to the bit line is fine-tuned by closing or opening one or more of the first fine-tuning switches, and the fine-tuned voltage corresponding to the bit line is proportional to the total number of currently closed first fine-tuning switches of the first clamp circuit, and, The voltage corresponding to the reference bit line is fine-tuned by closing or opening one or more of the second fine-tuning switches, and the fine-tuned voltage corresponding to the reference bit line is proportional to a total number of currently closed second fine-tuning switches of the second clamp circuit.

5. The sense amplifier according to claim 1 , wherein the voltage comparator comprises: First Circuit; as well as a second circuit, wherein the first circuit and the second circuit are coupled to the first I / O node and the second I / O node, Wherein, the first circuit includes: a first transistor, a second transistor, and a third transistor, wherein a first terminal of the first transistor and a first terminal of the second transistor are coupled to a first reference voltage level, The control terminal of the first transistor, the control terminal of the second transistor, and the control terminal of the third transistor are coupled to receive a precharge signal, The second terminal of the first transistor and the second terminal of the third transistor are coupled to the first I / O node, a connection node between the first transistor and the third transistor, and The second terminal of the second transistor and the first terminal of the third transistor are coupled to the second I / O node, a further connection node between the second transistor and the third transistor.

6. The sense amplifier according to claim 5, wherein: The second circuit of the voltage comparator includes: a fourth transistor, a fifth transistor, a first p-type transistor pair, a first n-type transistor pair, a second p-type transistor pair, and a second n-type transistor pair, wherein the first p-type transistor pair and the first n-type transistor pair form a third circuit, The second p-type transistor pair and the second n-type transistor pair form a fourth circuit, The third circuit is cross-coupled to the fourth circuit, and outputs of the third circuit and the fourth circuit are coupled to the first I / O node and the second I / O node, wherein the fourth transistor is coupled to the third circuit and the fourth circuit, wherein a first terminal of the fourth transistor is coupled to the first reference voltage level, a second terminal of the fourth transistor is coupled to a connection node between the fourth transistor, the third circuit, and the fourth circuit, a control terminal of the fourth transistor coupled to receive a first enable signal, wherein the fifth transistor is coupled to the third circuit and the fourth circuit, in, a first terminal of the fifth transistor is coupled to a connection node between the fifth transistor, the third circuit, and the fourth circuit, A second terminal of the fifth transistor is coupled to a second reference voltage level, and The control terminal of the fifth transistor is coupled to receive a second enable signal.

7. The sense amplifier according to claim 1, wherein: A difference between a first output voltage and a second output voltage corresponding to the readout signal is greater than a difference between the first input voltage and the second input voltage, wherein the first input voltage is input to the voltage comparator via the first I / O node, the second input voltage is input to the voltage comparator via the second I / O node, the first output voltage is output from the voltage comparator via the first I / O node, and the second output voltage is output from the voltage comparator via the second I / O node. And the sense amplifier further includes: a first resistor coupled between the first clamp circuit and the bit line; and A second resistor is coupled between the second clamp circuit and the reference bit line.

8. A sense amplifier comprising: a voltage comparator coupled to the bit line and the reference bit line and configured to compare a first input voltage and a second input voltage to output a readout signal; as well as a clamp circuit coupled between the voltage comparator, the bit line, and the reference bit line, wherein one of the voltage comparator and the clamping circuit has offset compensation, The voltage comparator is further configured to fine-tune a first voltage corresponding to the bit line and a second voltage corresponding to the reference bit line to match the voltage corresponding to the reference bit line with the voltage corresponding to the bit line.

9. The sense amplifier according to claim 8, wherein: The voltage comparator comprises: First Circuit; a second circuit; and a third circuit, wherein the second circuit is cross-coupled to the third circuit via the first I / O node and the second I / O node of the sense amplifier, Wherein, the first circuit includes: a first transistor, a second transistor, and a third transistor, wherein the first terminal of the first transistor and the first terminal of the second transistor are coupled to a first reference voltage level, The control terminal of the first transistor, the control terminal of the second transistor, and the control terminal of the third transistor are coupled to receive a precharge signal, The second terminal of the first transistor and the second terminal of the third transistor are coupled to a first node, a connection node between the first transistor and the third transistor, and The second terminal of the second transistor and the first terminal of the third transistor are coupled to a second node, a further connection node between the second transistor and the third transistor.

10. The sense amplifier according to claim 9, wherein The second circuit includes: a fourth transistor; a first main branch circuit; and a plurality of first fine-tuning branch circuits, wherein a first terminal of the fourth transistor is coupled to the first reference voltage level, A control terminal of the fourth transistor is coupled to the first node, and a second terminal of the fourth transistor is coupled to the first main branch circuit via the first I / O node, The first fine-tuning branch circuit is coupled to the first main branch circuit via a third node.

11. The sense amplifier according to claim 10, wherein: The first main branch circuit includes: a first master transistor, wherein a first terminal of the first master transistor is coupled to the first I / O node, a control terminal of the first master transistor is coupled to a first connection node between the first node and the second I / O node, and a second terminal of the first master transistor is coupled to the third node, and Each of the first trimming sub-circuits comprises: a first fine-tuning switch; and a first trimming transistor, wherein a first terminal of the first trimming transistor is coupled to the first trimming switch, a control terminal of the first trimming transistor is coupled to the first connection node, and a second terminal of the first trimming transistor is coupled to the third node, wherein the first fine-tuning switch is coupled between the first terminal of the first fine-tuning transistor and the first reference voltage level, wherein turning on the first fine-tuning switch electrically couples the first reference voltage level to the first fine-tuning transistor, and turning off the first fine-tuning switch electrically isolates the first reference voltage level from the first fine-tuning transistor, The voltage corresponding to the third node is fine-tuned by closing or opening one or more of the first fine-tuning switches, and the fine-tuned voltage corresponding to the third node is proportional to the total number of currently closed first fine-tuning switches of the third circuit.

12. The sense amplifier according to claim 9, wherein: The third circuit includes: a fifth transistor; a second main branch circuit; and a plurality of second fine-tuning branch circuits, wherein a first terminal of the fifth transistor is coupled to the first reference voltage level, The control terminal of the fifth transistor is coupled to the second node, and a second terminal of the fifth transistor is coupled to the second main branch circuit via the second I / O node, The second fine-tuning branch circuit is coupled to the second main branch circuit via a fourth node.

13. The sense amplifier according to claim 12, wherein: The second main branch circuit includes: a second master transistor, wherein a first terminal of the second master transistor is coupled to the second I / O node, a control terminal of the second master transistor is coupled to a second connection node between the second node and the first I / O node, and a second terminal of the second master transistor is coupled to the fourth node, and Each of the second trimming sub-circuits comprises: a second fine-tuning switch; and a second fine-tuning transistor, wherein a first terminal of the second fine-tuning transistor is coupled to the second fine-tuning switch, a control terminal of the second fine-tuning transistor is coupled to the second connection node, and a second terminal of the second fine-tuning transistor is coupled to the fourth node, wherein the second fine-tuning switch is coupled between the first terminal of the second fine-tuning transistor and the first reference voltage level, wherein turning on the second fine-tuning switch electrically couples the first reference voltage level to the second fine-tuning transistor, and turning off the second fine-tuning switch electrically isolates the first reference voltage level from the second fine-tuning transistor, The voltage corresponding to the fourth node is fine-tuned by closing or opening one or more of the second fine-tuning switches, and the fine-tuned voltage corresponding to the fourth node is proportional to the total number of currently closed second fine-tuning switches of the third circuit.

14. The sense amplifier according to claim 9, wherein The clamping circuit comprises: a first clamping circuit coupled between the voltage comparator and the bit line; a second clamp circuit coupled between the voltage comparator and the reference bit line; and An operational amplifier having an output terminal, a first input terminal, and a second input terminal, wherein the output terminal is coupled to a connection node between the first clamp circuit and the second clamp circuit, the first input terminal is coupled to receive a bias voltage, and the second input terminal is coupled to another connection node between the first clamp circuit and the second clamp circuit.

15. The sense amplifier according to claim 14, wherein The first clamping circuit includes a first transistor, a first switch, a second switch and a first capacitor. wherein a first terminal of the first transistor is coupled to a third node of the second circuit, and a control terminal of the first transistor is coupled to a first connection node between the first switch and a first terminal of the first capacitor, a second terminal of the first capacitor is coupled to a second reference voltage level, The first switch is coupled between the first connection node and the connection node between the first clamping circuit and the second clamping circuit, wherein turning on the first switch electrically couples the connection node to the first transistor and the first capacitor, and turning off the first switch electrically isolates the connection node from the first transistor and the first capacitor. the second switch is coupled between the second terminal of the first transistor and the further connection node between the first clamping circuit and the second clamping circuit, wherein turning on the second switch electrically couples the further connection node to the first transistor and turning off the second switch electrically isolates the further connection node from the first transistor, and The first capacitor is configured to store charge corresponding to a voltage of the control terminal of the first transistor.

16. The sense amplifier according to claim 15, wherein The second clamping circuit includes a second transistor, a third switch, a fourth switch and a second capacitor. wherein a first terminal of the second transistor is coupled to a fourth node of the third circuit, and a control terminal of the second transistor is coupled to a second connection node between the third switch and the first terminal of the second capacitor, a second terminal of the second capacitor coupled to the second reference voltage level, The third switch is coupled between the second connection node and the connection node between the first clamp circuit and the second clamp circuit, wherein turning on the third switch electrically couples the connection node to the second transistor and the second capacitor, and turning off the third switch electrically isolates the connection node from the second transistor and the second capacitor. the fourth switch is coupled between the second terminal of the second transistor and the further connection node between the first clamping circuit and the second clamping circuit, wherein turning on the fourth switch electrically couples the further connection node to the second transistor, and turning off the fourth switch electrically isolates the further connection node from the second transistor, and The second capacitor is configured to store charge corresponding to a voltage of the control terminal of the second transistor.

17. The sense amplifier of claim 16 , further comprising: a first resistor coupled between the bit line and a third connection node between the second switch and the second terminal of the first transistor; as well as a second resistor coupled between the reference bit line and a fourth connection node between the fourth switch and the second terminal of the second transistor, wherein, after both the first switch and the second switch are closed and both the third switch and the fourth switch are opened, a voltage across the first resistor corresponding to the bit line is obtained, and Wherein, after both the third switch and the fourth switch are closed and both the first switch and the second switch are opened, a voltage corresponding to the second resistor of the bit line is obtained.

18. The sense amplifier according to claim 17, wherein: in response to the operational amplifier entering a steady state after closing both the first switch and the second switch and opening the third switch and the fourth switch, the obtained voltage of the first resistor being equal to the bias voltage, and the charge corresponding to the voltage of the control terminal of the first transistor being stored in the first capacitor, In response to the operational amplifier entering another steady state after opening both the first switch and the second switch and closing the third switch and the fourth switch, the obtained voltage of the second resistor is equal to the bias voltage, and the charge corresponding to the voltage of the control terminal of the second transistor is stored in the second capacitor, and After the first, second, third, and fourth switches are disconnected together, the first capacitor discharges the stored charge to the control terminal of the first transistor to provide the first clamping voltage to the control terminal of the first transistor, and the second capacitor discharges the stored charge to the control terminal of the second transistor to provide the second clamping voltage to the control terminal of the second transistor, so that the voltage across the first resistor and the voltage across the second resistor are the same as the bias voltage.

19. An operating method for a non-volatile memory, the non-volatile memory comprising a memory array and a sense amplifier, wherein: The sense amplifier includes a voltage comparator with offset compensation, a first clamp circuit coupled between a first I / O node of the sense amplifier and a bit line, and a second clamp circuit coupled between a second I / O node of the sense amplifier and a reference bit line. The operation method includes: the voltage comparator compares a first input voltage and a second input voltage via the first I / O node and the second I / O node of the sense amplifier, respectively, to output a readout signal; and The first clamping circuit and the second clamping circuit respectively fine-tune a voltage corresponding to the bit line and a voltage corresponding to the reference bit line so that the voltage corresponding to the reference bit line matches the voltage corresponding to the bit line.

20. A method for operating a nonvolatile memory, the nonvolatile memory comprising a memory array and a sense amplifier, wherein: The sense amplifier includes a voltage comparator and a clamp circuit, the clamp circuit being coupled to a first I / O node of the sense amplifier, a bit line, a second I / O node of the sense amplifier, and a reference bit line, and one of the voltage comparator and the clamp circuit having offset compensation, The operation method includes: the voltage comparator compares a first input voltage and a second input voltage via the first I / O node and the second I / O node of the sense amplifier, respectively, to output a readout signal; and The voltage comparator fine-tunes a voltage corresponding to the bit line and a voltage corresponding to the reference bit line, respectively, so that the voltage corresponding to the reference bit line matches the voltage corresponding to the bit line.

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