A hybrid write structure and write method for STT-MRAM
By connecting transistors M1 and M2 in the STT-MRAM, selecting the appropriate transistor size and voltage according to the write direction, the problem of write asymmetry in the traditional 1T1R structure is solved, low current write and low energy consumption operation are achieved, and the life of the MTJ device is extended.
Patent Information
- Application Number
- CN202111337304.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2021-11-12
- Publication Date
- 2025-08-26
- Estimated Expiration
- 2041-11-12
AI Technical Summary
In the traditional 1T1R structure, the write operation of STT-MRAM has a write asymmetry problem, resulting in excessive write current, increasing dynamic power consumption and total write energy cost, and the lifetime of MTJ devices is limited.
Using a hybrid write structure, by connecting two transistors M1 and M2 in parallel, selecting the appropriate transistor size and voltage according to different writing directions, adjusting the current size, and realizing on-demand write operations.
Reduces write current, reduces write power consumption, extends the life of MTJ devices, and optimizes write energy costs.
Smart Images
Figure CN114121069B_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to a hybrid writing structure and writing method for STT-MRAM, belonging to the technical field of computer storage. Background Art
[0002] Spin-transfer torque magnetic RAM (STT-MRAM) is a new type of non-volatile magnetic random access memory that uses spin current to write information. The core of the STT-MRAM memory cell is a magnetic tunnel junction (MTJ). STT-MRAM is considered one of the most promising new memory alternatives to Flash and has broad application prospects in various computer storage-related fields.
[0003] The information storage of STT-MRAM relies on write operations, so the study of write operations is crucial for STT-MRAM. The memory cell in STT-MRAM consists of a transistor (denoted as T) for access control of the memory cell and a non-volatile memory device (denoted as R) for storing binary data, which is called a 1T1R non-volatile memory cell. Figure 1 The figure shows the traditional 1T1R write structure used in STT-MRAM. The bidirectional write operation is completed by the same STT-MTJ and transistor. Since the switching of the STT-MTJ resistance corresponds to different current magnitudes and directions, when the write current I W STT-MRAM can only complete the write operation correctly when the current is greater than the critical flip current of STT-MTJ and the duration is greater than the flip delay time. Figure 1 It can be seen that the writing principle of its writing structure is: applying a writing voltage to both ends of the STT-MRAM generates a writing current. When the source line (SL) of the STT-MRAM is connected to the writing voltage V W When the bit line (BL) is connected to GND, the current flowing through the STT-MTJ is from the fixed layer to the free layer. Under the premise of meeting the magnitude and duration of the flip current, the resistance of the STT-MTJ switches to the high-resistance AP state, and the STT-MRAM writes the information "1"; when the bit line is connected to the write voltage V W When the source line is grounded, the write current flows from the BL of the STT-MRAM to the SL, and the current flowing through the STT-MTJ is from the free layer to the fixed layer. Under the premise of meeting the magnitude and duration of the flip current, the resistance of the STT-MTJ switches to the low-resistance P state, and the STT-MRAM writes the information "0".
[0004] The write operation of STT-MRAM requires bidirectional current to program information into the magnetization direction of the MTJ free layer. When the current flows from BL to SL, since the source of transistor M is grounded, its overdrive voltage is V W -V th (i.e., Vov = V W -V th , where V th is the transistor threshold voltage); when the current flows from SL to BL, the MTJ acts as a negative feedback, which limits the current. At the same time, in this case, the body effect (V SB <0) also reduces the overdrive voltage of the transistor. Therefore, relative to the above operation, the overdrive voltage of the transistor (V OV =V W -(V th +ΔV th_Body )-V OS ) becomes smaller. Therefore, when designing the transistor width, it is necessary to meet the bidirectional current requirements. In traditional circuit design, the width of the access transistor is usually taken to correspond to the worst-case width, that is, the maximum current is required. At the same time, because the write current must be greater than the critical flip current to complete the write operation, a high write current is required, which directly increases dynamic power consumption and the total write energy cost.
[0005] In the traditional 1T1R structure, process variations affecting the STT-MTJ and transistors lead to write asymmetry in bidirectional write operations in STT-MRAM. To ensure the write capability of the memory cell, the access transistor size is typically selected to the largest possible size. This selection criterion can be called a "worst-case" approach. Consequently, the traditional 1T1R structure can lead to excessive write current in one direction in STT-MRAM. Summary of the Invention
[0006] In order to solve the problem of excessive write current caused by the asymmetric write of the traditional 1T1R structure, the present invention proposes a new dual-power hybrid write structure for STT-MRAM, which adopts an "on-demand" standard when setting the size of the transistor.
[0007] The present invention proposes a hybrid write structure for STT-MRAM, which is a hybrid structure with an "on-demand" selection standard write operation structure. When the STT-MRAM writes "0", since the required write current is small, the access transistor selects a smaller transistor M1 to provide the write current. When writing "1", since the required write current is large, the transistor M1 and the transistor M2 are connected in parallel to provide the write current. In the hybrid write structure of the present invention, W M1 、W M2Respectively represent the widths of transistor M1, transistor M2, and transistor M3.
[0008] According to the technical solution of the present invention, by adjusting the aspect ratio of the transistor, the current can be adjusted to meet the switching current requirement. At the same voltage, the larger the aspect ratio of the transistor, the greater the corresponding current. Moreover, during circuit analysis, the resistance of the MTJ device is generally considered to be independent of current and is a passive component. Therefore, the current flowing through the MTJ is the sum of the transistor current.
[0009] According to the technical solution of the present invention, the present invention first proposes a hybrid write structure for STT-MRAM as follows Figure 2 As shown, the write structure includes: an STT-MTJ, a first transistor M1 and a second transistor M2, wherein the first transistor M1 and the second transistor M2 are connected in parallel and connected to the STT-MTJ.
[0010] When the write structure performs a write operation, the source lines SL1 and SL2 of the STT-MRAM are connected to the write voltage V W , when the bit line BL is connected to GND, the write current flows from the fixed layer of the STT-MTJ to the free layer, and the STT-MRAM performs a write "1" operation;
[0011] When the bit line BL of the STT-MRAM is connected to the write voltage V W When the source line SL1 of the STT-MRAM is connected to GND, the second transistor M2 is in the off state, the write current flows from the free layer to the fixed layer of the STT-MTJ, and the STT-MRAM performs a write "0" operation.
[0012] According to the technical solution of the present invention, when performing a write operation, when the SL1 and SL2 terminals of the STT-MRAM are connected to the write voltage V W When BL is connected to GND, the STT-MRAM performs a write "1" operation. At this time, the write current I flowing through the MTJ W1 It is provided by transistors M1 and M2. In circuit analysis, two parallel transistors are simply equivalent to the superposition of two transistors with a width-to-length ratio, or twice that of the same single transistor. Since the width of the parallel transistors is W=W M1 +W M2 , so I W1 =I M1 +I M2 . Thus, when writing voltage V W At the same time, Figure 1 and Figure 2The current flowing through the MTJ of the STT-MRAM in the process of writing "1" is equal. When the STT-MRAM writes "0", the BL terminal of the STT-MRAM is connected to the write voltage V W , SL1 is connected to GND, and the transistor M2 is turned off by controlling the enable terminal. At this time, the current I W0 Provided by transistor M1. Figure 2 In the hybrid write structure shown in FIG W0 =I M1 , and in Figure 1 Middle I W0 =I M1 +I M2 >I M1 , so when writing "0", Figure 2 In the hybrid write structure, the current flowing through the MTJ is smaller, thereby achieving the purpose of reducing the write current during the write "0" operation.
[0013] like Figure 3 The present invention proposes Figure 2 The resistance model diagram of the hybrid writing structure in Figure 3 When the STT-MRAM is ready to write data "1", the resistance value of the STT-MTJ R MTJ =R AP , the resistance of the transistor R ON1 =R M1 / / R M2 , write current I W1 =V W / (R AP +R M1 / / R M2 ).exist Figure 3 When the STT-MRAM is ready to write data "0", the resistance of the STT-MTJ R MTJ =R P , the transistor resistance R ON0 =R M1 , write current I W0 =V W / (R P +R M1 ). Due to R AP >R P , R AP +R M1 >R P +R M1 / / R M2 , thus R P +R M1 and R AP +R M1 / / R M2The difference between the two cannot be determined, so at the same write voltage V W In this case, it is not necessarily satisfied W1 >I W0 .
[0014] In view of the above problems, the inventors considered the TMR value of the MTJ device in the STTM-RAM when designing the hybrid write structure for the STT-MRAM, TMR=R P / (R P +R AP ), when the TMR value is greater than 150%, the hybrid write structure designed in the above technical solution of the present invention can meet I W1 >I W0 requirements.
[0015] Furthermore, since the lifespan of MTJ devices is greatly affected by voltage, the higher the voltage, the shorter the lifespan. Therefore, the present invention also proposes a hybrid write structure using dual power supplies to provide different write voltages for the above-mentioned hybrid write structure for STT-MRAM. That is, corresponding write voltages are formulated for write operations in different directions to achieve low write voltages and thus improve the lifespan of MTJ devices.
[0016] According to the technical solution of the present invention, the hybrid write structure using dual power supplies includes: an STT-MTJ, a first transistor M1 and a second transistor M2, the first transistor M1 and the second transistor M2 are connected in parallel and connected to the STT-MTJ; when the write structure performs a write operation, when the source lines SL1 and SL2 of the STT-MRAM are connected to a first write voltage and the bit line BL of the STT-MRAM is connected to GND, the write current flows from the fixed layer of the STT-MTJ to the free layer, and the STT-MRAM performs a write "1" operation; when the bit line BL of the STT-MRAM is connected to a second write voltage, the source line SL1 of the STT-MRAM is connected to GND, the second transistor M2 is in an off state, the write current flows from the free layer of the STT-MTJ to the fixed layer, and the STT-MRAM performs a write "0" operation.
[0017] According to the technical solution of the present invention, in the hybrid write structure using dual power supplies, the first voltage is greater than the second voltage.
[0018] The present invention further provides a hybrid writing method for STT-MRAM, wherein the writing method adopts the hybrid writing structure of the present invention, and the writing method comprises:
[0019] When the write structure performs a write operation, when the source lines SL1 and SL2 of the STT-MRAM are connected to a first write voltage and the bit line BL is connected to GND, a write current flows from the fixed layer to the free layer of the STT-MTJ, and the STT-MRAM performs a write "1" operation;
[0020] When the bit line BL of the STT-MRAM is connected to the second write voltage, the source line SL1 of the STT-MRAM is connected to GND, the second transistor M2 is placed in a cut-off state, the write current flows from the free layer of the STT-MTJ to the fixed layer, and the STT-MRAM performs a write "0" operation.
[0021] According to the writing method of the present invention, the first writing voltage is the same as the second writing voltage or the first writing voltage is greater than the second writing voltage.
[0022] According to the write structure and write method of the present invention, during a write operation of the STT-MRAM, by making the first write voltage greater than the second write voltage, the current flowing through the STT-MTJ is smaller when the STT-MRAM writes "0", and low-voltage writing is achieved at the same time, thereby further increasing the service life of the STT-MTJ.
[0023] The beneficial effects of the present invention are:
[0024] Because the voltage applied to the MTJ is determined by the voltage divider formed by the transistor and the MTJ, the hybrid write structure and method of the present invention appropriately controls the reduction in current flowing through the MTJ by connecting two transistors in parallel and adjusting the transistor width. The reduction in excess current and voltage across the STT-MTJ alleviates tunneling oxide stress, significantly increasing the lifespan of the STT-MTJ.
[0025] Since the lifespan of MTJ devices is greatly affected by voltage, the higher the voltage, the shorter the lifespan. Therefore, the present invention proposes a hybrid write structure using dual power supplies to provide different write voltages for the write operation of the STT-MRAM. That is, for write operations in different directions, corresponding write voltages are formulated to achieve low write voltage.
[0026] According to the dual-power hybrid write structure and write method of the present invention, by making the first write voltage greater than the second write voltage during the STT-MRAM write operation, the current flowing through the STT-MTJ is smaller when the STT-MRAM writes "0", thereby achieving low-voltage writing, reducing write power consumption, and further increasing the service life of the STT-MTJ. BRIEF DESCRIPTION OF THE DRAWINGS
[0027] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.
[0028] Figure 1 It is a schematic diagram of the traditional 1T1R type writing structure;
[0029] Figure 2 is a schematic diagram of a hybrid writing structure of the present invention;
[0030] Figure 3 This is a resistance model diagram of a hybrid write structure of the present invention;
[0031] Figure 4 is a schematic diagram of a dual-power hybrid writing structure of the present invention;
[0032] Figure 5 It is a transient simulation comparison diagram of a 1T1R type writing structure and a hybrid writing structure of the present invention. DETAILED DESCRIPTION
[0033] To make the objectives, technical solutions and advantages of the present invention more clear, the embodiments of the present invention will be described in further detail below with reference to the accompanying drawings.
[0034] Example 1:
[0035] According to the technical solution of the present invention, a hybrid write structure for STT-MRAM proposed in this embodiment is as follows Figure 2 As shown, the write structure includes: an STT-MTJ, a first transistor M1 and a second transistor M2, wherein the first transistor M1 and the second transistor M2 are connected in parallel and connected to the STT-MTJ.
[0036] When the write structure performs a write operation, the source lines SL1 and SL2 of the STT-MRAM are connected to the write voltage V W , when the bit line BL is connected to GND, the write current flows from the fixed layer of the STT-MTJ to the free layer, and the STT-MRAM performs a write "1" operation;
[0037] When the bit line BL of the STT-MRAM is connected to the write voltage V W When the source line SL1 of the STT-MRAM is connected to GND, the second transistor M2 is in the off state, the write current flows from the free layer to the fixed layer of the STT-MTJ, and the STT-MRAM performs a write "0" operation.
[0038] like Figure 2 The write structure shown in the figure is in the process of performing a write operation. When the SL1 and SL2 terminals of the STT-MRAM are connected to the write voltage V W When the BL terminal is connected to GND, the current flows from the fixed layer of the STT-MTJ to the free layer, and the memory writes "1". At this time, the write current I flowing through the STT-MTJ is W1 is provided by transistors M1 and M2, so I W1 =I M1 +I M2 Therefore, when writing voltage V W At the same time, Figure 1 and Figure 2 The current flowing through the STT-MTJ in the STT-MRAM during the writing of "1" is equal.
[0039] When STT-MRAM writes “0”, BL is connected to the write voltage V W , SL1 is connected to GND, and the transistor M2 is turned off by controlling the enable terminal. The current flows from the BL terminal to the SL1 terminal. At this time, the current I W0 Provided by transistor M1, the write current flows from the free layer to the fixed layer of the MTJ. Figure 2 The write structure I W0 =I M1 , and in Figure 1 Middle I W0 =I M1 +I M2 >I M1 , so when writing "0", Figure 2 The write structure has a smaller current flowing through the STT-MTJ, achieving the purpose of reducing the write voltage.
[0040] Because the voltage applied to the STT-MTJ is determined by the voltage divider formed by the transistor and the STT-MTJ, the reduction in current flowing through the STT-MTJ can be appropriately controlled by adjusting the width of the transistor. The reduction in excess current and voltage across the STT-MTJ alleviates the stress conditions in the tunneling oxide, effectively increasing the lifespan of the STT-MTJ.
[0041] like Figure 3 This is the resistance model diagram of the new hybrid write structure proposed in this patent. Figure 3 When the STT-MRAM is ready to write data "1", the resistance value of the STT-MTJ R MTJ =R AP , the resistance of the transistor R ON1 =R M1 / / R M2 , write current I W1 =V W / (RAP +R M1 / / R M2 ). Figure 3 The left side shows the operation of writing "1", and the resistance value of STT-MTJ R MTJ It turns out to be R P , by writing “1” operation, the resistance value R MTJ =R AP .exist Figure 3 In the STT-MRAM write "0" operation, the resistance value of the STT-MTJ R MTJ =R P , the resistance of the transistor R ON0 =R M1 , write current I W0 =V W / (R P +R M1 ). Due to R AP >R P , R AP +R M1 >R P +R M1 / / R M2 , thus R P +R M1 and R AP +R M1 / / R M2 The difference between the two cannot be determined, so at the same write voltage V W In this case, it is not necessarily satisfied W1 >I W0 .
[0042] In view of the above problems, the inventors considered the TMR value of the MTJ device in the STTM-RAM when designing the hybrid write structure for the STT-MRAM, TMR=R P / (R P +R AP ), when the TMR value is greater than 150%, the hybrid write structure designed in the above technical solution of this embodiment can meet I W1 >I W0 requirements.
[0043] Example 2:
[0044] Since the lifespan of MTJ devices is greatly affected by voltage, the higher the voltage, the shorter the lifespan. Therefore, this embodiment proposes a hybrid write structure using dual power supplies to provide different write voltages for the hybrid write structure used for STT-MRAM. That is, corresponding write voltages are formulated for write operations in different directions to achieve low write voltages, thereby further improving the lifespan of MTJ devices.
[0045] This embodiment proposes to adopt a dual power supply structure to provide different write voltages for the hybrid write structure of the present invention. That is, for write operations in different directions, corresponding write voltages are formulated to achieve low write voltages, which can further reduce write power consumption.
[0046] The hybrid write structure using dual power supplies includes: an STT-MTJ, a first transistor M1, and a second transistor M2; the first transistor M1 and the second transistor M2 are connected in parallel and connected to the STT-MTJ; when the write structure performs a write operation, when the source lines SL1 and SL2 of the STT-MRAM are connected to a first write voltage and the bit line BL of the STT-MRAM is connected to GND, a write current flows from the fixed layer of the STT-MTJ to the free layer, and the STT-MRAM performs a write "1" operation; when the bit line BL of the STT-MRAM is connected to a second write voltage, the source line SL1 of the STT-MRAM is connected to GND, the second transistor M2 is in an off state, a write current flows from the free layer of the STT-MTJ to the fixed layer, and the STT-MRAM performs a write "0" operation.
[0047] According to the technical solution of this embodiment, in the hybrid write structure using dual power supplies, the first voltage is greater than the second voltage.
[0048] like Figure 4 The figure shows the dual power hybrid write structure proposed in this embodiment. In this structure, when STT-MRAM writes "1", a low voltage V L When writing "0", a high voltage V is used as the write voltage. H As a write voltage, the current flowing through the STT-MTJ is smaller when the STT-MRAM writes a "0" operation, thereby achieving low-voltage writing when writing a "0" operation, reducing write power consumption, and further improving the service life of the MTJ device.
[0049] Example 3:
[0050] This embodiment further provides a hybrid writing method for STT-MRAM, wherein the writing method adopts the hybrid writing structure described in the first or second embodiment of the present invention, and the writing method includes:
[0051] When the write structure performs a write operation, when the source lines SL1 and SL2 of the STT-MRAM are connected to a first write voltage and the bit line BL is connected to GND, a write current flows from the fixed layer to the free layer of the STT-MTJ, and the STT-MRAM performs a write "1" operation;
[0052] When the bit line BL of the STT-MRAM is connected to the second write voltage, the source line SL1 of the STT-MRAM is connected to GND, the second transistor M2 is placed in a cut-off state, the write current flows from the free layer of the STT-MTJ to the fixed layer, and the STT-MRAM performs a write "0" operation.
[0053] According to the writing method of the present invention, the first writing voltage is the same as the second writing voltage or the first writing voltage is greater than the second writing voltage.
[0054] According to the write method of the present invention, during a write operation, the STT-MRAM makes the first write voltage greater than the second write voltage so that when the STT-MRAM writes "0", the current flowing through the STT-MTJ is smaller, and low-voltage writing is achieved, thereby reducing write power consumption and further increasing the service life of the STT-MTJ.
[0055] Example 4:
[0056] like Figure 5 As shown, Figure 1 Transient simulation comparison of the 1T1R write structure in the present invention and the hybrid write structure. Assuming the initial state of the STT-MRAM is "0" and the duration of each write is 10ns. Figure 1 The traditional structure mode shown uses a write voltage of 0.9V. When the STT-MRAM performs the write process from "0" to "1", the write current of the two structures is kept equal. However, since the access transistor of the new structure is composed of two transistors in parallel, its overall resistance is smaller than that of the traditional structure. Therefore, under the same write circuit requirements, the required write voltage is smaller. The final write voltage V L When STT-MRAM changes from 1 to 0, the write voltage of the traditional structure is still 0.9V.
[0057] Since the present invention adopts a hybrid write structure, the write voltage can be appropriately selected according to the current required to write "0". Therefore, the write voltage V H is 0.68V. Figure 5It can be seen that when the STT-MRAM changes from "0" to "1", the write current is about 120μA, and the write delay is about 1.6ns; when the STT-MRAM changes from "1" to "0", the write voltage of the new structure is 72.59μA, while the write voltage of the traditional structure is about 107.67μA, and the write current is reduced by 30%. However, since the delay is inversely proportional to the current, the write delay of the hybrid structure of the present invention is about 0.4ns longer than the traditional structure, about 2.3ns. During a normal write operation, in order to ensure a successful write, a larger margin is usually set for the duration of the write voltage. At this time, when the write operation from "1" to "0" is successful, the write current will become larger. If the write operation is not terminated in time, it will cause greater energy loss. Figure 5 It can be seen from the figure that the hybrid write structure proposed by the present invention can keep the write current within 100 μA even after the write is successful, which can save at least 30% of the power consumption for the entire write operation.
[0058] Some steps in the embodiments of the present invention may be implemented using software, and the corresponding software program may be stored in a readable storage medium, such as a CD or a hard disk.
[0059] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.
Claims
1. A hybrid write circuit for STT-MRAM, characterized in that: The write circuit includes: an STT-MTJ, a first transistor M1 and a second transistor M2; wherein the first transistor M1 and the second transistor M2 are connected in parallel and connected to the STT-MTJ; When the write circuit performs a write operation, the source lines SL1 and SL2 of the STT-MRAM are connected to the write voltage V W When the bit line BL is connected to GND, the write current flows from the fixed layer of the STT-MTJ to the free layer, and the STT-MRAM performs a write "1" operation; When the bit line BL of the STT-MRAM is connected to the write voltage V W When , the source line SL1 of the STT-MRAM is connected to GND, the second transistor M2 is in the off state, the write current flows from the free layer of the STT-MTJ to the fixed layer, and the STT-MRAM performs a write "0" operation; The STT-MRAM writes current when performing a write "0" operation I W0 provided by the first transistor M1, I W0 =I M1 ; The STT-MRAM writes current when performing a write "1" operation I W1 Provided jointly by the first transistor M1 and the second transistor M2, I W1 =I M1 +I M2 ; The write current when the STT-MRAM performs a write "0" operation I W0 Less than the write current when the STT-MRAM performs a write "1" operation I W1 ; The TMR value of the STT-MTJ in the STT-MRAM is: TMR= R P / ( R P + R AP ); Among them, when STT-MRAM writes "0" operation, the resistance of STT-MTJ R MTJ =R P When STT-MRAM writes "1", the resistance of STT-MTJ R MTJ =R AP When the TMR value is greater than 150%, the write circuit satisfies I W1 >I W0 requirements.
2. A hybrid write method for STT-MRAM, wherein the hybrid write circuit according to claim 1 is used, The writing method includes: When the write circuit performs a write operation, when the source lines SL1 and SL2 of the STT-MRAM are connected to a first write voltage and the bit line BL is connected to GND, a write current flows from the fixed layer to the free layer of the STT-MTJ, and the STT-MRAM performs a write "1" operation; When the bit line BL of the STT-MRAM is connected to the second write voltage, the source line SL1 of the STT-MRAM is connected to GND, the second transistor M2 is placed in a cut-off state, and the write current flows from the free layer to the fixed layer of the STT-MTJ, and the STT-MRAM performs a write "0" operation; During a write operation of the STT-MRAM, the first write voltage is made greater than the second write voltage, so that when the STT-MRAM writes "0", the current flowing through the STT-MTJ is smaller, and low-voltage writing is achieved.
3. A hybrid writing method for STT-MRAM according to claim 2, characterized in that: The first write voltage is the same as the second write voltage.
4. A hybrid writing method for STT-MRAM according to claim 2, characterized in that: The first write voltage is greater than the second write voltage.