Interface circuit, data transmission circuit and memory

Abstract

The embodiment of the present invention provides an interface circuit, a data transmission circuit and a memory, wherein the interface circuit includes a clock pad, a data pad and an input buffer circuit, wherein the clock pad and the data pad are arranged in the first row, and M data pads are arranged on both sides of the clock pad, with half of the M data pads arranged on each side, and M input buffer circuits are arranged in the second row, with the data pad as a reference, forming an axis perpendicular to the first row, and M input buffer circuits are arranged on both sides of the axis, with half of the M input buffer circuits arranged on each side, and the distance between each input buffer circuit and the axis is less than the distance between the data pad corresponding to the input buffer circuit and the axis. The embodiment of the present invention is conducive to shortening the length of the clock path corresponding to each input buffer circuit, reducing timing violations, and improving the matching degree between the clock path corresponding to each input buffer circuit and the input data path.

Description

Technical Field

[0001] The embodiments of the present invention relate to the field of semiconductor technology, and in particular to an interface circuit, a data transmission circuit and a memory. Background Art

[0002] Dynamic Random Access Memory (DRAM) is a semiconductor memory device commonly used in computers, consisting of many repeated storage cells. Each storage cell usually includes a capacitor and a transistor. The gate of the transistor is connected to the word line, the drain is connected to the bit line, and the source is connected to the capacitor. The voltage signal on the word line can control the opening or closing of the transistor, and then read the data information stored in the capacitor through the bit line, or write the data information into the capacitor through the bit line for storage.

[0003] DRAM can be divided into double data rate (DDR) dynamic random access memory, GDDR (Graphics Double Data Rate) dynamic random access memory, and low power double data rate (LPDDR) dynamic random access memory. As DRAM is applied in more and more fields, such as DRAM is increasingly used in the mobile field, users have higher and higher requirements for DRAM speed, power consumption and other indicators.

[0004] However, current DRAM performance still needs to be improved. Summary of the invention

[0005] The technical problem solved by the embodiments of the present invention is to provide an interface circuit, a data transmission circuit and a memory, which centralizes the processing of input buffer circuits in the interface circuit to optimize key clocks, thereby improving clock performance and reducing power loss.

[0006] To solve the above problems, an embodiment of the present invention provides an interface circuit, comprising: a clock pad for transmitting a clock signal; M data pads for transmitting a data signal; M input buffer circuits corresponding to the data pads one by one, each of the input buffer circuits receiving the data signal transmitted by the data pad corresponding to the input buffer circuit under the drive of the clock signal; wherein the clock pad and the data pad are arranged in a first row, and the M data pads are arranged on both sides of the clock pad, with half of the M data pads arranged on each side, and the M input buffer circuits are arranged in a second row, with the clock pad as a reference, forming an axis perpendicular to the first row, the M input buffer circuits are arranged on both sides of the axis, with half of the M input buffer circuits arranged on each side, the distance between each input buffer circuit and the axis is less than the distance between the data pad corresponding to the input buffer circuit and the axis, and M is an integer greater than or equal to 2.

[0007] In addition, the input data path length between each input buffer circuit and the data pad corresponding to the input buffer circuit is a first length, and the clock path length between each input buffer circuit and the clock pad is a second length, and the first length is positively correlated with the second length.

[0008] In addition, the clock pad is a differential input pad, including a first clock pad and a second clock pad, and the first clock pad and the second clock pad transmit complementary clock signals respectively.

[0009] In addition, the first clock pad and the second clock pad are arranged symmetrically with respect to the axis.

[0010] In addition, it also includes: a clock processing circuit, which is electrically connected to the clock pad and the M input buffer circuits, and is used to receive the clock signal and process the clock signal as a driving clock for the M input buffer circuits.

[0011] In addition, the clock processing circuit includes a clock receiving circuit and a clock generating circuit. The clock receiving circuit is electrically connected to the clock pad and is used to receive the clock signal. The output of the clock receiving circuit serves as the input of the clock generating circuit, and the clock generating circuit is used to generate the driving clock.

[0012] In addition, it also includes: a flag pad for transmitting a flag signal; and a flag buffer circuit corresponding to the flag pad and used to receive the flag signal transmitted by the flag pad under the drive of the clock signal.

[0013] In addition, the flag pad is arranged in the first row and is located between the data pad and the clock pad; the flag buffer circuit is arranged in the second row and is located on the same side of the axis as the flag pad, and is located between the input buffer circuit and the axis; the distance between the flag buffer circuit and the axis is smaller than the distance between the flag pad corresponding to the flag buffer circuit and the axis.

[0014] In addition, it also includes: M output buffer circuits corresponding to the data pads one by one, and each of the output buffer circuits sends the data signal to the corresponding data pad under the drive of the clock signal.

[0015] In addition, the length of the output data path between each of the output buffer circuits and the data pad corresponding to the output buffer circuit is the same.

[0016] In addition, the input buffer circuit includes a multiplexer and a latch. The multiplexer receives the data signal and outputs the processed data signal to the latch. The output of the latch serves as the output of the input buffer circuit.

[0017] Correspondingly, an embodiment of the present invention also provides a data transmission circuit, comprising: the above-mentioned interface circuit; M serial-to-parallel conversion circuits, the M serial-to-parallel conversion circuits corresponding one-to-one to the M input buffer circuits, and the output of each input buffer circuit serves as the input of the corresponding serial-to-parallel conversion circuit.

[0018] In addition, the M serial-to-parallel conversion circuits are arranged in a third row, and the transmission path lengths between each of the input buffer circuits located on the same side of the axis and the serial-to-parallel conversion circuit corresponding to the input buffer circuit are different.

[0019] In addition, the M serial-to-parallel conversion circuits correspond to the M data pads one by one, and the distance between each serial-to-parallel conversion circuit and the data pad corresponding to the serial-to-parallel conversion circuit is the same.

[0020] In addition, it also includes: M first-in-first-out circuits, which correspond one-to-one to the M serial-to-parallel conversion circuits; M parallel-to-serial conversion circuits, which correspond one-to-one to the M first-in-first-out circuits, and the output of each of the first-in-first-out circuits serves as the input of the parallel-to-serial conversion circuit corresponding to the first-in-first-out circuit; M driving circuits, which correspond one-to-one to the M parallel-to-serial conversion circuits, and the output of each of the parallel-to-serial conversion circuits serves as the input of the driving circuit corresponding to the parallel-to-serial conversion circuit; and the M driving circuits also correspond one-to-one to the M data pads.

[0021] In addition, M optional input buffer circuits are included, the number of the M optional input buffer circuits is the same as the number of the input buffer circuits, and the M optional input buffer circuits are arranged side by side with the input buffer circuits.

[0022] In addition, the M input buffer circuits and / or two of the M optional input buffer circuits, one of the M serial-to-parallel conversion circuits, one of the M first-in-first-out circuits, one of the M parallel-to-serial conversion circuits and one of the M driving circuits together constitute a data transmission unit, and the working environment of each of the data transmission units is matched.

[0023] In addition, the serial-to-parallel conversion circuit and the first-in first-out circuit in the same data transmission unit are arranged side by side or in parallel.

[0024] In addition, the first-in first-out circuits in different data transmission units are arranged side by side.

[0025] Correspondingly, an embodiment of the present invention further provides a memory, comprising the above-mentioned interface circuit.

[0026] Compared with the prior art, the technical solution provided by the embodiment of the present invention has at least the following advantages:

[0027] The embodiment of the present invention provides an interface circuit with superior structural performance, wherein M data pads and clock pads are arranged in the first row, and the M data pads are arranged on both sides of the clock pads respectively, and an axis perpendicular to the first row is formed with the data pads as a reference; M input buffer circuits are arranged on both sides of the axis, and half of the M input buffer circuits are arranged on each side, and the distance between each input buffer circuit and the axis is less than the distance between the data pad corresponding to the input buffer circuit and the axis. In the embodiment of the present invention, by centralizing the input buffer circuits, the clock path for transmitting the clock signal to each input buffer circuit is shortened, and the matching degree between the clock path and the data path is improved, which is beneficial to reduce tDQS2DQ and timing violations; in addition, since the clock path is reduced, the power loss of the interface circuit is reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] One or more embodiments are exemplarily described by pictures in the corresponding drawings, and these exemplified descriptions do not constitute limitations on the embodiments. Elements with the same reference numerals in the drawings represent similar elements, and unless otherwise stated, the figures in the drawings do not constitute proportional limitations.

[0029] Figure 1 It is a structural schematic diagram of an interface circuit;

[0030] Figure 2 A schematic diagram of the structure of an interface circuit provided by an embodiment of the present invention;

[0031] Figure 3 Another structural schematic diagram of an interface circuit provided by an embodiment of the present invention;

[0032] Figure 4 A schematic diagram of another structure of an interface circuit provided by an embodiment of the present invention;

[0033] Figure 5 A schematic diagram of the layout of an interface circuit provided by an embodiment of the present invention;

[0034] Figure 6 for Figure 1 The layout diagram corresponding to the provided interface circuit;

[0035] Figures 7 to 9 Four structural schematic diagrams of an interface circuit in which the data pads provided in the embodiments of the present invention include a command pad and an address pad;

[0036] Fig.10 A schematic diagram of the layout of a data transmission circuit provided by an embodiment of the present invention;

[0037] Fig.11 A schematic diagram of a structure in which a memory provided in an embodiment of the present invention is applied to a storage system. DETAILED DESCRIPTION

[0038] As can be seen from the background technology, the performance of DRAM in the prior art still needs to be improved.

[0039] In the memory, the write data sampling signal (Dqs signal or Wck signal) is used as the clock for writing data; during the write operation, the edge (rising edge and falling edge) of the Dqs or Wck signal should be aligned with the center of the data signal (DQ signal) in terms of timing (considering the timing margin, it may also be allowed to be basically aligned at the center). The transmission path of the DQ signal is defined as the data path. The length of the data path will affect the time when the edge of the DQ signal reaches the device port (such as the data port of the register). The transmission path of the Dqs or Wck signal is defined as the clock path. The length of the clock path will affect the time when the Dqs or Wck signal reaches the device port (such as the clock port of the register). The difference between the data path of the DQ signal and the clock path of the Dqs or Wck signal (the time interval between the edge of the Dqs or Wck signal and the center of the DQ signal) is defined as tDQS2DQ or tWCK2DQ. The smaller tDQS2DQ or tWCK2DQ is, the more the data path matches the clock path, and the better the corresponding circuit timing is.

[0040] Now combined Figure 1 Conduct a specific analysis. Figure 1 A schematic diagram of the structure of an interface circuit.

[0041] refer to Figure 1 The interface circuit includes: a plurality of data pads 11 arranged side by side for transmitting data signals, a central axis AA1, and half of the plurality of data pads 11 are distributed on one side of the central axis AA1, and the other half are distributed on the other side of the central axis AA1; a clock pad 13, the clock pad 13 is located at the central axis AA1; a plurality of input buffer circuits 14, corresponding to the data pads 11, and the data paths between each input buffer circuit 14 and the corresponding data pad 11 are the same (or substantially the same within a certain error range, considering that the same path is only an ideal situation in the actual circuit design and manufacturing process, the same path described here and below is included in a certain The meaning of "essentially the same within the error range" is that the certain error range here can be understood but not limited to the error between different paths being within 1% or within 3%); multiple output buffer circuits (not shown), corresponding to the data pad 101, and the timing path between each output buffer circuit and the corresponding data pad 11 is the same; a clock receiving circuit 16 and a clock generating circuit 17, the clock receiving circuit 16 is electrically connected to the clock pad 13, and is used to receive a clock signal and transmit the clock signal to the clock generating circuit 17, the clock generating circuit 17 receives the clock signal and generates a driving clock, and the input buffer circuit 14 receives the driving clock and the data signal and transmits the data signal.

[0042] Figure 1 In the figure, the data pad 11 is marked with DQ0 / DQ1...DQ7, the clock pad 13 is marked with Dqs (Dqs is taken as an example hereinafter, and the application of Wck is the same or similar to Dqs, for example, the clock is called Dqs in LPDDR4, and the clock is called Wck in LPDDR5), the input buffer circuit 14 is marked with RX0 / RX1...RX7, and the input buffer circuit 14 is also a receiving circuit, the clock receiving circuit 16 is marked with RX_CLK, and the clock generating circuit 17 is marked with CLK GEN.

[0043] The data path for transmitting the data signal of the data pad 11 to the corresponding input buffer circuit 14 is the first path, and the timing path for transmitting the clock signal of the clock pad to the corresponding input buffer circuit 14 is the second path. Figure 1 In the embodiment, different input buffer circuits 14 have the same first path, but the input buffer circuit 14 that is farther from the clock pad has a longer second path. Therefore, the farther from the clock pad, the greater the gap between the corresponding first path and the second path, resulting in a larger corresponding tDQS2DQ and a more serious timing violation problem. Figure 1 The middle mark shows tDQS2DQ corresponding to the input buffer circuit 14 farthest from the clock pad.

[0044] The data signals of different data pads 11 arrive at the corresponding input buffer circuit 14 at similar times. Figure 1 Taking the input buffer circuits 14 farthest and closest to the clock pad as examples, the clock signal reaches the input buffer circuit 14 farthest from the clock pad 13 (the input buffer circuit 14 corresponding to DQ0) the latest, and the clock signal reaches the input buffer circuit 14 closest to the clock pad (the input buffer circuit 14 corresponding to DQ3) the earliest, which causes the input buffer circuit 14 closest to the clock pad to receive and transmit the data signal first, while the input buffer circuit 14 farthest from the clock pad transmits the data signal the latest, and the time difference between the two input buffer circuits 14 transmitting the data signal is large. Accordingly, if the clock path of the input buffer circuit 14 corresponding to DQ3 matches the data path, then the clock path of the input buffer circuit 14 corresponding to DQ0 is not easy to match.

[0045] Specifically, combined Figure 1 , each data pad 11 has a first port d0 / d1...d7 respectively, each input buffer circuit 14 has a second port r0 / r1...r7 connected to the first port of the corresponding data pad 11, each input buffer circuit 14 has a third port v0 / v1...v7 connected to the clock generating circuit 17, the clock generating circuit 17 has a fourth port c0 connected to each input buffer circuit 14 located on one side of the central axis AA1, and the clock generating circuit 17 also has a fifth port c1 connected to each input buffer circuit 14 located on the other side of the central axis AA1. For RX0, the clock path of the clock signal is c0→v0, and the data path of the data signal is d0→r0; for RX1, the clock path of the clock signal is c1→v1, and the data path of the data signal is d1→r1; and so on; it is not difficult to find that for different input buffer circuits 14, the corresponding data paths remain unchanged, but the input buffer circuit 14 that is closer to the central axis AA1 has a shorter clock path, so there is a problem of large tDQS2DQ difference.

[0046] From the above analysis, it can be seen that the tDQS2DQ corresponding to different input buffer circuits 14 vary greatly. In the memory, there are strict requirements on the value of tDQS2DQ, for example, the value of tDQS2DQ cannot be greater than 800ps, otherwise it will cause timing violation.

[0047] To solve the above problems, an embodiment of the present invention provides an interface circuit, which shortens the clock path of the clock signal transmitted to each input buffer circuit by centrally arranging each input buffer circuit, thereby shortening tDQS2DQ and further improving the timing violation problem. The interface circuit provided by this embodiment will be described in detail below in conjunction with the accompanying drawings.

[0048] Figure 2A schematic diagram of the structure of an interface circuit provided by an embodiment of the present invention.

[0049] refer to Figure 2 In this embodiment, the interface circuit includes: a clock pad 102 for transmitting a clock signal; M data pads 101 for transmitting a data signal; M input buffer circuits 103 corresponding to the data pads 101 one by one, and each input buffer circuit 103 receives a data signal transmitted by the data pad 101 corresponding to the input buffer circuit 103 under the drive of the clock signal; wherein the clock pad 102 and the data pad 101 are arranged in the first row, and the M data pads 101 are arranged on both sides of the clock pad 102. The clock pad 102 is used as a reference to form an axis AA1 perpendicular to the first row. The M input buffer circuits 103 are arranged on both sides of the axis AA1, and half of the M input buffer circuits 103 are arranged on each side. The distance between each input buffer circuit 103 and the axis AA1 is less than the distance between the data pad 101 corresponding to the input buffer circuit 103 and the axis AA1. M is an integer greater than or equal to 2. When M is an even number, for example, M is equal to 8, 4 data pads 101 are arranged on each side of the axis AA1; when M is an odd number, for example, M is equal to 7, 3 data pads 101 are arranged on one side of the axis AA1, and 4 data pads 101 are arranged on the other side. The "half" mentioned above should be understood as M / 2 when M is an even number, and should be understood as (M-1) / 2 or (M+1) / 2 when M is an odd number, and the same below.

[0050] The interface circuit provided in this embodiment will be described in detail below with reference to the accompanying drawings.

[0051] In this embodiment, the interface circuit can be applied to DRAM, such as LPDDR4.

[0052] In this embodiment, half of the M data pads 101 are located on one side of the axis AA1, and the other half of the M data pads 101 are located on the other side of the axis AA1. The data pads 101 are used to transmit DQ signals, that is, the data signals are DQ signals.

[0053] Figure 2 In the figure, eight data pads 101 are taken as an example, and each data pad 101 is labeled with DQ0, DQ1, DQ2, DQ3, DQ4, DQ5, DQ6, and DQ7; accordingly, the number of input buffer circuits 103 is also eight, and each input buffer circuit 103 is labeled with RX0, RX1, RX2, RX3, RX4, RX5, RX6, and RX7. It can be understood that in other embodiments, the number of data pads can be reasonably set according to the actual requirements of the interface circuit.

[0054] The clock pad 102 can be used to transmit a Dqs signal, that is, the clock signal is a Dqs signal, and the Dqs signal refers to a write clock signal or a read clock signal. Figure 2 The clock pad 102 is labeled as Dqs.

[0055] Figure 3 Another structural diagram of the interface circuit provided by the embodiment of the present invention. Figure 3 As shown, the clock pad 102 may be a differential input pad, including a first clock pad 112 and a second clock pad 122, and the first clock pad 112 and the second clock pad 122 transmit complementary clock signals respectively. Specifically, Figure 3 In the figure, the first clock pad 112 is marked with Dqs_t, and the first clock pad 112 is used to transmit the Dqs_t clock signal; the second clock pad 122 is marked with Dqs_c, and the second clock pad 122 is used to transmit the Dqs_c clock signal.

[0056] In this embodiment, the first clock pad 112 and the second clock pad 122 are arranged symmetrically with respect to the axis AA1. The clock path between the first clock pad 112 and the input buffer circuit 103 located on one side of the axis AA1 is the first clock path, and the clock path between the second clock pad 122 and the input buffer circuit 103 located on the other side of the axis AA1 is the second clock path. Such an arrangement is conducive to reducing the gap between the first clock path and the second clock path, thereby reducing or avoiding the adverse effect on tDQS2DQ caused by the large gap between the first clock path and the second clock path.

[0057] It should be noted that, in other embodiments, the first clock pad and the second clock pad may also be arranged on the same side of the axis.

[0058] It should also be noted that the "first row" does not mean that the clock pads and the data pads 101 are located in the first row of the overall pads of the interface circuit, but is only for the purpose of illustrating that the clock pads and the data pads 101 are arranged in the same row, and for the convenience of defining the axis AA1. In an actual interface circuit, the clock pads and the data pads 101 may be located in any row of the overall pads of the interface circuit.

[0059] Similarly, the “second row” does not mean that the input buffer circuit 103 is located in the second row of the overall pads of the interface circuit, but is only used to illustrate that the M input buffer circuits 103 are arranged in the same row and are located in different rows from the clock pads and the data pads 101. In an actual interface circuit, the M input buffer circuits 103 can be located in any row of the overall pads of the interface circuit, and one or more rows of pads can be arranged between the input buffer circuit 103 and the data pads 101.

[0060] In this embodiment, the interface circuit may further include: a clock processing circuit, which is electrically connected to the clock pad and the M input buffer circuits 103, and is used to receive a clock signal and process the clock signal as a driving clock for the M input buffer circuits 103. In other words, the input buffer circuit 103 is driven by the clock signal, which is actually the input buffer circuit 103 being driven by the driving clock generated by processing the clock signal.

[0061] The clock processing circuit coincides with the axis AA1, that is, the clock processing circuit is located at the location of the axis AA1. In this way, it is helpful to reduce the difference in the clock path required for the drive clock to be transmitted to the input buffer circuit 103 located on both sides of the axis AA1. The above-mentioned clock processing circuit is located at the location of the axis AA1, which does not mean that the clock processing circuit is completely symmetrical with respect to the axis AA1. Considering the actual situation of circuit design and manufacturing, the clock circuit is roughly located at the location of AA1, and its center line is allowed to deviate from AA1 by a certain value, such as 10% or 20%.

[0062] In this embodiment, the clock processing circuit includes a clock receiving circuit 114 and a clock generating circuit 115. The clock receiving circuit 114 is electrically connected to the clock pad and is used to receive a clock signal. The output of the clock receiving circuit 114 is used as the input of the clock generating circuit 115. The clock generating circuit 115 is used to generate a driving clock. The clock generating circuit 115 is located on the axis AA1. Figure 2 In FIG. 1 , the clock receiving circuit 114 is denoted by RX_CLK and the clock receiving circuit 115 is denoted by CLK GEN.

[0063] Specifically, the clock receiving circuit 114 includes: a first clock receiving circuit electrically connected to the first clock pad 112, for receiving the Dqs_t clock signal; a second clock receiving circuit electrically connected to the second clock pad 122, for receiving the Dqs_c clock signal. The first clock receiving circuit and the second clock circuit are symmetrically arranged relative to the axis AA1.

[0064] As for the input buffer circuit 103, it receives the data signal under the drive of the clock signal and continues to transmit the data signal. That is to say, when the data signal of the data pad 101 is transmitted to the input buffer circuit 103, the input buffer circuit 103 will receive the data signal and transmit the data signal only when the clock signal has been transmitted to the input buffer circuit 103; if the data signal is transmitted to the input buffer circuit 103 and the clock signal has not yet arrived, the input buffer circuit 103 will not transmit the data signal.

[0065] In this embodiment, the distance between each input buffer circuit 103 and the axis AA1 is less than the distance between the data pad 101 corresponding to the input buffer circuit 103 and the axis AA1, that is, each input buffer circuit 103 is closer to the axis AA1 than the data pad 101. Specifically, with the axis AA1 as a reference, the layout density of the M input buffer circuits 103 is greater than the layout density of the M data pads 101; for each data pad 101 and its corresponding input buffer circuit 103, the distance between the data pad 101 and the axis AA1 is greater than the distance between the input buffer circuit 103 and the axis AA1. Moreover, the closer the distance between the data pad 101 and the axis AA1, the closer the distance between the input buffer circuit 103 corresponding to the data pad 101 and the axis AA1.

[0066] Specifically, the input data path length between each input buffer circuit 103 and the data pad 101 corresponding to the input buffer circuit 103 is a first length, and the clock path length between each input buffer circuit 103 and the clock pad 102 is a second length, and the first length is positively correlated with the second length. That is, for all input buffer circuits 103, the larger the first length is, the larger the corresponding second length is, and the smaller the first length is, the smaller the corresponding second length is. In other words, the farther the data pad 101 is from the axis AA1, the farther the corresponding input buffer circuit 103 is from the axis AA1; the closer the data pad 101 is to the axis AA1, the closer the corresponding input buffer circuit 103 is to the axis AA1.

[0067] Compared to Figure 1 For the solution in which the distance between each input buffer circuit and the axis is equal to the distance between the corresponding data pad and the axis, in this embodiment, for each data pad 101 and input buffer circuit 103 on the same side of the axis AA1, the clock path of the input buffer circuit 103 farthest from the clock pad is reduced, so that the clock signal can be transmitted to the input buffer circuit 103 farthest from the clock pad more quickly, thereby reducing the signal delay time caused by the arrival of the data signal but the failure of the clock signal. Accordingly, the clock path of each input buffer circuit 103 is reduced, so the signal delay time of all input buffer circuits 103 can be reduced accordingly. In other words, this embodiment can reduce tDQS2DQ, reduce timing violations, and reduce the power consumed on the clock path.

[0068] In addition, the difference between the data path between each data pad 101 and the input buffer circuit 103 and the clock path between each clock pad 102 and the input buffer circuit 103 is reduced, so that the present embodiment can shorten the tDQS2DQ of different input buffer circuits 103, thereby improving the matching degree between the clock path and the data path of different input buffer circuits 103, thereby improving the timing characteristics of data signal transmission by different input buffer circuits 103.

[0069] Specifically, combined Figure 2 , each data pad 101 has a first port d0 / d1...d7, each input buffer circuit 103 has a second port r0 / r1...r7 connected to the first port of the corresponding data pad 101, each input buffer circuit 103 has a third port v0 / v1...v7 connected to the clock generation circuit 115, the clock generation circuit 115 has a fourth port c0 connected to each input buffer circuit 14 located on one side of the central axis AA1, and the clock generation circuit 115 also has a fifth port c1 connected to each input buffer circuit 103 located on the other side of the central axis AA1. For RX0, the clock path of the clock signal is c0→v0, and the data path of the data signal is d0→r0; for RX1, the clock path of the clock signal is c1→v1, and the data path of the data signal is d1→r1; and so on.

[0070] For example, Figure 2 The data signal of the data pad 101 marked as DQ0 is transmitted to the corresponding input buffer circuit 103 via a first length transmission path. Figure 2 The corresponding input buffer circuit is marked with RX0, and the clock signal is transmitted to the corresponding input buffer circuit 103 via the second length transmission path; the first length refers to the length from point d0 to point v0, and the second length refers to the length from point c0 to point v0. When the data signal is transmitted to RX0, the clock signal is transmitted to RX0 after t1 time, thereby ensuring that RX0 can transmit the data signal within t1 time after receiving the data signal; as the data pad 101 transmits the data signal DQ0 at a higher and higher rate, the time for DQ0 to maintain a high level "1" or a low level "0" is getting shorter and shorter, thereby requiring the waiting time t1 to be smaller and smaller, and further requiring the first length (corresponding to the data path) and the second length (corresponding to the clock path) to match as much as possible.

[0071] Figure 2 The data signal of the data pad 101 marked as DQ3 is transmitted to the corresponding input buffer circuit 103 via a first length transmission path. Figure 2The corresponding input buffer circuit is marked with RX3, and the clock signal is transmitted to the corresponding input buffer circuit 103 via the second length transmission path; the first length refers to the length from point d3 to point v3, and the second length refers to the length from point c0 to point v3. When the data signal is transmitted to the input buffer circuit 103, the clock signal is transmitted to RX3 after t2 time, thereby ensuring that RX3 can transmit the data signal within t2 time after receiving the data signal. For the data pads 101 marked as DQ0 and marked as DQ3, since the first length and the second length of the input buffer circuit 103 corresponding to DQ0 are matched, the first length and the second length of the input buffer circuit 103 corresponding to DQ3 are also matched, so t1 is equal to or approximately equal to t2. Therefore, this embodiment can improve the consistency of data signal transmission between RX0 and RX3.

[0072] In addition, combined Figure 2 It is not difficult to find that the data paths for each input buffer circuit 103 are different, and the clock paths for each input buffer circuit 103 are also different. For different input buffer circuits 103, the longer the data paths, the longer the corresponding clock paths. Therefore, in this embodiment, the time consistency of data signals transmitted by different input buffer circuits 103 can be improved, that is, better timing characteristics.

[0073] Figure 4 Another structural diagram of the interface circuit provided by the embodiment of the present invention is as follows: Figure 4 As shown, the interface circuit may further include: a flag pad 106 for transmitting a flag signal; a flag buffer circuit 107 corresponding to the flag pad 106 and used to receive the flag signal transmitted by the flag pad 106 under the drive of the clock signal; and a flag output buffer circuit (not shown).

[0074] The flag signal is usually called a data mask inverter, which is used to indicate whether each data signal is inverted. The flag pad 106 is usually called a DMI (data mask inverter) pad, a DM pad, or a DBI pad. Figure 4 In the figure, the flag pad 106 is marked with DMI, and the flag buffer circuit 107 is marked with DMI_RX.

[0075] In this embodiment, the flag pads 106 are arranged in the first row and between the data pads 101 and the clock pads 102. The flag buffer circuit 107 is arranged in the second row and is located on the same side of the axis AA1 as the flag pads 106 and between the input buffer circuit 103 and the axis AA1.

[0076] In addition, the distance between the flag buffer circuit 107 and the axis AA1 is smaller than the distance between the flag pad 106 corresponding to the flag buffer circuit 107 and the axis AA1.

[0077] Figure 5 A schematic diagram of the layout of the interface circuit provided by the embodiment of the present invention is shown in FIG. Figure 5 As shown, the interface circuit may further include: M output buffer circuits 108, corresponding to the data pads 101 one by one, each output buffer circuit 108, driven by the clock signal, sends the data signal to the corresponding data pad 101. In addition to being electrically connected to the data pad 101, the output buffer circuit 108 is also electrically connected to the clock pad. Figure 5 8 output buffer circuits 108 are illustrated as TX0, TX1, TX2, TX3, TX4, TX5, TX6, and TX7.

[0078] Specifically, the output buffer circuit 108 is electrically connected to the clock pad 102 via the clock receiving circuit 114 and the clock generating circuit 115 .

[0079] In this embodiment, the length of the output data path between each output buffer circuit 108 and the data pad 101 corresponding to the output buffer circuit 108 is the same. Specifically, each output buffer circuit 108 is located directly below the corresponding data pad 101, or in other words, the distance between each output buffer circuit 108 and the axis AA1 is equal to the distance between the corresponding data pad 101 and the axis AA1. Similarly, considering the actual situation of circuit design and manufacturing, the above-mentioned same length or equal distance can also be approximately the same or approximately equal, and a certain error is allowed, and similar descriptions are not repeated later.

[0080] The input buffer circuit 103 may include a multiplexer (mux) and a latch (latch). The multiplexer receives a data signal, processes the data signal, and outputs the processed data signal to the latch. The output of the latch serves as the output of the input buffer circuit 103 .

[0081] The interface circuit may further include: a plurality of power pads (not shown) and ground pads (not shown) for connecting to the ground or a fixed power source, wherein the plurality of power pads and the ground pads are located in the same row as the data pads.

[0082] like Figure 5 As shown, the interface circuit may further include: M optional input buffer circuits 109, and the number of the optional input buffer circuits 109 is the same as the number of the input buffer circuits 103, and the optional input buffer circuits 109 are arranged side by side with the input buffer circuits 103, Figure 5OPTION is used to illustrate the optional input buffer circuit 109. Specifically, in this embodiment, the optional input buffer circuit 109 is located on both sides of the input buffer circuit 103 corresponding to the four data pads 101 that are farthest from the central axis AA1. For example, the optional input buffer circuit 109 can play the role of DUMMY (as a virtual input buffer circuit for working environment matching) when it is not selected. In some cases, the optional input buffer circuit 109 can be re-selected through configuration.

[0083] Figure 6 for Figure 1 The layout diagram corresponding to the interface circuit provided, Figure 6 There is an output buffer circuit and a capacitor. It should be noted that for the convenience of comparison, Figure 6 The output buffer circuit is also illustrated using RX0, RX1...RX7. Figure 6 In the figure, other circuits are indicated by OTHERS, for example, OTHERS may be a capacitor.

[0084] Combined with reference Figure 5 and Figure 6 , based on the clock generation circuit, Figure 5 The layout density of the input buffer circuit 103 in Figure 6 The input buffer circuit layout density in . Taking DQ6 as an example, Figure 5 The clock path of the clock signal reaching the input buffer circuit corresponding to DQ6 is shown as Figure 6 The clock path of the clock signal shown to reach the input buffer circuit corresponding to DQ6 is short.

[0085] The above examples all take the data pad 101 as a DQ pad and the data signal as a DQ signal as an example. It can be understood that in other embodiments, the data pad can also be a command / address pad or a chip select pad, and the corresponding data signal is a command signal or an address signal. The interface circuit can be applied to LPDDR5. Figures 7 to 9 Four structural schematic diagrams of interface circuits whose data pads include command pads and address pads.

[0086] like Figure 7 As shown, the data pad 101 includes a plurality of command / address pads and a chip select pad, the command / address pads are marked with CA0 / CA1 / CA2 / CA3 / CA4 / CA5 / CA6, and the chip select pad is marked with CS. The command / address pads transmit command / address signals, the chip select pad transmits chip select signals, and the clock pad 102 is marked with CK.

[0087] In an example, Figure 7 As shown, all input buffer circuits 103 are in the same row.

[0088] In another example, Figure 8 As shown, some input buffer circuits 103 are in the same row, and the remaining input buffer circuits 103 are in another row. Specifically, it can be set as follows: half of all input buffer circuits 103 are in the same row, and the other half are in another row, and the input buffer circuits 103 corresponding to which data pads 101 are in the same row can be arbitrarily selected to ensure that the input data path length between each input buffer circuit 103 and the data pad 101 corresponding to the input buffer circuit 103 is a first length, and the clock path length between each input buffer circuit 103 and the clock pad 102 is a second length, and the first length is positively correlated with the second length.

[0089] like Fig. 9 As shown, the clock pads may include a first clock pad 112 and a second clock pad 122 , the first clock pad 112 is labeled as CK_t, and the second clock pad 122 is labeled as CK_c.

[0090] For a detailed description of the input buffer circuit 103, please refer to the above detailed description, which will not be repeated here. Figure 7-Figure 9 The interface circuit shown also has the beneficial effects of reducing tDQS2DQ, reducing timing violations, and reducing the power consumed on the clock path.

[0091] Correspondingly, an embodiment of the present invention also provides a data transmission circuit, including the interface circuit in the above embodiment, and also including M serial-to-parallel conversion circuits, and the number of the M serial-to-parallel conversion circuits corresponds one-to-one to the M input buffer circuits, and the output of each input buffer circuit serves as the input of the corresponding serial-to-parallel conversion circuit. Fig.10 A schematic diagram of the planar layout of the data transmission circuit provided in this embodiment.

[0092] The input buffer circuit 103 may include a multiplexer (mux) and a latch (latch). The multiplexer receives a data signal, processes the data signal, and outputs the processed data signal to the latch. The output of the latch serves as the output of the input buffer circuit 103 . Fig.10In the figure, MUX0, MUX1, MUX2, MUX3, MUX4, MUX5, MUX6, and MUX7 are used to indicate the multiplexers corresponding to the eight input buffer circuits 103, and IB0, IB1, IB2, IB3, IB4, IB5, IB6, and IB7 are used to indicate the latches corresponding to the eight input buffer circuits 103. In this embodiment, the data transmission circuit includes: the interface circuit provided in the above embodiment; M serial to parallel conversion circuits (Sequential to Parallel) S2P, the M serial to parallel conversion circuits S2P correspond to the M input buffer circuits 103 one by one, and the output of each input buffer circuit 103 serves as the input of the corresponding serial to parallel conversion circuit S2P.

[0093] Specifically, the M serial-to-parallel conversion circuits S2P are arranged in the third row, and the transmission path lengths between each input buffer circuit 103 and the serial-to-parallel conversion circuit S2P corresponding to the input buffer circuit 103 on the same side of the axis AA1 are different.

[0094] More specifically, the transmission path lengths between the latch 123 corresponding to each input buffer circuit 103 and the corresponding serial-to-parallel conversion circuit S2P on the same side of the axis AA1 are different.

[0095] In addition, the M serial-to-parallel conversion circuits S2P correspond to the M data pads 101 one by one, and the distance between each serial-to-parallel conversion circuit S2P and the corresponding data pad 101 is the same. It can be considered that each serial-to-parallel conversion circuit S2P is arranged directly below the corresponding data pad 101.

[0096] In this embodiment, the data transmission circuit also includes: M first-in first-out circuits Output FIFO, corresponding one-to-one to the M serial-to-parallel conversion circuits; M parallel-to-serial conversion circuits (Parallel to Sequential) P2S, corresponding one-to-one to the M first-in first-out circuits (First Input First Output) Output FIFO, and the output of each first-in first-out circuit Output FIFO serves as the input of the parallel-to-serial conversion circuit P2S corresponding to the first-in first-out circuit Output FIFO; M driving circuits, corresponding one-to-one to the M parallel-to-serial conversion circuits P2S, and the output of each parallel-to-serial conversion circuit P2S serves as the input of the driving circuit corresponding to the parallel-to-serial conversion circuit P2S; and the M driving circuits also correspond one-to-one to the M data pads 101. Fig.10DR0, DR1, DR2, DR3, DR4, DR5, DR6, and DR7 are used to indicate the driving circuits corresponding to the eight data pads 101. In this embodiment, the parallel-to-serial conversion circuit P2S is arranged directly below each data pad 101, and is located between adjacent latches and arranged in the same row as the latches. The driving circuit is arranged directly below each data pad 101, and is located between the data pad 101 and the row where the multiplexer is located.

[0097] It can be understood that the driving circuit and the corresponding parallel-to-serial conversion circuit P2S constitute the output buffer circuit 108 .

[0098] The data transmission circuit may further include: a pre-driving circuit. The pre-driving circuit is electrically connected to the driving circuit and is located between the driving circuit 204 and the parallel-to-serial conversion circuit P2S. In this embodiment, the pre-driving circuit may be located between adjacent multiplexers and arranged in the same row as the multiplexers.

[0099] The data transmission circuit may further include: an electrostatic discharge circuit and a capacitor, etc.

[0100] The data transmission circuit further includes: M optional input buffer circuits 109, and the number of the M optional input buffer circuits 109 is the same as that of the input buffer circuits 103, and the M optional input buffer circuits 109 are arranged in parallel with the input buffer circuits 103. For detailed description of the optional input buffer circuits 109, reference may be made to the previous embodiment.

[0101] Specifically, the optional input buffer circuit 109 includes an optional multiplexer and an optional latch, wherein the optional multiplexer is arranged side by side with the multiplexer, and the optional latch is arranged side by side with the latch. Fig.10 In the figure, MUX is used to indicate an optional multiplexer, and IB is used to indicate an optional latch. As mentioned above, the multiplexer and latch that are farthest from the axis AA1 and do not play a role in signal transmission are used as the optional multiplexer and the optional latch, respectively.

[0102] In this embodiment, two of the M input buffer circuits 103 and / or the M optional input buffer circuits 109, one of the M serial-to-parallel conversion circuits S2P, one of the M first-in first-out circuits Output FIFO, one of the M parallel-to-serial conversion circuits P2S, and one of the M driving circuits together constitute a data transmission unit DQ cell, and the working environment of each data transmission unit DQ cell is matched.

[0103] The working environment matching means that, for each data transmission unit DQ cell, latches or optional latches are distributed on both sides of each parallel-to-serial conversion circuit P2S. Therefore, the working environment of each serial-to-parallel conversion circuit S2P is consistent, such as the degree of noise interference.

[0104] For example, for a data pad labeled DQ5, the data transmission unit DQ cell includes: an input buffer circuit 103, an optional input buffer circuit 109, a first-in first-out circuit Output FIFO, a serial-to-parallel conversion circuit S2P, and a driving circuit. For a data pad labeled DQ4, the data transmission unit DQ cell includes: an input buffer circuit 103, an optional input buffer circuit 109, a first-in first-out circuit Output FIFO, a serial-to-parallel conversion circuit S2P, and a driving circuit. For a data pad labeled DQ6, the data transmission unit DQ cell includes: two optional input buffer circuits 109, a first-in first-out circuit Output FIFO, a serial-to-parallel conversion circuit S2P, and a driving circuit.

[0105] In one example, the serial-to-parallel conversion circuit S2P and the first-in first-out circuit Output FIFO in the same data transmission unit DQ cell are arranged in parallel, that is, the serial-to-parallel conversion circuit S2P and the first-in first-out circuit Output FIFO in the same data transmission unit DQ cell are located in the same row.

[0106] In another example, the serial-to-parallel conversion circuit S2P and the first-in-first-out circuit Output FIFO in the same data transmission unit DQ cell are arranged side by side, that is, the serial-to-parallel conversion circuit S2P and the first-in-first-out circuit Output FIFO in the same data transmission unit DQ cell are located in different rows, and the first-in-first-out circuit Output FIFO is located between the serial-to-parallel conversion circuit S2P and the input buffer circuit 103.

[0107] Furthermore, in other embodiments, the first-in-first-out circuits in different data transmission units may also be arranged side by side.

[0108] For ease of understanding, Fig.10 Schematically illustrates a bus BUS, a sense amplifier SA and a plurality of storage blocks, wherein 8 storage blocks are illustrated as BANK0, BANK1, BANK2, BANK3, BANK4, BANK5, BANK6 and BANK7. In other embodiments, the number of storage blocks can be reasonably set according to the required performance.

[0109] Fig.10In the figure, the dotted arrows indicate the data path and clock path during the period of reading data from the storage block, that is, the data path and clock path during the process of reading data from the storage block to the corresponding data pad 101; the solid arrows indicate the data path and clock path during the period of writing data to the storage block, that is, the data path and clock path during the process of storing data from the data pad 101 to the corresponding storage block. It should be noted that the solid arrows in the aforementioned figures also correspond to the data path and clock path during the period of writing data, and the dotted arrows correspond to the data path and clock path during the period of reading data.

[0110] The working principle of the data transmission circuit provided in this embodiment is described below in conjunction with the accompanying drawings:

[0111] During data writing: taking the DQ6 data pad as an example, DQ6 transmits the data signal to the multiplexer MUX6, and the multiplexer MUX6 continues to transmit the data signal to the latch IB6; the signal provided by the clock generating circuit 115 is transmitted to the latch IB6 after passing through the clock path length; when the clock signal reaches the latch IB6, driven by the clock signal, the latch IB6 transmits the data signal to the serial-to-parallel conversion circuit S2P; the serial-to-parallel conversion circuit S2P transmits the data signal to the bus BUS, and the data signal is amplified by the sensing amplifier SA and stored in the corresponding storage block BANK6. As can be seen from the relevant analysis of the aforementioned interface circuit, for DQ0 / DQ1 / DQ2 / DQ3 / DQ4 / DQ5 / DQ6 / DQ7, the length of the clock path that the clock signal needs to go through to reach the corresponding latch is short and the difference in the length of each clock path is small. Therefore, the time delay for the latch corresponding to DQ0 / DQ1 / DQ2 / DQ3 / DQ4 / DQ5 / DQ6 / DQ7 to transmit the data signal to the corresponding serial-to-parallel conversion circuit S2P is small, thereby improving the matching degree of the data path and clock path corresponding to each input buffer circuit, reducing the difference in the time required for data in different data pads 101 to be written to the corresponding storage block, thereby improving the write performance.

[0112] During data reading: Continuing with the example of the DQ6 data pad, the data signal from the storage block BANK6 is amplified by the sense amplifier SA and then transmitted to the bus BUS; the data signal is transmitted to the corresponding first-in first-out circuit Output FIFO via the bus BUS; the first-in first-out circuit Output FIFO transmits the data signal to the parallel-to-serial conversion circuit P2S, and the data signal reaches the DQ6 data pad after passing through the parallel-to-serial conversion circuit P2S, the pre-drive circuit and the drive circuit DR6.

[0113] In the data transmission circuit provided in this embodiment, a centralized input buffer circuit layout is adopted to shorten the clock path length required for transmitting the clock signal to each input buffer circuit, improve the matching degree between the clock path and the data path, thereby reducing tDQS2DQ and timing violations. The clock path lengths corresponding to each input buffer circuit are relatively small, which can simultaneously meet the requirements of high matching degree between the clock path and the data path of each input buffer circuit.

[0114] In addition, since the length of the clock path is shortened, the length of the wire transmitting the clock signal is correspondingly shortened, so the power consumption of the data transmission circuit can be reduced to a certain extent.

[0115] Correspondingly, an embodiment of the present invention further provides a memory, including the above-mentioned data transmission circuit. Specifically, the structural diagram of the memory can be referred to Fig.10 The above memory can be applied to Fig.11 In the storage system shown, Fig.11 A schematic diagram of a structure of a memory provided in an embodiment of the present invention applied to a storage system, wherein MemoryController is a controller, Memory is a memory, IO Circuit is an interface circuit, Data Path is a data path, and Array is a storage array. IO Circuit can be, for example, an interface circuit of the present application, and Data Path can include, for example, a transmission circuit of the present application.

[0116] The memory may be a DRAM, SRAM, MRAM, FeRAM, PCRAM, NAND, NOR, etc. For example, the memory may be an LPDDR4 memory or an LPDDR5 memory.

[0117] Those skilled in the art will appreciate that the above embodiments are specific examples of the present invention, and in practical applications, various changes may be made to the embodiments in form and detail without departing from the spirit and scope of the present invention. Any person skilled in the art may make changes and modifications without departing from the spirit and scope of the present invention, and therefore the scope of protection of the present invention shall be subject to the scope defined in the claims.

Claims

1. An interface circuit, characterized in that: include: Clock pad, used to transmit clock signal; M data pads, used for transmitting data signals; M input buffer circuits, corresponding to the data pads one by one, each of the input buffer circuits receiving the data signal transmitted by the data pad corresponding to the input buffer circuit under the drive of the clock signal; The clock pad and the data pad are arranged in a first row, and the M data pads are arranged on both sides of the clock pad, with half of the M data pads arranged on each side, and the M input buffer circuits are arranged in a second row, with the clock pad as a reference, forming an axis perpendicular to the first row, the M input buffer circuits are arranged on both sides of the axis, with half of the M input buffer circuits arranged on each side, a distance between each input buffer circuit and the axis is less than a distance between the data pad corresponding to the input buffer circuit and the axis, and M is an integer greater than or equal to 2; M output buffer circuits, corresponding to the data pads one by one, each of the output buffer circuits sending the data signal to the corresponding data pad under the drive of the clock signal, and each of the output buffer circuits is located directly below the corresponding data pad; M optional input buffer circuits, the number of the M optional input buffer circuits is the same as the number of the input buffer circuits, and the M optional input buffer circuits are arranged side by side with the input buffer circuits; Among them, the M input buffer circuits, the M output buffer circuits, and the M optional input buffer circuits are arranged in such a manner that one of the M output buffer circuits corresponds to two of the M input buffer circuits, or one of the M output buffer circuits corresponds to two of the M optional input buffer circuits.

2. The interface circuit according to claim 1, characterized in that: The input data path length between each input buffer circuit and the data pad corresponding to the input buffer circuit is a first length, and the clock path length between each input buffer circuit and the clock pad is a second length, and the first length is positively correlated with the second length.

3. The interface circuit according to claim 1, characterized in that: The clock pad is a differential input pad, including a first clock pad and a second clock pad, and the first clock pad and the second clock pad transmit complementary clock signals respectively.

4. The interface circuit according to claim 3, characterized in that: The first clock pad and the second clock pad are arranged symmetrically with respect to the axis.

5. The interface circuit according to claim 1, characterized in that: Also includes: The clock processing circuit is electrically connected to the clock pad and the M input buffer circuits, and is used to receive the clock signal and process the clock signal as a driving clock for the M input buffer circuits.

6. The interface circuit according to claim 5, characterized in that: The clock processing circuit includes a clock receiving circuit and a clock generating circuit. The clock receiving circuit is electrically connected to the clock pad and is used to receive the clock signal. The output of the clock receiving circuit serves as the input of the clock generating circuit, and the clock generating circuit is used to generate the driving clock.

7. The interface circuit according to claim 1, characterized in that: Also includes: A logo pad, used for transmitting a logo signal; The flag buffer circuit corresponds to the flag pad and is used for receiving the flag signal transmitted by the flag pad under the drive of the clock signal.

8. The interface circuit according to claim 7, characterized in that: The flag pad is arranged in the first row and is located between the data pad and the clock pad; the flag buffer circuit is arranged in the second row and is located on the same side of the axis as the flag pad, and is located between the input buffer circuit and the axis; the distance between the flag buffer circuit and the axis is smaller than the distance between the flag pad corresponding to the flag buffer circuit and the axis.

9. The interface circuit according to claim 1, characterized in that: The output data path length between each of the output buffer circuits and the data pad corresponding to the output buffer circuit is the same.

10. The interface circuit according to claim 1, characterized in that: The input buffer circuit includes a multiplexer and a latch. The multiplexer receives the data signal and outputs the processed data signal to the latch. The output of the latch serves as the output of the input buffer circuit.

11. A data transmission circuit, characterized in that: The interface circuit comprises any one of claims 1 to 10, and further comprises: M serial-to-parallel conversion circuits, wherein the M serial-to-parallel conversion circuits correspond one-to-one to the M input buffer circuits, and the output of each input buffer circuit serves as the input of the corresponding serial-to-parallel conversion circuit.

12. The data transmission circuit according to claim 11, characterized in that: The M serial-to-parallel conversion circuits are arranged in a third row, and the transmission path lengths between each input buffer circuit and the serial-to-parallel conversion circuit corresponding to the input buffer circuit on the same side of the axis are different.

13. The data transmission circuit according to claim 11, characterized in that: The M serial-to-parallel conversion circuits correspond to the M data pads one by one, and the distance between each of the serial-to-parallel conversion circuits and the data pad corresponding to the serial-to-parallel conversion circuit is the same.

14. The data transmission circuit according to claim 11, characterized in that: Also includes: M first-in-first-out circuits, corresponding one-to-one to the M serial-to-parallel conversion circuits; M parallel-to-serial conversion circuits correspond one-to-one to the M first-in-first-out circuits, and the output of each first-in-first-out circuit serves as the input of the parallel-to-serial conversion circuit corresponding to the first-in-first-out circuit; The M driving circuits correspond one-to-one to the M parallel-to-serial conversion circuits, and the output of each parallel-to-serial conversion circuit serves as the input of the driving circuit corresponding to the parallel-to-serial conversion circuit; the M driving circuits also correspond one-to-one to the M data pads.

15. The data transmission circuit according to claim 14, characterized in that: The M input buffer circuits and / or two of the M optional input buffer circuits, one of the M serial-to-parallel conversion circuits, one of the M first-in-first-out circuits, one of the M parallel-to-serial conversion circuits and one of the M driving circuits together constitute a data transmission unit, and the working environment of each of the data transmission units is matched.

16. The data transmission circuit according to claim 15, characterized in that: The serial-to-parallel conversion circuit and the first-in-first-out circuit in the same data transmission unit are arranged side by side or in parallel.

17. The data transmission circuit according to claim 15, characterized in that: The first-in first-out circuits in different data transmission units are arranged side by side.

18. A memory, characterized in that: The data transmission circuit comprises any one of claims 11 to 17.

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