Apparatus and method for providing data rate operation

Abstract

This application relates to apparatus and methods for providing data rate operation. In some instances, the memory device may include internal synchronization circuitry to enable double data rate operation of the memory device when an external single data rate signal is provided to the memory device. In some instances, the external signal may be a command and / or address signal provided by external test circuitry. The internal synchronization circuitry may latch and / or delay at least some of the external signals such that different external commands are provided at the rising and falling edges of the clock signal of the memory device. The memory device may latch the external signals at both the rising and falling edges of the clock signal for double data rate operation of the memory device.

Description

TECHNICAL FIELD

[0001] The present disclosure relates generally to semiconductor devices, and more specifically to semiconductor memory devices. In particular, the present disclosure relates to volatile memory, such as dynamic random access memory (DRAM). BACKGROUND

[0002] Memory operations, such as read and write operations, are performed based on timing signals provided by a clocking circuit. Timing signals are also referred to as clock signals, which can be periodic signals oscillating between two clock levels, such as a high clock level and a low clock level. Different types of DRAMs are designed to operate in various modes with respect to clock signals. For example, single data rate (SDR) DRAMs can perform various operations only on a rising (e.g., transitioning from a low clock level to a high clock level) or falling (e.g., transitioning from a high clock level to a low clock level) edge of a clock signal. For example, SDR DRAMs can detect (e.g., latch) commands, addresses, data, and / or other signals only on a rising or falling edge of a clock signal. In contrast, double data rate (DDR) DRAMs can perform various operations, such as detecting commands, addresses, data, and / or other signals, on both a rising and a falling edge of a clock signal. In some applications, DDR DRAMs can operate at a faster rate compared to SDR DRAMs, even if both DRAMs receive a clock signal having the same frequency, because at least some DDR DRAM operations can occur at twice the rate per clock cycle (e.g., DDR) rather than once per clock cycle (e.g., SDR). Thus, in some applications, DDR DRAMs can provide higher throughput and / or faster-performing memory operations compared to SDR DRAMs.

[0003] Generally, memory manufacturers test DRAM dies to confirm that the DRAMs operate according to specifications before packaging and / or shipping to customers. It can be desirable to test DRAMs with test conditions similar to operating conditions in which the DRAMs are used to help ensure that the DRAMs will function properly when used by customers. SUMMARY

[0004] According to one aspect of the present application, an apparatus is provided. The apparatus includes a first latch configured to latch a command / address signal on a first edge of a clock signal, wherein the command / address signal includes a first portion and a second portion; a second latch configured to latch the command / address signal on a second edge of the clock signal, wherein the first edge and the second edge are included within a same clock cycle of the clock signal; and a test synchronization circuit configured to provide a delay for the command / address signal provided to the first latch and the second latch, wherein the delay causes a transition of the command / address signal from the first portion to the second portion to occur at a time after the first edge of the clock signal and before the second edge of the clock signal, wherein the first latch latches the command / address signal before the transition and the second latch latches the command / address signal after the transition.

[0005] According to another aspect of the present application, a system is provided. The system includes a test device configured to provide a command / address signal and a clock signal; a memory device coupled to the test device, the memory device including a clock input circuit configured to receive the clock signal and generate an internal clock signal based at least in part on the clock signal; a test synchronization circuit configured to receive the command / address signal and the clock signal and generate a delayed command / address signal based on the command / address signal; a command / address input circuit including a first latch and a second latch configured to receive the internal clock signal and the delayed command / address signal, wherein the first latch is configured to latch the delayed command / address signal on a first edge of the internal clock signal and the second latch is configured to latch the delayed command / address signal on a second edge of the internal clock signal, wherein the delayed command / address signal includes a first command / address at the first edge and the delayed command / address signal includes a second command / address at the second edge.

[0006] According to yet another aspect of the present application, a method is provided. The method includes receiving a test clock signal at a first rate, receiving a test command / address signal at a second rate slower than the first rate, delaying the test clock signal through a test synchronization circuit, triggering a latching of the test command / address signal by the test synchronization circuit through the delayed test clock signal, providing the latched test command / address signal to a first latch and a second latch through the test synchronization circuit, latching the test command / address signal through the first latch in response to a first edge of a second clock signal, and latching the test command / address signal through the second latch in response to a second edge of the second clock signal. BRIEF DESCRIPTION OF DRAWINGS

[0007] Figure 1 is a block diagram of a semiconductor device according to an embodiment of the present disclosure.

[0008] Figure 2 is a block diagram of a portion of a semiconductor device according to an embodiment of the present disclosure.

[0009] Figure 3 is a timing diagram of signals of a semiconductor device according to an embodiment of the present disclosure.

[0010] Figure 4 is a block diagram of a test system according to an embodiment of the present disclosure.

[0011] Figure 5 is a flowchart of a method according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0012] The following description of certain examples is merely exemplary in nature and is in no way intended to limit the scope of the disclosure, its application, or uses. In the following detailed description of embodiments of the application, reference is made to the accompanying drawings, which form a part hereof, and in which are shown by way of illustration specific embodiments in which the described devices, systems, and methods can be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the disclosed devices, systems, and methods, and it is to be understood that other embodiments can be utilized and that structural and logical changes can be made without departing from the spirit and scope of the present disclosure. Furthermore, to the extent that the terms "includes" and "including" are used in the detailed description and claims, these terms are intended to be inclusive in a manner similar to the term "comprising" as "comprising" is interpreted when employed as a transitional term in the claim. Furthermore, certain features of the described embodiments can be used to advantage without the use of other features. As such, the following description is not to be considered an enumeration of necessary features of the described embodiments, nor is it considered a limitation on the scope of the disclosure.

[0013] As memory devices, such as DRAM, become smaller, they become more susceptible to damage. This makes testing the memory before packaging more difficult. A memory device die typically contains various pads for providing signals to and receiving signals from external devices, such as memory controllers. For example, pads for providing and receiving data (e.g., DQ pads), pads for receiving command and address information (e.g., CA pads), and / or pads for receiving clock signals may be included on the die. These pads can be coupled to external devices when the memory is packaged in a device (e.g., as part of a memory module). Testing the memory before packaging may be necessary to avoid having to discard the entire device if only the memory is defective. However, testing can damage the pads, making it impossible for the memory to be coupled to external devices when packaged.

[0014] To address this issue, some memory manufacturers provide a second set of pads on the die containing the memory device for testing purposes. This second set of pads can be located at different positions on the die to reduce the risk of accidental contact and thus damage to the pads used to couple the memory device to external devices. This second set of pads may be collectively referred to as external direct access (DA) pads, although the external DA pads may be included on the same die as the memory device.

[0015] The test setup can provide clock signals, commands, addresses, and / or data to the memory device via a DA pad. The test setup can further receive data and / or other signals from the memory die via the DA pad. The test setup can analyze the received data and / or signals to determine whether the memory is operating properly.

[0016] Typically, memory manufacturers use test setups that test several memory dies in parallel (e.g., simultaneously or nearly simultaneously) to increase throughput. However, due at least in part to the large number of memory dies being tested in parallel, the test setup may not be able to provide command and / or address signals at high speeds. In some applications, the test setup may only provide certain signals at SDR operations (e.g., providing commands on the rising edge of the clock signal). This prevents testing some or all of the DDR operations of the memory die during some test modes (e.g., latching and executing commands received on both the rising and falling edges of the clock signal). Therefore, it may be undesirable not to verify that all operations of the memory die are working properly before packaging.

[0017] In some embodiments of this disclosure, the memory device may include internal synchronization circuitry that modulates the timing of SDR signals (e.g., signals provided at the speed for SDR operation) received from the DA pad to simulate DDR signals (e.g., signals provided at the speed for DDR operation). In some embodiments, the internal synchronization circuitry may latch and delay certain signals received from the DA pad such that the signals are shifted (e.g., delayed) relative to the memory device's internal clock signal. This signal shifting allows the memory device to latch the signals on both the rising and falling edges of the memory device's clock signal. This may permit testing the DDR operation of the memory device in some applications.

[0018] Figure 1 This is a block diagram of a semiconductor device according to an embodiment of the present disclosure. Semiconductor device 100 may be a semiconductor memory device, such as a DRAM device integrated on a single semiconductor chip. In some embodiments, device 100 may be DDRDRAM.

[0019] Semiconductor device 100 includes memory array 118. Memory array 118 is shown as comprising multiple memory groups. Figure 1 In one embodiment, the memory array 118 is shown as comprising eight memory groups BANK0 to BANK7. In other embodiments, the memory array 118 may contain more or fewer groups. Each memory group comprises multiple word lines WL, multiple bit lines BL and / BL, and multiple memory cells MC arranged at the intersections of the multiple word lines WL and the multiple bit lines BL and / BL. The selection of word lines WL is performed by the row decoder 108, and the selection of bit lines BL and / BL is performed by the column decoder 110. Figure 1 In this embodiment, row decoder 108 includes a corresponding row decoder for each memory bank, and column decoder 110 includes a corresponding column decoder for each memory bank. Bit lines BL and / BL are coupled to corresponding sense amplifiers (SAMPs) 126. Read data from bit lines BL and / BL is amplified by sense amplifier 126 and signaled to sub-amplifier (SB) 128 via local data line (LIOT / B). Sub-amplifier 128 may provide signals to master data line (MIOT / B). Master data line may provide signals to read / write amplifier (RWAMP) 120. Read / write amplifier 120 may provide read data to input / output (IO) circuitry 122 via global data bus (GBUS). Conversely, write data received from IO circuitry 122 via global data bus is provided from read / write amplifier 120 to sense amplifier 126 via master data line MIO, sub-amplifier 128, and local data line LIOT / B, and written to memory cells MC coupled to bit lines BL and / BL.

[0020] The semiconductor device 100 may employ multiple external terminals, including a command and address (CA) terminal coupled to the command and address bus to receive command and address signals and chip select signals, a clock terminal to receive clocks CK_t and CK_c, a data terminal DQ to provide data, and a power supply terminal to receive power supply potentials VDD, VSS, VDDQ, and VSSQ.

[0021] External clocks CK_t and CK_c are supplied to the clock terminals and are provided to input circuit 112. The external clocks are complementary. Input circuit 112 generates an internal clock ICLK based on the CK_t and CK_c clocks. The ICLK clock is provided to command / address input circuit 102, command decoder 106, and internal clock generator 114. Internal clock generator 114 provides various internal clocks LCLK based on the ICLK clock. The LCLK clock can be used for timing operations of various internal circuits. The internal data clock LCLK is provided to input / output circuit 122 to time the operation of circuits contained within input / output circuit 122, for example, to a data receiver to time the reception of written data.

[0022] The CA terminal can supply a memory address. The memory address supplied to the CA terminal is transmitted to the address decoder 104 via the command / address input circuit 102. The address decoder 104 receives the address and supplies the decoded row address XADD to the row decoder 108 and the decoded column address YADD to the column decoder 110. The address decoder 104 can also supply a decoded group address BADD, which indicates a group of memory arrays 118 containing the decoded row address XADD and column address YADD. The CA terminal can supply commands. Examples of commands include access commands for accessing memory, such as read commands for performing read operations and write commands for performing write operations, as well as other commands and operations. Access commands can be associated with one or more row addresses XADD, column addresses YADD, and group addresses BADD used to indicate the memory cell to be accessed. Commands can be provided as internal command signals to the command decoder 106 via the command / address input circuit 102. Command decoder 106 includes circuitry for decoding internal command signals to generate various internal signals and commands for performing operations. For example, command decoder 106 may provide row command signals for selecting word lines and column command signals for selecting bit lines.

[0023] Command / address input circuit 102 may include one or more latches for (at least temporarily) storing commands and / or addresses received from the CA terminal. Figure 1(Not shown in the diagram). In some embodiments, the command / address input circuit 102 may include one or more latches that latch the command and / or address on the rising edge of ICLK and one or more latches that latch the command and / or address on the falling edge of ICLK. The inclusion of latches for latching on the rising clock edge and latches for latching on the falling clock edge allows the device 100 to operate in DDR mode. In some embodiments, the latches included in the command / address input circuit 102 may latch the command and / or address on the rising clock edge. However, a clock signal ICLK may be provided for some latches, while a complementary clock signal / ICLK may be provided for others. Therefore, the command and / or address can be latched by the command / address input circuit 102 at times corresponding to both the rising and falling edges of ICLK.

[0024] Device 100 can receive access commands as read commands. When an activation and read command is received, and the group address, row address, and column address are supplied in a timely manner for the activation and read command, read data is read from the memory cells corresponding to the row address and column address in the memory array 118. Command decoder 106 receives the activation and read command and provides an internal command to provide the read data from the memory array 118 to the read / write amplifier 120. The read data is output to the outside via I / O circuit 122 from the data terminal DQ.

[0025] Device 100 can receive access commands as write commands. When an activation and write command is received, and the group address, row address, and column address are supplied in a timely manner for the activation and write command, write data supplied to the data terminal DQ is written to the memory cells in memory array 118 corresponding to the row address and column address. Command decoder 106 receives the activation and write command and provides an internal command to cause the data receiver in I / O circuit 122 to receive the write data. A write clock can also be provided to an external clock terminal for timing the data receiver in I / O circuit 122 to receive the write data. Write data is supplied to read / write amplifier 120 via I / O circuit 122, and then supplied to memory array 118 via read / write amplifier 120 to be written into memory cell MC.

[0026] The memory cells of memory array 118 may require periodic refresh to store data in the memory cells MC. A refresh signal AREF may be supplied to refresh control circuitry 116. Refresh control circuitry 116 supplies a refresh row address RXADD to row decoder 108, which refreshes one or more word lines WL indicated by refresh row address RXADD. Refresh control circuitry 116 can control the timing of the refresh operation and can generate and provide refresh address RXADD. Refresh control circuitry 116 can be controlled to change the details of refresh address RXADD, or refresh control circuitry 116 can be operated based on internal logic.

[0027] Power supply potentials VDD and VSS are supplied to the power supply terminals. These potentials VDD and VSS are then supplied to the internal voltage generator circuit 124. The internal voltage generator circuit 124 generates various internal potentials VPP, VOD, VARY, VPERI, etc., based on the power supply potentials VDD and VSS supplied to the power supply terminals. Internal potential VPP is primarily used in the line decoder 108, internal potentials VOD and VARY are primarily used in the sense amplifier 126 included in the memory array 118, and internal potential VPERI is used in many peripheral circuit blocks.

[0028] Power potentials VDDQ and VSSQ are also supplied to the power terminals. These power potentials VDDQ and VSSQ are supplied to the I / O circuit 122. In one embodiment of this disclosure, the power potentials VDDQ and VSSQ supplied to the power terminals may be the same as the power potentials VDD and VSS supplied to the power terminals. In another embodiment of this disclosure, the power potentials VDDQ and VSSQ supplied to the power terminals may be different from the power potentials VDD and VSS supplied to the power terminals. The power potentials VDDQ and VSSQ supplied to the power terminals are used in the I / O circuit 122 so that power supply noise generated by the I / O circuit 122 does not propagate to other circuit blocks.

[0029] In some embodiments, such as in Figure 1 In one embodiment shown, device 100 may include an external DA pad 130. For testing purposes, the external DA pad 130 provides access to device 100. The external DA pad 130 may include features for accessing the device from a test apparatus (…). Figure 1 (Not shown) Receives signals and / or provides signals to one or more terminals of the test apparatus. For example, the external DA pad 130 may include terminals for receiving clock signals (TEST_CK), command / address signals (TEST_CA), and / or test command signals (TEST_CMD). Although in Figure 1The external DA pad 130 is shown as a single pad, but in some embodiments, it may comprise multiple pads. The external DA pad 130 may provide signals to various components of the device 100. In some embodiments, the TEST_CK signal may be provided to the clock input circuit 112 and / or the command / address input circuit 102. In some embodiments, the TEST_CA signal may be provided to the command / address input circuit 102. In some embodiments, the TEST_CMD signal may be provided to the test decoder circuit 132. The test command signal TEST_CMD may contain information about the test being performed by the test device. For example, the TEST_CMD signal may contain information indicating the test mode (e.g., loopback test, 1DQ test). In response to the TEST_CMD signal, the test decoder circuit 132 may provide various signals to one or more components of the device 100. For example, the test decoder circuit 132 may provide signals to enable or disable various internal test circuits (e.g., the test synchronization circuit 134 included in the command / address input circuit 102). In some embodiments, the test decoder circuit 132 may provide a control signal in response to TEST_CMD. In some embodiments, the control signal may be used to select between different signals and / or signal paths.

[0030] According to embodiments of this disclosure, the command / address input circuit 102 may include a test synchronization circuit 134. The test synchronization circuit 134 may receive a command address signal TEST_CA from an external DA pad 130 during testing of the device 100. In some embodiments, the test synchronization circuit 134 may receive a clock signal TEST_CK from the external DA pad 130 during testing. However, in some embodiments, the tester input circuit may receive TEST_CK via a clock input circuit 112. As mentioned, the test synchronization circuit 134 may receive one or more enable signals and / or control signals from the test decoder circuit 132.

[0031] In some applications, the test apparatus may provide a command address signal TEST_CA at the SDR. In some embodiments, the test synchronization circuit 134 provides a signal that allows DDR operation of the test apparatus 100. For example, the test synchronization circuit 134 may allow the test apparatus to determine whether the command / address input circuit 102 properly latches the command at both the rising and falling edges of ICLK. In some embodiments, the test synchronization circuit 134 may delay the TEST_CA signal so that the command of the TEST_CA signal is received at the latch of the command / address input circuit 102 at both the rising and falling edges of the clock signal ICLK.

[0032] Figure 2This is a block diagram of a portion of a semiconductor device according to embodiments of the present disclosure. In some embodiments, the semiconductor device 200 may be a DDR device. In some embodiments, the semiconductor device 200 may be included in... Figure 1 In the semiconductor device 100 shown, device 200 may include clock input circuitry 202, command / address input circuitry 204, and external DA pad 206. In some embodiments, clock input circuitry 202 may be included in clock input circuitry 112, command / address input circuitry 204 may be included in command / address input circuitry 112, and / or external DA pad 206 may be included in external DA pad 130. Although in Figure 2 The diagram shows a single pad, but in some embodiments, the outer DA pad 206 may contain separate pads for different signals (e.g., different DA pads for TEST_CK and TEST_CA).

[0033] During normal operation of device 200 (e.g., when communicating with a memory controller), clock input circuit 202 may receive complementary clock signals CK_t and CK_c at terminals. Clock signals CK_t and CK_c may be provided to input buffer 208, which may then provide the clock signals to clock controller / buffer 210. Clock controller / buffer 210 may generate internal clock signals Clk_R and Clk_F based at least in part on clock signals CK_t and CK_c. In some embodiments, Clk_R and Clk_F may be complementary clock signals.

[0034] During testing of device 200 (e.g., when communicating with a test device), clock input circuitry 202 may receive a clock signal TEST_CK from external DA pad 206. In some embodiments, the TEST_CK signal may be received from a test device (not shown) coupled to external DA pad 206 and / or based on a signal received from the test device (not shown) coupled to external DA pad 206. In some embodiments, the clock signal TEST_CK may include complementary clock signals. In some embodiments, TEST_CK may be provided to input buffer 208 via buffer 212. The TEST_CK signal may then be provided from input buffer 208 to clock controller / buffer 210 to generate internal clock signals Clk_R and Clk_F. In some embodiments, control logic 214 may be used to enable and disable the TEST_CK signal. Figure 2In the example shown, control logic 214 includes AND logic circuitry. Control logic 214 can receive a test enable signal DAenable. In some embodiments, the DAenable signal may be provided by, for example, the test decoder circuitry of test decoder circuitry 132. In other embodiments, the DAenable signal may be provided from a test device via an external DA pad 206. When the DAenable signal is active (e.g., logic high), a TEST_CK signal may be provided to buffer 212. When the DAenable signal is inactive (e.g., logic low), the TEST_CK signal may not be provided (e.g., it remains logic low). Although control logic 214 in Figure 2 The portion shown is the clock input circuit 202, but in other embodiments, the control logic 214 may be located in another part of the device 200. For example, the control logic 214 may be located adjacent to the external DA pad 206.

[0035] During normal operation of device 200, command / address input circuit 204 may receive commands and / or addresses CA at its terminals. Commands and / or addresses may be provided to input buffer 216. Input buffer 216 may provide buffered commands and / or addresses BUF_CA to latches 218 and 220. Latch 218 may receive a clock signal Clk_R, and latch 220 may receive a complementary clock signal Clk_F from clock input circuit 202. Both latches 218 and 220 may be configured to latch commands and / or addresses BUF_CA from input buffer 216 on the rising edge of their respective clock signals. That is, when Clk_R transitions from a low clock level to a high clock level, latch 218 may latch the commands and / or addresses BUF_CA provided by input buffer 216, and when Clk_F transitions from a low clock level to a high clock level, latch 220 may latch the commands and / or addresses BUF_CA provided by input buffer 216. Because the clock signals Clk_R and Clk_F are complementary, the command / address input circuit 204 latches the command / address at both the rising and falling edges of the clock signals via latches 218 and 220. The command and / or address CAxR latched by latch 218 and the command and / or address CAxF latched by latch 220 can be provided to the command decoder circuit and / or address decoder circuit, such as command decoder 106 and address decoder 104.

[0036] During testing of device 200, command / address input circuitry 204 may receive command and / or address TEST_CA from external DA pad 206. The TEST_CA signal may be received from the test device coupled to external DA pad 206. The command and / or address MTEST_CA signal based on the TEST_CA signal may be provided to input buffer 216, which may provide the command and / or address of MTEST_CA as BUF_CA to latches 218 and 220. The MTEST_CA signal may be provided to input buffer 216 from buffer 232. Buffer 232 may receive the MTEST_CA signal from test synchronization circuitry 222. Although the test device may provide a clock signal TEST_CK at a frequency high enough to test the DDR specification of device 200, the test device may provide the command and / or address TEST_CA at SDR. Test synchronization circuitry 222 may allow an estimate (e.g., simulation) of DDR operation based on the SDR TEST_CA signal.

[0037] Test synchronization circuit 222 can receive the TEST_CA signal and latch the command and / or address of the TEST_CA signal via flip-flop 226. Test synchronization circuit 222 can receive the clock signal TEST_CK. Test synchronization circuit 222 can delay the TEST_CK signal via delay circuit 224 to provide a delayed TEST_CK signal DTEST_CK. In some embodiments, delay circuit 224 may include a series of inverters and / or signal buffers. The DTEST_CK signal can be used to trigger flip-flop 226. Flip-flop 226, triggered by the DTEST_CK signal, can delay the propagation of TEST_CA to provide the delayed TEST_CA signal DTEST_CA as the MTEST_CA signal to input buffer 216. See reference Figure 3 In more detail, the delay circuit 224 can be selected such that the command and / or address TEST_CA exists as the BUF_CA signal at latches 218 and 220 during the rising edges of clock signals Clk_R and Clk_F.

[0038] Optionally, in some embodiments, for example in Figure 2In one embodiment shown, the test synchronization circuit 222 may include a multiplexer 228. The multiplexer 228 may receive a DTEST_CA signal from a trigger 226 and a current TEST_CA signal from an external DA pad 206. The multiplexer 228 provides either the DTEST_CA signal or the current TEST_CA signal as the MTEST_CA signal. Whether the DTEST_CA signal or the current TEST_CA signal is provided from the multiplexer 228 as the MTEST_CA signal may be controlled by a control signal tmIntsync. In some embodiments, the test decoder circuitry may provide tmIntsync. In other embodiments, tmIntsync may be provided from the test apparatus via the external DA pad 206. In some applications, the delay of commands and / or addresses simulating DDR operation may only be desired in certain test modes. Therefore, for some test modes, tmIntsync can be provided with a logic state that causes the multiplexer 228 to provide a current TEST_CA signal as the MTEST_CA signal, and in other test modes, tmIntsync can be provided with another logic state that causes the multiplexer 228 to provide a DTEST_CA signal from the flip-flop 226 as the MTEST_CA signal.

[0039] In some embodiments, control logic 230 can be used to enable and disable the MTEST_CA signal provided by the test synchronization circuit 222. Figure 2 In the example shown, control logic 230 includes AND logic circuitry. Control logic 230 can receive a test enable signal DAenable. When the DAenable signal is active, the MTEST_CA signal can be provided to buffer 232. When the DAenable signal is inactive, the MTEST_CA signal may not be provided.

[0040] Although shown separated from command / address input circuitry 204, in some embodiments, such as in Figure 1 As shown in the example, the test synchronization circuit 222 may be included together with the command / address input circuit 204.

[0041] exist Figure 2In the embodiment shown, the command / address input circuit 204 includes latches 218 and 220, both configured to latch commands and / or addresses on the rising edges of clock signals Clk_R and Clk_F, respectively. However, in other embodiments, one of latches 218 or 220 may latch a command on the rising edge of a clock signal, while the other latches 218 or 220 latch a command on the falling edge of a clock signal. In these embodiments, only one clock signal (e.g., CK, TEST_CK) rather than two complementary clock signals may be provided to both latches 218 and 220.

[0042] Figure 3 This is a timing diagram of signals from a semiconductor device according to an embodiment of the present disclosure. The timing diagram 300 can reflect the state of signals from device 100 and / or device 200, and will be referenced... Figure 1 and 2 The signals described in timing diagram 300. However, timing diagram 300 can reflect signals other than those described in the original text. Figure 1 and 2 Operation of memory devices other than the memory devices shown in the embodiments of this disclosure.

[0043] The first row of timing diagram 300 shows the clock signal TEST_CK provided to device 100 and / or device 200 via a test device. The TEST_CK signal can be provided to clock input circuits 112 and / or 202. The timing of the clock signal TEST_CK shown in the first row can be the timing when TEST_CK is provided at external DA pad 130 and / or external DA pad 206. The second row of timing diagram 300 shows the command / address signal TEST_CA provided to device 100 and / or device 200 via a test device. The command / address signal TEST_CA can contain commands and / or addresses. Figure 3 In the example shown, the command / address signal TEST_CA includes command / address CmdR and CmdF. In some embodiments, CmdR and CmdF may contain separate commands and / or addresses. The separate commands and / or addresses may be different or the same (e.g., repeated commands and / or addresses). In some embodiments, CmdR and CmdF may contain portions of commands and / or addresses. For example, CmdR may contain a command and CmdF may contain an address associated with the command. However, other combinations of portions of commands and / or addresses provided in CmdR and CmdF may be used in other embodiments. The TEST_CA signal may be provided to command / address input circuits 102 and / or 204. The timing of the TEST_CA signal shown in the second row may be the timing when TEST_CA is provided at external DA pads 130 and / or 206.

[0044] The third row of timing diagram 300 is the clock signal DTEST_CK. The DTEST_CK signal can be a delayed TEST_CK signal provided, for example, from the delay circuit 224 of the test synchronization circuit 134 and / or 222. The fourth row of timing diagram 300 is the command / address signal DTEST_CA. The DTEST_CA signal can be a TEST_CA signal provided at the output of the flip-flop 226, which may be included in the test synchronization circuit 134 and / or 222, from the external DA pads 130 and / or 206.

[0045] The fifth and sixth rows of timing diagram 300 are complementary clock signals Clk_R and Clk_F, respectively, provided to latches 218 and 220 by a clock controller / buffer circuit 210, which may be included in clock input circuits 112 and / or 202. The seventh row of timing diagram 300 is the command / address signal BUF_CA (DTEST_CA), provided as the BUF_CA signal to latches 218 and 220. The BUF_CA (DTEST_CA) signal can be the TEST_CA signal. The last row of timing diagram 300 is the exemplary DDR command / address signal DDR CA.

[0046] At or near time T0, the command and / or address CmdR may be provided as Test_CA along with the clock signal TEST_CK from external DA pads 130 and / or 206. The TEST_CK signal may be provided to delay circuit 224, which delays TEST_CK and provides DTEST_CK. The clock signal TEST_CK may have a rising edge at or near time T1 (e.g., transition from a low clock level to a high clock level), while DTEST_CK does not have a rising edge until at or near time T2. In some embodiments, DTEST_CK may be delayed by approximately 1 / 4 of a clock cycle relative to TEST_CK (e.g., delayed by 10-30% of a clock cycle). The rising edge of DTEST_CK may be used to trigger flip-flop 226 at or near time T2 to latch CmdR. Due to DTEST_CK, the TEST_CA signal, which includes CmdR provided by flip-flop 226 as DTEST_CA, is delayed relative to the TEST_CA provided by external DA pads 130 and / or 206. At or near time T3, the command and / or address CmdF as TEST_CA can be provided from the external DA pad 206. CmdF can be latched at or near time T4 via flip-flop 226 in response to another rising edge of the clock signal DTEST_CA. Once latched, flip-flop 226 can provide CmdF as DTEST_CA.

[0047] As disclosed herein, complementary clock signals Clk_R and Clk_F can be generated at least in part based on TEST_CK. However, as shown in timing diagram 300, Clk_R and Clk_F may be delayed relative to TEST_CK. This delay can be attributed to the individual propagation delays of one or more components of devices 100 and / or 200. For example, control logic 214, buffer 212, input buffer 208, and / or clock controller / buffer circuitry 210 may contribute to the delay of TEST_CK, which can cause a total delay in Clk_R and Clk_F relative to TEST_CK.

[0048] The DTEST_CA signal (e.g., a delayed TEST_CA signal) can be provided from flip-flop 226 to latches 218 and 220 as BUF_CA (DTEST_CA). However, as shown in timing diagram 300, similar to Clk_R and Clk_F, DTEST_CA can be further delayed by one or more components of device 200. For example, multiplexer 228, control logic 230, buffer 232, and / or input buffer 216 can facilitate the propagation delay of the DTEST_CA signal. Thus, CmdR provided as by the BUF_CA (DTEST_CA) signal can be delayed relative to CmdR provided as by DTEST_CA at the FF signal. The total delay of TEST_CA from external DA pad 206 to latches 218 and 220 allows two consecutive command / address CmdR and CmdF to be provided at latches 218 and 220, respectively, during the rising edges of Clk_R and Clk_F. From another perspective, the total delay of TEST_CA allows the transition between two consecutive command / address signals CmdR and CmdF of the command / address signal BUF_CA to occur between the rising edge of Clk_R and the rising edge of Clk_F.

[0049] As shown in timing diagram 300, Clk_R has a rising edge at or near time T5, while CmdR is provided as BUF_CA (DTEST_CA). Latch 218 latches CmdR in response to the rising edge of Clk_R. As previously described, CmdF is latched at or near time T4 in response to flip-flop 226, and BUF_CA (DTEST_CA) transitions from CmdR to CmdF at or near time T6. Clk_F has a rising edge at or near time T7. Latch 220 latches CmdF in response to the rising edge of Clk_F. Therefore, the command / address signal provided by TEST_CA (provided as the BUF_CA (DTEST_CA) signal) is latched on the rising edges of both Clk_R and Clk_F. Then, latched commands / addresses CmdR and CmdF can be provided as commands and / or addresses CAxR and CAxF respectively via latches 218 and 220.

[0050] DDR CA describes the “analog” or estimated DDR timing of the command / address signals of devices 100 and / or 200, which is based in part on the delay of TEST_CA provided by test synchronization circuits 134 and / or 222. As disclosed herein, devices 100 and / or 200 may be DDR DRAM memory devices. That is, the devices may be able to receive and latch clock signals (e.g., Figure 1 The command / address signal is provided at both the rising and falling edges of ICLK (in DDR). In typical DDR operation, the command / address signal is provided within half of the clock cycle, and in typical SDR operation, it is provided throughout the entire clock cycle. Although the test synchronization circuits 134 and / or 222 may not reduce the time periods during which command / address CmdR and CmdF are provided, by changing command / address CmdR and CmdF so that the transition between CmdR and CmdF occurs between the rising edges of Clk_R and Clk_F, devices 100 and / or 200 latch the command / address signal as if CmdR and CmdF were already provided at DDR. As shown by the large shaded area in DDR CA, the command throughput of DDR is not simulated or estimated from the SDR TEST_CA signal. However, the ability to test command latching in DDR operation at lower throughput is sufficient to confirm proper operation of devices 100 and / or 200.

[0051] Figure 4This is a block diagram of a test system according to embodiments of the present disclosure. The test system 400 may include a test device 402 and a memory device 404. In some embodiments, the memory device 404 may include device 100 and / or device 200. In some embodiments, the test device 402 may provide signals to and receive signals from the memory device 404 via an external DA pad 406. In some embodiments, the external DA pad 406 may be located at a different orientation on the memory device 404 than a pad 408 that can be coupled to an external device (e.g., a memory controller). The pad 408 may include a DQ pad, a CK / CK terminal, and / or a CA terminal.

[0052] like Figure 4 As shown, in some embodiments, test device 402 may provide a test clock signal TEST_CK and / or a test command / address signal TEST_CA to memory device 404 via an external DA pad 406. The test clock signal and the test command / address signal may be provided to a clock input circuit (e.g., clock input circuit 112) and a command / address input circuit (e.g., command / address input circuit 102) of memory device 404, respectively. In some embodiments, the TEST_CK signal may be provided under DDR (e.g., 2GB / s) and the TEST_CA signal may be provided under SDR (e.g., 1GB / s). The TEST_CK signal may be used to generate an internal timing signal for memory device 404 during testing. The TEST_CA signal may be used to provide commands and / or addresses for memory operations during testing. Test device 402 may provide a test command signal TEST_CMD to external DA pad 406. In some embodiments, the TEST_CMD signal may be provided to a test command decoder circuit (e.g., test command decoder circuit 132). The test command signal TEST_CMD may contain information about the test performed by the test device 402. For example, the TEST_CMD signal may contain information indicating the test mode (e.g., loopback test, 1DQ test).

[0053] For certain test modes, such as those indicated by the TEST_CMD signal, the test synchronization circuit 410 of memory device 404 can be used to delay the Test_CA signal provided to the latch of the command / address input circuit. In some embodiments, the delay provided by the test synchronization circuit 410 can cause the command / address signal provided by the TEST_CA signal to transition between the rising and falling edges of the clock signal provided to the latch. In some embodiments, the delay provided by the test synchronization circuit 410 can be selected so that the command / address signal provided by the TEST_CA signal transitions between the rising edges of two complementary clock signals provided to the latch. In this way, the SDR command provided by TEST_CA can be latched according to DDR operation. This allows test device 402 to test some or all of the DDR functionality of memory device 404.

[0054] In some embodiments, memory device 404 may provide data TEST_DATA to test device 402. TEST_DATA may be provided at least in part in response to the command / address signal TEST_CA. Test device 402 may analyze the received TEST_DATA to determine whether memory device 404 is operating properly. If memory device 404 is determined to be operating properly, then in some embodiments, memory device 404 may be packaged with an external device. If memory device 404 is determined to be defective (e.g., not operating properly), then memory device 404 may be discarded or repaired and tested again.

[0055] Optionally, in some embodiments, test apparatus 402 can test multiple memory devices in parallel (e.g., simultaneously). For example, the test apparatus can test memory device 412 while also testing memory device 404. In some embodiments, memory device 412 may contain substantially the same components as memory device 404. Although only two memory devices are shown coupled to test apparatus 402, any number (e.g., 4, 8, 16) of memory devices can be coupled to test apparatus 402.

[0056] Figure 5 This is a flowchart of a method according to an embodiment of the present disclosure. In some embodiments, method 500 may be performed at least in part by means of apparatus 100, 200, 404 and / or 412.

[0057] At block 502, "receiving a test clock signal" can be performed. In some embodiments, the test clock signal can be received at a rate (e.g., DDR, 2GB / s). In some embodiments, the test clock signal can be received by clock input circuitry (e.g., clock input circuitry 112 and / or 202). In some embodiments, the test clock signal can be received by test synchronization circuitry (e.g., test synchronization circuitry 134, 222, and / or 410). At block 504, "receiving a test command / address signal at a rate different from the rate at which the test clock signal is received" can be performed. In some embodiments, the test command / address signal can be received at a slower rate compared to the rate at which the test clock signal is received. In some embodiments, the test command / address signal can be received by test synchronization circuitry.

[0058] At block 506, a "delay test clock signal" can be performed. In some embodiments, block 506 can be performed by test synchronization circuitry. In some embodiments, the delay can be provided by a delay circuit, such as delay circuitry 224. At block 508, a "latch of a trigger test command / address signal" can be performed. In some instances, the triggering and latching can be performed by test synchronization circuitry. In some embodiments, the triggering can be based on a delayed test clock signal. In some embodiments, the latching can be performed by a trigger, such as trigger 226.

[0059] At block 510, the action of "providing a latched test command / address signal to a first latch and a second latch" can be performed. In some embodiments, the latched test command / address signal may be provided by a test synchronization circuit. At block 512, the action of "latching a test command / address signal via a first latch" can be performed. In some embodiments, the latching may be performed by the first latch in response to a first edge of a second clock signal. At block 514, the action of "latching a test command / address signal via a second latch" can be performed. In some embodiments, the latching may be performed by the second latch in response to a second edge of a second clock signal. In some embodiments, the second clock signal may be generated at least partially based on a test clock signal. For example, in some embodiments, the second clock signal may be generated by clock input circuitry 112 and / or clock input circuitry 202. In some embodiments, the first latch may latch at least one of a first command or address provided by the test command / address signal, and the second latch may latch at least one of a second command or address provided by the test command / address signal.

[0060] In some embodiments, prior to block 502, an enable test clock signal and a test command / address signal may be executed. In some embodiments, the enable may be executed by, for example, control logic of control logics 214 and 230. In some embodiments, the enable may be in response to an enable signal provided by, for example, a test decoder circuit of test decoder circuit 132.

[0061] Of course, it should be understood that any of the examples, embodiments, or processes described herein may be combined with or separated from one or more other examples, embodiments, and / or processes and / or performed in a separate device or device portion of a system, apparatus, or method according to the present invention.

[0062] Finally, the foregoing discussion is intended merely to illustrate the apparatus, system, and method of the present invention and should not be construed as limiting the appended claims to any particular embodiment or group of embodiments. Therefore, while the apparatus, system, and method of the present invention have been described in detail with reference to exemplary embodiments, it should be understood that those skilled in the art can devise numerous modifications and alternative embodiments without departing from the broader spirit and scope of the inventive system as set forth in the appended claims. Consequently, the specification and drawings should be viewed in an illustrative manner and are not intended to limit the scope of the appended claims.

Claims

1. An apparatus comprising: a first latch configured to latch a command / address signal on a first edge of a clock signal, wherein the command / address signal includes a first portion and a second portion; a second latch configured to latch the command / address signal on a second edge of the clock signal, wherein the first edge and the second edge are included within a same clock cycle of the clock signal; and a test synchronization circuit configured to provide a delay for the command / address signal provided to the first latch and the second latch, wherein the delay causes a transition of the command / address signal from the first portion to the second portion to occur at a time after the first edge of the clock signal and before the second edge of the clock signal, wherein the first latch latches the command / address signal before the transition and the second latch latches the command / address signal after the transition.

2. The apparatus of claim 1, wherein the test synchronization circuit comprises a flip-flop configured to latch the command / address signal.

3. The apparatus of claim 2, wherein the test synchronization circuit further comprises a delay circuit configured to receive a second clock signal and provide the second clock signal with a second delay to the flip-flop, wherein the second clock signal with the second delay is used to trigger the flip-flop.

4. The apparatus of claim 3, wherein the delay circuit comprises a plurality of series inverters.

5. The apparatus of claim 2, wherein the test synchronization circuit further comprises a multiplexer configured to provide the command / address signal with the delay or the command / address signal without the delay in response to a control signal.

6. The apparatus of claim 5, further comprising a test decoder circuit, wherein the test decoder circuit is configured to provide the control signal to the multiplexer.

7. The apparatus of claim 2, wherein the test synchronization circuit further comprises a control logic circuit configured to enable the command / address signal in response to an enable signal.

8. The apparatus of claim 7, further comprising a test decoder circuit, wherein the test decoder circuit is configured to provide the enable signal to the control logic circuit.

9. The apparatus of claim 1, further comprising a clock controller / buffer circuit configured to generate a second clock signal and a third clock signal complementary to the second clock signal based on the clock signal and provide the second clock signal to the first latch and the third clock signal to the second latch, wherein the first edge of the clock signal is a rising edge and corresponds to a rising edge of the second clock signal and the second edge of the clock signal is a falling edge and corresponds to a rising edge of the third clock signal. ​ 10. The apparatus of claim 1, further comprising an external pad, wherein the command / address signals and the clock signals are provided from a test device via the external pad.

11. A system comprising: a test device configured to provide command / address signals and clock signals; a memory device coupled to the test device, the memory device comprising: a clock input circuit configured to receive the clock signals and generate internal clock signals based at least in part on the clock signals; a test synchronization circuit configured to receive the command / address signals and the clock signals and generate delayed command / address signals based on the command / address signals; a command / address input circuit comprising first and second latches configured to receive the internal clock signals and the delayed command / address signals, wherein the first latch is configured to latch the delayed command / address signals at a first edge of the internal clock signals and the second latch is configured to latch the delayed command / address signals at a second edge of the internal clock signals, wherein the delayed command / address signals include a first command / address at the first edge and the delayed command / address signals include a second command / address at the second edge.

12. The system of claim 11, wherein the internal clock signals comprise a first clock signal and a second clock signal complementary to the first clock signal, wherein the first latch receives the first clock signal and the second latch receives the second clock signal, wherein the first edge is a rising edge of the first clock signal and the second edge is a rising edge of the second clock signal.

13. The system of claim 11, further comprising a second memory device coupled to the test device, wherein the test device is configured to provide the command / address signals and the clock signals to the memory device and the second memory device in parallel.

14. The system of claim 11, wherein the memory device is configured to provide data to the test device and the test device is further configured to analyze the data to determine whether the memory device is operating properly.

15. The system of claim 11, wherein the clock signals are double data rate signals and the command / address signals are single data rate signals.

16. A method comprising: receiving test clock signals at a first rate; receiving test command / address signals at a second rate slower than the first rate; delaying the test clock signals by a test synchronization circuit; triggering latching of the test command / address signals by the test synchronization circuit by the delayed test clock signals; providing the latched test command / address signals to first and second latches by the test synchronization circuit; latching the test command / address signals by the first latch in response to a first edge of a second clock signal; and and The test command / address signals are latched by the second latch responsive to a second edge of the second clock signal.

17. The method of claim 16, wherein the first latch latches at least one of a first command or address provided by the test command / address signals, and the second latch latches at least one of a second command or address provided by the test command / address signals.

18. The method of claim 16, further comprising enabling the test clock signal and the test command / address signals responsive to an enable signal provided by a test decoder circuit.

19. The method of claim 16, further comprising generating the second clock signal based at least in part on the test clock signal.

20. The method of claim 16, wherein the test synchronization circuit latches the test command / address signals through a flip-flop.

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